1 /** 2 ****************************************************************************** 3 * @file lps33k_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps33k_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS33K_REGS_H 23 #define LPS33K_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS33K 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 167 /** @defgroup LPS22HB_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format. **/ 173 #define LPS33K_I2C_ADD 0xBBU 174 175 /** Device Identification (Who am I) **/ 176 #define LPS33K_ID 0xB1U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LPS33K_WHO_AM_I 0x0FU 184 #define LPS33K_CTRL_REG1 0x10U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t not_used_01 : 1; 189 uint8_t bdu : 1; 190 uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ 191 uint8_t odr : 3; 192 uint8_t not_used_02 : 1; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t not_used_02 : 1; 195 uint8_t odr : 3; 196 uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ 197 uint8_t bdu : 1; 198 uint8_t not_used_01 : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } lps33k_ctrl_reg1_t; 201 202 #define LPS33K_CTRL_REG2 0x11U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t one_shot : 1; 207 uint8_t not_used_01 : 1; 208 uint8_t swreset : 1; 209 uint8_t not_used_02 : 1; 210 uint8_t if_add_inc : 1; 211 uint8_t not_used_03 : 2; 212 uint8_t boot : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t boot : 1; 215 uint8_t not_used_03 : 2; 216 uint8_t if_add_inc : 1; 217 uint8_t not_used_02 : 1; 218 uint8_t swreset : 1; 219 uint8_t not_used_01 : 1; 220 uint8_t one_shot : 1; 221 #endif /* DRV_BYTE_ORDER */ 222 } lps33k_ctrl_reg2_t; 223 224 #define LPS33K_RPDS_L 0x18U 225 #define LPS33K_RPDS_H 0x19U 226 227 #define LPS33K_RES_CONF 0x1AU 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t lc_en : 1; 232 uint8_t not_used_01 : 7; 233 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 234 uint8_t not_used_01 : 7; 235 uint8_t lc_en : 1; 236 #endif /* DRV_BYTE_ORDER */ 237 } lps33k_res_conf_t; 238 239 #define LPS33K_STATUS 0x27U 240 typedef struct 241 { 242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 243 uint8_t p_da : 1; 244 uint8_t t_da : 1; 245 uint8_t not_used_02 : 2; 246 uint8_t p_or : 1; 247 uint8_t t_or : 1; 248 uint8_t not_used_01 : 2; 249 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 250 uint8_t not_used_01 : 2; 251 uint8_t t_or : 1; 252 uint8_t p_or : 1; 253 uint8_t not_used_02 : 2; 254 uint8_t t_da : 1; 255 uint8_t p_da : 1; 256 #endif /* DRV_BYTE_ORDER */ 257 } lps33k_status_t; 258 259 #define LPS33K_PRESS_OUT_XL 0x28U 260 #define LPS33K_PRESS_OUT_L 0x29U 261 #define LPS33K_PRESS_OUT_H 0x2AU 262 #define LPS33K_TEMP_OUT_L 0x2BU 263 #define LPS33K_TEMP_OUT_H 0x2CU 264 #define LPS33K_LPFP_RES 0x33U 265 266 /** 267 * @defgroup LPS33K_Register_Union 268 * @brief This union group all the registers having a bit-field 269 * description. 270 * This union is useful but it's not needed by the driver. 271 * 272 * REMOVING this union you are compliant with: 273 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 274 * 275 * @{ 276 * 277 */ 278 279 typedef union 280 { 281 lps33k_ctrl_reg1_t ctrl_reg1; 282 lps33k_ctrl_reg2_t ctrl_reg2; 283 lps33k_res_conf_t res_conf; 284 lps33k_status_t status; 285 bitwise_t bitwise; 286 uint8_t byte; 287 } lps33k_reg_t; 288 289 /** 290 * @} 291 * 292 */ 293 294 #ifndef __weak 295 #define __weak __attribute__((weak)) 296 #endif /* __weak */ 297 298 /* 299 * These are the basic platform dependent I/O routines to read 300 * and write device registers connected on a standard bus. 301 * The driver keeps offering a default implementation based on function 302 * pointers to read/write routines for backward compatibility. 303 * The __weak directive allows the final application to overwrite 304 * them with a custom implementation. 305 */ 306 307 int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 308 uint16_t len); 309 int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 310 uint8_t *data, 311 uint16_t len); 312 313 float_t lps33k_from_lsb_to_hpa(int32_t lsb); 314 315 float_t lps33k_from_lsb_to_degc(int16_t lsb); 316 317 int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 318 int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 319 320 typedef enum 321 { 322 LPS33K_LPF_ODR_DIV_2 = 0, 323 LPS33K_LPF_ODR_DIV_9 = 2, 324 LPS33K_LPF_ODR_DIV_20 = 3, 325 } lps33k_lpfp_t; 326 int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx, 327 lps33k_lpfp_t val); 328 int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx, 329 lps33k_lpfp_t *val); 330 331 typedef enum 332 { 333 LPS33K_POWER_DOWN = 0, 334 LPS33K_ODR_1_Hz = 1, 335 LPS33K_ODR_10_Hz = 2, 336 LPS33K_ODR_25_Hz = 3, 337 LPS33K_ODR_50_Hz = 4, 338 LPS33K_ODR_75_Hz = 5, 339 } lps33k_odr_t; 340 int32_t lps33k_data_rate_set(stmdev_ctx_t *ctx, lps33k_odr_t val); 341 int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val); 342 343 int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); 344 int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val); 345 346 int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); 347 int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); 348 349 int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 350 351 int32_t lps33k_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 352 353 int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 354 355 int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 356 357 int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); 358 359 int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); 360 361 int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff); 362 363 int32_t lps33k_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 364 365 int32_t lps33k_reset_set(stmdev_ctx_t *ctx, uint8_t val); 366 int32_t lps33k_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 367 368 int32_t lps33k_boot_set(stmdev_ctx_t *ctx, uint8_t val); 369 int32_t lps33k_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 370 371 int32_t lps33k_low_power_set(stmdev_ctx_t *ctx, uint8_t val); 372 int32_t lps33k_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); 373 374 int32_t lps33k_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); 375 int32_t lps33k_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); 376 377 /** 378 *@} 379 * 380 */ 381 382 #ifdef __cplusplus 383 } 384 #endif 385 386 #endif /* LPS33K_REGS_H */ 387 388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 389
