1 /*
2 ******************************************************************************
3 * @file lps28dfw_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS28DFW driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps28dfw_reg.h"
21
22 /**
23 * @defgroup LPS28DFW
24 * @brief This file provides a set of functions needed to drive the
25 * lps28dfw nano pressure sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps28dfw_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps28dfw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
lps28dfw_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak lps28dfw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup Private_functions
96 * @brief Section collect all the utility functions needed by APIs.
97 * @{
98 *
99 */
100
bytecpy(uint8_t * target,uint8_t * source)101 static void bytecpy(uint8_t *target, uint8_t *source)
102 {
103 if ((target != NULL) && (source != NULL))
104 {
105 *target = *source;
106 }
107 }
108
109 /**
110 * @}
111 *
112 */
113
114 /**
115 * @defgroup Sensitivity
116 * @brief These functions convert raw-data into engineering units.
117 * @{
118 *
119 */
120
lps28dfw_from_fs1260_to_hPa(int32_t lsb)121 float_t lps28dfw_from_fs1260_to_hPa(int32_t lsb)
122 {
123 return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */
124 }
125
lps28dfw_from_fs4060_to_hPa(int32_t lsb)126 float_t lps28dfw_from_fs4060_to_hPa(int32_t lsb)
127 {
128 return ((float_t)lsb / 524288.0f); /* 2048.0f * 256 */
129 }
130
lps28dfw_from_lsb_to_celsius(int16_t lsb)131 float_t lps28dfw_from_lsb_to_celsius(int16_t lsb)
132 {
133 return ((float_t)lsb / 100.0f);
134 }
135
136 /**
137 * @}
138 *
139 */
140
141 /**
142 * @defgroup Basic functions
143 * @brief This section groups all the functions concerning device basic
144 * configuration.
145 * @{
146 *
147 */
148
149 /**
150 * @brief Device "Who am I".[get]
151 *
152 * @param ctx communication interface handler.(ptr)
153 * @param val ID values.(ptr)
154 * @retval interface status (MANDATORY: return 0 -> no Error)
155 *
156 */
lps28dfw_id_get(const stmdev_ctx_t * ctx,lps28dfw_id_t * val)157 int32_t lps28dfw_id_get(const stmdev_ctx_t *ctx, lps28dfw_id_t *val)
158 {
159 uint8_t reg;
160 int32_t ret;
161
162 ret = lps28dfw_read_reg(ctx, LPS28DFW_WHO_AM_I, ®, 1);
163 val->whoami = reg;
164
165 return ret;
166 }
167
168 /**
169 * @brief Configures the bus operating mode.[set]
170 *
171 * @param ctx communication interface handler.(ptr)
172 * @param val configures the bus operating mode.(ptr)
173 * @retval interface status (MANDATORY: return 0 -> no Error)
174 *
175 */
lps28dfw_bus_mode_set(const stmdev_ctx_t * ctx,lps28dfw_bus_mode_t * val)176 int32_t lps28dfw_bus_mode_set(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val)
177 {
178 lps28dfw_i3c_if_ctrl_t i3c_if_ctrl;
179 lps28dfw_if_ctrl_t if_ctrl;
180 int32_t ret;
181
182 ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
183 if (ret == 0)
184 {
185 if_ctrl.int_en_i3c = ((uint8_t)val->interface & 0x04U) >> 2;
186 ret = lps28dfw_write_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
187 }
188
189 if (ret != 0)
190 {
191 return ret;
192 }
193
194 ret = lps28dfw_read_reg(ctx, LPS28DFW_I3C_IF_CTRL,
195 (uint8_t *)&i3c_if_ctrl, 1);
196 if (ret == 0)
197 {
198 i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U;
199 i3c_if_ctrl.I3C_Bus_Avb_Sel = (uint8_t)val->bus_avb_time & 0x03U;
200 ret = lps28dfw_write_reg(ctx, LPS28DFW_I3C_IF_CTRL,
201 (uint8_t *)&i3c_if_ctrl, 1);
202 }
203
204 return ret;
205 }
206
207 /**
208 * @brief Configures the bus operating mode.[set]
209 *
210 * @param ctx communication interface handler.(ptr)
211 * @param val configures the bus operating mode.(ptr)
212 * @retval interface status (MANDATORY: return 0 -> no Error)
213 *
214 */
lps28dfw_bus_mode_get(const stmdev_ctx_t * ctx,lps28dfw_bus_mode_t * val)215 int32_t lps28dfw_bus_mode_get(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val)
216 {
217 lps28dfw_i3c_if_ctrl_t i3c_if_ctrl;
218 lps28dfw_if_ctrl_t if_ctrl;
219 int32_t ret;
220
221 ret = lps28dfw_read_reg(ctx, LPS28DFW_I3C_IF_CTRL, (uint8_t *)&i3c_if_ctrl, 1);
222 if (ret == 0)
223 {
224 ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
225
226 switch (if_ctrl.int_en_i3c << 2)
227 {
228 case LPS28DFW_SEL_BY_HW:
229 val->interface = LPS28DFW_SEL_BY_HW;
230 break;
231 case LPS28DFW_INT_PIN_ON_I3C:
232 val->interface = LPS28DFW_INT_PIN_ON_I3C;
233 break;
234 default:
235 val->interface = LPS28DFW_SEL_BY_HW;
236 break;
237 }
238
239 switch (i3c_if_ctrl.asf_on)
240 {
241 case LPS28DFW_AUTO:
242 val->filter = LPS28DFW_AUTO;
243 break;
244 case LPS28DFW_ALWAYS_ON:
245 val->filter = LPS28DFW_ALWAYS_ON;
246 break;
247 default:
248 val->filter = LPS28DFW_AUTO;
249 break;
250 }
251
252 switch (i3c_if_ctrl.I3C_Bus_Avb_Sel)
253 {
254 case LPS28DFW_BUS_AVB_TIME_50us:
255 val->bus_avb_time = LPS28DFW_BUS_AVB_TIME_50us;
256 break;
257 case LPS28DFW_BUS_AVB_TIME_2us:
258 val->bus_avb_time = LPS28DFW_BUS_AVB_TIME_2us;
259 break;
260 case LPS28DFW_BUS_AVB_TIME_1ms:
261 val->bus_avb_time = LPS28DFW_BUS_AVB_TIME_1ms;
262 break;
263 case LPS28DFW_BUS_AVB_TIME_25ms:
264 val->bus_avb_time = LPS28DFW_BUS_AVB_TIME_25ms;
265 break;
266 default:
267 val->bus_avb_time = LPS28DFW_BUS_AVB_TIME_50us;
268 break;
269 }
270 }
271
272 return ret;
273 }
274
275 /**
276 * @brief Configures the bus operating mode.[get]
277 *
278 * @param ctx communication interface handler.(ptr)
279 * @param val configures the bus operating mode.(ptr)
280 * @retval interface status (MANDATORY: return 0 -> no Error)
281 *
282 */
lps28dfw_init_set(const stmdev_ctx_t * ctx,lps28dfw_init_t val)283 int32_t lps28dfw_init_set(const stmdev_ctx_t *ctx, lps28dfw_init_t val)
284 {
285 lps28dfw_ctrl_reg2_t ctrl_reg2;
286 lps28dfw_ctrl_reg3_t ctrl_reg3;
287 uint8_t reg[2];
288 int32_t ret;
289
290 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG2, reg, 2);
291 if (ret == 0)
292 {
293 bytecpy((uint8_t *)&ctrl_reg2, ®[0]);
294 bytecpy((uint8_t *)&ctrl_reg3, ®[1]);
295
296 switch (val)
297 {
298 case LPS28DFW_BOOT:
299 ctrl_reg2.boot = PROPERTY_ENABLE;
300 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG2,
301 (uint8_t *)&ctrl_reg2, 1);
302 break;
303 case LPS28DFW_RESET:
304 ctrl_reg2.swreset = PROPERTY_ENABLE;
305 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG2,
306 (uint8_t *)&ctrl_reg2, 1);
307 break;
308 case LPS28DFW_DRV_RDY:
309 ctrl_reg2.bdu = PROPERTY_ENABLE;
310 ctrl_reg3.if_add_inc = PROPERTY_ENABLE;
311 bytecpy(®[0], (uint8_t *)&ctrl_reg2);
312 bytecpy(®[1], (uint8_t *)&ctrl_reg3);
313 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG2, reg, 2);
314 break;
315 default:
316 ctrl_reg2.swreset = PROPERTY_ENABLE;
317 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG2,
318 (uint8_t *)&ctrl_reg2, 1);
319 break;
320 }
321 }
322 return ret;
323 }
324
325 /**
326 * @brief Get the status of the device.[get]
327 *
328 * @param ctx communication interface handler.(ptr)
329 * @param val the status of the device.(ptr)
330 * @retval interface status (MANDATORY: return 0 -> no Error)
331 *
332 */
lps28dfw_status_get(const stmdev_ctx_t * ctx,lps28dfw_stat_t * val)333 int32_t lps28dfw_status_get(const stmdev_ctx_t *ctx, lps28dfw_stat_t *val)
334 {
335 lps28dfw_interrupt_cfg_t interrupt_cfg;
336 lps28dfw_int_source_t int_source;
337 lps28dfw_ctrl_reg2_t ctrl_reg2;
338 lps28dfw_status_t status;
339 int32_t ret;
340
341 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG2,
342 (uint8_t *)&ctrl_reg2, 1);
343 if (ret == 0)
344 {
345 ret = lps28dfw_read_reg(ctx, LPS28DFW_INT_SOURCE, (uint8_t *)&int_source, 1);
346 }
347 if (ret == 0)
348 {
349 ret = lps28dfw_read_reg(ctx, LPS28DFW_STATUS, (uint8_t *)&status, 1);
350 }
351 if (ret == 0)
352 {
353 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG,
354 (uint8_t *)&interrupt_cfg, 1);
355 }
356 val->sw_reset = ctrl_reg2.swreset;
357 val->boot = int_source.boot_on;
358 val->drdy_pres = status.p_da;
359 val->drdy_temp = status.t_da;
360 val->ovr_pres = status.p_or;
361 val->ovr_temp = status.t_or;
362 val->end_meas = ~ctrl_reg2.oneshot;
363 val->ref_done = ~interrupt_cfg.autozero;
364
365 return ret;
366 }
367
368 /**
369 * @brief Electrical pin configuration.[set]
370 *
371 * @param ctx communication interface handler.(ptr)
372 * @param val the electrical settings for the configurable pins.(ptr)
373 * @retval interface status (MANDATORY: return 0 -> no Error)
374 *
375 */
lps28dfw_pin_conf_set(const stmdev_ctx_t * ctx,lps28dfw_pin_conf_t * val)376 int32_t lps28dfw_pin_conf_set(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val)
377 {
378 lps28dfw_ctrl_reg3_t ctrl_reg3;
379 lps28dfw_if_ctrl_t if_ctrl;
380 int32_t ret;
381
382 ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
383
384 if (ret == 0)
385 {
386 if_ctrl.int_pd_dis = ~val->int_pull_down;
387 if_ctrl.sda_pu_en = val->sda_pull_up;
388 ret = lps28dfw_write_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
389 }
390 if (ret == 0)
391 {
392 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
393 }
394 if (ret == 0)
395 {
396 ctrl_reg3.pp_od = ~val->int_push_pull;
397 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
398 }
399
400 return ret;
401 }
402
403 /**
404 * @brief Electrical pin configuration.[get]
405 *
406 * @param ctx communication interface handler.(ptr)
407 * @param val the electrical settings for the configurable pins.(ptr)
408 * @retval interface status (MANDATORY: return 0 -> no Error)
409 *
410 */
lps28dfw_pin_conf_get(const stmdev_ctx_t * ctx,lps28dfw_pin_conf_t * val)411 int32_t lps28dfw_pin_conf_get(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val)
412 {
413 lps28dfw_ctrl_reg3_t ctrl_reg3;
414 lps28dfw_if_ctrl_t if_ctrl;
415 int32_t ret;
416
417 ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
418 if (ret == 0)
419 {
420 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
421 }
422
423 val->int_pull_down = ~if_ctrl.int_pd_dis;
424 val->int_push_pull = ~ctrl_reg3.pp_od;
425 val->sda_pull_up = if_ctrl.sda_pu_en;
426
427 return ret;
428 }
429
430 /**
431 * @brief Get the status of all the interrupt sources.[get]
432 *
433 * @param ctx communication interface handler.(ptr)
434 * @param val the status of all the interrupt sources.(ptr)
435 * @retval interface status (MANDATORY: return 0 -> no Error)
436 *
437 */
lps28dfw_all_sources_get(const stmdev_ctx_t * ctx,lps28dfw_all_sources_t * val)438 int32_t lps28dfw_all_sources_get(const stmdev_ctx_t *ctx,
439 lps28dfw_all_sources_t *val)
440 {
441 lps28dfw_fifo_status2_t fifo_status2;
442 lps28dfw_int_source_t int_source;
443 lps28dfw_status_t status;
444 int32_t ret;
445
446 ret = lps28dfw_read_reg(ctx, LPS28DFW_STATUS, (uint8_t *)&status, 1);
447 if (ret == 0)
448 {
449 ret = lps28dfw_read_reg(ctx, LPS28DFW_INT_SOURCE,
450 (uint8_t *)&int_source, 1);
451 }
452 if (ret == 0)
453 {
454 ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_STATUS2,
455 (uint8_t *)&fifo_status2, 1);
456 }
457
458 val->drdy_pres = status.p_da;
459 val->drdy_temp = status.t_da;
460 val->over_pres = int_source.ph;
461 val->under_pres = int_source.pl;
462 val->thrsld_pres = int_source.ia;
463 val->fifo_full = fifo_status2.fifo_full_ia;
464 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
465 val->fifo_th = fifo_status2.fifo_wtm_ia;
466
467 return ret;
468 }
469
470
471 /**
472 * @brief Sensor conversion parameters selection.[set]
473 *
474 * @param ctx communication interface handler.(ptr)
475 * @param val set the sensor conversion parameters.(ptr)
476 * @retval interface status (MANDATORY: return 0 -> no Error)
477 *
478 */
lps28dfw_mode_set(const stmdev_ctx_t * ctx,lps28dfw_md_t * val)479 int32_t lps28dfw_mode_set(const stmdev_ctx_t *ctx, lps28dfw_md_t *val)
480 {
481 lps28dfw_ctrl_reg1_t ctrl_reg1;
482 lps28dfw_ctrl_reg2_t ctrl_reg2;
483 uint8_t reg[2];
484 int32_t ret;
485
486 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG1, reg, 2);
487
488 if (ret == 0)
489 {
490 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
491 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
492
493 ctrl_reg1.odr = (uint8_t)val->odr;
494 ctrl_reg1.avg = (uint8_t)val->avg;
495 ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U;
496 ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 1;
497 ctrl_reg2.fs_mode = (uint8_t)val->fs;
498
499 bytecpy(®[0], (uint8_t *)&ctrl_reg1);
500 bytecpy(®[1], (uint8_t *)&ctrl_reg2);
501 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG1, reg, 2);
502 }
503
504 return ret;
505 }
506
507 /**
508 * @brief Sensor conversion parameters selection.[get]
509 *
510 * @param ctx communication interface handler.(ptr)
511 * @param val get the sensor conversion parameters.(ptr)
512 * @retval interface status (MANDATORY: return 0 -> no Error)
513 *
514 */
lps28dfw_mode_get(const stmdev_ctx_t * ctx,lps28dfw_md_t * val)515 int32_t lps28dfw_mode_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *val)
516 {
517 lps28dfw_ctrl_reg1_t ctrl_reg1;
518 lps28dfw_ctrl_reg2_t ctrl_reg2;
519 uint8_t reg[2];
520 int32_t ret;
521
522 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG1, reg, 2);
523
524 if (ret == 0)
525 {
526 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
527 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
528
529 switch (ctrl_reg2.fs_mode)
530 {
531 case LPS28DFW_1260hPa:
532 val->fs = LPS28DFW_1260hPa;
533 break;
534 case LPS28DFW_4060hPa:
535 val->fs = LPS28DFW_4060hPa;
536 break;
537 default:
538 val->fs = LPS28DFW_1260hPa;
539 break;
540 }
541
542 switch (ctrl_reg1.odr)
543 {
544 case LPS28DFW_ONE_SHOT:
545 val->odr = LPS28DFW_ONE_SHOT;
546 break;
547 case LPS28DFW_1Hz:
548 val->odr = LPS28DFW_1Hz;
549 break;
550 case LPS28DFW_4Hz:
551 val->odr = LPS28DFW_4Hz;
552 break;
553 case LPS28DFW_10Hz:
554 val->odr = LPS28DFW_10Hz;
555 break;
556 case LPS28DFW_25Hz:
557 val->odr = LPS28DFW_25Hz;
558 break;
559 case LPS28DFW_50Hz:
560 val->odr = LPS28DFW_50Hz;
561 break;
562 case LPS28DFW_75Hz:
563 val->odr = LPS28DFW_75Hz;
564 break;
565 case LPS28DFW_100Hz:
566 val->odr = LPS28DFW_100Hz;
567 break;
568 case LPS28DFW_200Hz:
569 val->odr = LPS28DFW_200Hz;
570 break;
571 default:
572 val->odr = LPS28DFW_ONE_SHOT;
573 break;
574 }
575
576 switch (ctrl_reg1.avg)
577 {
578 case LPS28DFW_4_AVG:
579 val->avg = LPS28DFW_4_AVG;
580 break;
581 case LPS28DFW_8_AVG:
582 val->avg = LPS28DFW_8_AVG;
583 break;
584 case LPS28DFW_16_AVG:
585 val->avg = LPS28DFW_16_AVG;
586 break;
587 case LPS28DFW_32_AVG:
588 val->avg = LPS28DFW_32_AVG;
589 break;
590 case LPS28DFW_64_AVG:
591 val->avg = LPS28DFW_64_AVG;
592 break;
593 case LPS28DFW_128_AVG:
594 val->avg = LPS28DFW_128_AVG;
595 break;
596 case LPS28DFW_256_AVG:
597 val->avg = LPS28DFW_256_AVG;
598 break;
599 case LPS28DFW_512_AVG:
600 val->avg = LPS28DFW_512_AVG;
601 break;
602 default:
603 val->avg = LPS28DFW_4_AVG;
604 break;
605 }
606
607 switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp)
608 {
609 case LPS28DFW_LPF_DISABLE:
610 val->lpf = LPS28DFW_LPF_DISABLE;
611 break;
612 case LPS28DFW_LPF_ODR_DIV_4:
613 val->lpf = LPS28DFW_LPF_ODR_DIV_4;
614 break;
615 case LPS28DFW_LPF_ODR_DIV_9:
616 val->lpf = LPS28DFW_LPF_ODR_DIV_9;
617 break;
618 default:
619 val->lpf = LPS28DFW_LPF_DISABLE;
620 break;
621 }
622
623 }
624 return ret;
625 }
626
627 /**
628 * @brief Software trigger for One-Shot.[get]
629 *
630 * @param ctx communication interface handler.(ptr)
631 * @param md the sensor conversion parameters.(ptr)
632 * @retval interface status (MANDATORY: return 0 -> no Error)
633 *
634 */
lps28dfw_trigger_sw(const stmdev_ctx_t * ctx,lps28dfw_md_t * md)635 int32_t lps28dfw_trigger_sw(const stmdev_ctx_t *ctx, lps28dfw_md_t *md)
636 {
637 lps28dfw_ctrl_reg2_t ctrl_reg2;
638 int32_t ret = 0;
639
640 if (md->odr == LPS28DFW_ONE_SHOT)
641 {
642 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
643 ctrl_reg2.oneshot = PROPERTY_ENABLE;
644 if (ret == 0)
645 {
646 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
647 }
648 }
649 return ret;
650 }
651
652 /**
653 * @brief Retrieve sensor data.[get]
654 *
655 * @param ctx communication interface handler.(ptr)
656 * @param md the sensor conversion parameters.(ptr)
657 * @param data data retrived from the sensor.(ptr)
658 * @retval interface status (MANDATORY: return 0 -> no Error)
659 *
660 */
lps28dfw_data_get(const stmdev_ctx_t * ctx,lps28dfw_md_t * md,lps28dfw_data_t * data)661 int32_t lps28dfw_data_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *md,
662 lps28dfw_data_t *data)
663 {
664 uint8_t buff[5];
665 int32_t ret;
666
667 ret = lps28dfw_read_reg(ctx, LPS28DFW_PRESS_OUT_XL, buff, 5);
668
669 /* pressure conversion */
670 data->pressure.raw = (int32_t)buff[2];
671 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1];
672 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0];
673 data->pressure.raw = data->pressure.raw * 256;
674
675 switch (md->fs)
676 {
677 case LPS28DFW_1260hPa:
678 data->pressure.hpa = lps28dfw_from_fs1260_to_hPa(data->pressure.raw);
679 break;
680 case LPS28DFW_4060hPa:
681 data->pressure.hpa = lps28dfw_from_fs4060_to_hPa(data->pressure.raw);
682 break;
683 default:
684 data->pressure.hpa = 0.0f;
685 break;
686 }
687
688 /* temperature conversion */
689 data->heat.raw = (int16_t)buff[4];
690 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3];
691 data->heat.deg_c = lps28dfw_from_lsb_to_celsius(data->heat.raw);
692
693 return ret;
694 }
695
696 /**
697 * @brief Pressure output value.[get]
698 *
699 * @param ctx read / write interface definitions
700 * @param buff buffer that stores data read
701 * @retval interface status (MANDATORY: return 0 -> no Error)
702 *
703 */
lps28dfw_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)704 int32_t lps28dfw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
705 {
706 int32_t ret;
707 uint8_t reg[3];
708
709 ret = lps28dfw_read_reg(ctx, LPS28DFW_PRESS_OUT_XL, reg, 3);
710 *buff = reg[2];
711 *buff = (*buff * 256U) + reg[1];
712 *buff = (*buff * 256U) + reg[0];
713 *buff *= 256U;
714
715 return ret;
716 }
717
718 /**
719 * @brief Temperature output value.[get]
720 *
721 * @param ctx read / write interface definitions
722 * @param buff buffer that stores data read
723 * @retval interface status (MANDATORY: return 0 -> no Error)
724 *
725 */
lps28dfw_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)726 int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
727 {
728 int32_t ret;
729 uint8_t reg[2];
730
731 ret = lps28dfw_read_reg(ctx, LPS28DFW_TEMP_OUT_L, reg, 2);
732 *buff = (int16_t)reg[1];
733 *buff = (*buff * 256) + (int16_t)reg[0];
734
735 return ret;
736 }
737
738 /**
739 * @}
740 *
741 */
742
743 /**
744 * @defgroup FIFO functions
745 * @brief This section groups all the functions concerning the
746 * management of FIFO.
747 * @{
748 *
749 */
750
751 /**
752 * @brief FIFO operation mode selection.[set]
753 *
754 * @param ctx communication interface handler.(ptr)
755 * @param val set the FIFO operation mode.(ptr)
756 * @retval interface status (MANDATORY: return 0 -> no Error)
757 *
758 */
lps28dfw_fifo_mode_set(const stmdev_ctx_t * ctx,lps28dfw_fifo_md_t * val)759 int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val)
760 {
761 lps28dfw_fifo_ctrl_t fifo_ctrl;
762 lps28dfw_fifo_wtm_t fifo_wtm;
763 uint8_t reg[2];
764 int32_t ret;
765
766 ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2);
767 if (ret == 0)
768 {
769 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
770 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
771
772 fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U;
773 fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2;
774
775 if (val->watermark != 0x00U)
776 {
777 fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE;
778 }
779 else
780 {
781 fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE;
782 }
783
784 fifo_wtm.wtm = val->watermark;
785
786 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
787 bytecpy(®[1], (uint8_t *)&fifo_wtm);
788
789 ret = lps28dfw_write_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2);
790 }
791 return ret;
792 }
793
794 /**
795 * @brief FIFO operation mode selection.[get]
796 *
797 * @param ctx communication interface handler.(ptr)
798 * @param val get the FIFO operation mode.(ptr)
799 * @retval interface status (MANDATORY: return 0 -> no Error)
800 *
801 */
lps28dfw_fifo_mode_get(const stmdev_ctx_t * ctx,lps28dfw_fifo_md_t * val)802 int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val)
803 {
804 lps28dfw_fifo_ctrl_t fifo_ctrl;
805 lps28dfw_fifo_wtm_t fifo_wtm;
806 uint8_t reg[2];
807 int32_t ret;
808
809 ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2);
810
811 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
812 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
813
814 switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode)
815 {
816 case LPS28DFW_BYPASS:
817 val->operation = LPS28DFW_BYPASS;
818 break;
819 case LPS28DFW_FIFO:
820 val->operation = LPS28DFW_FIFO;
821 break;
822 case LPS28DFW_STREAM:
823 val->operation = LPS28DFW_STREAM;
824 break;
825 case LPS28DFW_STREAM_TO_FIFO:
826 val->operation = LPS28DFW_STREAM_TO_FIFO;
827 break;
828 case LPS28DFW_BYPASS_TO_STREAM:
829 val->operation = LPS28DFW_BYPASS_TO_STREAM;
830 break;
831 case LPS28DFW_BYPASS_TO_FIFO:
832 val->operation = LPS28DFW_BYPASS_TO_FIFO;
833 break;
834 default:
835 val->operation = LPS28DFW_BYPASS;
836 break;
837 }
838
839 val->watermark = fifo_wtm.wtm;
840
841 return ret;
842 }
843
844 /**
845 * @brief Get the number of samples stored in FIFO.[get]
846 *
847 * @param ctx communication interface handler.(ptr)
848 * @param md the sensor conversion parameters.(ptr)
849 * @param val number of samples stored in FIFO.(ptr)
850 * @retval interface status (MANDATORY: return 0 -> no Error)
851 *
852 */
lps28dfw_fifo_level_get(const stmdev_ctx_t * ctx,uint8_t * val)853 int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
854 {
855 lps28dfw_fifo_status1_t fifo_status1;
856 int32_t ret;
857
858 ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_STATUS1,
859 (uint8_t *)&fifo_status1, 1);
860
861 *val = fifo_status1.fss;
862
863 return ret;
864 }
865
866 /**
867 * @brief Software trigger for One-Shot.[get]
868 *
869 * @param ctx communication interface handler.(ptr)
870 * @param md the sensor conversion parameters.(ptr)
871 * @param fmd get the FIFO operation mode.(ptr)
872 * @param samp number of samples stored in FIFO.(ptr)
873 * @param data data retrived from FIFO.(ptr)
874 * @retval interface status (MANDATORY: return 0 -> no Error)
875 *
876 */
lps28dfw_fifo_data_get(const stmdev_ctx_t * ctx,uint8_t samp,lps28dfw_md_t * md,lps28dfw_fifo_data_t * data)877 int32_t lps28dfw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp,
878 lps28dfw_md_t *md, lps28dfw_fifo_data_t *data)
879 {
880 uint8_t fifo_data[3];
881 uint8_t i;
882 int32_t ret = 0;
883
884 for (i = 0U; i < samp; i++)
885 {
886 ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3);
887 data[i].raw = (int32_t)fifo_data[2];
888 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1];
889 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0];
890 data[i].raw = (data[i].raw * 256);
891
892 switch (md->fs)
893 {
894 case LPS28DFW_1260hPa:
895 data[i].hpa = lps28dfw_from_fs1260_to_hPa(data[i].raw);
896 break;
897 case LPS28DFW_4060hPa:
898 data[i].hpa = lps28dfw_from_fs4060_to_hPa(data[i].raw);
899 break;
900 default:
901 data[i].hpa = 0.0f;
902 break;
903 }
904 }
905
906 return ret;
907 }
908
909 /**
910 * @}
911 *
912 */
913
914 /**
915 * @defgroup Interrupt signals
916 * @brief This section groups all the functions concerning
917 * the management of interrupt signals.
918 * @{
919 *
920 */
921
922 /**
923 * @brief Interrupt pins hardware signal configuration.[set]
924 *
925 * @param ctx communication interface handler.(ptr)
926 * @param val the pins hardware signal settings.(ptr)
927 * @retval interface status (MANDATORY: return 0 -> no Error)
928 *
929 */
lps28dfw_interrupt_mode_set(const stmdev_ctx_t * ctx,lps28dfw_int_mode_t * val)930 int32_t lps28dfw_interrupt_mode_set(const stmdev_ctx_t *ctx,
931 lps28dfw_int_mode_t *val)
932 {
933 lps28dfw_interrupt_cfg_t interrupt_cfg;
934 lps28dfw_ctrl_reg3_t ctrl_reg3;
935 lps28dfw_ctrl_reg4_t ctrl_reg4;
936 uint8_t reg[2];
937 int32_t ret;
938
939 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, reg, 2);
940 if (ret == 0)
941 {
942 bytecpy((uint8_t *)&ctrl_reg3, ®[0]);
943 bytecpy((uint8_t *)&ctrl_reg4, ®[1]);
944
945 ctrl_reg3.int_h_l = val->active_low;
946 ctrl_reg4.drdy_pls = ~val->drdy_latched;
947
948 bytecpy(®[0], (uint8_t *)&ctrl_reg3);
949 bytecpy(®[1], (uint8_t *)&ctrl_reg4);
950
951 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG3, reg, 2);
952 }
953 if (ret == 0)
954 {
955 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG,
956 (uint8_t *)&interrupt_cfg, 1);
957 }
958 if (ret == 0)
959 {
960 interrupt_cfg.lir = val->int_latched ;
961 ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG,
962 (uint8_t *)&interrupt_cfg, 1);
963 }
964 return ret;
965 }
966
967 /**
968 * @brief Interrupt pins hardware signal configuration.[get]
969 *
970 * @param ctx communication interface handler.(ptr)
971 * @param val the pins hardware signal settings.(ptr)
972 * @retval interface status (MANDATORY: return 0 -> no Error)
973 *
974 */
lps28dfw_interrupt_mode_get(const stmdev_ctx_t * ctx,lps28dfw_int_mode_t * val)975 int32_t lps28dfw_interrupt_mode_get(const stmdev_ctx_t *ctx,
976 lps28dfw_int_mode_t *val)
977 {
978 lps28dfw_interrupt_cfg_t interrupt_cfg;
979 lps28dfw_ctrl_reg3_t ctrl_reg3;
980 lps28dfw_ctrl_reg4_t ctrl_reg4;
981 uint8_t reg[2];
982 int32_t ret;
983
984 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, reg, 2);
985 if (ret == 0)
986 {
987 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG,
988 (uint8_t *)&interrupt_cfg, 1);
989 }
990
991 bytecpy((uint8_t *)&ctrl_reg3, ®[0]);
992 bytecpy((uint8_t *)&ctrl_reg4, ®[1]);
993
994 val->active_low = ctrl_reg3.int_h_l;
995 val->drdy_latched = ~ctrl_reg4.drdy_pls;
996 val->int_latched = interrupt_cfg.lir;
997
998 return ret;
999 }
1000
1001 /**
1002 * @brief Route interrupt signals on int1 pin.[set]
1003 *
1004 * @param ctx communication interface handler.(ptr)
1005 * @param val the signals to route on int1 pin.(ptr)
1006 * @retval interface status (MANDATORY: return 0 -> no Error)
1007 *
1008 */
lps28dfw_pin_int_route_set(const stmdev_ctx_t * ctx,lps28dfw_pin_int_route_t * val)1009 int32_t lps28dfw_pin_int_route_set(const stmdev_ctx_t *ctx,
1010 lps28dfw_pin_int_route_t *val)
1011 {
1012 lps28dfw_ctrl_reg4_t ctrl_reg4;
1013 int32_t ret;
1014
1015 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1016 if (ret == 0)
1017 {
1018 ctrl_reg4.drdy = val->drdy_pres;
1019 ctrl_reg4.int_f_wtm = val->fifo_th;
1020 ctrl_reg4.int_f_ovr = val->fifo_ovr;
1021 ctrl_reg4.int_f_full = val->fifo_full;
1022
1023 if ((val->fifo_th != 0U) || (val->fifo_ovr != 0U) || (val->fifo_full != 0U))
1024 {
1025 ctrl_reg4.int_en = PROPERTY_ENABLE;
1026 }
1027 else
1028 {
1029 ctrl_reg4.int_en = PROPERTY_DISABLE;
1030 }
1031
1032 ret = lps28dfw_write_reg(ctx, LPS28DFW_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1033 }
1034 return ret;
1035 }
1036
1037 /**
1038 * @brief Route interrupt signals on int1 pin.[get]
1039 *
1040 * @param ctx communication interface handler.(ptr)
1041 * @param val the signals that are routed on int1 pin.(ptr)
1042 * @retval interface status (MANDATORY: return 0 -> no Error)
1043 *
1044 */
lps28dfw_pin_int_route_get(const stmdev_ctx_t * ctx,lps28dfw_pin_int_route_t * val)1045 int32_t lps28dfw_pin_int_route_get(const stmdev_ctx_t *ctx,
1046 lps28dfw_pin_int_route_t *val)
1047 {
1048 lps28dfw_ctrl_reg4_t ctrl_reg4;
1049 int32_t ret;
1050
1051 ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1052
1053 val->drdy_pres = ctrl_reg4.drdy;
1054 val->fifo_th = ctrl_reg4.int_f_wtm;
1055 val->fifo_ovr = ctrl_reg4.int_f_ovr;
1056 val->fifo_full = ctrl_reg4.int_f_full;
1057
1058 return ret;
1059
1060 }
1061
1062 /**
1063 * @}
1064 *
1065 */
1066
1067 /**
1068 * @defgroup Interrupt on threshold functions
1069 * @brief This section groups all the functions concerning
1070 * the wake up functionality.
1071 * @{
1072 *
1073 */
1074
1075 /**
1076 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1077 *
1078 * @param ctx communication interface handler.(ptr)
1079 * @param val parameters of configuration.(ptr)
1080 * @retval interface status (MANDATORY: return 0 -> no Error)
1081 *
1082 */
lps28dfw_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,lps28dfw_int_th_md_t * val)1083 int32_t lps28dfw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1084 lps28dfw_int_th_md_t *val)
1085 {
1086 lps28dfw_interrupt_cfg_t interrupt_cfg;
1087 lps28dfw_ths_p_l_t ths_p_l;
1088 lps28dfw_ths_p_h_t ths_p_h;
1089 uint8_t reg[3];
1090 int32_t ret;
1091
1092 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3);
1093 if (ret == 0)
1094 {
1095 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1096 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1097 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1098
1099 interrupt_cfg.phe = val->over_th;
1100 interrupt_cfg.ple = val->under_th;
1101 ths_p_h.ths = (uint8_t)(val->threshold / 256U);
1102 ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U));
1103
1104 bytecpy(®[0], (uint8_t *)&interrupt_cfg);
1105 bytecpy(®[1], (uint8_t *)&ths_p_l);
1106 bytecpy(®[2], (uint8_t *)&ths_p_h);
1107
1108 ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3);
1109 }
1110 return ret;
1111 }
1112
1113 /**
1114 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1115 *
1116 * @param ctx communication interface handler.(ptr)
1117 * @param val parameters of configuration.(ptr)
1118 * @retval interface status (MANDATORY: return 0 -> no Error)
1119 *
1120 */
lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,lps28dfw_int_th_md_t * val)1121 int32_t lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1122 lps28dfw_int_th_md_t *val)
1123 {
1124 lps28dfw_interrupt_cfg_t interrupt_cfg;
1125 lps28dfw_ths_p_l_t ths_p_l;
1126 lps28dfw_ths_p_h_t ths_p_h;
1127 uint8_t reg[3];
1128 int32_t ret;
1129
1130 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3);
1131
1132 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1133 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1134 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1135
1136 val->over_th = interrupt_cfg.phe;
1137 val->under_th = interrupt_cfg.ple;
1138 val->threshold = ths_p_h.ths;
1139 val->threshold = (val->threshold * 256U) + ths_p_l.ths;
1140
1141 return ret;
1142 }
1143
1144 /**
1145 * @}
1146 *
1147 */
1148
1149 /**
1150 * @defgroup Reference value of pressure
1151 * @brief This section groups all the functions concerning
1152 * the wake up functionality.
1153 * @{
1154 *
1155 */
1156
1157 /**
1158 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1159 *
1160 * @param ctx communication interface handler.(ptr)
1161 * @param val parameters of configuration.(ptr)
1162 * @retval interface status (MANDATORY: return 0 -> no Error)
1163 *
1164 */
lps28dfw_reference_mode_set(const stmdev_ctx_t * ctx,lps28dfw_ref_md_t * val)1165 int32_t lps28dfw_reference_mode_set(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val)
1166 {
1167 lps28dfw_interrupt_cfg_t interrupt_cfg;
1168 int32_t ret;
1169
1170 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG,
1171 (uint8_t *)&interrupt_cfg, 1);
1172 if (ret == 0)
1173 {
1174
1175 interrupt_cfg.autozero = val->get_ref;
1176 interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U;
1177
1178 interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1179 interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1180
1181 ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG,
1182 (uint8_t *)&interrupt_cfg, 1);
1183 }
1184 return ret;
1185 }
1186
1187 /**
1188 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1189 *
1190 * @param ctx communication interface handler.(ptr)
1191 * @param val parameters of configuration.(ptr)
1192 * @retval interface status (MANDATORY: return 0 -> no Error)
1193 *
1194 */
lps28dfw_reference_mode_get(const stmdev_ctx_t * ctx,lps28dfw_ref_md_t * val)1195 int32_t lps28dfw_reference_mode_get(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val)
1196 {
1197 lps28dfw_interrupt_cfg_t interrupt_cfg;
1198 int32_t ret;
1199
1200 ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG,
1201 (uint8_t *)&interrupt_cfg, 1);
1202
1203 switch ((interrupt_cfg.reset_az << 1) |
1204 interrupt_cfg.autorefp)
1205 {
1206 case LPS28DFW_OUT_AND_INTERRUPT:
1207 val->apply_ref = LPS28DFW_OUT_AND_INTERRUPT;
1208 break;
1209 case LPS28DFW_ONLY_INTERRUPT:
1210 val->apply_ref = LPS28DFW_ONLY_INTERRUPT;
1211 break;
1212 default:
1213 val->apply_ref = LPS28DFW_RST_REFS;
1214 break;
1215 }
1216 val->get_ref = interrupt_cfg.autozero;
1217
1218 return ret;
1219 }
1220
1221 /**
1222 * @brief Reference Pressure LSB data .[get]
1223 *
1224 * @param ctx communication interface handler.(ptr)
1225 * @param val parameters of configuration.(ptr)
1226 * @retval interface status (MANDATORY: return 0 -> no Error)
1227 *
1228 */
lps28dfw_refp_get(const stmdev_ctx_t * ctx,int16_t * val)1229 int32_t lps28dfw_refp_get(const stmdev_ctx_t *ctx, int16_t *val)
1230 {
1231 uint8_t reg[2];
1232 int32_t ret;
1233
1234 ret = lps28dfw_read_reg(ctx, LPS28DFW_REF_P_L, reg, 2);
1235
1236 *val = (int16_t)reg[1];
1237 *val = *val * 256 + (int16_t)reg[0];
1238
1239 return ret;
1240 }
1241
1242 /**
1243 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1244 *
1245 * @param ctx communication interface handler.(ptr)
1246 * @param val parameters of configuration.(ptr)
1247 * @retval interface status (MANDATORY: return 0 -> no Error)
1248 *
1249 */
lps28dfw_opc_set(const stmdev_ctx_t * ctx,int16_t val)1250 int32_t lps28dfw_opc_set(const stmdev_ctx_t *ctx, int16_t val)
1251 {
1252 uint8_t reg[2];
1253 int32_t ret;
1254
1255 reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U);
1256 reg[0] = (uint8_t)((uint16_t)val & 0x00FFU);
1257
1258 ret = lps28dfw_write_reg(ctx, LPS28DFW_RPDS_L, reg, 2);
1259
1260 return ret;
1261 }
1262
1263 /**
1264 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1265 *
1266 * @param ctx communication interface handler.(ptr)
1267 * @param val parameters of configuration.(ptr)
1268 * @retval interface status (MANDATORY: return 0 -> no Error)
1269 *
1270 */
lps28dfw_opc_get(const stmdev_ctx_t * ctx,int16_t * val)1271 int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val)
1272 {
1273 uint8_t reg[2];
1274 int32_t ret;
1275
1276 ret = lps28dfw_read_reg(ctx, LPS28DFW_RPDS_L, reg, 2);
1277
1278 *val = (int16_t)reg[1];
1279 *val = *val * 256 + (int16_t)reg[0];
1280
1281 return ret;
1282 }
1283
1284
1285 /**
1286 * @}
1287 *
1288 */
1289
1290 /**
1291 * @}
1292 *
1293 */
1294
1295 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1296
