1 /**
2 ******************************************************************************
3 * @file lps27hhw_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS27HHW driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps27hhw_reg.h"
21
22 /**
23 * @defgroup LPS27HHW
24 * @brief This file provides a set of functions needed to drive the
25 * lps27hhw enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LPS27HHW_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps27hhw_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps27hhw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lps27hhw_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lps27hhw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LPS27HHW_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
lps27hhw_from_lsb_to_hpa(int32_t lsb)102 float_t lps27hhw_from_lsb_to_hpa(int32_t lsb)
103 {
104 return ((float_t) lsb / 1048576.0f);
105 }
106
lps27hhw_from_lsb_to_celsius(int16_t lsb)107 float_t lps27hhw_from_lsb_to_celsius(int16_t lsb)
108 {
109 return ((float_t) lsb / 100.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup LPS27HHW_Data_Generation
119 * @brief This section groups all the functions concerning
120 * data generation.
121 * @{
122 *
123 */
124
125 /**
126 * @brief Reset Autozero function.[set]
127 *
128 * @param ctx read / write interface definitions
129 * @param val change the values of reset_az in reg INTERRUPT_CFG
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
lps27hhw_autozero_rst_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t lps27hhw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 lps27hhw_interrupt_cfg_t reg;
136 int32_t ret;
137
138 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
139
140 if (ret == 0)
141 {
142 reg.reset_az = val;
143 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
144 (uint8_t *) ®, 1);
145 }
146
147 return ret;
148 }
149
150 /**
151 * @brief Reset Autozero function.[get]
152 *
153 * @param ctx read / write interface definitions
154 * @param val change the values of reset_az in reg INTERRUPT_CFG
155 * @retval interface status (MANDATORY: return 0 -> no Error)
156 *
157 */
lps27hhw_autozero_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)158 int32_t lps27hhw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
159 {
160 lps27hhw_interrupt_cfg_t reg;
161 int32_t ret;
162
163 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
164 *val = reg.reset_az;
165
166 return ret;
167 }
168
169 /**
170 * @brief Enable Autozero function.[set]
171 *
172 * @param ctx read / write interface definitions
173 * @param val change the values of autozero in reg INTERRUPT_CFG
174 * @retval interface status (MANDATORY: return 0 -> no Error)
175 *
176 */
lps27hhw_autozero_set(const stmdev_ctx_t * ctx,uint8_t val)177 int32_t lps27hhw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val)
178 {
179 lps27hhw_interrupt_cfg_t reg;
180 int32_t ret;
181
182 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
183
184 if (ret == 0)
185 {
186 reg.autozero = val;
187 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
188 (uint8_t *) ®, 1);
189 }
190
191 return ret;
192 }
193
194 /**
195 * @brief Enable Autozero function.[get]
196 *
197 * @param ctx read / write interface definitions
198 * @param val change the values of autozero in reg INTERRUPT_CFG
199 * @retval interface status (MANDATORY: return 0 -> no Error)
200 *
201 */
lps27hhw_autozero_get(const stmdev_ctx_t * ctx,uint8_t * val)202 int32_t lps27hhw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val)
203 {
204 lps27hhw_interrupt_cfg_t reg;
205 int32_t ret;
206
207 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
208 *val = reg.autozero;
209
210 return ret;
211 }
212
213 /**
214 * @brief Reset AutoRifP function.[set]
215 *
216 * @param ctx read / write interface definitions
217 * @param val change the values of reset_arp in reg INTERRUPT_CFG
218 * @retval interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
lps27hhw_pressure_snap_rst_set(const stmdev_ctx_t * ctx,uint8_t val)221 int32_t lps27hhw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
222 {
223 lps27hhw_interrupt_cfg_t reg;
224 int32_t ret;
225
226 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
227
228 if (ret == 0)
229 {
230 reg.reset_arp = val;
231 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
232 (uint8_t *) ®, 1);
233 }
234
235 return ret;
236 }
237
238 /**
239 * @brief Reset AutoRifP function.[get]
240 *
241 * @param ctx read / write interface definitions
242 * @param val change the values of reset_arp in reg INTERRUPT_CFG
243 * @retval interface status (MANDATORY: return 0 -> no Error)
244 *
245 */
lps27hhw_pressure_snap_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)246 int32_t lps27hhw_pressure_snap_rst_get(const stmdev_ctx_t *ctx,
247 uint8_t *val)
248 {
249 lps27hhw_interrupt_cfg_t reg;
250 int32_t ret;
251
252 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
253 *val = reg.reset_arp;
254
255 return ret;
256 }
257
258 /**
259 * @brief Enable AutoRefP function.[set]
260 *
261 * @param ctx read / write interface definitions
262 * @param val change the values of autorefp in reg INTERRUPT_CFG
263 * @retval interface status (MANDATORY: return 0 -> no Error)
264 *
265 */
lps27hhw_pressure_snap_set(const stmdev_ctx_t * ctx,uint8_t val)266 int32_t lps27hhw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val)
267 {
268 lps27hhw_interrupt_cfg_t reg;
269 int32_t ret;
270
271 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
272
273 if (ret == 0)
274 {
275 reg.autorefp = val;
276 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
277 (uint8_t *) ®, 1);
278 }
279
280 return ret;
281 }
282
283 /**
284 * @brief Enable AutoRefP function.[get]
285 *
286 * @param ctx read / write interface definitions
287 * @param val change the values of autorefp in reg INTERRUPT_CFG
288 * @retval interface status (MANDATORY: return 0 -> no Error)
289 *
290 */
lps27hhw_pressure_snap_get(const stmdev_ctx_t * ctx,uint8_t * val)291 int32_t lps27hhw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val)
292 {
293 lps27hhw_interrupt_cfg_t reg;
294 int32_t ret;
295
296 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
297 *val = reg.autorefp;
298
299 return ret;
300 }
301
302 /**
303 * @brief Block Data Update.[set]
304 *
305 * @param ctx read / write interface definitions
306 * @param val change the values of bdu in reg CTRL_REG1
307 * @retval interface status (MANDATORY: return 0 -> no Error)
308 *
309 */
lps27hhw_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)310 int32_t lps27hhw_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
311 {
312 lps27hhw_ctrl_reg1_t reg;
313 int32_t ret;
314
315 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
316
317 if (ret == 0)
318 {
319 reg.bdu = val;
320 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
321 }
322
323 return ret;
324 }
325
326 /**
327 * @brief Block Data Update.[get]
328 *
329 * @param ctx read / write interface definitions
330 * @param val change the values of bdu in reg CTRL_REG1
331 * @retval interface status (MANDATORY: return 0 -> no Error)
332 *
333 */
lps27hhw_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)334 int32_t lps27hhw_block_data_update_get(const stmdev_ctx_t *ctx,
335 uint8_t *val)
336 {
337 lps27hhw_ctrl_reg1_t reg;
338 int32_t ret;
339
340 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
341 *val = reg.bdu;
342
343 return ret;
344 }
345
346 /**
347 * @brief Output data rate selection.[set]
348 *
349 * @param ctx read / write interface definitions
350 * @param val change the values of odr in reg CTRL_REG1
351 * @retval interface status (MANDATORY: return 0 -> no Error)
352 *
353 */
lps27hhw_data_rate_set(const stmdev_ctx_t * ctx,lps27hhw_odr_t val)354 int32_t lps27hhw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhw_odr_t val)
355 {
356 lps27hhw_ctrl_reg1_t ctrl_reg1;
357 lps27hhw_ctrl_reg2_t ctrl_reg2;
358 int32_t ret;
359
360 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1,
361 (uint8_t *)&ctrl_reg1, 1);
362
363 if (ret == 0)
364 {
365 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
366 (uint8_t *)&ctrl_reg2, 1);
367 }
368
369 if (ret == 0)
370 {
371 ctrl_reg1.odr = (uint8_t)val & 0x07U;
372 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1,
373 (uint8_t *)&ctrl_reg1, 1);
374 }
375
376 if (ret == 0)
377 {
378 ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
379 ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
380 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2,
381 (uint8_t *)&ctrl_reg2, 1);
382 }
383
384 return ret;
385 }
386
387 /**
388 * @brief Output data rate selection.[get]
389 *
390 * @param ctx read / write interface definitions
391 * @param val Get the values of odr in reg CTRL_REG1
392 * @retval interface status (MANDATORY: return 0 -> no Error)
393 *
394 */
lps27hhw_data_rate_get(const stmdev_ctx_t * ctx,lps27hhw_odr_t * val)395 int32_t lps27hhw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhw_odr_t *val)
396 {
397 lps27hhw_ctrl_reg1_t ctrl_reg1;
398 lps27hhw_ctrl_reg2_t ctrl_reg2;
399 int32_t ret;
400
401 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1,
402 (uint8_t *)&ctrl_reg1, 1);
403
404 if (ret == 0)
405 {
406 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
407 (uint8_t *)&ctrl_reg2, 1);
408 }
409
410 if (ret == 0)
411 {
412 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2,
413 (uint8_t *)&ctrl_reg2, 1);
414
415 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
416 ctrl_reg1.odr))
417 {
418 case LPS27HHW_POWER_DOWN:
419 *val = LPS27HHW_POWER_DOWN;
420 break;
421
422 case LPS27HHW_ONE_SHOOT:
423 *val = LPS27HHW_ONE_SHOOT;
424 break;
425
426 case LPS27HHW_1_Hz:
427 *val = LPS27HHW_1_Hz;
428 break;
429
430 case LPS27HHW_10_Hz:
431 *val = LPS27HHW_10_Hz;
432 break;
433
434 case LPS27HHW_25_Hz:
435 *val = LPS27HHW_25_Hz;
436 break;
437
438 case LPS27HHW_50_Hz:
439 *val = LPS27HHW_50_Hz;
440 break;
441
442 case LPS27HHW_75_Hz:
443 *val = LPS27HHW_75_Hz;
444 break;
445
446 case LPS27HHW_1_Hz_LOW_NOISE:
447 *val = LPS27HHW_1_Hz_LOW_NOISE;
448 break;
449
450 case LPS27HHW_10_Hz_LOW_NOISE:
451 *val = LPS27HHW_10_Hz_LOW_NOISE;
452 break;
453
454 case LPS27HHW_25_Hz_LOW_NOISE:
455 *val = LPS27HHW_25_Hz_LOW_NOISE;
456 break;
457
458 case LPS27HHW_50_Hz_LOW_NOISE:
459 *val = LPS27HHW_50_Hz_LOW_NOISE;
460 break;
461
462 case LPS27HHW_75_Hz_LOW_NOISE:
463 *val = LPS27HHW_75_Hz_LOW_NOISE;
464 break;
465
466 case LPS27HHW_100_Hz:
467 *val = LPS27HHW_100_Hz;
468 break;
469
470 case LPS27HHW_200_Hz:
471 *val = LPS27HHW_200_Hz;
472 break;
473
474 default:
475 *val = LPS27HHW_POWER_DOWN;
476 break;
477 }
478 }
479
480 return ret;
481 }
482
483 /**
484 * @brief The Reference pressure value is a 16-bit data
485 * expressed as 2’s complement. The value is used
486 * when AUTOZERO or AUTORIFP function is enabled.[set]
487 *
488 * @param ctx read / write interface definitions
489 * @param buff buffer that contains data to write
490 * @retval interface status (MANDATORY: return 0 -> no Error)
491 *
492 */
lps27hhw_pressure_ref_set(const stmdev_ctx_t * ctx,int16_t val)493 int32_t lps27hhw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val)
494 {
495 uint8_t buff[2];
496 int32_t ret;
497
498 buff[1] = (uint8_t)((uint16_t)val / 256U);
499 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
500 ret = lps27hhw_write_reg(ctx, LPS27HHW_REF_P_L, buff, 2);
501
502 return ret;
503 }
504
505 /**
506 * @brief The Reference pressure value is a 16-bit
507 * data expressed as 2’s complement.
508 * The value is used when AUTOZERO or AUTORIFP
509 * function is enabled.[get]
510 *
511 * @param ctx read / write interface definitions
512 * @param buff buffer that stores data read
513 * @retval interface status (MANDATORY: return 0 -> no Error)
514 *
515 */
lps27hhw_pressure_ref_get(const stmdev_ctx_t * ctx,int16_t * val)516 int32_t lps27hhw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val)
517 {
518 uint8_t buff[2];
519 int32_t ret;
520
521 ret = lps27hhw_read_reg(ctx, LPS27HHW_REF_P_L, buff, 2);
522 *val = (int16_t)buff[1];
523 *val = (*val * 256) + (int16_t)buff[0];
524
525 return ret;
526 }
527
528 /**
529 * @brief The pressure offset value is 16-bit data
530 * that can be used to implement one-point
531 * calibration (OPC) after soldering.[set]
532 *
533 * @param ctx read / write interface definitions
534 * @param buff buffer that contains data to write
535 * @retval interface status (MANDATORY: return 0 -> no Error)
536 *
537 */
lps27hhw_pressure_offset_set(const stmdev_ctx_t * ctx,int16_t val)538 int32_t lps27hhw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val)
539 {
540 uint8_t buff[2];
541 int32_t ret;
542
543 buff[1] = (uint8_t)((uint16_t)val / 256U);
544 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
545 ret = lps27hhw_write_reg(ctx, LPS27HHW_RPDS_L, buff, 2);
546
547 return ret;
548 }
549
550 /**
551 * @brief The pressure offset value is 16-bit
552 * data that can be used to implement
553 * one-point calibration (OPC) after
554 * soldering.[get]
555 *
556 * @param ctx read / write interface definitions
557 * @param buff buffer that stores data read
558 * @retval interface status (MANDATORY: return 0 -> no Error)
559 *
560 */
lps27hhw_pressure_offset_get(const stmdev_ctx_t * ctx,int16_t * val)561 int32_t lps27hhw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
562 {
563 uint8_t buff[2];
564 int32_t ret;
565
566 ret = lps27hhw_read_reg(ctx, LPS27HHW_RPDS_L, buff, 2);
567 *val = (int16_t)buff[1];
568 *val = (*val * 256) + (int16_t)buff[0];
569
570 return ret;
571 }
572
573 /**
574 * @brief Read all the interrupt/status flag of the device.[get]
575 *
576 * @param ctx read / write interface definitions
577 * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
578 * @retval interface status (MANDATORY: return 0 -> no Error)
579 *
580 */
lps27hhw_all_sources_get(const stmdev_ctx_t * ctx,lps27hhw_all_sources_t * val)581 int32_t lps27hhw_all_sources_get(const stmdev_ctx_t *ctx,
582 lps27hhw_all_sources_t *val)
583 {
584 int32_t ret;
585
586 ret = lps27hhw_read_reg(ctx, LPS27HHW_INT_SOURCE,
587 (uint8_t *) & (val->int_source), 1);
588
589 if (ret == 0)
590 {
591 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2,
592 (uint8_t *) & (val->fifo_status2), 1);
593 }
594
595 if (ret == 0)
596 {
597 ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS,
598 (uint8_t *) & (val->status), 1);
599 }
600
601 return ret;
602 }
603
604 /**
605 * @brief The STATUS_REG register is read by the primary interface.[get]
606 *
607 * @param ctx read / write interface definitions
608 * @param val structure of registers from STATUS to STATUS_REG
609 * @retval interface status (MANDATORY: return 0 -> no Error)
610 *
611 */
lps27hhw_status_reg_get(const stmdev_ctx_t * ctx,lps27hhw_status_t * val)612 int32_t lps27hhw_status_reg_get(const stmdev_ctx_t *ctx,
613 lps27hhw_status_t *val)
614 {
615 int32_t ret;
616
617 ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) val, 1);
618
619 return ret;
620 }
621
622 /**
623 * @brief Pressure new data available.[get]
624 *
625 * @param ctx read / write interface definitions
626 * @param val change the values of p_da in reg STATUS
627 * @retval interface status (MANDATORY: return 0 -> no Error)
628 *
629 */
lps27hhw_press_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)630 int32_t lps27hhw_press_flag_data_ready_get(const stmdev_ctx_t *ctx,
631 uint8_t *val)
632 {
633 lps27hhw_status_t reg;
634 int32_t ret;
635
636 ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1);
637 *val = reg.p_da;
638
639 return ret;
640 }
641
642 /**
643 * @brief Temperature data available.[get]
644 *
645 * @param ctx read / write interface definitions
646 * @param val change the values of t_da in reg STATUS
647 * @retval interface status (MANDATORY: return 0 -> no Error)
648 *
649 */
lps27hhw_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)650 int32_t lps27hhw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
651 uint8_t *val)
652 {
653 lps27hhw_status_t reg;
654 int32_t ret;
655
656 ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1);
657 *val = reg.t_da;
658
659 return ret;
660 }
661
662 /**
663 * @}
664 *
665 */
666
667 /**
668 * @defgroup LPS27HHW_Data_Output
669 * @brief This section groups all the data output functions.
670 * @{
671 *
672 */
673
674 /**
675 * @brief Pressure output value.[get]
676 *
677 * @param ctx read / write interface definitions
678 * @param buff buffer that stores data read
679 * @retval interface status (MANDATORY: return 0 -> no Error)
680 *
681 */
lps27hhw_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)682 int32_t lps27hhw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
683 {
684 uint8_t reg[3];
685 int32_t ret;
686
687 ret = lps27hhw_read_reg(ctx, LPS27HHW_PRESS_OUT_XL, reg, 3);
688 *buff = reg[2];
689 *buff = (*buff * 256) + reg[1];
690 *buff = (*buff * 256) + reg[0];
691 *buff *= 256;
692
693 return ret;
694 }
695
696 /**
697 * @brief Temperature output value.[get]
698 *
699 * @param ctx read / write interface definitions
700 * @param buff buffer that stores data read
701 * @retval interface status (MANDATORY: return 0 -> no Error)
702 *
703 */
lps27hhw_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)704 int32_t lps27hhw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
705 {
706 uint8_t reg[2];
707 int32_t ret;
708
709 ret = lps27hhw_read_reg(ctx, LPS27HHW_TEMP_OUT_L, reg, 2);
710 *buff = reg[1];
711 *buff = (*buff * 256) + reg[0];
712
713 return ret;
714 }
715
716 /**
717 * @brief Pressure output from FIFO value.[get]
718 *
719 * @param ctx read / write interface definitions
720 * @param buff buffer that stores data read
721 * @retval interface status (MANDATORY: return 0 -> no Error)
722 *
723 */
lps27hhw_fifo_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)724 int32_t lps27hhw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx,
725 uint32_t *buff)
726 {
727 uint8_t reg[3];
728 int32_t ret;
729
730 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_PRESS_XL, reg,
731 3);
732 *buff = reg[2];
733 *buff = (*buff * 256) + reg[1];
734 *buff = (*buff * 256) + reg[0];
735 *buff *= 256;
736
737 return ret;
738 }
739
740 /**
741 * @brief Temperature output from FIFO value.[get]
742 *
743 * @param ctx read / write interface definitions
744 * @param buff buffer that stores data read
745 * @retval interface status (MANDATORY: return 0 -> no Error)
746 *
747 */
lps27hhw_fifo_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)748 int32_t lps27hhw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx,
749 int16_t *buff)
750 {
751 uint8_t reg[2];
752 int32_t ret;
753
754 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_TEMP_L, reg, 2);
755 *buff = reg[1];
756 *buff = (*buff * 256) + reg[0];
757
758 return ret;
759 }
760
761 /**
762 * @}
763 *
764 */
765
766 /**
767 * @defgroup LPS27HHW_Common
768 * @brief This section groups common useful functions.
769 * @{
770 *
771 */
772
773 /**
774 * @brief DeviceWhoamI[get]
775 *
776 * @param ctx read / write interface definitions
777 * @param buff buffer that stores data read
778 * @retval interface status (MANDATORY: return 0 -> no Error)
779 *
780 */
lps27hhw_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)781 int32_t lps27hhw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
782 {
783 int32_t ret;
784
785 ret = lps27hhw_read_reg(ctx, LPS27HHW_WHO_AM_I, buff, 1);
786
787 return ret;
788 }
789
790 /**
791 * @brief Software reset. Restore the default values
792 * in user registers.[set]
793 *
794 * @param ctx read / write interface definitions
795 * @param val change the values of swreset in reg CTRL_REG2
796 * @retval interface status (MANDATORY: return 0 -> no Error)
797 *
798 */
lps27hhw_reset_set(const stmdev_ctx_t * ctx,uint8_t val)799 int32_t lps27hhw_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
800 {
801 lps27hhw_ctrl_reg2_t reg;
802 int32_t ret;
803
804 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
805
806 if (ret == 0)
807 {
808 reg.swreset = val;
809 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
810 }
811
812 return ret;
813 }
814
815 /**
816 * @brief Software reset. Restore the default values
817 * in user registers.[get]
818 *
819 * @param ctx read / write interface definitions
820 * @param val change the values of swreset in reg CTRL_REG2
821 * @retval interface status (MANDATORY: return 0 -> no Error)
822 *
823 */
lps27hhw_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)824 int32_t lps27hhw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
825 {
826 lps27hhw_ctrl_reg2_t reg;
827 int32_t ret;
828
829 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
830 *val = reg.swreset;
831
832 return ret;
833 }
834
835 /**
836 * @brief Register address automatically
837 * incremented during a multiple byte access
838 * with a serial interface.[set]
839 *
840 * @param ctx read / write interface definitions
841 * @param val change the values of if_add_inc in reg CTRL_REG2
842 * @retval interface status (MANDATORY: return 0 -> no Error)
843 *
844 */
lps27hhw_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)845 int32_t lps27hhw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
846 {
847 lps27hhw_ctrl_reg2_t reg;
848 int32_t ret;
849
850 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
851
852 if (ret == 0)
853 {
854 reg.if_add_inc = val;
855 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
856 }
857
858 return ret;
859 }
860
861 /**
862 * @brief Register address automatically
863 * incremented during a multiple byte
864 * access with a serial interface.[get]
865 *
866 * @param ctx read / write interface definitions
867 * @param val change the values of if_add_inc in reg CTRL_REG2
868 * @retval interface status (MANDATORY: return 0 -> no Error)
869 *
870 */
lps27hhw_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)871 int32_t lps27hhw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
872 {
873 lps27hhw_ctrl_reg2_t reg;
874 int32_t ret;
875
876 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
877 *val = reg.if_add_inc;
878
879 return ret;
880 }
881
882 /**
883 * @brief Reboot memory content. Reload the calibration
884 * parameters.[set]
885 *
886 * @param ctx read / write interface definitions
887 * @param val change the values of boot in reg CTRL_REG2
888 * @retval interface status (MANDATORY: return 0 -> no Error)
889 *
890 */
lps27hhw_boot_set(const stmdev_ctx_t * ctx,uint8_t val)891 int32_t lps27hhw_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
892 {
893 lps27hhw_ctrl_reg2_t reg;
894 int32_t ret;
895
896 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
897
898 if (ret == 0)
899 {
900 reg.boot = val;
901 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
902 }
903
904 return ret;
905 }
906
907 /**
908 * @brief Reboot memory content. Reload the calibration
909 * parameters.[get]
910 *
911 * @param ctx read / write interface definitions
912 * @param val change the values of boot in reg CTRL_REG2
913 * @retval interface status (MANDATORY: return 0 -> no Error)
914 *
915 */
lps27hhw_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)916 int32_t lps27hhw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
917 {
918 lps27hhw_ctrl_reg2_t reg;
919 int32_t ret;
920
921 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
922 *val = reg.boot;
923
924 return ret;
925 }
926
927 /**
928 * @}
929 *
930 */
931
932 /**
933 * @defgroup LPS27HHW_Filters
934 * @brief This section group all the functions concerning the
935 * filters configuration.
936 * @{
937 *
938 */
939
940 /**
941 * @brief Low-pass bandwidth selection.[set]
942 *
943 * @param ctx read / write interface definitions
944 * @param val change the values of lpfp_cfg in reg CTRL_REG1
945 * @retval interface status (MANDATORY: return 0 -> no Error)
946 *
947 */
lps27hhw_lp_bandwidth_set(const stmdev_ctx_t * ctx,lps27hhw_lpfp_cfg_t val)948 int32_t lps27hhw_lp_bandwidth_set(const stmdev_ctx_t *ctx,
949 lps27hhw_lpfp_cfg_t val)
950 {
951 lps27hhw_ctrl_reg1_t reg;
952 int32_t ret;
953
954 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
955
956 if (ret == 0)
957 {
958 reg.lpfp_cfg = (uint8_t)val;
959 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
960 }
961
962 return ret;
963 }
964
965 /**
966 * @brief Low-pass bandwidth selection.[get]
967 *
968 * @param ctx read / write interface definitions
969 * @param val Get the values of lpfp_cfg in reg CTRL_REG1
970 * @retval interface status (MANDATORY: return 0 -> no Error)
971 *
972 */
lps27hhw_lp_bandwidth_get(const stmdev_ctx_t * ctx,lps27hhw_lpfp_cfg_t * val)973 int32_t lps27hhw_lp_bandwidth_get(const stmdev_ctx_t *ctx,
974 lps27hhw_lpfp_cfg_t *val)
975 {
976 lps27hhw_ctrl_reg1_t reg;
977 int32_t ret;
978
979 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
980
981 switch (reg.lpfp_cfg)
982 {
983 case LPS27HHW_LPF_ODR_DIV_2:
984 *val = LPS27HHW_LPF_ODR_DIV_2;
985 break;
986
987 case LPS27HHW_LPF_ODR_DIV_9:
988 *val = LPS27HHW_LPF_ODR_DIV_9;
989 break;
990
991 case LPS27HHW_LPF_ODR_DIV_20:
992 *val = LPS27HHW_LPF_ODR_DIV_20;
993 break;
994
995 default:
996 *val = LPS27HHW_LPF_ODR_DIV_2;
997 break;
998 }
999
1000 return ret;
1001 }
1002
1003 /**
1004 * @}
1005 *
1006 */
1007
1008 /**
1009 * @defgroup LPS27HHW_Serial_Interface
1010 * @brief This section groups all the functions concerning serial
1011 * interface management
1012 * @{
1013 *
1014 */
1015
1016 /**
1017 * @brief Enable/Disable I2C interface.[set]
1018 *
1019 * @param ctx read / write interface definitions
1020 * @param val change the values of i2c_disable in reg IF_CTRL
1021 * @retval interface status (MANDATORY: return 0 -> no Error)
1022 *
1023 */
lps27hhw_i2c_interface_set(const stmdev_ctx_t * ctx,lps27hhw_i2c_disable_t val)1024 int32_t lps27hhw_i2c_interface_set(const stmdev_ctx_t *ctx,
1025 lps27hhw_i2c_disable_t val)
1026 {
1027 lps27hhw_if_ctrl_t reg;
1028 int32_t ret;
1029
1030 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1031
1032 if (ret == 0)
1033 {
1034 reg.i2c_disable = (uint8_t)val;
1035 ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1036 }
1037
1038 return ret;
1039 }
1040
1041 /**
1042 * @brief Enable/Disable I2C interface.[get]
1043 *
1044 * @param ctx read / write interface definitions
1045 * @param val Get the values of i2c_disable in reg IF_CTRL
1046 * @retval interface status (MANDATORY: return 0 -> no Error)
1047 *
1048 */
lps27hhw_i2c_interface_get(const stmdev_ctx_t * ctx,lps27hhw_i2c_disable_t * val)1049 int32_t lps27hhw_i2c_interface_get(const stmdev_ctx_t *ctx,
1050 lps27hhw_i2c_disable_t *val)
1051 {
1052 lps27hhw_if_ctrl_t reg;
1053 int32_t ret;
1054
1055 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1056
1057 switch (reg.i2c_disable)
1058 {
1059 case LPS27HHW_I2C_ENABLE:
1060 *val = LPS27HHW_I2C_ENABLE;
1061 break;
1062
1063 case LPS27HHW_I2C_DISABLE:
1064 *val = LPS27HHW_I2C_DISABLE;
1065 break;
1066
1067 default:
1068 *val = LPS27HHW_I2C_ENABLE;
1069 break;
1070 }
1071
1072 return ret;
1073 }
1074
1075 /**
1076 * @brief I3C Enable/Disable communication protocol.[set]
1077 *
1078 * @param ctx read / write interface definitions
1079 * @param val change the values of int_en_i3c in reg IF_CTRL
1080 * @retval interface status (MANDATORY: return 0 -> no Error)
1081 *
1082 */
lps27hhw_i3c_interface_set(const stmdev_ctx_t * ctx,lps27hhw_i3c_disable_t val)1083 int32_t lps27hhw_i3c_interface_set(const stmdev_ctx_t *ctx,
1084 lps27hhw_i3c_disable_t val)
1085 {
1086 lps27hhw_if_ctrl_t reg;
1087 int32_t ret;
1088
1089 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1090
1091 if (ret == 0)
1092 {
1093 reg.i3c_disable = ((uint8_t)val & 0x01u);
1094 reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
1095 ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1096 }
1097
1098 return ret;
1099 }
1100
1101 /**
1102 * @brief I3C Enable/Disable communication protocol.[get]
1103 *
1104 * @param ctx read / write interface definitions
1105 * @param val change the values of int_en_i3c in reg IF_CTRL
1106 * @retval interface status (MANDATORY: return 0 -> no Error)
1107 *
1108 */
lps27hhw_i3c_interface_get(const stmdev_ctx_t * ctx,lps27hhw_i3c_disable_t * val)1109 int32_t lps27hhw_i3c_interface_get(const stmdev_ctx_t *ctx,
1110 lps27hhw_i3c_disable_t *val)
1111 {
1112 lps27hhw_if_ctrl_t reg;
1113 int32_t ret;
1114
1115 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1116
1117 switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
1118 {
1119 case LPS27HHW_I3C_ENABLE:
1120 *val = LPS27HHW_I3C_ENABLE;
1121 break;
1122
1123 case LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE:
1124 *val = LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE;
1125 break;
1126
1127 case LPS27HHW_I3C_DISABLE:
1128 *val = LPS27HHW_I3C_DISABLE;
1129 break;
1130
1131 default:
1132 *val = LPS27HHW_I3C_ENABLE;
1133 break;
1134 }
1135
1136 return ret;
1137 }
1138
1139 /**
1140 * @brief Enable/Disable pull-up on SDO pin.[set]
1141 *
1142 * @param ctx read / write interface definitions
1143 * @param val change the values of sdo_pu_en in reg IF_CTRL
1144 * @retval interface status (MANDATORY: return 0 -> no Error)
1145 *
1146 */
lps27hhw_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lps27hhw_pu_en_t val)1147 int32_t lps27hhw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
1148 lps27hhw_pu_en_t val)
1149 {
1150 lps27hhw_if_ctrl_t reg;
1151 int32_t ret;
1152
1153 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1154
1155 if (ret == 0)
1156 {
1157 reg.sdo_pu_en = (uint8_t)val;
1158 ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1159 }
1160
1161 return ret;
1162 }
1163
1164 /**
1165 * @brief Enable/Disable pull-up on SDO pin.[get]
1166 *
1167 * @param ctx read / write interface definitions
1168 * @param val Get the values of sdo_pu_en in reg IF_CTRL
1169 * @retval interface status (MANDATORY: return 0 -> no Error)
1170 *
1171 */
lps27hhw_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lps27hhw_pu_en_t * val)1172 int32_t lps27hhw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
1173 lps27hhw_pu_en_t *val)
1174 {
1175 lps27hhw_if_ctrl_t reg;
1176 int32_t ret;
1177
1178 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1179
1180 switch (reg.sdo_pu_en)
1181 {
1182 case LPS27HHW_PULL_UP_DISCONNECT:
1183 *val = LPS27HHW_PULL_UP_DISCONNECT;
1184 break;
1185
1186 case LPS27HHW_PULL_UP_CONNECT:
1187 *val = LPS27HHW_PULL_UP_CONNECT;
1188 break;
1189
1190 default:
1191 *val = LPS27HHW_PULL_UP_DISCONNECT;
1192 break;
1193 }
1194
1195 return ret;
1196 }
1197
1198 /**
1199 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
1200 *
1201 * @param ctx read / write interface definitions
1202 * @param val change the values of sda_pu_en in reg IF_CTRL
1203 * @retval interface status (MANDATORY: return 0 -> no Error)
1204 *
1205 */
lps27hhw_sda_mode_set(const stmdev_ctx_t * ctx,lps27hhw_pu_en_t val)1206 int32_t lps27hhw_sda_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t val)
1207 {
1208 lps27hhw_if_ctrl_t reg;
1209 int32_t ret;
1210
1211 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1212
1213 if (ret == 0)
1214 {
1215 reg.sda_pu_en = (uint8_t)val;
1216 ret = lps27hhw_write_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1217 }
1218
1219 return ret;
1220 }
1221
1222 /**
1223 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
1224 *
1225 * @param ctx read / write interface definitions
1226 * @param val Get the values of sda_pu_en in reg IF_CTRL
1227 * @retval interface status (MANDATORY: return 0 -> no Error)
1228 *
1229 */
lps27hhw_sda_mode_get(const stmdev_ctx_t * ctx,lps27hhw_pu_en_t * val)1230 int32_t lps27hhw_sda_mode_get(const stmdev_ctx_t *ctx,
1231 lps27hhw_pu_en_t *val)
1232 {
1233 lps27hhw_if_ctrl_t reg;
1234 int32_t ret;
1235
1236 ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1);
1237
1238 switch (reg.sda_pu_en)
1239 {
1240 case LPS27HHW_PULL_UP_DISCONNECT:
1241 *val = LPS27HHW_PULL_UP_DISCONNECT;
1242 break;
1243
1244 case LPS27HHW_PULL_UP_CONNECT:
1245 *val = LPS27HHW_PULL_UP_CONNECT;
1246 break;
1247
1248 default:
1249 *val = LPS27HHW_PULL_UP_DISCONNECT;
1250 break;
1251 }
1252
1253 return ret;
1254 }
1255
1256 /**
1257 * @brief SPI Serial Interface Mode selection.[set]
1258 *
1259 * @param ctx read / write interface definitions
1260 * @param val change the values of sim in reg CTRL_REG1
1261 * @retval interface status (MANDATORY: return 0 -> no Error)
1262 *
1263 */
lps27hhw_spi_mode_set(const stmdev_ctx_t * ctx,lps27hhw_sim_t val)1264 int32_t lps27hhw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhw_sim_t val)
1265 {
1266 lps27hhw_ctrl_reg1_t reg;
1267 int32_t ret;
1268
1269 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
1270
1271 if (ret == 0)
1272 {
1273 reg.sim = (uint8_t)val;
1274 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
1275 }
1276
1277 return ret;
1278 }
1279
1280 /**
1281 * @brief SPI Serial Interface Mode selection.[get]
1282 *
1283 * @param ctx read / write interface definitions
1284 * @param val Get the values of sim in reg CTRL_REG1
1285 * @retval interface status (MANDATORY: return 0 -> no Error)
1286 *
1287 */
lps27hhw_spi_mode_get(const stmdev_ctx_t * ctx,lps27hhw_sim_t * val)1288 int32_t lps27hhw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhw_sim_t *val)
1289 {
1290 lps27hhw_ctrl_reg1_t reg;
1291 int32_t ret;
1292
1293 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1);
1294
1295 switch (reg.sim)
1296 {
1297 case LPS27HHW_SPI_4_WIRE:
1298 *val = LPS27HHW_SPI_4_WIRE;
1299 break;
1300
1301 case LPS27HHW_SPI_3_WIRE:
1302 *val = LPS27HHW_SPI_3_WIRE;
1303 break;
1304
1305 default:
1306 *val = LPS27HHW_SPI_4_WIRE;
1307 break;
1308 }
1309
1310 return ret;
1311 }
1312
1313 /**
1314 * @}
1315 *
1316 */
1317
1318 /**
1319 * @defgroup LPS27HHW_Interrupt_Pins
1320 * @brief This section groups all the functions that manage
1321 * interrupt pins.
1322 * @{
1323 *
1324 */
1325
1326 /**
1327 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
1328 *
1329 * @param ctx read / write interface definitions
1330 * @param val change the values of lir in reg INTERRUPT_CFG
1331 * @retval interface status (MANDATORY: return 0 -> no Error)
1332 *
1333 */
lps27hhw_int_notification_set(const stmdev_ctx_t * ctx,lps27hhw_lir_t val)1334 int32_t lps27hhw_int_notification_set(const stmdev_ctx_t *ctx,
1335 lps27hhw_lir_t val)
1336 {
1337 lps27hhw_interrupt_cfg_t reg;
1338 int32_t ret;
1339
1340 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
1341
1342 if (ret == 0)
1343 {
1344 reg.lir = (uint8_t)val;
1345 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
1346 (uint8_t *) ®, 1);
1347 }
1348
1349 return ret;
1350 }
1351
1352 /**
1353 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
1354 *
1355 * @param ctx read / write interface definitions
1356 * @param val Get the values of lir in reg INTERRUPT_CFG
1357 * @retval interface status (MANDATORY: return 0 -> no Error)
1358 *
1359 */
lps27hhw_int_notification_get(const stmdev_ctx_t * ctx,lps27hhw_lir_t * val)1360 int32_t lps27hhw_int_notification_get(const stmdev_ctx_t *ctx,
1361 lps27hhw_lir_t *val)
1362 {
1363 lps27hhw_interrupt_cfg_t reg;
1364 int32_t ret;
1365
1366 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
1367
1368 switch (reg.lir)
1369 {
1370 case LPS27HHW_INT_PULSED:
1371 *val = LPS27HHW_INT_PULSED;
1372 break;
1373
1374 case LPS27HHW_INT_LATCHED:
1375 *val = LPS27HHW_INT_LATCHED;
1376 break;
1377
1378 default:
1379 *val = LPS27HHW_INT_PULSED;
1380 break;
1381 }
1382
1383 return ret;
1384 }
1385
1386 /**
1387 * @brief Push-pull/open drain selection on interrupt pads.[set]
1388 *
1389 * @param ctx read / write interface definitions
1390 * @param val change the values of pp_od in reg CTRL_REG2
1391 * @retval interface status (MANDATORY: return 0 -> no Error)
1392 *
1393 */
lps27hhw_pin_mode_set(const stmdev_ctx_t * ctx,lps27hhw_pp_od_t val)1394 int32_t lps27hhw_pin_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pp_od_t val)
1395 {
1396 lps27hhw_ctrl_reg2_t reg;
1397 int32_t ret;
1398
1399 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1400
1401 if (ret == 0)
1402 {
1403 reg.pp_od = (uint8_t)val;
1404 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1405 }
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Push-pull/open drain selection on interrupt pads.[get]
1412 *
1413 * @param ctx read / write interface definitions
1414 * @param val Get the values of pp_od in reg CTRL_REG2
1415 * @retval interface status (MANDATORY: return 0 -> no Error)
1416 *
1417 */
lps27hhw_pin_mode_get(const stmdev_ctx_t * ctx,lps27hhw_pp_od_t * val)1418 int32_t lps27hhw_pin_mode_get(const stmdev_ctx_t *ctx,
1419 lps27hhw_pp_od_t *val)
1420 {
1421 lps27hhw_ctrl_reg2_t reg;
1422 int32_t ret;
1423
1424 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1425
1426 switch (reg.pp_od)
1427 {
1428 case LPS27HHW_PUSH_PULL:
1429 *val = LPS27HHW_PUSH_PULL;
1430 break;
1431
1432 case LPS27HHW_OPEN_DRAIN:
1433 *val = LPS27HHW_OPEN_DRAIN;
1434 break;
1435
1436 default:
1437 *val = LPS27HHW_PUSH_PULL;
1438 break;
1439 }
1440
1441 return ret;
1442 }
1443
1444 /**
1445 * @brief Interrupt active-high/low.[set]
1446 *
1447 * @param ctx read / write interface definitions
1448 * @param val change the values of int_h_l in reg CTRL_REG2
1449 * @retval interface status (MANDATORY: return 0 -> no Error)
1450 *
1451 */
lps27hhw_pin_polarity_set(const stmdev_ctx_t * ctx,lps27hhw_int_h_l_t val)1452 int32_t lps27hhw_pin_polarity_set(const stmdev_ctx_t *ctx,
1453 lps27hhw_int_h_l_t val)
1454 {
1455 lps27hhw_ctrl_reg2_t reg;
1456 int32_t ret;
1457
1458 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1459
1460 if (ret == 0)
1461 {
1462 reg.int_h_l = (uint8_t)val;
1463 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1464 }
1465
1466 return ret;
1467 }
1468
1469 /**
1470 * @brief Interrupt active-high/low.[get]
1471 *
1472 * @param ctx read / write interface definitions
1473 * @param val Get the values of int_h_l in reg CTRL_REG2
1474 * @retval interface status (MANDATORY: return 0 -> no Error)
1475 *
1476 */
lps27hhw_pin_polarity_get(const stmdev_ctx_t * ctx,lps27hhw_int_h_l_t * val)1477 int32_t lps27hhw_pin_polarity_get(const stmdev_ctx_t *ctx,
1478 lps27hhw_int_h_l_t *val)
1479 {
1480 lps27hhw_ctrl_reg2_t reg;
1481 int32_t ret;
1482
1483 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1);
1484
1485 switch (reg.int_h_l)
1486 {
1487 case LPS27HHW_ACTIVE_HIGH:
1488 *val = LPS27HHW_ACTIVE_HIGH;
1489 break;
1490
1491 case LPS27HHW_ACTIVE_LOW:
1492 *val = LPS27HHW_ACTIVE_LOW;
1493 break;
1494
1495 default:
1496 *val = LPS27HHW_ACTIVE_HIGH;
1497 break;
1498 }
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * @brief Select the signal that need to route on int pad.[set]
1505 *
1506 * @param ctx read / write interface definitions
1507 * @param val registers CTRL_REG3
1508 * @retval interface status (MANDATORY: return 0 -> no Error)
1509 *
1510 */
lps27hhw_pin_int_route_set(const stmdev_ctx_t * ctx,lps27hhw_ctrl_reg3_t * val)1511 int32_t lps27hhw_pin_int_route_set(const stmdev_ctx_t *ctx,
1512 lps27hhw_ctrl_reg3_t *val)
1513 {
1514 int32_t ret;
1515
1516 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *) val, 1);
1517
1518 return ret;
1519 }
1520
1521 /**
1522 * @brief Select the signal that need to route on int pad.[get]
1523 *
1524 * @param ctx read / write interface definitions
1525 * @param val registers CTRL_REG3
1526 * @retval interface status (MANDATORY: return 0 -> no Error)
1527 *
1528 */
lps27hhw_pin_int_route_get(const stmdev_ctx_t * ctx,lps27hhw_ctrl_reg3_t * val)1529 int32_t lps27hhw_pin_int_route_get(const stmdev_ctx_t *ctx,
1530 lps27hhw_ctrl_reg3_t *val)
1531 {
1532 int32_t ret;
1533
1534 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *) val, 1);
1535
1536 return ret;
1537 }
1538
1539 /**
1540 * @}
1541 *
1542 */
1543
1544 /**
1545 * @defgroup LPS27HHW_Interrupt_on_Threshold
1546 * @brief This section groups all the functions that manage the
1547 * interrupt on threshold event generation.
1548 * @{
1549 *
1550 */
1551
1552 /**
1553 * @brief Enable interrupt generation on pressure low/high event.[set]
1554 *
1555 * @param ctx read / write interface definitions
1556 * @param val change the values of pe in reg INTERRUPT_CFG
1557 * @retval interface status (MANDATORY: return 0 -> no Error)
1558 *
1559 */
lps27hhw_int_on_threshold_set(const stmdev_ctx_t * ctx,lps27hhw_pe_t val)1560 int32_t lps27hhw_int_on_threshold_set(const stmdev_ctx_t *ctx,
1561 lps27hhw_pe_t val)
1562 {
1563 lps27hhw_interrupt_cfg_t reg;
1564 int32_t ret;
1565
1566 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
1567
1568 if (ret == 0)
1569 {
1570 reg.pe = (uint8_t)val;
1571
1572 if (val == LPS27HHW_NO_THRESHOLD)
1573 {
1574 reg.diff_en = PROPERTY_DISABLE;
1575 }
1576
1577 else
1578 {
1579 reg.diff_en = PROPERTY_ENABLE;
1580 }
1581
1582 ret = lps27hhw_write_reg(ctx, LPS27HHW_INTERRUPT_CFG,
1583 (uint8_t *) ®, 1);
1584 }
1585
1586 return ret;
1587 }
1588
1589 /**
1590 * @brief Enable interrupt generation on pressure low/high event.[get]
1591 *
1592 * @param ctx read / write interface definitions
1593 * @param val Get the values of pe in reg INTERRUPT_CFG
1594 * @retval interface status (MANDATORY: return 0 -> no Error)
1595 *
1596 */
lps27hhw_int_on_threshold_get(const stmdev_ctx_t * ctx,lps27hhw_pe_t * val)1597 int32_t lps27hhw_int_on_threshold_get(const stmdev_ctx_t *ctx,
1598 lps27hhw_pe_t *val)
1599 {
1600 lps27hhw_interrupt_cfg_t reg;
1601 int32_t ret;
1602
1603 ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1);
1604
1605 switch (reg.pe)
1606 {
1607 case LPS27HHW_NO_THRESHOLD:
1608 *val = LPS27HHW_NO_THRESHOLD;
1609 break;
1610
1611 case LPS27HHW_POSITIVE:
1612 *val = LPS27HHW_POSITIVE;
1613 break;
1614
1615 case LPS27HHW_NEGATIVE:
1616 *val = LPS27HHW_NEGATIVE;
1617 break;
1618
1619 case LPS27HHW_BOTH:
1620 *val = LPS27HHW_BOTH;
1621 break;
1622
1623 default:
1624 *val = LPS27HHW_NO_THRESHOLD;
1625 break;
1626 }
1627
1628 return ret;
1629 }
1630
1631 /**
1632 * @brief User-defined threshold value for pressure interrupt event.[set]
1633 *
1634 * @param ctx read / write interface definitions
1635 * @param buff buffer that contains data to write
1636 * @retval interface status (MANDATORY: return 0 -> no Error)
1637 *
1638 */
lps27hhw_int_threshold_set(const stmdev_ctx_t * ctx,uint16_t buff)1639 int32_t lps27hhw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff)
1640 {
1641 int32_t ret;
1642
1643 lps27hhw_ths_p_l_t ths_p_l;
1644 lps27hhw_ths_p_h_t ths_p_h;
1645 ths_p_l.ths = (uint8_t)(buff & 0x00FFU);
1646 ths_p_h.ths = (uint8_t)((buff & 0x7F00U) >> 8);
1647 ret = lps27hhw_write_reg(ctx, LPS27HHW_THS_P_L,
1648 (uint8_t *)&ths_p_l, 1);
1649
1650 if (ret == 0)
1651 {
1652 ret = lps27hhw_write_reg(ctx, LPS27HHW_THS_P_H,
1653 (uint8_t *)&ths_p_h, 1);
1654 }
1655
1656 return ret;
1657 }
1658
1659 /**
1660 * @brief User-defined threshold value for pressure interrupt event.[get]
1661 *
1662 * @param ctx read / write interface definitions
1663 * @param buff buffer that stores data read
1664 * @retval interface status (MANDATORY: return 0 -> no Error)
1665 *
1666 */
lps27hhw_int_threshold_get(const stmdev_ctx_t * ctx,uint16_t * buff)1667 int32_t lps27hhw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff)
1668 {
1669 int32_t ret;
1670
1671 lps27hhw_ths_p_l_t ths_p_l;
1672 lps27hhw_ths_p_h_t ths_p_h;
1673 ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_L,
1674 (uint8_t *)&ths_p_l, 1);
1675
1676 if (ret == 0)
1677 {
1678 ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_H,
1679 (uint8_t *)&ths_p_h, 1);
1680 *buff = (uint16_t)ths_p_h.ths << 8;
1681 *buff |= (uint16_t)ths_p_l.ths;
1682 }
1683
1684 return ret;
1685 }
1686
1687 /**
1688 * @}
1689 *
1690 */
1691
1692 /**
1693 * @defgroup LPS27HHW_Fifo
1694 * @brief This section group all the functions concerning the fifo usage.
1695 * @{
1696 *
1697 */
1698
1699 /**
1700 * @brief Fifo Mode selection.[set]
1701 *
1702 * @param ctx read / write interface definitions
1703 * @param val change the values of f_mode in reg FIFO_CTRL
1704 * @retval interface status (MANDATORY: return 0 -> no Error)
1705 *
1706 */
lps27hhw_fifo_mode_set(const stmdev_ctx_t * ctx,lps27hhw_f_mode_t val)1707 int32_t lps27hhw_fifo_mode_set(const stmdev_ctx_t *ctx,
1708 lps27hhw_f_mode_t val)
1709 {
1710 lps27hhw_fifo_ctrl_t reg;
1711 int32_t ret;
1712
1713 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1714
1715 if (ret == 0)
1716 {
1717 reg.f_mode = (uint8_t)val;
1718 ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1719 }
1720
1721 return ret;
1722 }
1723
1724 /**
1725 * @brief Fifo Mode selection.[get]
1726 *
1727 * @param ctx read / write interface definitions
1728 * @param val Get the values of f_mode in reg FIFO_CTRL
1729 * @retval interface status (MANDATORY: return 0 -> no Error)
1730 *
1731 */
lps27hhw_fifo_mode_get(const stmdev_ctx_t * ctx,lps27hhw_f_mode_t * val)1732 int32_t lps27hhw_fifo_mode_get(const stmdev_ctx_t *ctx,
1733 lps27hhw_f_mode_t *val)
1734 {
1735 lps27hhw_fifo_ctrl_t reg;
1736 int32_t ret;
1737
1738 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1739
1740 switch (reg.f_mode)
1741 {
1742 case LPS27HHW_BYPASS_MODE:
1743 *val = LPS27HHW_BYPASS_MODE;
1744 break;
1745
1746 case LPS27HHW_FIFO_MODE:
1747 *val = LPS27HHW_FIFO_MODE;
1748 break;
1749
1750 case LPS27HHW_STREAM_MODE:
1751 *val = LPS27HHW_STREAM_MODE;
1752 break;
1753
1754 case LPS27HHW_DYNAMIC_STREAM_MODE:
1755 *val = LPS27HHW_DYNAMIC_STREAM_MODE;
1756 break;
1757
1758 case LPS27HHW_BYPASS_TO_FIFO_MODE:
1759 *val = LPS27HHW_BYPASS_TO_FIFO_MODE;
1760 break;
1761
1762 case LPS27HHW_BYPASS_TO_STREAM_MODE:
1763 *val = LPS27HHW_BYPASS_TO_STREAM_MODE;
1764 break;
1765
1766 case LPS27HHW_STREAM_TO_FIFO_MODE:
1767 *val = LPS27HHW_STREAM_TO_FIFO_MODE;
1768 break;
1769
1770 default:
1771 *val = LPS27HHW_BYPASS_MODE;
1772 break;
1773 }
1774
1775 return ret;
1776 }
1777
1778 /**
1779 * @brief Sensing chain FIFO stop values memorization at
1780 * threshold level.[set]
1781 *
1782 * @param ctx read / write interface definitions
1783 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1784 * @retval interface status (MANDATORY: return 0 -> no Error)
1785 *
1786 */
lps27hhw_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)1787 int32_t lps27hhw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
1788 {
1789 lps27hhw_fifo_ctrl_t reg;
1790 int32_t ret;
1791
1792 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1793
1794 if (ret == 0)
1795 {
1796 reg.stop_on_wtm = val;
1797 ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1798 }
1799
1800 return ret;
1801 }
1802
1803 /**
1804 * @brief Sensing chain FIFO stop values memorization at threshold
1805 * level.[get]
1806 *
1807 * @param ctx read / write interface definitions
1808 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1809 * @retval interface status (MANDATORY: return 0 -> no Error)
1810 *
1811 */
lps27hhw_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)1812 int32_t lps27hhw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
1813 {
1814 lps27hhw_fifo_ctrl_t reg;
1815 int32_t ret;
1816
1817 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1);
1818 *val = reg.stop_on_wtm;
1819
1820 return ret;
1821 }
1822
1823 /**
1824 * @brief FIFO watermark level selection.[set]
1825 *
1826 * @param ctx read / write interface definitions
1827 * @param val change the values of wtm in reg FIFO_WTM
1828 * @retval interface status (MANDATORY: return 0 -> no Error)
1829 *
1830 */
lps27hhw_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1831 int32_t lps27hhw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1832 {
1833 lps27hhw_fifo_wtm_t reg;
1834 int32_t ret;
1835
1836 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
1837
1838 if (ret == 0)
1839 {
1840 reg.wtm = val;
1841 ret = lps27hhw_write_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
1842 }
1843
1844 return ret;
1845 }
1846
1847 /**
1848 * @brief FIFO watermark level selection.[get]
1849 *
1850 * @param ctx read / write interface definitions
1851 * @param val change the values of wtm in reg FIFO_WTM
1852 * @retval interface status (MANDATORY: return 0 -> no Error)
1853 *
1854 */
lps27hhw_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1855 int32_t lps27hhw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1856 {
1857 lps27hhw_fifo_wtm_t reg;
1858 int32_t ret;
1859
1860 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1);
1861 *val = reg.wtm;
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief FIFO stored data level.[get]
1868 *
1869 * @param ctx read / write interface definitions
1870 * @param buff buffer that stores data read
1871 * @retval interface status (MANDATORY: return 0 -> no Error)
1872 *
1873 */
lps27hhw_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * buff)1874 int32_t lps27hhw_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1875 {
1876 int32_t ret;
1877
1878 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS1, buff, 1);
1879
1880 return ret;
1881 }
1882
1883 /**
1884 * @brief Read all the FIFO status flag of the device.[get]
1885 *
1886 * @param ctx read / write interface definitions
1887 * @param val registers FIFO_STATUS2
1888 * @retval interface status (MANDATORY: return 0 -> no Error)
1889 *
1890 */
lps27hhw_fifo_src_get(const stmdev_ctx_t * ctx,lps27hhw_fifo_status2_t * val)1891 int32_t lps27hhw_fifo_src_get(const stmdev_ctx_t *ctx,
1892 lps27hhw_fifo_status2_t *val)
1893 {
1894 int32_t ret;
1895
1896 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) val, 1);
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @brief Smart FIFO full status.[get]
1903 *
1904 * @param ctx read / write interface definitions
1905 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
1906 * @retval interface status (MANDATORY: return 0 -> no Error)
1907 *
1908 */
lps27hhw_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1909 int32_t lps27hhw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1910 {
1911 lps27hhw_fifo_status2_t reg;
1912 int32_t ret;
1913
1914 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1);
1915 *val = reg.fifo_full_ia;
1916
1917 return ret;
1918 }
1919
1920 /**
1921 * @brief FIFO overrun status.[get]
1922 *
1923 * @param ctx read / write interface definitions
1924 * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
1925 * @retval interface status (MANDATORY: return 0 -> no Error)
1926 *
1927 */
lps27hhw_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1928 int32_t lps27hhw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1929 {
1930 lps27hhw_fifo_status2_t reg;
1931 int32_t ret;
1932
1933 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1);
1934 *val = reg.fifo_ovr_ia;
1935
1936 return ret;
1937 }
1938
1939 /**
1940 * @brief FIFO watermark status.[get]
1941 *
1942 * @param ctx read / write interface definitions
1943 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
1944 * @retval interface status (MANDATORY: return 0 -> no Error)
1945 *
1946 */
lps27hhw_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1947 int32_t lps27hhw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1948 {
1949 lps27hhw_fifo_status2_t reg;
1950 int32_t ret;
1951
1952 ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *)®, 1);
1953 *val = reg.fifo_wtm_ia;
1954
1955 return ret;
1956 }
1957
1958 /**
1959 * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
1960 *
1961 * @param stmdev_ctx_t *ctx: read / write interface definitions
1962 * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
1963 * @retval interface status (MANDATORY: return 0 -> no Error)
1964 *
1965 */
lps27hhw_fifo_ovr_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)1966 int32_t lps27hhw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
1967 {
1968 lps27hhw_ctrl_reg3_t reg;
1969 int32_t ret;
1970
1971 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
1972
1973 if (ret == 0)
1974 {
1975 reg.int_f_ovr = val;
1976 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
1977 }
1978
1979 return ret;
1980 }
1981
1982 /**
1983 * @brief FIFO overrun interrupt on INT_DRDY pin.[get]
1984 *
1985 * @param stmdev_ctx_t *ctx: read / write interface definitions
1986 * @param uint8_t: change the values of f_ovr in reg CTRL_REG3
1987 * @retval interface status (MANDATORY: return 0 -> no Error)
1988 *
1989 */
lps27hhw_fifo_ovr_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)1990 int32_t lps27hhw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val)
1991 {
1992 lps27hhw_ctrl_reg3_t reg;
1993 int32_t ret;
1994
1995 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
1996 *val = reg.int_f_ovr;
1997
1998 return ret;
1999 }
2000
2001 /**
2002 * @brief FIFO watermark status on INT_DRDY pin.[set]
2003 *
2004 * @param stmdev_ctx_t *ctx: read / write interface definitions
2005 * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
2006 * @retval interface status (MANDATORY: return 0 -> no Error)
2007 *
2008 */
lps27hhw_fifo_threshold_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)2009 int32_t lps27hhw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx,
2010 uint8_t val)
2011 {
2012 lps27hhw_ctrl_reg3_t reg;
2013 int32_t ret;
2014
2015 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2016
2017 if (ret == 0)
2018 {
2019 reg.int_f_wtm = val;
2020 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2021 }
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @brief FIFO watermark status on INT_DRDY pin.[get]
2028 *
2029 * @param lps22hb_ctx_t *ctx: read / write interface definitions
2030 * @param uint8_t: change the values of f_fth in reg CTRL_REG3
2031 * @retval interface status (MANDATORY: return 0 -> no Error)
2032 *
2033 */
lps27hhw_fifo_threshold_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2034 int32_t lps27hhw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx,
2035 uint8_t *val)
2036 {
2037 lps27hhw_ctrl_reg3_t reg;
2038 int32_t ret;
2039
2040 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2041 *val = reg.int_f_wtm;
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @brief FIFO full flag on INT_DRDY pin.[set]
2048 *
2049 * @param stmdev_ctx_t *ctx: read / write interface definitions
2050 * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
2051 * @retval interface status (MANDATORY: return 0 -> no Error)
2052 *
2053 */
lps27hhw_fifo_full_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)2054 int32_t lps27hhw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
2055 {
2056 lps27hhw_ctrl_reg3_t reg;
2057 int32_t ret;
2058
2059 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2060
2061 if (ret == 0)
2062 {
2063 reg.int_f_full = val;
2064 ret = lps27hhw_write_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2065 }
2066
2067 return ret;
2068 }
2069
2070 /**
2071 * @brief FIFO full flag on INT_DRDY pin.[get]
2072 *
2073 * @param stmdev_ctx_t *ctx: read / write interface definitions
2074 * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
2075 * @retval interface status (MANDATORY: return 0 -> no Error)
2076 *
2077 */
lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2078 int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val)
2079 {
2080 lps27hhw_ctrl_reg3_t reg;
2081 int32_t ret;
2082
2083 ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1);
2084 *val = reg.int_f_full;
2085
2086 return ret;
2087 }
2088
2089 /**
2090 * @}
2091 *
2092 */
2093
2094 /**
2095 * @}
2096 *
2097 */
2098
2099 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2100
