1 /**
2 ******************************************************************************
3 * @file lps27hhtw_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS27HHTW driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps27hhtw_reg.h"
21
22 /**
23 * @defgroup LPS27HHTW
24 * @brief This file provides a set of functions needed to drive the
25 * lps27hhtw enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LPS27HHTW_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps27hhtw_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps27hhtw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lps27hhtw_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lps27hhtw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LPS27HHTW_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
lps27hhtw_from_lsb_to_hpa(int32_t lsb)102 float_t lps27hhtw_from_lsb_to_hpa(int32_t lsb)
103 {
104 return ((float_t) lsb / 1048576.0f);
105 }
106
lps27hhtw_from_lsb_to_celsius(int16_t lsb)107 float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb)
108 {
109 return ((float_t) lsb / 100.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup LPS27HHTW_Data_Generation
119 * @brief This section groups all the functions concerning
120 * data generation.
121 * @{
122 *
123 */
124
125 /**
126 * @brief Reset Autozero function.[set]
127 *
128 * @param ctx read / write interface definitions
129 * @param val change the values of reset_az in reg INTERRUPT_CFG
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
lps27hhtw_autozero_rst_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t lps27hhtw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 lps27hhtw_interrupt_cfg_t reg;
136 int32_t ret;
137
138 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
139 (uint8_t *) ®, 1);
140
141 if (ret == 0)
142 {
143 reg.reset_az = val;
144 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
145 (uint8_t *) ®, 1);
146 }
147
148 return ret;
149 }
150
151 /**
152 * @brief Reset Autozero function.[get]
153 *
154 * @param ctx read / write interface definitions
155 * @param val change the values of reset_az in reg INTERRUPT_CFG
156 * @retval interface status (MANDATORY: return 0 -> no Error)
157 *
158 */
lps27hhtw_autozero_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)159 int32_t lps27hhtw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
160 {
161 lps27hhtw_interrupt_cfg_t reg;
162 int32_t ret;
163
164 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
165 (uint8_t *) ®, 1);
166 *val = reg.reset_az;
167
168 return ret;
169 }
170
171 /**
172 * @brief Enable Autozero function.[set]
173 *
174 * @param ctx read / write interface definitions
175 * @param val change the values of autozero in reg INTERRUPT_CFG
176 * @retval interface status (MANDATORY: return 0 -> no Error)
177 *
178 */
lps27hhtw_autozero_set(const stmdev_ctx_t * ctx,uint8_t val)179 int32_t lps27hhtw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val)
180 {
181 lps27hhtw_interrupt_cfg_t reg;
182 int32_t ret;
183
184 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
185 (uint8_t *) ®, 1);
186
187 if (ret == 0)
188 {
189 reg.autozero = val;
190 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
191 (uint8_t *) ®, 1);
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief Enable Autozero function.[get]
199 *
200 * @param ctx read / write interface definitions
201 * @param val change the values of autozero in reg INTERRUPT_CFG
202 * @retval interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
lps27hhtw_autozero_get(const stmdev_ctx_t * ctx,uint8_t * val)205 int32_t lps27hhtw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val)
206 {
207 lps27hhtw_interrupt_cfg_t reg;
208 int32_t ret;
209
210 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
211 (uint8_t *) ®, 1);
212 *val = reg.autozero;
213
214 return ret;
215 }
216
217 /**
218 * @brief Reset AutoRifP function.[set]
219 *
220 * @param ctx read / write interface definitions
221 * @param val change the values of reset_arp in reg INTERRUPT_CFG
222 * @retval interface status (MANDATORY: return 0 -> no Error)
223 *
224 */
lps27hhtw_pressure_snap_rst_set(const stmdev_ctx_t * ctx,uint8_t val)225 int32_t lps27hhtw_pressure_snap_rst_set(const stmdev_ctx_t *ctx,
226 uint8_t val)
227 {
228 lps27hhtw_interrupt_cfg_t reg;
229 int32_t ret;
230
231 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
232 (uint8_t *) ®, 1);
233
234 if (ret == 0)
235 {
236 reg.reset_arp = val;
237 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
238 (uint8_t *) ®, 1);
239 }
240
241 return ret;
242 }
243
244 /**
245 * @brief Reset AutoRifP function.[get]
246 *
247 * @param ctx read / write interface definitions
248 * @param val change the values of reset_arp in reg INTERRUPT_CFG
249 * @retval interface status (MANDATORY: return 0 -> no Error)
250 *
251 */
lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)252 int32_t lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t *ctx,
253 uint8_t *val)
254 {
255 lps27hhtw_interrupt_cfg_t reg;
256 int32_t ret;
257
258 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
259 (uint8_t *) ®, 1);
260 *val = reg.reset_arp;
261
262 return ret;
263 }
264
265 /**
266 * @brief Enable AutoRefP function.[set]
267 *
268 * @param ctx read / write interface definitions
269 * @param val change the values of autorefp in reg INTERRUPT_CFG
270 * @retval interface status (MANDATORY: return 0 -> no Error)
271 *
272 */
lps27hhtw_pressure_snap_set(const stmdev_ctx_t * ctx,uint8_t val)273 int32_t lps27hhtw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val)
274 {
275 lps27hhtw_interrupt_cfg_t reg;
276 int32_t ret;
277
278 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
279 (uint8_t *) ®, 1);
280
281 if (ret == 0)
282 {
283 reg.autorefp = val;
284 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
285 (uint8_t *) ®, 1);
286 }
287
288 return ret;
289 }
290
291 /**
292 * @brief Enable AutoRefP function.[get]
293 *
294 * @param ctx read / write interface definitions
295 * @param val change the values of autorefp in reg INTERRUPT_CFG
296 * @retval interface status (MANDATORY: return 0 -> no Error)
297 *
298 */
lps27hhtw_pressure_snap_get(const stmdev_ctx_t * ctx,uint8_t * val)299 int32_t lps27hhtw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val)
300 {
301 lps27hhtw_interrupt_cfg_t reg;
302 int32_t ret;
303
304 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
305 (uint8_t *) ®, 1);
306 *val = reg.autorefp;
307
308 return ret;
309 }
310
311 /**
312 * @brief Block Data Update.[set]
313 *
314 * @param ctx read / write interface definitions
315 * @param val change the values of bdu in reg CTRL_REG1
316 * @retval interface status (MANDATORY: return 0 -> no Error)
317 *
318 */
lps27hhtw_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)319 int32_t lps27hhtw_block_data_update_set(const stmdev_ctx_t *ctx,
320 uint8_t val)
321 {
322 lps27hhtw_ctrl_reg1_t reg;
323 int32_t ret;
324
325 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
326
327 if (ret == 0)
328 {
329 reg.bdu = val;
330 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
331 }
332
333 return ret;
334 }
335
336 /**
337 * @brief Block Data Update.[get]
338 *
339 * @param ctx read / write interface definitions
340 * @param val change the values of bdu in reg CTRL_REG1
341 * @retval interface status (MANDATORY: return 0 -> no Error)
342 *
343 */
lps27hhtw_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)344 int32_t lps27hhtw_block_data_update_get(const stmdev_ctx_t *ctx,
345 uint8_t *val)
346 {
347 lps27hhtw_ctrl_reg1_t reg;
348 int32_t ret;
349
350 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
351 *val = reg.bdu;
352
353 return ret;
354 }
355
356 /**
357 * @brief Output data rate selection.[set]
358 *
359 * @param ctx read / write interface definitions
360 * @param val change the values of odr in reg CTRL_REG1
361 * @retval interface status (MANDATORY: return 0 -> no Error)
362 *
363 */
lps27hhtw_data_rate_set(const stmdev_ctx_t * ctx,lps27hhtw_odr_t val)364 int32_t lps27hhtw_data_rate_set(const stmdev_ctx_t *ctx,
365 lps27hhtw_odr_t val)
366 {
367 lps27hhtw_ctrl_reg1_t ctrl_reg1;
368 lps27hhtw_ctrl_reg2_t ctrl_reg2;
369 int32_t ret;
370
371 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1,
372 (uint8_t *)&ctrl_reg1, 1);
373
374 if (ret == 0)
375 {
376 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
377 (uint8_t *)&ctrl_reg2, 1);
378 }
379
380 if (ret == 0)
381 {
382 ctrl_reg1.odr = (uint8_t)val & 0x07U;
383 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1,
384 (uint8_t *)&ctrl_reg1, 1);
385 }
386
387 if (ret == 0)
388 {
389 ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
390 ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
391 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2,
392 (uint8_t *)&ctrl_reg2, 1);
393 }
394
395 return ret;
396 }
397
398 /**
399 * @brief Output data rate selection.[get]
400 *
401 * @param ctx read / write interface definitions
402 * @param val Get the values of odr in reg CTRL_REG1
403 * @retval interface status (MANDATORY: return 0 -> no Error)
404 *
405 */
lps27hhtw_data_rate_get(const stmdev_ctx_t * ctx,lps27hhtw_odr_t * val)406 int32_t lps27hhtw_data_rate_get(const stmdev_ctx_t *ctx,
407 lps27hhtw_odr_t *val)
408 {
409 lps27hhtw_ctrl_reg1_t ctrl_reg1;
410 lps27hhtw_ctrl_reg2_t ctrl_reg2;
411 int32_t ret;
412
413 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1,
414 (uint8_t *)&ctrl_reg1, 1);
415
416 if (ret == 0)
417 {
418 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
419 (uint8_t *)&ctrl_reg2, 1);
420 }
421
422 if (ret == 0)
423 {
424 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2,
425 (uint8_t *)&ctrl_reg2, 1);
426
427 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
428 ctrl_reg1.odr))
429 {
430 case LPS27HHTW_POWER_DOWN:
431 *val = LPS27HHTW_POWER_DOWN;
432 break;
433
434 case LPS27HHTW_ONE_SHOOT:
435 *val = LPS27HHTW_ONE_SHOOT;
436 break;
437
438 case LPS27HHTW_1_Hz:
439 *val = LPS27HHTW_1_Hz;
440 break;
441
442 case LPS27HHTW_10_Hz:
443 *val = LPS27HHTW_10_Hz;
444 break;
445
446 case LPS27HHTW_25_Hz:
447 *val = LPS27HHTW_25_Hz;
448 break;
449
450 case LPS27HHTW_50_Hz:
451 *val = LPS27HHTW_50_Hz;
452 break;
453
454 case LPS27HHTW_75_Hz:
455 *val = LPS27HHTW_75_Hz;
456 break;
457
458 case LPS27HHTW_1_Hz_LOW_NOISE:
459 *val = LPS27HHTW_1_Hz_LOW_NOISE;
460 break;
461
462 case LPS27HHTW_10_Hz_LOW_NOISE:
463 *val = LPS27HHTW_10_Hz_LOW_NOISE;
464 break;
465
466 case LPS27HHTW_25_Hz_LOW_NOISE:
467 *val = LPS27HHTW_25_Hz_LOW_NOISE;
468 break;
469
470 case LPS27HHTW_50_Hz_LOW_NOISE:
471 *val = LPS27HHTW_50_Hz_LOW_NOISE;
472 break;
473
474 case LPS27HHTW_75_Hz_LOW_NOISE:
475 *val = LPS27HHTW_75_Hz_LOW_NOISE;
476 break;
477
478 case LPS27HHTW_100_Hz:
479 *val = LPS27HHTW_100_Hz;
480 break;
481
482 case LPS27HHTW_200_Hz:
483 *val = LPS27HHTW_200_Hz;
484 break;
485
486 default:
487 *val = LPS27HHTW_POWER_DOWN;
488 break;
489 }
490 }
491
492 return ret;
493 }
494
495 /**
496 * @brief The Reference pressure value is a 16-bit data
497 * expressed as 2’s complement. The value is used
498 * when AUTOZERO or AUTORIFP function is enabled.[set]
499 *
500 * @param ctx read / write interface definitions
501 * @param buff buffer that contains data to write
502 * @retval interface status (MANDATORY: return 0 -> no Error)
503 *
504 */
lps27hhtw_pressure_ref_set(const stmdev_ctx_t * ctx,int16_t val)505 int32_t lps27hhtw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val)
506 {
507 uint8_t buff[2];
508 int32_t ret;
509
510 buff[1] = (uint8_t)((uint16_t)val / 256U);
511 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
512 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_REF_P_L, buff, 2);
513
514 return ret;
515 }
516
517 /**
518 * @brief The Reference pressure value is a 16-bit
519 * data expressed as 2’s complement.
520 * The value is used when AUTOZERO or AUTORIFP
521 * function is enabled.[get]
522 *
523 * @param ctx read / write interface definitions
524 * @param buff buffer that stores data read
525 * @retval interface status (MANDATORY: return 0 -> no Error)
526 *
527 */
lps27hhtw_pressure_ref_get(const stmdev_ctx_t * ctx,int16_t * val)528 int32_t lps27hhtw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val)
529 {
530 uint8_t buff[2];
531 int32_t ret;
532
533 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_REF_P_L, buff, 2);
534 *val = (int16_t)buff[1];
535 *val = (*val * 256) + (int16_t)buff[0];
536
537 return ret;
538 }
539
540 /**
541 * @brief The pressure offset value is 16-bit data
542 * that can be used to implement one-point
543 * calibration (OPC) after soldering.[set]
544 *
545 * @param ctx read / write interface definitions
546 * @param buff buffer that contains data to write
547 * @retval interface status (MANDATORY: return 0 -> no Error)
548 *
549 */
lps27hhtw_pressure_offset_set(const stmdev_ctx_t * ctx,int16_t val)550 int32_t lps27hhtw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val)
551 {
552 uint8_t buff[2];
553 int32_t ret;
554
555 buff[1] = (uint8_t)((uint16_t)val / 256U);
556 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
557 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_RPDS_L, buff, 2);
558
559 return ret;
560 }
561
562 /**
563 * @brief The pressure offset value is 16-bit
564 * data that can be used to implement
565 * one-point calibration (OPC) after
566 * soldering.[get]
567 *
568 * @param ctx read / write interface definitions
569 * @param buff buffer that stores data read
570 * @retval interface status (MANDATORY: return 0 -> no Error)
571 *
572 */
lps27hhtw_pressure_offset_get(const stmdev_ctx_t * ctx,int16_t * val)573 int32_t lps27hhtw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
574 {
575 uint8_t buff[2];
576 int32_t ret;
577
578 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_RPDS_L, buff, 2);
579 *val = (int16_t)buff[1];
580 *val = (*val * 256) + (int16_t)buff[0];
581
582 return ret;
583 }
584
585 /**
586 * @brief Read all the interrupt/status flag of the device.[get]
587 *
588 * @param ctx read / write interface definitions
589 * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
590 * @retval interface status (MANDATORY: return 0 -> no Error)
591 *
592 */
lps27hhtw_all_sources_get(const stmdev_ctx_t * ctx,lps27hhtw_all_sources_t * val)593 int32_t lps27hhtw_all_sources_get(const stmdev_ctx_t *ctx,
594 lps27hhtw_all_sources_t *val)
595 {
596 int32_t ret;
597
598 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INT_SOURCE,
599 (uint8_t *) & (val->int_source), 1);
600
601 if (ret == 0)
602 {
603 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
604 (uint8_t *) & (val->fifo_status2), 1);
605 }
606
607 if (ret == 0)
608 {
609 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS,
610 (uint8_t *) & (val->status), 1);
611 }
612
613 return ret;
614 }
615
616 /**
617 * @brief The STATUS_REG register is read by the primary interface.[get]
618 *
619 * @param ctx read / write interface definitions
620 * @param val structure of registers from STATUS to STATUS_REG
621 * @retval interface status (MANDATORY: return 0 -> no Error)
622 *
623 */
lps27hhtw_status_reg_get(const stmdev_ctx_t * ctx,lps27hhtw_status_t * val)624 int32_t lps27hhtw_status_reg_get(const stmdev_ctx_t *ctx,
625 lps27hhtw_status_t *val)
626 {
627 int32_t ret;
628
629 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) val, 1);
630
631 return ret;
632 }
633
634 /**
635 * @brief Pressure new data available.[get]
636 *
637 * @param ctx read / write interface definitions
638 * @param val change the values of p_da in reg STATUS
639 * @retval interface status (MANDATORY: return 0 -> no Error)
640 *
641 */
lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)642 int32_t lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t *ctx,
643 uint8_t *val)
644 {
645 lps27hhtw_status_t reg;
646 int32_t ret;
647
648 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1);
649 *val = reg.p_da;
650
651 return ret;
652 }
653
654 /**
655 * @brief Temperature data available.[get]
656 *
657 * @param ctx read / write interface definitions
658 * @param val change the values of t_da in reg STATUS
659 * @retval interface status (MANDATORY: return 0 -> no Error)
660 *
661 */
lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)662 int32_t lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
663 uint8_t *val)
664 {
665 lps27hhtw_status_t reg;
666 int32_t ret;
667
668 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1);
669 *val = reg.t_da;
670
671 return ret;
672 }
673
674 /**
675 * @}
676 *
677 */
678
679 /**
680 * @defgroup LPS27HHTW_Data_Output
681 * @brief This section groups all the data output functions.
682 * @{
683 *
684 */
685
686 /**
687 * @brief Pressure output value.[get]
688 *
689 * @param ctx read / write interface definitions
690 * @param buff buffer that stores data read
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
lps27hhtw_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)694 int32_t lps27hhtw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
695 {
696 uint8_t reg[3];
697 int32_t ret;
698
699 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_PRESS_OUT_XL, reg, 3);
700 *buff = reg[2];
701 *buff = (*buff * 256) + reg[1];
702 *buff = (*buff * 256) + reg[0];
703 *buff *= 256;
704
705 return ret;
706 }
707
708 /**
709 * @brief Temperature output value.[get]
710 *
711 * @param ctx read / write interface definitions
712 * @param buff buffer that stores data read
713 * @retval interface status (MANDATORY: return 0 -> no Error)
714 *
715 */
lps27hhtw_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)716 int32_t lps27hhtw_temperature_raw_get(const stmdev_ctx_t *ctx,
717 int16_t *buff)
718 {
719 uint8_t reg[2];
720 int32_t ret;
721
722 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_TEMP_OUT_L, reg, 2);
723 *buff = reg[1];
724 *buff = (*buff * 256) + reg[0];
725
726 return ret;
727 }
728
729 /**
730 * @brief Pressure output from FIFO value.[get]
731 *
732 * @param ctx read / write interface definitions
733 * @param buff buffer that stores data read
734 * @retval interface status (MANDATORY: return 0 -> no Error)
735 *
736 */
lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)737 int32_t lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx,
738 uint32_t *buff)
739 {
740 uint8_t reg[3];
741 int32_t ret;
742
743 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_PRESS_XL, reg,
744 3);
745 *buff = reg[2];
746 *buff = (*buff * 256) + reg[1];
747 *buff = (*buff * 256) + reg[0];
748 *buff *= 256;
749
750 return ret;
751 }
752
753 /**
754 * @brief Temperature output from FIFO value.[get]
755 *
756 * @param ctx read / write interface definitions
757 * @param buff buffer that stores data read
758 * @retval interface status (MANDATORY: return 0 -> no Error)
759 *
760 */
lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)761 int32_t lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx,
762 int16_t *buff)
763 {
764 uint8_t reg[2];
765 int32_t ret;
766
767 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_TEMP_L, reg,
768 2);
769 *buff = reg[1];
770 *buff = (*buff * 256) + reg[0];
771
772 return ret;
773 }
774
775 /**
776 * @}
777 *
778 */
779
780 /**
781 * @defgroup LPS27HHTW_Common
782 * @brief This section groups common useful functions.
783 * @{
784 *
785 */
786
787 /**
788 * @brief DeviceWhoamI[get]
789 *
790 * @param ctx read / write interface definitions
791 * @param buff buffer that stores data read
792 * @retval interface status (MANDATORY: return 0 -> no Error)
793 *
794 */
lps27hhtw_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)795 int32_t lps27hhtw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
796 {
797 int32_t ret;
798
799 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_WHO_AM_I, buff, 1);
800
801 return ret;
802 }
803
804 /**
805 * @brief Software reset. Restore the default values
806 * in user registers.[set]
807 *
808 * @param ctx read / write interface definitions
809 * @param val change the values of swreset in reg CTRL_REG2
810 * @retval interface status (MANDATORY: return 0 -> no Error)
811 *
812 */
lps27hhtw_reset_set(const stmdev_ctx_t * ctx,uint8_t val)813 int32_t lps27hhtw_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
814 {
815 lps27hhtw_ctrl_reg2_t reg;
816 int32_t ret;
817
818 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
819
820 if (ret == 0)
821 {
822 reg.swreset = val;
823 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
824 }
825
826 return ret;
827 }
828
829 /**
830 * @brief Software reset. Restore the default values
831 * in user registers.[get]
832 *
833 * @param ctx read / write interface definitions
834 * @param val change the values of swreset in reg CTRL_REG2
835 * @retval interface status (MANDATORY: return 0 -> no Error)
836 *
837 */
lps27hhtw_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)838 int32_t lps27hhtw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
839 {
840 lps27hhtw_ctrl_reg2_t reg;
841 int32_t ret;
842
843 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
844 *val = reg.swreset;
845
846 return ret;
847 }
848
849 /**
850 * @brief Register address automatically
851 * incremented during a multiple byte access
852 * with a serial interface.[set]
853 *
854 * @param ctx read / write interface definitions
855 * @param val change the values of if_add_inc in reg CTRL_REG2
856 * @retval interface status (MANDATORY: return 0 -> no Error)
857 *
858 */
lps27hhtw_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)859 int32_t lps27hhtw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
860 {
861 lps27hhtw_ctrl_reg2_t reg;
862 int32_t ret;
863
864 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
865
866 if (ret == 0)
867 {
868 reg.if_add_inc = val;
869 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
870 }
871
872 return ret;
873 }
874
875 /**
876 * @brief Register address automatically
877 * incremented during a multiple byte
878 * access with a serial interface.[get]
879 *
880 * @param ctx read / write interface definitions
881 * @param val change the values of if_add_inc in reg CTRL_REG2
882 * @retval interface status (MANDATORY: return 0 -> no Error)
883 *
884 */
lps27hhtw_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)885 int32_t lps27hhtw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
886 {
887 lps27hhtw_ctrl_reg2_t reg;
888 int32_t ret;
889
890 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
891 *val = reg.if_add_inc;
892
893 return ret;
894 }
895
896 /**
897 * @brief Reboot memory content. Reload the calibration
898 * parameters.[set]
899 *
900 * @param ctx read / write interface definitions
901 * @param val change the values of boot in reg CTRL_REG2
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
lps27hhtw_boot_set(const stmdev_ctx_t * ctx,uint8_t val)905 int32_t lps27hhtw_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
906 {
907 lps27hhtw_ctrl_reg2_t reg;
908 int32_t ret;
909
910 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
911
912 if (ret == 0)
913 {
914 reg.boot = val;
915 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
916 }
917
918 return ret;
919 }
920
921 /**
922 * @brief Reboot memory content. Reload the calibration
923 * parameters.[get]
924 *
925 * @param ctx read / write interface definitions
926 * @param val change the values of boot in reg CTRL_REG2
927 * @retval interface status (MANDATORY: return 0 -> no Error)
928 *
929 */
lps27hhtw_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)930 int32_t lps27hhtw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
931 {
932 lps27hhtw_ctrl_reg2_t reg;
933 int32_t ret;
934
935 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
936 *val = reg.boot;
937
938 return ret;
939 }
940
941 /**
942 * @}
943 *
944 */
945
946 /**
947 * @defgroup LPS27HHTW_Filters
948 * @brief This section group all the functions concerning the
949 * filters configuration.
950 * @{
951 *
952 */
953
954 /**
955 * @brief Low-pass bandwidth selection.[set]
956 *
957 * @param ctx read / write interface definitions
958 * @param val change the values of lpfp_cfg in reg CTRL_REG1
959 * @retval interface status (MANDATORY: return 0 -> no Error)
960 *
961 */
lps27hhtw_lp_bandwidth_set(const stmdev_ctx_t * ctx,lps27hhtw_lpfp_cfg_t val)962 int32_t lps27hhtw_lp_bandwidth_set(const stmdev_ctx_t *ctx,
963 lps27hhtw_lpfp_cfg_t val)
964 {
965 lps27hhtw_ctrl_reg1_t reg;
966 int32_t ret;
967
968 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
969
970 if (ret == 0)
971 {
972 reg.lpfp_cfg = (uint8_t)val;
973 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
974 }
975
976 return ret;
977 }
978
979 /**
980 * @brief Low-pass bandwidth selection.[get]
981 *
982 * @param ctx read / write interface definitions
983 * @param val Get the values of lpfp_cfg in reg CTRL_REG1
984 * @retval interface status (MANDATORY: return 0 -> no Error)
985 *
986 */
lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t * ctx,lps27hhtw_lpfp_cfg_t * val)987 int32_t lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t *ctx,
988 lps27hhtw_lpfp_cfg_t *val)
989 {
990 lps27hhtw_ctrl_reg1_t reg;
991 int32_t ret;
992
993 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
994
995 switch (reg.lpfp_cfg)
996 {
997 case LPS27HHTW_LPF_ODR_DIV_2:
998 *val = LPS27HHTW_LPF_ODR_DIV_2;
999 break;
1000
1001 case LPS27HHTW_LPF_ODR_DIV_9:
1002 *val = LPS27HHTW_LPF_ODR_DIV_9;
1003 break;
1004
1005 case LPS27HHTW_LPF_ODR_DIV_20:
1006 *val = LPS27HHTW_LPF_ODR_DIV_20;
1007 break;
1008
1009 default:
1010 *val = LPS27HHTW_LPF_ODR_DIV_2;
1011 break;
1012 }
1013
1014 return ret;
1015 }
1016
1017 /**
1018 * @}
1019 *
1020 */
1021
1022 /**
1023 * @defgroup LPS27HHTW_Serial_Interface
1024 * @brief This section groups all the functions concerning serial
1025 * interface management
1026 * @{
1027 *
1028 */
1029
1030 /**
1031 * @brief Enable/Disable I2C interface.[set]
1032 *
1033 * @param ctx read / write interface definitions
1034 * @param val change the values of i2c_disable in reg IF_CTRL
1035 * @retval interface status (MANDATORY: return 0 -> no Error)
1036 *
1037 */
lps27hhtw_i2c_interface_set(const stmdev_ctx_t * ctx,lps27hhtw_i2c_disable_t val)1038 int32_t lps27hhtw_i2c_interface_set(const stmdev_ctx_t *ctx,
1039 lps27hhtw_i2c_disable_t val)
1040 {
1041 lps27hhtw_if_ctrl_t reg;
1042 int32_t ret;
1043
1044 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1045
1046 if (ret == 0)
1047 {
1048 reg.i2c_disable = (uint8_t)val;
1049 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1050 }
1051
1052 return ret;
1053 }
1054
1055 /**
1056 * @brief Enable/Disable I2C interface.[get]
1057 *
1058 * @param ctx read / write interface definitions
1059 * @param val Get the values of i2c_disable in reg IF_CTRL
1060 * @retval interface status (MANDATORY: return 0 -> no Error)
1061 *
1062 */
lps27hhtw_i2c_interface_get(const stmdev_ctx_t * ctx,lps27hhtw_i2c_disable_t * val)1063 int32_t lps27hhtw_i2c_interface_get(const stmdev_ctx_t *ctx,
1064 lps27hhtw_i2c_disable_t *val)
1065 {
1066 lps27hhtw_if_ctrl_t reg;
1067 int32_t ret;
1068
1069 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1070
1071 switch (reg.i2c_disable)
1072 {
1073 case LPS27HHTW_I2C_ENABLE:
1074 *val = LPS27HHTW_I2C_ENABLE;
1075 break;
1076
1077 case LPS27HHTW_I2C_DISABLE:
1078 *val = LPS27HHTW_I2C_DISABLE;
1079 break;
1080
1081 default:
1082 *val = LPS27HHTW_I2C_ENABLE;
1083 break;
1084 }
1085
1086 return ret;
1087 }
1088
1089 /**
1090 * @brief I3C Enable/Disable communication protocol.[set]
1091 *
1092 * @param ctx read / write interface definitions
1093 * @param val change the values of int_en_i3c in reg IF_CTRL
1094 * @retval interface status (MANDATORY: return 0 -> no Error)
1095 *
1096 */
lps27hhtw_i3c_interface_set(const stmdev_ctx_t * ctx,lps27hhtw_i3c_disable_t val)1097 int32_t lps27hhtw_i3c_interface_set(const stmdev_ctx_t *ctx,
1098 lps27hhtw_i3c_disable_t val)
1099 {
1100 lps27hhtw_if_ctrl_t reg;
1101 int32_t ret;
1102
1103 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1104
1105 if (ret == 0)
1106 {
1107 reg.i3c_disable = ((uint8_t)val & 0x01u);
1108 reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
1109 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1110 }
1111
1112 return ret;
1113 }
1114
1115 /**
1116 * @brief I3C Enable/Disable communication protocol.[get]
1117 *
1118 * @param ctx read / write interface definitions
1119 * @param val change the values of int_en_i3c in reg IF_CTRL
1120 * @retval interface status (MANDATORY: return 0 -> no Error)
1121 *
1122 */
lps27hhtw_i3c_interface_get(const stmdev_ctx_t * ctx,lps27hhtw_i3c_disable_t * val)1123 int32_t lps27hhtw_i3c_interface_get(const stmdev_ctx_t *ctx,
1124 lps27hhtw_i3c_disable_t *val)
1125 {
1126 lps27hhtw_if_ctrl_t reg;
1127 int32_t ret;
1128
1129 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1130
1131 switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
1132 {
1133 case LPS27HHTW_I3C_ENABLE:
1134 *val = LPS27HHTW_I3C_ENABLE;
1135 break;
1136
1137 case LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE:
1138 *val = LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE;
1139 break;
1140
1141 case LPS27HHTW_I3C_DISABLE:
1142 *val = LPS27HHTW_I3C_DISABLE;
1143 break;
1144
1145 default:
1146 *val = LPS27HHTW_I3C_ENABLE;
1147 break;
1148 }
1149
1150 return ret;
1151 }
1152
1153 /**
1154 * @brief Enable/Disable pull-up on SDO pin.[set]
1155 *
1156 * @param ctx read / write interface definitions
1157 * @param val change the values of sdo_pu_en in reg IF_CTRL
1158 * @retval interface status (MANDATORY: return 0 -> no Error)
1159 *
1160 */
lps27hhtw_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lps27hhtw_pu_en_t val)1161 int32_t lps27hhtw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
1162 lps27hhtw_pu_en_t val)
1163 {
1164 lps27hhtw_if_ctrl_t reg;
1165 int32_t ret;
1166
1167 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1168
1169 if (ret == 0)
1170 {
1171 reg.sdo_pu_en = (uint8_t)val;
1172 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1173 }
1174
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Enable/Disable pull-up on SDO pin.[get]
1180 *
1181 * @param ctx read / write interface definitions
1182 * @param val Get the values of sdo_pu_en in reg IF_CTRL
1183 * @retval interface status (MANDATORY: return 0 -> no Error)
1184 *
1185 */
lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lps27hhtw_pu_en_t * val)1186 int32_t lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
1187 lps27hhtw_pu_en_t *val)
1188 {
1189 lps27hhtw_if_ctrl_t reg;
1190 int32_t ret;
1191
1192 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1193
1194 switch (reg.sdo_pu_en)
1195 {
1196 case LPS27HHTW_PULL_UP_DISCONNECT:
1197 *val = LPS27HHTW_PULL_UP_DISCONNECT;
1198 break;
1199
1200 case LPS27HHTW_PULL_UP_CONNECT:
1201 *val = LPS27HHTW_PULL_UP_CONNECT;
1202 break;
1203
1204 default:
1205 *val = LPS27HHTW_PULL_UP_DISCONNECT;
1206 break;
1207 }
1208
1209 return ret;
1210 }
1211
1212 /**
1213 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
1214 *
1215 * @param ctx read / write interface definitions
1216 * @param val change the values of sda_pu_en in reg IF_CTRL
1217 * @retval interface status (MANDATORY: return 0 -> no Error)
1218 *
1219 */
lps27hhtw_sda_mode_set(const stmdev_ctx_t * ctx,lps27hhtw_pu_en_t val)1220 int32_t lps27hhtw_sda_mode_set(const stmdev_ctx_t *ctx,
1221 lps27hhtw_pu_en_t val)
1222 {
1223 lps27hhtw_if_ctrl_t reg;
1224 int32_t ret;
1225
1226 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1227
1228 if (ret == 0)
1229 {
1230 reg.sda_pu_en = (uint8_t)val;
1231 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1232 }
1233
1234 return ret;
1235 }
1236
1237 /**
1238 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
1239 *
1240 * @param ctx read / write interface definitions
1241 * @param val Get the values of sda_pu_en in reg IF_CTRL
1242 * @retval interface status (MANDATORY: return 0 -> no Error)
1243 *
1244 */
lps27hhtw_sda_mode_get(const stmdev_ctx_t * ctx,lps27hhtw_pu_en_t * val)1245 int32_t lps27hhtw_sda_mode_get(const stmdev_ctx_t *ctx,
1246 lps27hhtw_pu_en_t *val)
1247 {
1248 lps27hhtw_if_ctrl_t reg;
1249 int32_t ret;
1250
1251 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1);
1252
1253 switch (reg.sda_pu_en)
1254 {
1255 case LPS27HHTW_PULL_UP_DISCONNECT:
1256 *val = LPS27HHTW_PULL_UP_DISCONNECT;
1257 break;
1258
1259 case LPS27HHTW_PULL_UP_CONNECT:
1260 *val = LPS27HHTW_PULL_UP_CONNECT;
1261 break;
1262
1263 default:
1264 *val = LPS27HHTW_PULL_UP_DISCONNECT;
1265 break;
1266 }
1267
1268 return ret;
1269 }
1270
1271 /**
1272 * @brief SPI Serial Interface Mode selection.[set]
1273 *
1274 * @param ctx read / write interface definitions
1275 * @param val change the values of sim in reg CTRL_REG1
1276 * @retval interface status (MANDATORY: return 0 -> no Error)
1277 *
1278 */
lps27hhtw_spi_mode_set(const stmdev_ctx_t * ctx,lps27hhtw_sim_t val)1279 int32_t lps27hhtw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_sim_t val)
1280 {
1281 lps27hhtw_ctrl_reg1_t reg;
1282 int32_t ret;
1283
1284 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
1285
1286 if (ret == 0)
1287 {
1288 reg.sim = (uint8_t)val;
1289 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
1290 }
1291
1292 return ret;
1293 }
1294
1295 /**
1296 * @brief SPI Serial Interface Mode selection.[get]
1297 *
1298 * @param ctx read / write interface definitions
1299 * @param val Get the values of sim in reg CTRL_REG1
1300 * @retval interface status (MANDATORY: return 0 -> no Error)
1301 *
1302 */
lps27hhtw_spi_mode_get(const stmdev_ctx_t * ctx,lps27hhtw_sim_t * val)1303 int32_t lps27hhtw_spi_mode_get(const stmdev_ctx_t *ctx,
1304 lps27hhtw_sim_t *val)
1305 {
1306 lps27hhtw_ctrl_reg1_t reg;
1307 int32_t ret;
1308
1309 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1);
1310
1311 switch (reg.sim)
1312 {
1313 case LPS27HHTW_SPI_4_WIRE:
1314 *val = LPS27HHTW_SPI_4_WIRE;
1315 break;
1316
1317 case LPS27HHTW_SPI_3_WIRE:
1318 *val = LPS27HHTW_SPI_3_WIRE;
1319 break;
1320
1321 default:
1322 *val = LPS27HHTW_SPI_4_WIRE;
1323 break;
1324 }
1325
1326 return ret;
1327 }
1328
1329 /**
1330 * @}
1331 *
1332 */
1333
1334 /**
1335 * @defgroup LPS27HHTW_Interrupt_Pins
1336 * @brief This section groups all the functions that manage
1337 * interrupt pins.
1338 * @{
1339 *
1340 */
1341
1342 /**
1343 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
1344 *
1345 * @param ctx read / write interface definitions
1346 * @param val change the values of lir in reg INTERRUPT_CFG
1347 * @retval interface status (MANDATORY: return 0 -> no Error)
1348 *
1349 */
lps27hhtw_int_notification_set(const stmdev_ctx_t * ctx,lps27hhtw_lir_t val)1350 int32_t lps27hhtw_int_notification_set(const stmdev_ctx_t *ctx,
1351 lps27hhtw_lir_t val)
1352 {
1353 lps27hhtw_interrupt_cfg_t reg;
1354 int32_t ret;
1355
1356 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1357 (uint8_t *) ®, 1);
1358
1359 if (ret == 0)
1360 {
1361 reg.lir = (uint8_t)val;
1362 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1363 (uint8_t *) ®, 1);
1364 }
1365
1366 return ret;
1367 }
1368
1369 /**
1370 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
1371 *
1372 * @param ctx read / write interface definitions
1373 * @param val Get the values of lir in reg INTERRUPT_CFG
1374 * @retval interface status (MANDATORY: return 0 -> no Error)
1375 *
1376 */
lps27hhtw_int_notification_get(const stmdev_ctx_t * ctx,lps27hhtw_lir_t * val)1377 int32_t lps27hhtw_int_notification_get(const stmdev_ctx_t *ctx,
1378 lps27hhtw_lir_t *val)
1379 {
1380 lps27hhtw_interrupt_cfg_t reg;
1381 int32_t ret;
1382
1383 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1384 (uint8_t *) ®, 1);
1385
1386 switch (reg.lir)
1387 {
1388 case LPS27HHTW_INT_PULSED:
1389 *val = LPS27HHTW_INT_PULSED;
1390 break;
1391
1392 case LPS27HHTW_INT_LATCHED:
1393 *val = LPS27HHTW_INT_LATCHED;
1394 break;
1395
1396 default:
1397 *val = LPS27HHTW_INT_PULSED;
1398 break;
1399 }
1400
1401 return ret;
1402 }
1403
1404 /**
1405 * @brief Push-pull/open drain selection on interrupt pads.[set]
1406 *
1407 * @param ctx read / write interface definitions
1408 * @param val change the values of pp_od in reg CTRL_REG2
1409 * @retval interface status (MANDATORY: return 0 -> no Error)
1410 *
1411 */
lps27hhtw_pin_mode_set(const stmdev_ctx_t * ctx,lps27hhtw_pp_od_t val)1412 int32_t lps27hhtw_pin_mode_set(const stmdev_ctx_t *ctx,
1413 lps27hhtw_pp_od_t val)
1414 {
1415 lps27hhtw_ctrl_reg2_t reg;
1416 int32_t ret;
1417
1418 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1419
1420 if (ret == 0)
1421 {
1422 reg.pp_od = (uint8_t)val;
1423 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1424 }
1425
1426 return ret;
1427 }
1428
1429 /**
1430 * @brief Push-pull/open drain selection on interrupt pads.[get]
1431 *
1432 * @param ctx read / write interface definitions
1433 * @param val Get the values of pp_od in reg CTRL_REG2
1434 * @retval interface status (MANDATORY: return 0 -> no Error)
1435 *
1436 */
lps27hhtw_pin_mode_get(const stmdev_ctx_t * ctx,lps27hhtw_pp_od_t * val)1437 int32_t lps27hhtw_pin_mode_get(const stmdev_ctx_t *ctx,
1438 lps27hhtw_pp_od_t *val)
1439 {
1440 lps27hhtw_ctrl_reg2_t reg;
1441 int32_t ret;
1442
1443 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1444
1445 switch (reg.pp_od)
1446 {
1447 case LPS27HHTW_PUSH_PULL:
1448 *val = LPS27HHTW_PUSH_PULL;
1449 break;
1450
1451 case LPS27HHTW_OPEN_DRAIN:
1452 *val = LPS27HHTW_OPEN_DRAIN;
1453 break;
1454
1455 default:
1456 *val = LPS27HHTW_PUSH_PULL;
1457 break;
1458 }
1459
1460 return ret;
1461 }
1462
1463 /**
1464 * @brief Interrupt active-high/low.[set]
1465 *
1466 * @param ctx read / write interface definitions
1467 * @param val change the values of int_h_l in reg CTRL_REG2
1468 * @retval interface status (MANDATORY: return 0 -> no Error)
1469 *
1470 */
lps27hhtw_pin_polarity_set(const stmdev_ctx_t * ctx,lps27hhtw_int_h_l_t val)1471 int32_t lps27hhtw_pin_polarity_set(const stmdev_ctx_t *ctx,
1472 lps27hhtw_int_h_l_t val)
1473 {
1474 lps27hhtw_ctrl_reg2_t reg;
1475 int32_t ret;
1476
1477 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1478
1479 if (ret == 0)
1480 {
1481 reg.int_h_l = (uint8_t)val;
1482 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1483 }
1484
1485 return ret;
1486 }
1487
1488 /**
1489 * @brief Interrupt active-high/low.[get]
1490 *
1491 * @param ctx read / write interface definitions
1492 * @param val Get the values of int_h_l in reg CTRL_REG2
1493 * @retval interface status (MANDATORY: return 0 -> no Error)
1494 *
1495 */
lps27hhtw_pin_polarity_get(const stmdev_ctx_t * ctx,lps27hhtw_int_h_l_t * val)1496 int32_t lps27hhtw_pin_polarity_get(const stmdev_ctx_t *ctx,
1497 lps27hhtw_int_h_l_t *val)
1498 {
1499 lps27hhtw_ctrl_reg2_t reg;
1500 int32_t ret;
1501
1502 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1);
1503
1504 switch (reg.int_h_l)
1505 {
1506 case LPS27HHTW_ACTIVE_HIGH:
1507 *val = LPS27HHTW_ACTIVE_HIGH;
1508 break;
1509
1510 case LPS27HHTW_ACTIVE_LOW:
1511 *val = LPS27HHTW_ACTIVE_LOW;
1512 break;
1513
1514 default:
1515 *val = LPS27HHTW_ACTIVE_HIGH;
1516 break;
1517 }
1518
1519 return ret;
1520 }
1521
1522 /**
1523 * @brief Select the signal that need to route on int pad.[set]
1524 *
1525 * @param ctx read / write interface definitions
1526 * @param val registers CTRL_REG3
1527 * @retval interface status (MANDATORY: return 0 -> no Error)
1528 *
1529 */
lps27hhtw_pin_int_route_set(const stmdev_ctx_t * ctx,lps27hhtw_ctrl_reg3_t * val)1530 int32_t lps27hhtw_pin_int_route_set(const stmdev_ctx_t *ctx,
1531 lps27hhtw_ctrl_reg3_t *val)
1532 {
1533 int32_t ret;
1534
1535 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *) val, 1);
1536
1537 return ret;
1538 }
1539
1540 /**
1541 * @brief Select the signal that need to route on int pad.[get]
1542 *
1543 * @param ctx read / write interface definitions
1544 * @param val registers CTRL_REG3
1545 * @retval interface status (MANDATORY: return 0 -> no Error)
1546 *
1547 */
lps27hhtw_pin_int_route_get(const stmdev_ctx_t * ctx,lps27hhtw_ctrl_reg3_t * val)1548 int32_t lps27hhtw_pin_int_route_get(const stmdev_ctx_t *ctx,
1549 lps27hhtw_ctrl_reg3_t *val)
1550 {
1551 int32_t ret;
1552
1553 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *) val, 1);
1554
1555 return ret;
1556 }
1557
1558 /**
1559 * @}
1560 *
1561 */
1562
1563 /**
1564 * @defgroup LPS27HHTW_Interrupt_on_Threshold
1565 * @brief This section groups all the functions that manage the
1566 * interrupt on threshold event generation.
1567 * @{
1568 *
1569 */
1570
1571 /**
1572 * @brief Enable interrupt generation on pressure low/high event.[set]
1573 *
1574 * @param ctx read / write interface definitions
1575 * @param val change the values of pe in reg INTERRUPT_CFG
1576 * @retval interface status (MANDATORY: return 0 -> no Error)
1577 *
1578 */
lps27hhtw_int_on_threshold_set(const stmdev_ctx_t * ctx,lps27hhtw_pe_t val)1579 int32_t lps27hhtw_int_on_threshold_set(const stmdev_ctx_t *ctx,
1580 lps27hhtw_pe_t val)
1581 {
1582 lps27hhtw_interrupt_cfg_t reg;
1583 int32_t ret;
1584
1585 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1586 (uint8_t *) ®, 1);
1587
1588 if (ret == 0)
1589 {
1590 reg.pe = (uint8_t)val;
1591
1592 if (val == LPS27HHTW_NO_THRESHOLD)
1593 {
1594 reg.diff_en = PROPERTY_DISABLE;
1595 }
1596
1597 else
1598 {
1599 reg.diff_en = PROPERTY_ENABLE;
1600 }
1601
1602 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1603 (uint8_t *) ®, 1);
1604 }
1605
1606 return ret;
1607 }
1608
1609 /**
1610 * @brief Enable interrupt generation on pressure low/high event.[get]
1611 *
1612 * @param ctx read / write interface definitions
1613 * @param val Get the values of pe in reg INTERRUPT_CFG
1614 * @retval interface status (MANDATORY: return 0 -> no Error)
1615 *
1616 */
lps27hhtw_int_on_threshold_get(const stmdev_ctx_t * ctx,lps27hhtw_pe_t * val)1617 int32_t lps27hhtw_int_on_threshold_get(const stmdev_ctx_t *ctx,
1618 lps27hhtw_pe_t *val)
1619 {
1620 lps27hhtw_interrupt_cfg_t reg;
1621 int32_t ret;
1622
1623 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG,
1624 (uint8_t *) ®, 1);
1625
1626 switch (reg.pe)
1627 {
1628 case LPS27HHTW_NO_THRESHOLD:
1629 *val = LPS27HHTW_NO_THRESHOLD;
1630 break;
1631
1632 case LPS27HHTW_POSITIVE:
1633 *val = LPS27HHTW_POSITIVE;
1634 break;
1635
1636 case LPS27HHTW_NEGATIVE:
1637 *val = LPS27HHTW_NEGATIVE;
1638 break;
1639
1640 case LPS27HHTW_BOTH:
1641 *val = LPS27HHTW_BOTH;
1642 break;
1643
1644 default:
1645 *val = LPS27HHTW_NO_THRESHOLD;
1646 break;
1647 }
1648
1649 return ret;
1650 }
1651
1652 /**
1653 * @brief User-defined threshold value for pressure interrupt event.[set]
1654 *
1655 * @param ctx read / write interface definitions
1656 * @param buff buffer that contains data to write
1657 * @retval interface status (MANDATORY: return 0 -> no Error)
1658 *
1659 */
lps27hhtw_int_threshold_set(const stmdev_ctx_t * ctx,uint16_t buff)1660 int32_t lps27hhtw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff)
1661 {
1662 int32_t ret;
1663
1664 lps27hhtw_ths_p_l_t ths_p_l;
1665 lps27hhtw_ths_p_h_t ths_p_h;
1666 ths_p_l.ths = (uint8_t)(buff & 0x00FFU);
1667 ths_p_h.ths = (uint8_t)((buff & 0x7F00U) >> 8);
1668 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_THS_P_L,
1669 (uint8_t *)&ths_p_l, 1);
1670
1671 if (ret == 0)
1672 {
1673 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_THS_P_H,
1674 (uint8_t *)&ths_p_h, 1);
1675 }
1676
1677 return ret;
1678 }
1679
1680 /**
1681 * @brief User-defined threshold value for pressure interrupt event.[get]
1682 *
1683 * @param ctx read / write interface definitions
1684 * @param buff buffer that stores data read
1685 * @retval interface status (MANDATORY: return 0 -> no Error)
1686 *
1687 */
lps27hhtw_int_threshold_get(const stmdev_ctx_t * ctx,uint16_t * buff)1688 int32_t lps27hhtw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff)
1689 {
1690 int32_t ret;
1691
1692 lps27hhtw_ths_p_l_t ths_p_l;
1693 lps27hhtw_ths_p_h_t ths_p_h;
1694 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_L,
1695 (uint8_t *)&ths_p_l, 1);
1696
1697 if (ret == 0)
1698 {
1699 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_H,
1700 (uint8_t *)&ths_p_h, 1);
1701 *buff = (uint16_t)ths_p_h.ths << 8;
1702 *buff |= (uint16_t)ths_p_l.ths;
1703 }
1704
1705 return ret;
1706 }
1707
1708 /**
1709 * @}
1710 *
1711 */
1712
1713 /**
1714 * @defgroup LPS27HHTW_Fifo
1715 * @brief This section group all the functions concerning the fifo usage.
1716 * @{
1717 *
1718 */
1719
1720 /**
1721 * @brief Fifo Mode selection.[set]
1722 *
1723 * @param ctx read / write interface definitions
1724 * @param val change the values of f_mode in reg FIFO_CTRL
1725 * @retval interface status (MANDATORY: return 0 -> no Error)
1726 *
1727 */
lps27hhtw_fifo_mode_set(const stmdev_ctx_t * ctx,lps27hhtw_f_mode_t val)1728 int32_t lps27hhtw_fifo_mode_set(const stmdev_ctx_t *ctx,
1729 lps27hhtw_f_mode_t val)
1730 {
1731 lps27hhtw_fifo_ctrl_t reg;
1732 int32_t ret;
1733
1734 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1735
1736 if (ret == 0)
1737 {
1738 reg.f_mode = (uint8_t)val;
1739 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1740 }
1741
1742 return ret;
1743 }
1744
1745 /**
1746 * @brief Fifo Mode selection.[get]
1747 *
1748 * @param ctx read / write interface definitions
1749 * @param val Get the values of f_mode in reg FIFO_CTRL
1750 * @retval interface status (MANDATORY: return 0 -> no Error)
1751 *
1752 */
lps27hhtw_fifo_mode_get(const stmdev_ctx_t * ctx,lps27hhtw_f_mode_t * val)1753 int32_t lps27hhtw_fifo_mode_get(const stmdev_ctx_t *ctx,
1754 lps27hhtw_f_mode_t *val)
1755 {
1756 lps27hhtw_fifo_ctrl_t reg;
1757 int32_t ret;
1758
1759 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1760
1761 switch (reg.f_mode)
1762 {
1763 case LPS27HHTW_BYPASS_MODE:
1764 *val = LPS27HHTW_BYPASS_MODE;
1765 break;
1766
1767 case LPS27HHTW_FIFO_MODE:
1768 *val = LPS27HHTW_FIFO_MODE;
1769 break;
1770
1771 case LPS27HHTW_STREAM_MODE:
1772 *val = LPS27HHTW_STREAM_MODE;
1773 break;
1774
1775 case LPS27HHTW_DYNAMIC_STREAM_MODE:
1776 *val = LPS27HHTW_DYNAMIC_STREAM_MODE;
1777 break;
1778
1779 case LPS27HHTW_BYPASS_TO_FIFO_MODE:
1780 *val = LPS27HHTW_BYPASS_TO_FIFO_MODE;
1781 break;
1782
1783 case LPS27HHTW_BYPASS_TO_STREAM_MODE:
1784 *val = LPS27HHTW_BYPASS_TO_STREAM_MODE;
1785 break;
1786
1787 case LPS27HHTW_STREAM_TO_FIFO_MODE:
1788 *val = LPS27HHTW_STREAM_TO_FIFO_MODE;
1789 break;
1790
1791 default:
1792 *val = LPS27HHTW_BYPASS_MODE;
1793 break;
1794 }
1795
1796 return ret;
1797 }
1798
1799 /**
1800 * @brief Sensing chain FIFO stop values memorization at
1801 * threshold level.[set]
1802 *
1803 * @param ctx read / write interface definitions
1804 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1805 * @retval interface status (MANDATORY: return 0 -> no Error)
1806 *
1807 */
lps27hhtw_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)1808 int32_t lps27hhtw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
1809 {
1810 lps27hhtw_fifo_ctrl_t reg;
1811 int32_t ret;
1812
1813 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1814
1815 if (ret == 0)
1816 {
1817 reg.stop_on_wtm = val;
1818 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1819 }
1820
1821 return ret;
1822 }
1823
1824 /**
1825 * @brief Sensing chain FIFO stop values memorization at threshold
1826 * level.[get]
1827 *
1828 * @param ctx read / write interface definitions
1829 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1830 * @retval interface status (MANDATORY: return 0 -> no Error)
1831 *
1832 */
lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)1833 int32_t lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
1834 uint8_t *val)
1835 {
1836 lps27hhtw_fifo_ctrl_t reg;
1837 int32_t ret;
1838
1839 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1);
1840 *val = reg.stop_on_wtm;
1841
1842 return ret;
1843 }
1844
1845 /**
1846 * @brief FIFO watermark level selection.[set]
1847 *
1848 * @param ctx read / write interface definitions
1849 * @param val change the values of wtm in reg FIFO_WTM
1850 * @retval interface status (MANDATORY: return 0 -> no Error)
1851 *
1852 */
lps27hhtw_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1853 int32_t lps27hhtw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1854 {
1855 lps27hhtw_fifo_wtm_t reg;
1856 int32_t ret;
1857
1858 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
1859
1860 if (ret == 0)
1861 {
1862 reg.wtm = val;
1863 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
1864 }
1865
1866 return ret;
1867 }
1868
1869 /**
1870 * @brief FIFO watermark level selection.[get]
1871 *
1872 * @param ctx read / write interface definitions
1873 * @param val change the values of wtm in reg FIFO_WTM
1874 * @retval interface status (MANDATORY: return 0 -> no Error)
1875 *
1876 */
lps27hhtw_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1877 int32_t lps27hhtw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1878 {
1879 lps27hhtw_fifo_wtm_t reg;
1880 int32_t ret;
1881
1882 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1);
1883 *val = reg.wtm;
1884
1885 return ret;
1886 }
1887
1888 /**
1889 * @brief FIFO stored data level.[get]
1890 *
1891 * @param ctx read / write interface definitions
1892 * @param buff buffer that stores data read
1893 * @retval interface status (MANDATORY: return 0 -> no Error)
1894 *
1895 */
lps27hhtw_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * buff)1896 int32_t lps27hhtw_fifo_data_level_get(const stmdev_ctx_t *ctx,
1897 uint8_t *buff)
1898 {
1899 int32_t ret;
1900
1901 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS1, buff, 1);
1902
1903 return ret;
1904 }
1905
1906 /**
1907 * @brief Read all the FIFO status flag of the device.[get]
1908 *
1909 * @param ctx read / write interface definitions
1910 * @param val registers FIFO_STATUS2
1911 * @retval interface status (MANDATORY: return 0 -> no Error)
1912 *
1913 */
lps27hhtw_fifo_src_get(const stmdev_ctx_t * ctx,lps27hhtw_fifo_status2_t * val)1914 int32_t lps27hhtw_fifo_src_get(const stmdev_ctx_t *ctx,
1915 lps27hhtw_fifo_status2_t *val)
1916 {
1917 int32_t ret;
1918
1919 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
1920 (uint8_t *) val, 1);
1921
1922 return ret;
1923 }
1924
1925 /**
1926 * @brief Smart FIFO full status.[get]
1927 *
1928 * @param ctx read / write interface definitions
1929 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
1930 * @retval interface status (MANDATORY: return 0 -> no Error)
1931 *
1932 */
lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1933 int32_t lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1934 {
1935 lps27hhtw_fifo_status2_t reg;
1936 int32_t ret;
1937
1938 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
1939 (uint8_t *) ®, 1);
1940 *val = reg.fifo_full_ia;
1941
1942 return ret;
1943 }
1944
1945 /**
1946 * @brief FIFO overrun status.[get]
1947 *
1948 * @param ctx read / write interface definitions
1949 * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
1950 * @retval interface status (MANDATORY: return 0 -> no Error)
1951 *
1952 */
lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1953 int32_t lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1954 {
1955 lps27hhtw_fifo_status2_t reg;
1956 int32_t ret;
1957
1958 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2,
1959 (uint8_t *) ®, 1);
1960 *val = reg.fifo_ovr_ia;
1961
1962 return ret;
1963 }
1964
1965 /**
1966 * @brief FIFO watermark status.[get]
1967 *
1968 * @param ctx read / write interface definitions
1969 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
1970 * @retval interface status (MANDATORY: return 0 -> no Error)
1971 *
1972 */
lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1973 int32_t lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1974 {
1975 lps27hhtw_fifo_status2_t reg;
1976 int32_t ret;
1977
1978 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2, (uint8_t *)®, 1);
1979 *val = reg.fifo_wtm_ia;
1980
1981 return ret;
1982 }
1983
1984 /**
1985 * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
1986 *
1987 * @param stmdev_ctx_t *ctx: read / write interface definitions
1988 * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
1989 * @retval interface status (MANDATORY: return 0 -> no Error)
1990 *
1991 */
lps27hhtw_fifo_ovr_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)1992 int32_t lps27hhtw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
1993 {
1994 lps27hhtw_ctrl_reg3_t reg;
1995 int32_t ret;
1996
1997 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
1998
1999 if (ret == 0)
2000 {
2001 reg.int_f_ovr = val;
2002 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2003 }
2004
2005 return ret;
2006 }
2007
2008 /**
2009 * @brief FIFO overrun interrupt on INT_DRDY pin.[get]
2010 *
2011 * @param stmdev_ctx_t *ctx: read / write interface definitions
2012 * @param uint8_t: change the values of f_ovr in reg CTRL_REG3
2013 * @retval interface status (MANDATORY: return 0 -> no Error)
2014 *
2015 */
lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2016 int32_t lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val)
2017 {
2018 lps27hhtw_ctrl_reg3_t reg;
2019 int32_t ret;
2020
2021 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2022 *val = reg.int_f_ovr;
2023
2024 return ret;
2025 }
2026
2027 /**
2028 * @brief FIFO watermark status on INT_DRDY pin.[set]
2029 *
2030 * @param stmdev_ctx_t *ctx: read / write interface definitions
2031 * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
2032 * @retval interface status (MANDATORY: return 0 -> no Error)
2033 *
2034 */
lps27hhtw_fifo_threshold_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)2035 int32_t lps27hhtw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx,
2036 uint8_t val)
2037 {
2038 lps27hhtw_ctrl_reg3_t reg;
2039 int32_t ret;
2040
2041 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2042
2043 if (ret == 0)
2044 {
2045 reg.int_f_wtm = val;
2046 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2047 }
2048
2049 return ret;
2050 }
2051
2052 /**
2053 * @brief FIFO watermark status on INT_DRDY pin.[get]
2054 *
2055 * @param lps22hb_ctx_t *ctx: read / write interface definitions
2056 * @param uint8_t: change the values of f_fth in reg CTRL_REG3
2057 * @retval interface status (MANDATORY: return 0 -> no Error)
2058 *
2059 */
lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2060 int32_t lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx,
2061 uint8_t *val)
2062 {
2063 lps27hhtw_ctrl_reg3_t reg;
2064 int32_t ret;
2065
2066 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2067 *val = reg.int_f_wtm;
2068
2069 return ret;
2070 }
2071
2072 /**
2073 * @brief FIFO full flag on INT_DRDY pin.[set]
2074 *
2075 * @param stmdev_ctx_t *ctx: read / write interface definitions
2076 * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
2077 * @retval interface status (MANDATORY: return 0 -> no Error)
2078 *
2079 */
lps27hhtw_fifo_full_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)2080 int32_t lps27hhtw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
2081 {
2082 lps27hhtw_ctrl_reg3_t reg;
2083 int32_t ret;
2084
2085 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2086
2087 if (ret == 0)
2088 {
2089 reg.int_f_full = val;
2090 ret = lps27hhtw_write_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2091 }
2092
2093 return ret;
2094 }
2095
2096 /**
2097 * @brief FIFO full flag on INT_DRDY pin.[get]
2098 *
2099 * @param stmdev_ctx_t *ctx: read / write interface definitions
2100 * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
2101 * @retval interface status (MANDATORY: return 0 -> no Error)
2102 *
2103 */
lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2104 int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx,
2105 uint8_t *val)
2106 {
2107 lps27hhtw_ctrl_reg3_t reg;
2108 int32_t ret;
2109
2110 ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1);
2111 *val = reg.int_f_full;
2112
2113 return ret;
2114 }
2115
2116 /**
2117 * @}
2118 *
2119 */
2120
2121 /**
2122 * @}
2123 *
2124 */
2125
2126 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2127
