1 /**
2 ******************************************************************************
3 * @file lps22hh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS22HH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps22hh_reg.h"
21
22 /**
23 * @defgroup LPS22HH
24 * @brief This file provides a set of functions needed to drive the
25 * lps22hh enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LPS22HH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps22hh_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps22hh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lps22hh_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lps22hh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LPS22HH_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
lps22hh_from_lsb_to_hpa(uint32_t lsb)102 float_t lps22hh_from_lsb_to_hpa(uint32_t lsb)
103 {
104 return ((float_t) lsb / 1048576.0f);
105 }
106
lps22hh_from_lsb_to_celsius(int16_t lsb)107 float_t lps22hh_from_lsb_to_celsius(int16_t lsb)
108 {
109 return ((float_t) lsb / 100.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup LPS22HH_Data_Generation
119 * @brief This section groups all the functions concerning
120 * data generation.
121 * @{
122 *
123 */
124
125 /**
126 * @brief Reset Autozero function.[set]
127 *
128 * @param ctx read / write interface definitions
129 * @param val change the values of reset_az in reg INTERRUPT_CFG
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
lps22hh_autozero_rst_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t lps22hh_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 lps22hh_interrupt_cfg_t reg;
136 int32_t ret;
137
138 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
139
140 if (ret == 0)
141 {
142 reg.reset_az = val;
143 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
144 }
145
146 return ret;
147 }
148
149 /**
150 * @brief Reset Autozero function.[get]
151 *
152 * @param ctx read / write interface definitions
153 * @param val change the values of reset_az in reg INTERRUPT_CFG
154 * @retval interface status (MANDATORY: return 0 -> no Error)
155 *
156 */
lps22hh_autozero_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)157 int32_t lps22hh_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
158 {
159 lps22hh_interrupt_cfg_t reg;
160 int32_t ret;
161
162 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
163 *val = reg.reset_az;
164
165 return ret;
166 }
167
168 /**
169 * @brief Enable Autozero function.[set]
170 *
171 * @param ctx read / write interface definitions
172 * @param val change the values of autozero in reg INTERRUPT_CFG
173 * @retval interface status (MANDATORY: return 0 -> no Error)
174 *
175 */
lps22hh_autozero_set(const stmdev_ctx_t * ctx,uint8_t val)176 int32_t lps22hh_autozero_set(const stmdev_ctx_t *ctx, uint8_t val)
177 {
178 lps22hh_interrupt_cfg_t reg;
179 int32_t ret;
180
181 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
182
183 if (ret == 0)
184 {
185 reg.autozero = val;
186 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Enable Autozero function.[get]
194 *
195 * @param ctx read / write interface definitions
196 * @param val change the values of autozero in reg INTERRUPT_CFG
197 * @retval interface status (MANDATORY: return 0 -> no Error)
198 *
199 */
lps22hh_autozero_get(const stmdev_ctx_t * ctx,uint8_t * val)200 int32_t lps22hh_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val)
201 {
202 lps22hh_interrupt_cfg_t reg;
203 int32_t ret;
204
205 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
206 *val = reg.autozero;
207
208 return ret;
209 }
210
211 /**
212 * @brief Reset AutoRifP function.[set]
213 *
214 * @param ctx read / write interface definitions
215 * @param val change the values of reset_arp in reg INTERRUPT_CFG
216 * @retval interface status (MANDATORY: return 0 -> no Error)
217 *
218 */
lps22hh_pressure_snap_rst_set(const stmdev_ctx_t * ctx,uint8_t val)219 int32_t lps22hh_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
220 {
221 lps22hh_interrupt_cfg_t reg;
222 int32_t ret;
223
224 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
225
226 if (ret == 0)
227 {
228 reg.reset_arp = val;
229 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
230 }
231
232 return ret;
233 }
234
235 /**
236 * @brief Reset AutoRifP function.[get]
237 *
238 * @param ctx read / write interface definitions
239 * @param val change the values of reset_arp in reg INTERRUPT_CFG
240 * @retval interface status (MANDATORY: return 0 -> no Error)
241 *
242 */
lps22hh_pressure_snap_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)243 int32_t lps22hh_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
244 {
245 lps22hh_interrupt_cfg_t reg;
246 int32_t ret;
247
248 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
249 *val = reg.reset_arp;
250
251 return ret;
252 }
253
254 /**
255 * @brief Enable AutoRefP function.[set]
256 *
257 * @param ctx read / write interface definitions
258 * @param val change the values of autorefp in reg INTERRUPT_CFG
259 * @retval interface status (MANDATORY: return 0 -> no Error)
260 *
261 */
lps22hh_pressure_snap_set(const stmdev_ctx_t * ctx,uint8_t val)262 int32_t lps22hh_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val)
263 {
264 lps22hh_interrupt_cfg_t reg;
265 int32_t ret;
266
267 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
268
269 if (ret == 0)
270 {
271 reg.autorefp = val;
272 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
273 }
274
275 return ret;
276 }
277
278 /**
279 * @brief Enable AutoRefP function.[get]
280 *
281 * @param ctx read / write interface definitions
282 * @param val change the values of autorefp in reg INTERRUPT_CFG
283 * @retval interface status (MANDATORY: return 0 -> no Error)
284 *
285 */
lps22hh_pressure_snap_get(const stmdev_ctx_t * ctx,uint8_t * val)286 int32_t lps22hh_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val)
287 {
288 lps22hh_interrupt_cfg_t reg;
289 int32_t ret;
290
291 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
292 *val = reg.autorefp;
293
294 return ret;
295 }
296
297 /**
298 * @brief Block Data Update.[set]
299 *
300 * @param ctx read / write interface definitions
301 * @param val change the values of bdu in reg CTRL_REG1
302 * @retval interface status (MANDATORY: return 0 -> no Error)
303 *
304 */
lps22hh_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)305 int32_t lps22hh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
306 {
307 lps22hh_ctrl_reg1_t reg;
308 int32_t ret;
309
310 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
311
312 if (ret == 0)
313 {
314 reg.bdu = val;
315 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
316 }
317
318 return ret;
319 }
320
321 /**
322 * @brief Block Data Update.[get]
323 *
324 * @param ctx read / write interface definitions
325 * @param val change the values of bdu in reg CTRL_REG1
326 * @retval interface status (MANDATORY: return 0 -> no Error)
327 *
328 */
lps22hh_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)329 int32_t lps22hh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
330 {
331 lps22hh_ctrl_reg1_t reg;
332 int32_t ret;
333
334 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
335 *val = reg.bdu;
336
337 return ret;
338 }
339
340 /**
341 * @brief Output data rate selection.[set]
342 *
343 * @param ctx read / write interface definitions
344 * @param val change the values of odr in reg CTRL_REG1
345 * @retval interface status (MANDATORY: return 0 -> no Error)
346 *
347 */
lps22hh_data_rate_set(const stmdev_ctx_t * ctx,lps22hh_odr_t val)348 int32_t lps22hh_data_rate_set(const stmdev_ctx_t *ctx, lps22hh_odr_t val)
349 {
350 lps22hh_ctrl_reg1_t ctrl_reg1;
351 lps22hh_ctrl_reg2_t ctrl_reg2;
352 int32_t ret;
353
354 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
355
356 if (ret == 0)
357 {
358 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
359 }
360
361 if (ret == 0)
362 {
363 ctrl_reg1.odr = (uint8_t)val & 0x07U;
364 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
365 }
366
367 if (ret == 0)
368 {
369 ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
370 ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
371 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
372 }
373
374 return ret;
375 }
376
377 /**
378 * @brief Output data rate selection.[get]
379 *
380 * @param ctx read / write interface definitions
381 * @param val Get the values of odr in reg CTRL_REG1
382 * @retval interface status (MANDATORY: return 0 -> no Error)
383 *
384 */
lps22hh_data_rate_get(const stmdev_ctx_t * ctx,lps22hh_odr_t * val)385 int32_t lps22hh_data_rate_get(const stmdev_ctx_t *ctx, lps22hh_odr_t *val)
386 {
387 lps22hh_ctrl_reg1_t ctrl_reg1;
388 lps22hh_ctrl_reg2_t ctrl_reg2;
389 int32_t ret;
390
391 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
392
393 if (ret == 0)
394 {
395 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
396 }
397
398 if (ret == 0)
399 {
400 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
401
402 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
403 ctrl_reg1.odr))
404 {
405 case LPS22HH_POWER_DOWN:
406 *val = LPS22HH_POWER_DOWN;
407 break;
408
409 case LPS22HH_ONE_SHOOT:
410 *val = LPS22HH_ONE_SHOOT;
411 break;
412
413 case LPS22HH_1_Hz:
414 *val = LPS22HH_1_Hz;
415 break;
416
417 case LPS22HH_10_Hz:
418 *val = LPS22HH_10_Hz;
419 break;
420
421 case LPS22HH_25_Hz:
422 *val = LPS22HH_25_Hz;
423 break;
424
425 case LPS22HH_50_Hz:
426 *val = LPS22HH_50_Hz;
427 break;
428
429 case LPS22HH_75_Hz:
430 *val = LPS22HH_75_Hz;
431 break;
432
433 case LPS22HH_1_Hz_LOW_NOISE:
434 *val = LPS22HH_1_Hz_LOW_NOISE;
435 break;
436
437 case LPS22HH_10_Hz_LOW_NOISE:
438 *val = LPS22HH_10_Hz_LOW_NOISE;
439 break;
440
441 case LPS22HH_25_Hz_LOW_NOISE:
442 *val = LPS22HH_25_Hz_LOW_NOISE;
443 break;
444
445 case LPS22HH_50_Hz_LOW_NOISE:
446 *val = LPS22HH_50_Hz_LOW_NOISE;
447 break;
448
449 case LPS22HH_75_Hz_LOW_NOISE:
450 *val = LPS22HH_75_Hz_LOW_NOISE;
451 break;
452
453 case LPS22HH_100_Hz:
454 *val = LPS22HH_100_Hz;
455 break;
456
457 case LPS22HH_200_Hz:
458 *val = LPS22HH_200_Hz;
459 break;
460
461 default:
462 *val = LPS22HH_POWER_DOWN;
463 break;
464 }
465 }
466
467 return ret;
468 }
469
470 /**
471 * @brief The Reference pressure value is a 16-bit data
472 * expressed as 2's complement. The value is used
473 * when AUTOZERO or AUTORIFP function is enabled.[set]
474 *
475 * @param ctx read / write interface definitions
476 * @param buff buffer that contains data to write
477 * @retval interface status (MANDATORY: return 0 -> no Error)
478 *
479 */
lps22hh_pressure_ref_set(const stmdev_ctx_t * ctx,int16_t val)480 int32_t lps22hh_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val)
481 {
482 uint8_t buff[2];
483 int32_t ret;
484
485 buff[1] = (uint8_t)((uint16_t)val / 256U);
486 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
487 ret = lps22hh_write_reg(ctx, LPS22HH_REF_P_L, buff, 2);
488
489 return ret;
490 }
491
492 /**
493 * @brief The Reference pressure value is a 16-bit
494 * data expressed as 2's complement.
495 * The value is used when AUTOZERO or AUTORIFP
496 * function is enabled.[get]
497 *
498 * @param ctx read / write interface definitions
499 * @param buff buffer that stores data read
500 * @retval interface status (MANDATORY: return 0 -> no Error)
501 *
502 */
lps22hh_pressure_ref_get(const stmdev_ctx_t * ctx,int16_t * val)503 int32_t lps22hh_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val)
504 {
505 uint8_t buff[2];
506 int32_t ret;
507
508 ret = lps22hh_read_reg(ctx, LPS22HH_REF_P_L, buff, 2);
509 *val = (int16_t)buff[1];
510 *val = (*val * 256) + (int16_t)buff[0];
511
512 return ret;
513 }
514
515 /**
516 * @brief The pressure offset value is 16-bit data
517 * that can be used to implement one-point
518 * calibration (OPC) after soldering.[set]
519 *
520 * @param ctx read / write interface definitions
521 * @param buff buffer that contains data to write
522 * @retval interface status (MANDATORY: return 0 -> no Error)
523 *
524 */
lps22hh_pressure_offset_set(const stmdev_ctx_t * ctx,int16_t val)525 int32_t lps22hh_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val)
526 {
527 uint8_t buff[2];
528 int32_t ret;
529
530 buff[1] = (uint8_t)((uint16_t)val / 256U);
531 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
532 ret = lps22hh_write_reg(ctx, LPS22HH_RPDS_L, buff, 2);
533
534 return ret;
535 }
536
537 /**
538 * @brief The pressure offset value is 16-bit
539 * data that can be used to implement
540 * one-point calibration (OPC) after
541 * soldering.[get]
542 *
543 * @param ctx read / write interface definitions
544 * @param buff buffer that stores data read
545 * @retval interface status (MANDATORY: return 0 -> no Error)
546 *
547 */
lps22hh_pressure_offset_get(const stmdev_ctx_t * ctx,int16_t * val)548 int32_t lps22hh_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
549 {
550 uint8_t buff[2];
551 int32_t ret;
552
553 ret = lps22hh_read_reg(ctx, LPS22HH_RPDS_L, buff, 2);
554 *val = (int16_t)buff[1];
555 *val = (*val * 256) + (int16_t)buff[0];
556
557 return ret;
558 }
559
560 /**
561 * @brief Read all the interrupt/status flag of the device.[get]
562 *
563 * @param ctx read / write interface definitions
564 * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
565 * @retval interface status (MANDATORY: return 0 -> no Error)
566 *
567 */
lps22hh_all_sources_get(const stmdev_ctx_t * ctx,lps22hh_all_sources_t * val)568 int32_t lps22hh_all_sources_get(const stmdev_ctx_t *ctx,
569 lps22hh_all_sources_t *val)
570 {
571 int32_t ret;
572
573 ret = lps22hh_read_reg(ctx, LPS22HH_INT_SOURCE,
574 (uint8_t *) & (val->int_source), 1);
575
576 if (ret == 0)
577 {
578 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2,
579 (uint8_t *) & (val->fifo_status2), 1);
580 }
581
582 if (ret == 0)
583 {
584 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS,
585 (uint8_t *) & (val->status), 1);
586 }
587
588 return ret;
589 }
590
591 /**
592 * @brief The STATUS_REG register is read by the primary interface.[get]
593 *
594 * @param ctx read / write interface definitions
595 * @param val structure of registers from STATUS to STATUS_REG
596 * @retval interface status (MANDATORY: return 0 -> no Error)
597 *
598 */
lps22hh_status_reg_get(const stmdev_ctx_t * ctx,lps22hh_status_t * val)599 int32_t lps22hh_status_reg_get(const stmdev_ctx_t *ctx,
600 lps22hh_status_t *val)
601 {
602 int32_t ret;
603
604 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) val, 1);
605
606 return ret;
607 }
608
609 /**
610 * @brief Pressure new data available.[get]
611 *
612 * @param ctx read / write interface definitions
613 * @param val change the values of p_da in reg STATUS
614 * @retval interface status (MANDATORY: return 0 -> no Error)
615 *
616 */
lps22hh_press_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)617 int32_t lps22hh_press_flag_data_ready_get(const stmdev_ctx_t *ctx,
618 uint8_t *val)
619 {
620 lps22hh_status_t reg;
621 int32_t ret;
622
623 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1);
624 *val = reg.p_da;
625
626 return ret;
627 }
628
629 /**
630 * @brief Temperature data available.[get]
631 *
632 * @param ctx read / write interface definitions
633 * @param val change the values of t_da in reg STATUS
634 * @retval interface status (MANDATORY: return 0 -> no Error)
635 *
636 */
lps22hh_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)637 int32_t lps22hh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
638 uint8_t *val)
639 {
640 lps22hh_status_t reg;
641 int32_t ret;
642
643 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1);
644 *val = reg.t_da;
645
646 return ret;
647 }
648
649 /**
650 * @}
651 *
652 */
653
654 /**
655 * @defgroup LPS22HH_Data_Output
656 * @brief This section groups all the data output functions.
657 * @{
658 *
659 */
660
661 /**
662 * @brief Pressure output value.[get]
663 *
664 * @param ctx read / write interface definitions
665 * @param buff buffer that stores data read
666 * @retval interface status (MANDATORY: return 0 -> no Error)
667 *
668 */
lps22hh_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)669 int32_t lps22hh_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
670 {
671 int32_t ret;
672
673 uint8_t reg[3];
674 ret = lps22hh_read_reg(ctx, LPS22HH_PRESS_OUT_XL, reg, 3);
675 *buff = reg[2];
676 *buff = (*buff * 256U) + reg[1];
677 *buff = (*buff * 256U) + reg[0];
678 *buff *= 256U;
679
680 return ret;
681 }
682
683 /**
684 * @brief Temperature output value.[get]
685 *
686 * @param ctx read / write interface definitions
687 * @param buff buffer that stores data read
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lps22hh_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)691 int32_t lps22hh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
692 {
693 int32_t ret;
694 uint8_t reg[2];
695
696 ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, reg, 2);
697 *buff = (int16_t)reg[1];
698 *buff = (*buff * 256) + (int16_t)reg[0];
699
700 return ret;
701 }
702
703 /**
704 * @brief Pressure output from FIFO value.[get]
705 *
706 * @param ctx read / write interface definitions
707 * @param buff buffer that stores data read
708 * @retval interface status (MANDATORY: return 0 -> no Error)
709 *
710 */
lps22hh_fifo_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)711 int32_t lps22hh_fifo_pressure_raw_get(const stmdev_ctx_t *ctx,
712 uint32_t *buff)
713 {
714 int32_t ret;
715
716 uint8_t reg[3];
717 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, reg, 3);
718 *buff = reg[2];
719 *buff = (*buff * 256U) + reg[1];
720 *buff = (*buff * 256U) + reg[0];
721 *buff *= 256U;
722
723 return ret;
724 }
725
726 /**
727 * @brief Temperature output from FIFO value.[get]
728 *
729 * @param ctx read / write interface definitions
730 * @param buff buffer that stores data read
731 * @retval interface status (MANDATORY: return 0 -> no Error)
732 *
733 */
lps22hh_fifo_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)734 int32_t lps22hh_fifo_temperature_raw_get(const stmdev_ctx_t *ctx,
735 int16_t *buff)
736 {
737 int32_t ret;
738
739 uint8_t reg[2];
740 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, reg, 2);
741 *buff = (int16_t)reg[1];
742 *buff = (*buff * 256) + (int16_t)reg[0];
743
744 return ret;
745 }
746
747 /**
748 * @}
749 *
750 */
751
752 /**
753 * @defgroup LPS22HH_Common
754 * @brief This section groups common useful functions.
755 * @{
756 *
757 */
758
759 /**
760 * @brief DeviceWhoamI[get]
761 *
762 * @param ctx read / write interface definitions
763 * @param buff buffer that stores data read
764 * @retval interface status (MANDATORY: return 0 -> no Error)
765 *
766 */
lps22hh_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)767 int32_t lps22hh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
768 {
769 int32_t ret;
770
771 ret = lps22hh_read_reg(ctx, LPS22HH_WHO_AM_I, buff, 1);
772
773 return ret;
774 }
775
776 /**
777 * @brief Software reset. Restore the default values
778 * in user registers.[set]
779 *
780 * @param ctx read / write interface definitions
781 * @param val change the values of swreset in reg CTRL_REG2
782 * @retval interface status (MANDATORY: return 0 -> no Error)
783 *
784 */
lps22hh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)785 int32_t lps22hh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
786 {
787 lps22hh_ctrl_reg2_t reg;
788 int32_t ret;
789
790 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
791
792 if (ret == 0)
793 {
794 reg.swreset = val;
795 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
796 }
797
798 return ret;
799 }
800
801 /**
802 * @brief Software reset. Restore the default values
803 * in user registers.[get]
804 *
805 * @param ctx read / write interface definitions
806 * @param val change the values of swreset in reg CTRL_REG2
807 * @retval interface status (MANDATORY: return 0 -> no Error)
808 *
809 */
lps22hh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)810 int32_t lps22hh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
811 {
812 lps22hh_ctrl_reg2_t reg;
813 int32_t ret;
814
815 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
816 *val = reg.swreset;
817
818 return ret;
819 }
820
821 /**
822 * @brief Register address automatically
823 * incremented during a multiple byte access
824 * with a serial interface.[set]
825 *
826 * @param ctx read / write interface definitions
827 * @param val change the values of if_add_inc in reg CTRL_REG2
828 * @retval interface status (MANDATORY: return 0 -> no Error)
829 *
830 */
lps22hh_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)831 int32_t lps22hh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
832 {
833 lps22hh_ctrl_reg2_t reg;
834 int32_t ret;
835
836 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
837
838 if (ret == 0)
839 {
840 reg.if_add_inc = val;
841 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
842 }
843
844 return ret;
845 }
846
847 /**
848 * @brief Register address automatically
849 * incremented during a multiple byte
850 * access with a serial interface.[get]
851 *
852 * @param ctx read / write interface definitions
853 * @param val change the values of if_add_inc in reg CTRL_REG2
854 * @retval interface status (MANDATORY: return 0 -> no Error)
855 *
856 */
lps22hh_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)857 int32_t lps22hh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
858 {
859 lps22hh_ctrl_reg2_t reg;
860 int32_t ret;
861
862 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
863 *val = reg.if_add_inc;
864
865 return ret;
866 }
867
868 /**
869 * @brief Reboot memory content. Reload the calibration
870 * parameters.[set]
871 *
872 * @param ctx read / write interface definitions
873 * @param val change the values of boot in reg CTRL_REG2
874 * @retval interface status (MANDATORY: return 0 -> no Error)
875 *
876 */
lps22hh_boot_set(const stmdev_ctx_t * ctx,uint8_t val)877 int32_t lps22hh_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
878 {
879 lps22hh_ctrl_reg2_t reg;
880 int32_t ret;
881
882 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
883
884 if (ret == 0)
885 {
886 reg.boot = val;
887 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
888 }
889
890 return ret;
891 }
892
893 /**
894 * @brief Reboot memory content. Reload the calibration
895 * parameters.[get]
896 *
897 * @param ctx read / write interface definitions
898 * @param val change the values of boot in reg CTRL_REG2
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
lps22hh_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)902 int32_t lps22hh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
903 {
904 lps22hh_ctrl_reg2_t reg;
905 int32_t ret;
906
907 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
908 *val = reg.boot;
909
910 return ret;
911 }
912
913 /**
914 * @}
915 *
916 */
917
918 /**
919 * @defgroup LPS22HH_Filters
920 * @brief This section group all the functions concerning the
921 * filters configuration.
922 * @{
923 *
924 */
925
926 /**
927 * @brief Low-pass bandwidth selection.[set]
928 *
929 * @param ctx read / write interface definitions
930 * @param val change the values of lpfp_cfg in reg CTRL_REG1
931 * @retval interface status (MANDATORY: return 0 -> no Error)
932 *
933 */
lps22hh_lp_bandwidth_set(const stmdev_ctx_t * ctx,lps22hh_lpfp_cfg_t val)934 int32_t lps22hh_lp_bandwidth_set(const stmdev_ctx_t *ctx,
935 lps22hh_lpfp_cfg_t val)
936 {
937 lps22hh_ctrl_reg1_t reg;
938 int32_t ret;
939
940 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
941
942 if (ret == 0)
943 {
944 reg.lpfp_cfg = (uint8_t)val;
945 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
946 }
947
948 return ret;
949 }
950
951 /**
952 * @brief Low-pass bandwidth selection.[get]
953 *
954 * @param ctx read / write interface definitions
955 * @param val Get the values of lpfp_cfg in reg CTRL_REG1
956 * @retval interface status (MANDATORY: return 0 -> no Error)
957 *
958 */
lps22hh_lp_bandwidth_get(const stmdev_ctx_t * ctx,lps22hh_lpfp_cfg_t * val)959 int32_t lps22hh_lp_bandwidth_get(const stmdev_ctx_t *ctx,
960 lps22hh_lpfp_cfg_t *val)
961 {
962 lps22hh_ctrl_reg1_t reg;
963 int32_t ret;
964
965 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
966
967 switch (reg.lpfp_cfg)
968 {
969 case LPS22HH_LPF_ODR_DIV_2:
970 *val = LPS22HH_LPF_ODR_DIV_2;
971 break;
972
973 case LPS22HH_LPF_ODR_DIV_9:
974 *val = LPS22HH_LPF_ODR_DIV_9;
975 break;
976
977 case LPS22HH_LPF_ODR_DIV_20:
978 *val = LPS22HH_LPF_ODR_DIV_20;
979 break;
980
981 default:
982 *val = LPS22HH_LPF_ODR_DIV_2;
983 break;
984 }
985
986 return ret;
987 }
988
989 /**
990 * @}
991 *
992 */
993
994 /**
995 * @defgroup LPS22HH_Serial_Interface
996 * @brief This section groups all the functions concerning serial
997 * interface management
998 * @{
999 *
1000 */
1001
1002 /**
1003 * @brief Enable/Disable I2C interface.[set]
1004 *
1005 * @param ctx read / write interface definitions
1006 * @param val change the values of i2c_disable in reg IF_CTRL
1007 * @retval interface status (MANDATORY: return 0 -> no Error)
1008 *
1009 */
lps22hh_i2c_interface_set(const stmdev_ctx_t * ctx,lps22hh_i2c_disable_t val)1010 int32_t lps22hh_i2c_interface_set(const stmdev_ctx_t *ctx,
1011 lps22hh_i2c_disable_t val)
1012 {
1013 lps22hh_if_ctrl_t reg;
1014 int32_t ret;
1015
1016 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1017
1018 if (ret == 0)
1019 {
1020 reg.i2c_disable = (uint8_t)val;
1021 ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1022 }
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Enable/Disable I2C interface.[get]
1029 *
1030 * @param ctx read / write interface definitions
1031 * @param val Get the values of i2c_disable in reg IF_CTRL
1032 * @retval interface status (MANDATORY: return 0 -> no Error)
1033 *
1034 */
lps22hh_i2c_interface_get(const stmdev_ctx_t * ctx,lps22hh_i2c_disable_t * val)1035 int32_t lps22hh_i2c_interface_get(const stmdev_ctx_t *ctx,
1036 lps22hh_i2c_disable_t *val)
1037 {
1038 lps22hh_if_ctrl_t reg;
1039 int32_t ret;
1040
1041 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1042
1043 switch (reg.i2c_disable)
1044 {
1045 case LPS22HH_I2C_ENABLE:
1046 *val = LPS22HH_I2C_ENABLE;
1047 break;
1048
1049 case LPS22HH_I2C_DISABLE:
1050 *val = LPS22HH_I2C_DISABLE;
1051 break;
1052
1053 default:
1054 *val = LPS22HH_I2C_ENABLE;
1055 break;
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @brief I3C Enable/Disable communication protocol.[set]
1063 *
1064 * @param ctx read / write interface definitions
1065 * @param val change the values of int_en_i3c in reg IF_CTRL
1066 * @retval interface status (MANDATORY: return 0 -> no Error)
1067 *
1068 */
lps22hh_i3c_interface_set(const stmdev_ctx_t * ctx,lps22hh_i3c_disable_t val)1069 int32_t lps22hh_i3c_interface_set(const stmdev_ctx_t *ctx,
1070 lps22hh_i3c_disable_t val)
1071 {
1072 lps22hh_if_ctrl_t reg;
1073 int32_t ret;
1074
1075 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1076
1077 if (ret == 0)
1078 {
1079 reg.i3c_disable = ((uint8_t)val & 0x01u);
1080 reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4;
1081 ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1082 }
1083
1084 return ret;
1085 }
1086
1087 /**
1088 * @brief I3C Enable/Disable communication protocol.[get]
1089 *
1090 * @param ctx read / write interface definitions
1091 * @param val change the values of int_en_i3c in reg IF_CTRL
1092 * @retval interface status (MANDATORY: return 0 -> no Error)
1093 *
1094 */
lps22hh_i3c_interface_get(const stmdev_ctx_t * ctx,lps22hh_i3c_disable_t * val)1095 int32_t lps22hh_i3c_interface_get(const stmdev_ctx_t *ctx,
1096 lps22hh_i3c_disable_t *val)
1097 {
1098 lps22hh_if_ctrl_t reg;
1099 int32_t ret;
1100
1101 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1102
1103 switch ((reg.int_en_i3c << 4) + reg.int_en_i3c)
1104 {
1105 case LPS22HH_I3C_ENABLE:
1106 *val = LPS22HH_I3C_ENABLE;
1107 break;
1108
1109 case LPS22HH_I3C_ENABLE_INT_PIN_ENABLE:
1110 *val = LPS22HH_I3C_ENABLE_INT_PIN_ENABLE;
1111 break;
1112
1113 case LPS22HH_I3C_DISABLE:
1114 *val = LPS22HH_I3C_DISABLE;
1115 break;
1116
1117 default:
1118 *val = LPS22HH_I3C_ENABLE;
1119 break;
1120 }
1121
1122 return ret;
1123 }
1124
1125 /**
1126 * @brief Enable/Disable pull-up on SDO pin.[set]
1127 *
1128 * @param ctx read / write interface definitions
1129 * @param val change the values of sdo_pu_en in reg IF_CTRL
1130 * @retval interface status (MANDATORY: return 0 -> no Error)
1131 *
1132 */
lps22hh_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lps22hh_pu_en_t val)1133 int32_t lps22hh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
1134 lps22hh_pu_en_t val)
1135 {
1136 lps22hh_if_ctrl_t reg;
1137 int32_t ret;
1138
1139 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1140
1141 if (ret == 0)
1142 {
1143 reg.sdo_pu_en = (uint8_t)val;
1144 ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1145 }
1146
1147 return ret;
1148 }
1149
1150 /**
1151 * @brief Enable/Disable pull-up on SDO pin.[get]
1152 *
1153 * @param ctx read / write interface definitions
1154 * @param val Get the values of sdo_pu_en in reg IF_CTRL
1155 * @retval interface status (MANDATORY: return 0 -> no Error)
1156 *
1157 */
lps22hh_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lps22hh_pu_en_t * val)1158 int32_t lps22hh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
1159 lps22hh_pu_en_t *val)
1160 {
1161 lps22hh_if_ctrl_t reg;
1162 int32_t ret;
1163
1164 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1165
1166 switch (reg.sdo_pu_en)
1167 {
1168 case LPS22HH_PULL_UP_DISCONNECT:
1169 *val = LPS22HH_PULL_UP_DISCONNECT;
1170 break;
1171
1172 case LPS22HH_PULL_UP_CONNECT:
1173 *val = LPS22HH_PULL_UP_CONNECT;
1174 break;
1175
1176 default:
1177 *val = LPS22HH_PULL_UP_DISCONNECT;
1178 break;
1179 }
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
1186 *
1187 * @param ctx read / write interface definitions
1188 * @param val change the values of sda_pu_en in reg IF_CTRL
1189 * @retval interface status (MANDATORY: return 0 -> no Error)
1190 *
1191 */
lps22hh_sda_mode_set(const stmdev_ctx_t * ctx,lps22hh_pu_en_t val)1192 int32_t lps22hh_sda_mode_set(const stmdev_ctx_t *ctx, lps22hh_pu_en_t val)
1193 {
1194 lps22hh_if_ctrl_t reg;
1195 int32_t ret;
1196
1197 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1198
1199 if (ret == 0)
1200 {
1201 reg.sda_pu_en = (uint8_t)val;
1202 ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1203 }
1204
1205 return ret;
1206 }
1207
1208 /**
1209 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
1210 *
1211 * @param ctx read / write interface definitions
1212 * @param val Get the values of sda_pu_en in reg IF_CTRL
1213 * @retval interface status (MANDATORY: return 0 -> no Error)
1214 *
1215 */
lps22hh_sda_mode_get(const stmdev_ctx_t * ctx,lps22hh_pu_en_t * val)1216 int32_t lps22hh_sda_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val)
1217 {
1218 lps22hh_if_ctrl_t reg;
1219 int32_t ret;
1220
1221 ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1);
1222
1223 switch (reg.sda_pu_en)
1224 {
1225 case LPS22HH_PULL_UP_DISCONNECT:
1226 *val = LPS22HH_PULL_UP_DISCONNECT;
1227 break;
1228
1229 case LPS22HH_PULL_UP_CONNECT:
1230 *val = LPS22HH_PULL_UP_CONNECT;
1231 break;
1232
1233 default:
1234 *val = LPS22HH_PULL_UP_DISCONNECT;
1235 break;
1236 }
1237
1238 return ret;
1239 }
1240
1241 /**
1242 * @brief SPI Serial Interface Mode selection.[set]
1243 *
1244 * @param ctx read / write interface definitions
1245 * @param val change the values of sim in reg CTRL_REG1
1246 * @retval interface status (MANDATORY: return 0 -> no Error)
1247 *
1248 */
lps22hh_spi_mode_set(const stmdev_ctx_t * ctx,lps22hh_sim_t val)1249 int32_t lps22hh_spi_mode_set(const stmdev_ctx_t *ctx, lps22hh_sim_t val)
1250 {
1251 lps22hh_ctrl_reg1_t reg;
1252 int32_t ret;
1253
1254 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
1255
1256 if (ret == 0)
1257 {
1258 reg.sim = (uint8_t)val;
1259 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
1260 }
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief SPI Serial Interface Mode selection.[get]
1267 *
1268 * @param ctx read / write interface definitions
1269 * @param val Get the values of sim in reg CTRL_REG1
1270 * @retval interface status (MANDATORY: return 0 -> no Error)
1271 *
1272 */
lps22hh_spi_mode_get(const stmdev_ctx_t * ctx,lps22hh_sim_t * val)1273 int32_t lps22hh_spi_mode_get(const stmdev_ctx_t *ctx, lps22hh_sim_t *val)
1274 {
1275 lps22hh_ctrl_reg1_t reg;
1276 int32_t ret;
1277
1278 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1);
1279
1280 switch (reg.sim)
1281 {
1282 case LPS22HH_SPI_4_WIRE:
1283 *val = LPS22HH_SPI_4_WIRE;
1284 break;
1285
1286 case LPS22HH_SPI_3_WIRE:
1287 *val = LPS22HH_SPI_3_WIRE;
1288 break;
1289
1290 default:
1291 *val = LPS22HH_SPI_4_WIRE;
1292 break;
1293 }
1294
1295 return ret;
1296 }
1297
1298 /**
1299 * @}
1300 *
1301 */
1302
1303 /**
1304 * @defgroup LPS22HH_Interrupt_Pins
1305 * @brief This section groups all the functions that manage
1306 * interrupt pins.
1307 * @{
1308 *
1309 */
1310
1311 /**
1312 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
1313 *
1314 * @param ctx read / write interface definitions
1315 * @param val change the values of lir in reg INTERRUPT_CFG
1316 * @retval interface status (MANDATORY: return 0 -> no Error)
1317 *
1318 */
lps22hh_int_notification_set(const stmdev_ctx_t * ctx,lps22hh_lir_t val)1319 int32_t lps22hh_int_notification_set(const stmdev_ctx_t *ctx,
1320 lps22hh_lir_t val)
1321 {
1322 lps22hh_interrupt_cfg_t reg;
1323 int32_t ret;
1324
1325 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1326
1327 if (ret == 0)
1328 {
1329 reg.lir = (uint8_t)val;
1330 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1331 }
1332
1333 return ret;
1334 }
1335
1336 /**
1337 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
1338 *
1339 * @param ctx read / write interface definitions
1340 * @param val Get the values of lir in reg INTERRUPT_CFG
1341 * @retval interface status (MANDATORY: return 0 -> no Error)
1342 *
1343 */
lps22hh_int_notification_get(const stmdev_ctx_t * ctx,lps22hh_lir_t * val)1344 int32_t lps22hh_int_notification_get(const stmdev_ctx_t *ctx,
1345 lps22hh_lir_t *val)
1346 {
1347 lps22hh_interrupt_cfg_t reg;
1348 int32_t ret;
1349
1350 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1351
1352 switch (reg.lir)
1353 {
1354 case LPS22HH_INT_PULSED:
1355 *val = LPS22HH_INT_PULSED;
1356 break;
1357
1358 case LPS22HH_INT_LATCHED:
1359 *val = LPS22HH_INT_LATCHED;
1360 break;
1361
1362 default:
1363 *val = LPS22HH_INT_PULSED;
1364 break;
1365 }
1366
1367 return ret;
1368 }
1369
1370 /**
1371 * @brief Push-pull/open drain selection on interrupt pads.[set]
1372 *
1373 * @param ctx read / write interface definitions
1374 * @param val change the values of pp_od in reg CTRL_REG2
1375 * @retval interface status (MANDATORY: return 0 -> no Error)
1376 *
1377 */
lps22hh_pin_mode_set(const stmdev_ctx_t * ctx,lps22hh_pp_od_t val)1378 int32_t lps22hh_pin_mode_set(const stmdev_ctx_t *ctx, lps22hh_pp_od_t val)
1379 {
1380 lps22hh_ctrl_reg2_t reg;
1381 int32_t ret;
1382
1383 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1384
1385 if (ret == 0)
1386 {
1387 reg.pp_od = (uint8_t)val;
1388 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1389 }
1390
1391 return ret;
1392 }
1393
1394 /**
1395 * @brief Push-pull/open drain selection on interrupt pads.[get]
1396 *
1397 * @param ctx read / write interface definitions
1398 * @param val Get the values of pp_od in reg CTRL_REG2
1399 * @retval interface status (MANDATORY: return 0 -> no Error)
1400 *
1401 */
lps22hh_pin_mode_get(const stmdev_ctx_t * ctx,lps22hh_pp_od_t * val)1402 int32_t lps22hh_pin_mode_get(const stmdev_ctx_t *ctx, lps22hh_pp_od_t *val)
1403 {
1404 lps22hh_ctrl_reg2_t reg;
1405 int32_t ret;
1406
1407 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1408
1409 switch (reg.pp_od)
1410 {
1411 case LPS22HH_PUSH_PULL:
1412 *val = LPS22HH_PUSH_PULL;
1413 break;
1414
1415 case LPS22HH_OPEN_DRAIN:
1416 *val = LPS22HH_OPEN_DRAIN;
1417 break;
1418
1419 default:
1420 *val = LPS22HH_PUSH_PULL;
1421 break;
1422 }
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief Interrupt active-high/low.[set]
1429 *
1430 * @param ctx read / write interface definitions
1431 * @param val change the values of int_h_l in reg CTRL_REG2
1432 * @retval interface status (MANDATORY: return 0 -> no Error)
1433 *
1434 */
lps22hh_pin_polarity_set(const stmdev_ctx_t * ctx,lps22hh_int_h_l_t val)1435 int32_t lps22hh_pin_polarity_set(const stmdev_ctx_t *ctx,
1436 lps22hh_int_h_l_t val)
1437 {
1438 lps22hh_ctrl_reg2_t reg;
1439 int32_t ret;
1440
1441 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1442
1443 if (ret == 0)
1444 {
1445 reg.int_h_l = (uint8_t)val;
1446 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1447 }
1448
1449 return ret;
1450 }
1451
1452 /**
1453 * @brief Interrupt active-high/low.[get]
1454 *
1455 * @param ctx read / write interface definitions
1456 * @param val Get the values of int_h_l in reg CTRL_REG2
1457 * @retval interface status (MANDATORY: return 0 -> no Error)
1458 *
1459 */
lps22hh_pin_polarity_get(const stmdev_ctx_t * ctx,lps22hh_int_h_l_t * val)1460 int32_t lps22hh_pin_polarity_get(const stmdev_ctx_t *ctx,
1461 lps22hh_int_h_l_t *val)
1462 {
1463 lps22hh_ctrl_reg2_t reg;
1464 int32_t ret;
1465
1466 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1);
1467
1468 switch (reg.int_h_l)
1469 {
1470 case LPS22HH_ACTIVE_HIGH:
1471 *val = LPS22HH_ACTIVE_HIGH;
1472 break;
1473
1474 case LPS22HH_ACTIVE_LOW:
1475 *val = LPS22HH_ACTIVE_LOW;
1476 break;
1477
1478 default:
1479 *val = LPS22HH_ACTIVE_HIGH;
1480 break;
1481 }
1482
1483 return ret;
1484 }
1485
1486 /**
1487 * @brief Route interrupt signals on int1 pin.[set]
1488 *
1489 * @param ctx communication interface handler.(ptr)
1490 * @param val the signals to route on int1 pin.(ptr)
1491 * @retval interface status (MANDATORY: return 0 -> no Error)
1492 *
1493 */
lps22hh_pin_int_route_set(const stmdev_ctx_t * ctx,lps22hh_pin_int_route_t * val)1494 int32_t lps22hh_pin_int_route_set(const stmdev_ctx_t *ctx,
1495 lps22hh_pin_int_route_t *val)
1496 {
1497 lps22hh_ctrl_reg3_t ctrl_reg3;
1498 int32_t ret;
1499
1500 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1501 if (ret == 0)
1502 {
1503 ctrl_reg3.drdy = val->drdy_pres;
1504 ctrl_reg3.int_f_wtm = val->fifo_th;
1505 ctrl_reg3.int_f_ovr = val->fifo_ovr;
1506 ctrl_reg3.int_f_full = val->fifo_full;
1507
1508 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1509 }
1510 return ret;
1511 }
1512
1513 /**
1514 * @brief Route interrupt signals on int1 pin.[get]
1515 *
1516 * @param ctx communication interface handler.(ptr)
1517 * @param val the signals that are routed on int1 pin.(ptr)
1518 * @retval interface status (MANDATORY: return 0 -> no Error)
1519 *
1520 */
lps22hh_pin_int_route_get(const stmdev_ctx_t * ctx,lps22hh_pin_int_route_t * val)1521 int32_t lps22hh_pin_int_route_get(const stmdev_ctx_t *ctx,
1522 lps22hh_pin_int_route_t *val)
1523 {
1524 lps22hh_ctrl_reg3_t ctrl_reg3;
1525 int32_t ret;
1526
1527 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
1528
1529 val->drdy_pres = ctrl_reg3.drdy;
1530 val->fifo_th = ctrl_reg3.int_f_wtm;
1531 val->fifo_ovr = ctrl_reg3.int_f_ovr;
1532 val->fifo_full = ctrl_reg3.int_f_full;
1533
1534 return ret;
1535 }
1536
1537 /**
1538 * @}
1539 *
1540 */
1541
1542 /**
1543 * @defgroup LPS22HH_Interrupt_on_Threshold
1544 * @brief This section groups all the functions that manage the
1545 * interrupt on threshold event generation.
1546 * @{
1547 *
1548 */
1549
1550 /**
1551 * @brief Enable interrupt generation on pressure low/high event.[set]
1552 *
1553 * @param ctx read / write interface definitions
1554 * @param val change the values of pe in reg INTERRUPT_CFG
1555 * @retval interface status (MANDATORY: return 0 -> no Error)
1556 *
1557 */
lps22hh_int_on_threshold_set(const stmdev_ctx_t * ctx,lps22hh_pe_t val)1558 int32_t lps22hh_int_on_threshold_set(const stmdev_ctx_t *ctx,
1559 lps22hh_pe_t val)
1560 {
1561 lps22hh_interrupt_cfg_t reg;
1562 int32_t ret;
1563
1564 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1565
1566 if (ret == 0)
1567 {
1568 reg.pe = (uint8_t)val;
1569
1570 if (val == LPS22HH_NO_THRESHOLD)
1571 {
1572 reg.diff_en = PROPERTY_DISABLE;
1573 }
1574
1575 else
1576 {
1577 reg.diff_en = PROPERTY_ENABLE;
1578 }
1579
1580 ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1581 }
1582
1583 return ret;
1584 }
1585
1586 /**
1587 * @brief Enable interrupt generation on pressure low/high event.[get]
1588 *
1589 * @param ctx read / write interface definitions
1590 * @param val Get the values of pe in reg INTERRUPT_CFG
1591 * @retval interface status (MANDATORY: return 0 -> no Error)
1592 *
1593 */
lps22hh_int_on_threshold_get(const stmdev_ctx_t * ctx,lps22hh_pe_t * val)1594 int32_t lps22hh_int_on_threshold_get(const stmdev_ctx_t *ctx,
1595 lps22hh_pe_t *val)
1596 {
1597 lps22hh_interrupt_cfg_t reg;
1598 int32_t ret;
1599
1600 ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1601
1602 switch (reg.pe)
1603 {
1604 case LPS22HH_NO_THRESHOLD:
1605 *val = LPS22HH_NO_THRESHOLD;
1606 break;
1607
1608 case LPS22HH_POSITIVE:
1609 *val = LPS22HH_POSITIVE;
1610 break;
1611
1612 case LPS22HH_NEGATIVE:
1613 *val = LPS22HH_NEGATIVE;
1614 break;
1615
1616 case LPS22HH_BOTH:
1617 *val = LPS22HH_BOTH;
1618 break;
1619
1620 default:
1621 *val = LPS22HH_NO_THRESHOLD;
1622 break;
1623 }
1624
1625 return ret;
1626 }
1627
1628 /**
1629 * @brief User-defined threshold value for pressure interrupt event.[set]
1630 *
1631 * @param ctx read / write interface definitions
1632 * @param buff buffer that contains data to write
1633 * @retval interface status (MANDATORY: return 0 -> no Error)
1634 *
1635 */
lps22hh_int_threshold_set(const stmdev_ctx_t * ctx,uint16_t buff)1636 int32_t lps22hh_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff)
1637 {
1638 int32_t ret;
1639
1640 lps22hh_ths_p_l_t ths_p_l;
1641 lps22hh_ths_p_h_t ths_p_h;
1642 ths_p_h.ths = (uint8_t)(buff / 256U);
1643 ths_p_l.ths = (uint8_t)(buff - (ths_p_h.ths * 256U));
1644 ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_L,
1645 (uint8_t *)&ths_p_l, 1);
1646
1647 if (ret == 0)
1648 {
1649 ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_H,
1650 (uint8_t *)&ths_p_h, 1);
1651 }
1652
1653 return ret;
1654 }
1655
1656 /**
1657 * @brief User-defined threshold value for pressure interrupt event.[get]
1658 *
1659 * @param ctx read / write interface definitions
1660 * @param buff buffer that stores data read
1661 * @retval interface status (MANDATORY: return 0 -> no Error)
1662 *
1663 */
lps22hh_int_threshold_get(const stmdev_ctx_t * ctx,uint16_t * buff)1664 int32_t lps22hh_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff)
1665 {
1666 int32_t ret;
1667
1668 lps22hh_ths_p_l_t ths_p_l;
1669 lps22hh_ths_p_h_t ths_p_h;
1670 ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_L,
1671 (uint8_t *)&ths_p_l, 1);
1672
1673 if (ret == 0)
1674 {
1675 ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_H,
1676 (uint8_t *)&ths_p_h, 1);
1677 *buff = (uint16_t)ths_p_h.ths;
1678 *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths;
1679 }
1680
1681 return ret;
1682 }
1683
1684 /**
1685 * @}
1686 *
1687 */
1688
1689 /**
1690 * @defgroup LPS22HH_Fifo
1691 * @brief This section group all the functions concerning the fifo usage.
1692 * @{
1693 *
1694 */
1695
1696 /**
1697 * @brief Fifo Mode selection.[set]
1698 *
1699 * @param ctx read / write interface definitions
1700 * @param val change the values of f_mode in reg FIFO_CTRL
1701 * @retval interface status (MANDATORY: return 0 -> no Error)
1702 *
1703 */
lps22hh_fifo_mode_set(const stmdev_ctx_t * ctx,lps22hh_f_mode_t val)1704 int32_t lps22hh_fifo_mode_set(const stmdev_ctx_t *ctx, lps22hh_f_mode_t val)
1705 {
1706 lps22hh_fifo_ctrl_t reg;
1707 int32_t ret;
1708
1709 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1710
1711 if (ret == 0)
1712 {
1713 reg.f_mode = (uint8_t)val;
1714 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1715 }
1716
1717 return ret;
1718 }
1719
1720 /**
1721 * @brief Fifo Mode selection.[get]
1722 *
1723 * @param ctx read / write interface definitions
1724 * @param val Get the values of f_mode in reg FIFO_CTRL
1725 * @retval interface status (MANDATORY: return 0 -> no Error)
1726 *
1727 */
lps22hh_fifo_mode_get(const stmdev_ctx_t * ctx,lps22hh_f_mode_t * val)1728 int32_t lps22hh_fifo_mode_get(const stmdev_ctx_t *ctx,
1729 lps22hh_f_mode_t *val)
1730 {
1731 lps22hh_fifo_ctrl_t reg;
1732 int32_t ret;
1733
1734 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1735
1736 switch (reg.f_mode)
1737 {
1738 case LPS22HH_BYPASS_MODE:
1739 *val = LPS22HH_BYPASS_MODE;
1740 break;
1741
1742 case LPS22HH_FIFO_MODE:
1743 *val = LPS22HH_FIFO_MODE;
1744 break;
1745
1746 case LPS22HH_STREAM_MODE:
1747 *val = LPS22HH_STREAM_MODE;
1748 break;
1749
1750 case LPS22HH_DYNAMIC_STREAM_MODE:
1751 *val = LPS22HH_DYNAMIC_STREAM_MODE;
1752 break;
1753
1754 case LPS22HH_BYPASS_TO_FIFO_MODE:
1755 *val = LPS22HH_BYPASS_TO_FIFO_MODE;
1756 break;
1757
1758 case LPS22HH_BYPASS_TO_STREAM_MODE:
1759 *val = LPS22HH_BYPASS_TO_STREAM_MODE;
1760 break;
1761
1762 case LPS22HH_STREAM_TO_FIFO_MODE:
1763 *val = LPS22HH_STREAM_TO_FIFO_MODE;
1764 break;
1765
1766 default:
1767 *val = LPS22HH_BYPASS_MODE;
1768 break;
1769 }
1770
1771 return ret;
1772 }
1773
1774 /**
1775 * @brief Sensing chain FIFO stop values memorization at
1776 * threshold level.[set]
1777 *
1778 * @param ctx read / write interface definitions
1779 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1780 * @retval interface status (MANDATORY: return 0 -> no Error)
1781 *
1782 */
lps22hh_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)1783 int32_t lps22hh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
1784 {
1785 lps22hh_fifo_ctrl_t reg;
1786 int32_t ret;
1787
1788 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1789
1790 if (ret == 0)
1791 {
1792 reg.stop_on_wtm = val;
1793 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1794 }
1795
1796 return ret;
1797 }
1798
1799 /**
1800 * @brief Sensing chain FIFO stop values memorization at threshold
1801 * level.[get]
1802 *
1803 * @param ctx read / write interface definitions
1804 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1805 * @retval interface status (MANDATORY: return 0 -> no Error)
1806 *
1807 */
lps22hh_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)1808 int32_t lps22hh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
1809 {
1810 lps22hh_fifo_ctrl_t reg;
1811 int32_t ret;
1812
1813 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1);
1814 *val = reg.stop_on_wtm;
1815
1816 return ret;
1817 }
1818
1819 /**
1820 * @brief FIFO watermark level selection.[set]
1821 *
1822 * @param ctx read / write interface definitions
1823 * @param val change the values of wtm in reg FIFO_WTM
1824 * @retval interface status (MANDATORY: return 0 -> no Error)
1825 *
1826 */
lps22hh_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1827 int32_t lps22hh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1828 {
1829 lps22hh_fifo_wtm_t reg;
1830 int32_t ret;
1831
1832 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
1833
1834 if (ret == 0)
1835 {
1836 reg.wtm = val;
1837 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
1838 }
1839
1840 return ret;
1841 }
1842
1843 /**
1844 * @brief FIFO watermark level selection.[get]
1845 *
1846 * @param ctx read / write interface definitions
1847 * @param val change the values of wtm in reg FIFO_WTM
1848 * @retval interface status (MANDATORY: return 0 -> no Error)
1849 *
1850 */
lps22hh_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1851 int32_t lps22hh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1852 {
1853 lps22hh_fifo_wtm_t reg;
1854 int32_t ret;
1855
1856 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1);
1857 *val = reg.wtm;
1858
1859 return ret;
1860 }
1861
1862 /**
1863 * @brief FIFO stored data level.[get]
1864 *
1865 * @param ctx read / write interface definitions
1866 * @param num buffer that stores data read
1867 * @retval interface status (MANDATORY: return 0 -> no Error)
1868 *
1869 */
lps22hh_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * num)1870 int32_t lps22hh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *num)
1871 {
1872 int32_t ret;
1873
1874 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, num, 1);
1875
1876 return ret;
1877 }
1878
1879 /**
1880 * @brief Read all the FIFO status flag of the device.[get]
1881 *
1882 * @param ctx read / write interface definitions
1883 * @param val registers FIFO_STATUS2
1884 * @retval interface status (MANDATORY: return 0 -> no Error)
1885 *
1886 */
lps22hh_fifo_src_get(const stmdev_ctx_t * ctx,lps22hh_fifo_status2_t * val)1887 int32_t lps22hh_fifo_src_get(const stmdev_ctx_t *ctx,
1888 lps22hh_fifo_status2_t *val)
1889 {
1890 int32_t ret;
1891
1892 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) val, 1);
1893
1894 return ret;
1895 }
1896
1897 /**
1898 * @brief Smart FIFO full status.[get]
1899 *
1900 * @param ctx read / write interface definitions
1901 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
1902 * @retval interface status (MANDATORY: return 0 -> no Error)
1903 *
1904 */
lps22hh_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1905 int32_t lps22hh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1906 {
1907 lps22hh_fifo_status2_t reg;
1908 int32_t ret;
1909
1910 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1);
1911 *val = reg.fifo_full_ia;
1912
1913 return ret;
1914 }
1915
1916 /**
1917 * @brief FIFO overrun status.[get]
1918 *
1919 * @param ctx read / write interface definitions
1920 * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
1921 * @retval interface status (MANDATORY: return 0 -> no Error)
1922 *
1923 */
lps22hh_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1924 int32_t lps22hh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1925 {
1926 lps22hh_fifo_status2_t reg;
1927 int32_t ret;
1928
1929 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1);
1930 *val = reg.fifo_ovr_ia;
1931
1932 return ret;
1933 }
1934
1935 /**
1936 * @brief FIFO watermark status.[get]
1937 *
1938 * @param ctx read / write interface definitions
1939 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
1940 * @retval interface status (MANDATORY: return 0 -> no Error)
1941 *
1942 */
lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1943 int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1944 {
1945 lps22hh_fifo_status2_t reg;
1946 int32_t ret;
1947
1948 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *)®, 1);
1949 *val = reg.fifo_wtm_ia;
1950
1951 return ret;
1952 }
1953
1954 /**
1955 * @}
1956 *
1957 */
1958
1959 /**
1960 * @}
1961 *
1962 */
1963
1964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1965
