1 /**
2 ******************************************************************************
3 * @file lps22ch_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS22CH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps22ch_reg.h"
21
22 /**
23 * @defgroup LPS22CH
24 * @brief This file provides a set of functions needed to drive the
25 * lps22ch enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LPS22CH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps22ch_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps22ch_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lps22ch_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lps22ch_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LPS22CH_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
lps22ch_from_lsb_to_hpa(uint32_t lsb)102 float_t lps22ch_from_lsb_to_hpa(uint32_t lsb)
103 {
104 return ((float_t) lsb / 1048576.0f);
105 }
106
lps22ch_from_lsb_to_celsius(int16_t lsb)107 float_t lps22ch_from_lsb_to_celsius(int16_t lsb)
108 {
109 return ((float_t) lsb / 100.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup LPS22CH_Data_Generation
119 * @brief This section groups all the functions concerning
120 * data generation.
121 * @{
122 *
123 */
124
125 /**
126 * @brief Reset Autozero function.[set]
127 *
128 * @param ctx read / write interface definitions
129 * @param val change the values of reset_az in reg INTERRUPT_CFG
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
lps22ch_autozero_rst_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t lps22ch_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 lps22ch_interrupt_cfg_t reg;
136 int32_t ret;
137
138 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
139
140 if (ret == 0)
141 {
142 reg.reset_az = val;
143 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
144 }
145
146 return ret;
147 }
148
149 /**
150 * @brief Reset Autozero function.[get]
151 *
152 * @param ctx read / write interface definitions
153 * @param val change the values of reset_az in reg INTERRUPT_CFG
154 * @retval interface status (MANDATORY: return 0 -> no Error)
155 *
156 */
lps22ch_autozero_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)157 int32_t lps22ch_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
158 {
159 lps22ch_interrupt_cfg_t reg;
160 int32_t ret;
161
162 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
163 *val = reg.reset_az;
164
165 return ret;
166 }
167
168 /**
169 * @brief Enable Autozero function.[set]
170 *
171 * @param ctx read / write interface definitions
172 * @param val change the values of autozero in reg INTERRUPT_CFG
173 * @retval interface status (MANDATORY: return 0 -> no Error)
174 *
175 */
lps22ch_autozero_set(const stmdev_ctx_t * ctx,uint8_t val)176 int32_t lps22ch_autozero_set(const stmdev_ctx_t *ctx, uint8_t val)
177 {
178 lps22ch_interrupt_cfg_t reg;
179 int32_t ret;
180
181 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
182
183 if (ret == 0)
184 {
185 reg.autozero = val;
186 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Enable Autozero function.[get]
194 *
195 * @param ctx read / write interface definitions
196 * @param val change the values of autozero in reg INTERRUPT_CFG
197 * @retval interface status (MANDATORY: return 0 -> no Error)
198 *
199 */
lps22ch_autozero_get(const stmdev_ctx_t * ctx,uint8_t * val)200 int32_t lps22ch_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val)
201 {
202 lps22ch_interrupt_cfg_t reg;
203 int32_t ret;
204
205 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
206 *val = reg.autozero;
207
208 return ret;
209 }
210
211 /**
212 * @brief Reset AutoRifP function.[set]
213 *
214 * @param ctx read / write interface definitions
215 * @param val change the values of reset_arp in reg INTERRUPT_CFG
216 * @retval interface status (MANDATORY: return 0 -> no Error)
217 *
218 */
lps22ch_pressure_snap_rst_set(const stmdev_ctx_t * ctx,uint8_t val)219 int32_t lps22ch_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val)
220 {
221 lps22ch_interrupt_cfg_t reg;
222 int32_t ret;
223
224 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
225
226 if (ret == 0)
227 {
228 reg.reset_arp = val;
229 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
230 }
231
232 return ret;
233 }
234
235 /**
236 * @brief Reset AutoRifP function.[get]
237 *
238 * @param ctx read / write interface definitions
239 * @param val change the values of reset_arp in reg INTERRUPT_CFG
240 * @retval interface status (MANDATORY: return 0 -> no Error)
241 *
242 */
lps22ch_pressure_snap_rst_get(const stmdev_ctx_t * ctx,uint8_t * val)243 int32_t lps22ch_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val)
244 {
245 lps22ch_interrupt_cfg_t reg;
246 int32_t ret;
247
248 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
249 *val = reg.reset_arp;
250
251 return ret;
252 }
253
254 /**
255 * @brief Enable AutoRefP function.[set]
256 *
257 * @param ctx read / write interface definitions
258 * @param val change the values of autorefp in reg INTERRUPT_CFG
259 * @retval interface status (MANDATORY: return 0 -> no Error)
260 *
261 */
lps22ch_pressure_snap_set(const stmdev_ctx_t * ctx,uint8_t val)262 int32_t lps22ch_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val)
263 {
264 lps22ch_interrupt_cfg_t reg;
265 int32_t ret;
266
267 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
268
269 if (ret == 0)
270 {
271 reg.autorefp = val;
272 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
273 }
274
275 return ret;
276 }
277
278 /**
279 * @brief Enable AutoRefP function.[get]
280 *
281 * @param ctx read / write interface definitions
282 * @param val change the values of autorefp in reg INTERRUPT_CFG
283 * @retval interface status (MANDATORY: return 0 -> no Error)
284 *
285 */
lps22ch_pressure_snap_get(const stmdev_ctx_t * ctx,uint8_t * val)286 int32_t lps22ch_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val)
287 {
288 lps22ch_interrupt_cfg_t reg;
289 int32_t ret;
290
291 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
292 *val = reg.autorefp;
293
294 return ret;
295 }
296
297 /**
298 * @brief Block Data Update.[set]
299 *
300 * @param ctx read / write interface definitions
301 * @param val change the values of bdu in reg CTRL_REG1
302 * @retval interface status (MANDATORY: return 0 -> no Error)
303 *
304 */
lps22ch_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)305 int32_t lps22ch_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
306 {
307 lps22ch_ctrl_reg1_t reg;
308 int32_t ret;
309
310 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
311
312 if (ret == 0)
313 {
314 reg.bdu = val;
315 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
316 }
317
318 return ret;
319 }
320
321 /**
322 * @brief Block Data Update.[get]
323 *
324 * @param ctx read / write interface definitions
325 * @param val change the values of bdu in reg CTRL_REG1
326 * @retval interface status (MANDATORY: return 0 -> no Error)
327 *
328 */
lps22ch_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)329 int32_t lps22ch_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
330 {
331 lps22ch_ctrl_reg1_t reg;
332 int32_t ret;
333
334 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
335 *val = reg.bdu;
336
337 return ret;
338 }
339
340 /**
341 * @brief Output data rate selection.[set]
342 *
343 * @param ctx read / write interface definitions
344 * @param val change the values of odr in reg CTRL_REG1
345 * @retval interface status (MANDATORY: return 0 -> no Error)
346 *
347 */
lps22ch_data_rate_set(const stmdev_ctx_t * ctx,lps22ch_odr_t val)348 int32_t lps22ch_data_rate_set(const stmdev_ctx_t *ctx, lps22ch_odr_t val)
349 {
350 lps22ch_ctrl_reg1_t ctrl_reg1;
351 lps22ch_ctrl_reg2_t ctrl_reg2;
352 int32_t ret;
353
354 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
355
356 if (ret == 0)
357 {
358 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
359 }
360
361 if (ret == 0)
362 {
363 ctrl_reg1.odr = (uint8_t)val & 0x07U;
364 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
365 }
366
367 if (ret == 0)
368 {
369 ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
370 ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
371 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
372 }
373
374 return ret;
375 }
376
377 /**
378 * @brief Output data rate selection.[get]
379 *
380 * @param ctx read / write interface definitions
381 * @param val Get the values of odr in reg CTRL_REG1
382 * @retval interface status (MANDATORY: return 0 -> no Error)
383 *
384 */
lps22ch_data_rate_get(const stmdev_ctx_t * ctx,lps22ch_odr_t * val)385 int32_t lps22ch_data_rate_get(const stmdev_ctx_t *ctx, lps22ch_odr_t *val)
386 {
387 lps22ch_ctrl_reg1_t ctrl_reg1;
388 lps22ch_ctrl_reg2_t ctrl_reg2;
389 int32_t ret;
390
391 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
392
393 if (ret == 0)
394 {
395 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
396 }
397
398 if (ret == 0)
399 {
400 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
401
402 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
403 ctrl_reg1.odr))
404 {
405 case LPS22CH_POWER_DOWN:
406 *val = LPS22CH_POWER_DOWN;
407 break;
408
409 case LPS22CH_ONE_SHOOT:
410 *val = LPS22CH_ONE_SHOOT;
411 break;
412
413 case LPS22CH_1_Hz:
414 *val = LPS22CH_1_Hz;
415 break;
416
417 case LPS22CH_10_Hz:
418 *val = LPS22CH_10_Hz;
419 break;
420
421 case LPS22CH_25_Hz:
422 *val = LPS22CH_25_Hz;
423 break;
424
425 case LPS22CH_50_Hz:
426 *val = LPS22CH_50_Hz;
427 break;
428
429 case LPS22CH_75_Hz:
430 *val = LPS22CH_75_Hz;
431 break;
432
433 case LPS22CH_1_Hz_LOW_NOISE:
434 *val = LPS22CH_1_Hz_LOW_NOISE;
435 break;
436
437 case LPS22CH_10_Hz_LOW_NOISE:
438 *val = LPS22CH_10_Hz_LOW_NOISE;
439 break;
440
441 case LPS22CH_25_Hz_LOW_NOISE:
442 *val = LPS22CH_25_Hz_LOW_NOISE;
443 break;
444
445 case LPS22CH_50_Hz_LOW_NOISE:
446 *val = LPS22CH_50_Hz_LOW_NOISE;
447 break;
448
449 case LPS22CH_75_Hz_LOW_NOISE:
450 *val = LPS22CH_75_Hz_LOW_NOISE;
451 break;
452
453 case LPS22CH_100_Hz:
454 *val = LPS22CH_100_Hz;
455 break;
456
457 case LPS22CH_200_Hz:
458 *val = LPS22CH_200_Hz;
459 break;
460
461 default:
462 *val = LPS22CH_POWER_DOWN;
463 break;
464 }
465 }
466
467 return ret;
468 }
469
470 /**
471 * @brief The Reference pressure value is a 16-bit data
472 * expressed as 2’s complement. The value is used
473 * when AUTOZERO or AUTORIFP function is enabled.[set]
474 *
475 * @param ctx read / write interface definitions
476 * @param buff buffer that contains data to write
477 * @retval interface status (MANDATORY: return 0 -> no Error)
478 *
479 */
lps22ch_pressure_ref_set(const stmdev_ctx_t * ctx,int16_t val)480 int32_t lps22ch_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val)
481 {
482 uint8_t buff[2];
483 int32_t ret;
484
485 buff[1] = (uint8_t)((uint16_t)val / 256U);
486 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
487 ret = lps22ch_write_reg(ctx, LPS22CH_REF_P_L, buff, 2);
488
489 return ret;
490 }
491
492 /**
493 * @brief The Reference pressure value is a 16-bit
494 * data expressed as 2’s complement.
495 * The value is used when AUTOZERO or AUTORIFP
496 * function is enabled.[get]
497 *
498 * @param ctx read / write interface definitions
499 * @param buff buffer that stores data read
500 * @retval interface status (MANDATORY: return 0 -> no Error)
501 *
502 */
lps22ch_pressure_ref_get(const stmdev_ctx_t * ctx,int16_t * val)503 int32_t lps22ch_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val)
504 {
505 uint8_t buff[2];
506 int32_t ret;
507
508 ret = lps22ch_read_reg(ctx, LPS22CH_REF_P_L, buff, 2);
509 *val = (int16_t)buff[1];
510 *val = (*val * 256) + (int16_t)buff[0];
511
512 return ret;
513 }
514
515 /**
516 * @brief The pressure offset value is 16-bit data
517 * that can be used to implement one-point
518 * calibration (OPC) after soldering.[set]
519 *
520 * @param ctx read / write interface definitions
521 * @param buff buffer that contains data to write
522 * @retval interface status (MANDATORY: return 0 -> no Error)
523 *
524 */
lps22ch_pressure_offset_set(const stmdev_ctx_t * ctx,int16_t val)525 int32_t lps22ch_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val)
526 {
527 uint8_t buff[2];
528 int32_t ret;
529
530 buff[1] = (uint8_t)((uint16_t)val / 256U);
531 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
532 ret = lps22ch_write_reg(ctx, LPS22CH_RPDS_L, buff, 2);
533
534 return ret;
535 }
536
537 /**
538 * @brief The pressure offset value is 16-bit
539 * data that can be used to implement
540 * one-point calibration (OPC) after
541 * soldering.[get]
542 *
543 * @param ctx read / write interface definitions
544 * @param buff buffer that stores data read
545 * @retval interface status (MANDATORY: return 0 -> no Error)
546 *
547 */
lps22ch_pressure_offset_get(const stmdev_ctx_t * ctx,int16_t * val)548 int32_t lps22ch_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
549 {
550 uint8_t buff[2];
551 int32_t ret;
552
553 ret = lps22ch_read_reg(ctx, LPS22CH_RPDS_L, buff, 2);
554 *val = (int16_t)buff[1];
555 *val = (*val * 256) + (int16_t)buff[0];
556
557 return ret;
558 }
559
560 /**
561 * @brief Read all the interrupt/status flag of the device.[get]
562 *
563 * @param ctx read / write interface definitions
564 * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE
565 * @retval interface status (MANDATORY: return 0 -> no Error)
566 *
567 */
lps22ch_all_sources_get(const stmdev_ctx_t * ctx,lps22ch_all_sources_t * val)568 int32_t lps22ch_all_sources_get(const stmdev_ctx_t *ctx,
569 lps22ch_all_sources_t *val)
570 {
571 int32_t ret;
572
573 ret = lps22ch_read_reg(ctx, LPS22CH_INT_SOURCE,
574 (uint8_t *) & (val->int_source), 1);
575
576 if (ret == 0)
577 {
578 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2,
579 (uint8_t *) & (val->fifo_status2), 1);
580 }
581
582 if (ret == 0)
583 {
584 ret = lps22ch_read_reg(ctx, LPS22CH_STATUS,
585 (uint8_t *) & (val->status), 1);
586 }
587
588 return ret;
589 }
590
591 /**
592 * @brief The STATUS_REG register is read by the primary interface.[get]
593 *
594 * @param ctx read / write interface definitions
595 * @param val structure of registers from STATUS to STATUS_REG
596 * @retval interface status (MANDATORY: return 0 -> no Error)
597 *
598 */
lps22ch_status_reg_get(const stmdev_ctx_t * ctx,lps22ch_status_t * val)599 int32_t lps22ch_status_reg_get(const stmdev_ctx_t *ctx,
600 lps22ch_status_t *val)
601 {
602 int32_t ret;
603
604 ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) val, 1);
605
606 return ret;
607 }
608
609 /**
610 * @brief Pressure new data available.[get]
611 *
612 * @param ctx read / write interface definitions
613 * @param val change the values of p_da in reg STATUS
614 * @retval interface status (MANDATORY: return 0 -> no Error)
615 *
616 */
lps22ch_press_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)617 int32_t lps22ch_press_flag_data_ready_get(const stmdev_ctx_t *ctx,
618 uint8_t *val)
619 {
620 lps22ch_status_t reg;
621 int32_t ret;
622
623 ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1);
624 *val = reg.p_da;
625
626 return ret;
627 }
628
629 /**
630 * @brief Temperature data available.[get]
631 *
632 * @param ctx read / write interface definitions
633 * @param val change the values of t_da in reg STATUS
634 * @retval interface status (MANDATORY: return 0 -> no Error)
635 *
636 */
lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)637 int32_t lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
638 uint8_t *val)
639 {
640 lps22ch_status_t reg;
641 int32_t ret;
642
643 ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1);
644 *val = reg.t_da;
645
646 return ret;
647 }
648
649 /**
650 * @}
651 *
652 */
653
654 /**
655 * @defgroup LPS22CH_Data_Output
656 * @brief This section groups all the data output functions.
657 * @{
658 *
659 */
660
661 /**
662 * @brief Pressure output value.[get]
663 *
664 * @param ctx read / write interface definitions
665 * @param buff buffer that stores data read
666 * @retval interface status (MANDATORY: return 0 -> no Error)
667 *
668 */
lps22ch_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)669 int32_t lps22ch_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
670 {
671 int32_t ret;
672
673 uint8_t reg[3];
674 ret = lps22ch_read_reg(ctx, LPS22CH_PRESS_OUT_XL, reg, 3);
675 *buff = reg[2];
676 *buff = (*buff * 256) + reg[1];
677 *buff = (*buff * 256) + reg[0];
678 *buff *= 256;
679
680 return ret;
681 }
682
683 /**
684 * @brief Temperature output value.[get]
685 *
686 * @param ctx read / write interface definitions
687 * @param buff buffer that stores data read
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lps22ch_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)691 int32_t lps22ch_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
692 {
693 int32_t ret;
694
695 uint8_t reg[2];
696 ret = lps22ch_read_reg(ctx, LPS22CH_TEMP_OUT_L, reg, 2);
697 *buff = reg[1];
698 *buff = (*buff * 256) + reg[0];
699
700 return ret;
701 }
702
703 /**
704 * @brief Pressure output from FIFO value.[get]
705 *
706 * @param ctx read / write interface definitions
707 * @param buff buffer that stores data read
708 * @retval interface status (MANDATORY: return 0 -> no Error)
709 *
710 */
lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)711 int32_t lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t *ctx,
712 uint32_t *buff)
713 {
714 int32_t ret;
715
716 uint8_t reg[3];
717 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_PRESS_XL, reg, 3);
718 *buff = reg[2];
719 *buff = (*buff * 256) + reg[1];
720 *buff = (*buff * 256) + reg[0];
721 *buff *= 256;
722
723 return ret;
724 }
725
726 /**
727 * @brief Temperature output from FIFO value.[get]
728 *
729 * @param ctx read / write interface definitions
730 * @param buff buffer that stores data read
731 * @retval interface status (MANDATORY: return 0 -> no Error)
732 *
733 */
lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)734 int32_t lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t *ctx,
735 int16_t *buff)
736 {
737 int32_t ret;
738
739 uint8_t reg[2];
740 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_TEMP_L, reg, 2);
741 *buff = reg[1];
742 *buff = (*buff * 256) + reg[0];
743
744 return ret;
745 }
746
747 /**
748 * @}
749 *
750 */
751
752 /**
753 * @defgroup LPS22CH_Common
754 * @brief This section groups common useful functions.
755 * @{
756 *
757 */
758
759 /**
760 * @brief DeviceWhoamI.[get]
761 *
762 * @param ctx read / write interface definitions
763 * @param buff buffer that stores data read
764 * @retval interface status (MANDATORY: return 0 -> no Error)
765 *
766 */
lps22ch_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)767 int32_t lps22ch_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
768 {
769 int32_t ret;
770
771 ret = lps22ch_read_reg(ctx, LPS22CH_WHO_AM_I, buff, 1);
772
773 return ret;
774 }
775
776 /**
777 * @brief Software reset. Restore the default values
778 * in user registers.[set]
779 *
780 * @param ctx read / write interface definitions
781 * @param val change the values of swreset in reg CTRL_REG2
782 * @retval interface status (MANDATORY: return 0 -> no Error)
783 *
784 */
lps22ch_reset_set(const stmdev_ctx_t * ctx,uint8_t val)785 int32_t lps22ch_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
786 {
787 lps22ch_ctrl_reg2_t reg;
788 int32_t ret;
789
790 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
791
792 if (ret == 0)
793 {
794 reg.swreset = val;
795 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
796 }
797
798 return ret;
799 }
800
801 /**
802 * @brief Software reset. Restore the default values
803 * in user registers.[get]
804 *
805 * @param ctx read / write interface definitions
806 * @param val change the values of swreset in reg CTRL_REG2
807 * @retval interface status (MANDATORY: return 0 -> no Error)
808 *
809 */
lps22ch_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)810 int32_t lps22ch_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
811 {
812 lps22ch_ctrl_reg2_t reg;
813 int32_t ret;
814
815 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
816 *val = reg.swreset;
817
818 return ret;
819 }
820
821 /**
822 * @brief Register address automatically
823 * incremented during a multiple byte access
824 * with a serial interface.[set]
825 *
826 * @param ctx read / write interface definitions
827 * @param val change the values of if_add_inc in reg CTRL_REG2
828 * @retval interface status (MANDATORY: return 0 -> no Error)
829 *
830 */
lps22ch_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)831 int32_t lps22ch_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
832 {
833 lps22ch_ctrl_reg2_t reg;
834 int32_t ret;
835
836 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
837
838 if (ret == 0)
839 {
840 reg.if_add_inc = val;
841 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
842 }
843
844 return ret;
845 }
846
847 /**
848 * @brief Register address automatically
849 * incremented during a multiple byte
850 * access with a serial interface.[get]
851 *
852 * @param ctx read / write interface definitions
853 * @param val change the values of if_add_inc in reg CTRL_REG2
854 * @retval interface status (MANDATORY: return 0 -> no Error)
855 *
856 */
lps22ch_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)857 int32_t lps22ch_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
858 {
859 lps22ch_ctrl_reg2_t reg;
860 int32_t ret;
861
862 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
863 *val = reg.if_add_inc;
864
865 return ret;
866 }
867
868 /**
869 * @brief Reboot memory content. Reload the calibration
870 * parameters.[set]
871 *
872 * @param ctx read / write interface definitions
873 * @param val change the values of boot in reg CTRL_REG2
874 * @retval interface status (MANDATORY: return 0 -> no Error)
875 *
876 */
lps22ch_boot_set(const stmdev_ctx_t * ctx,uint8_t val)877 int32_t lps22ch_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
878 {
879 lps22ch_ctrl_reg2_t reg;
880 int32_t ret;
881
882 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
883
884 if (ret == 0)
885 {
886 reg.boot = val;
887 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
888 }
889
890 return ret;
891 }
892
893 /**
894 * @brief Reboot memory content. Reload the calibration
895 * parameters.[get]
896 *
897 * @param ctx read / write interface definitions
898 * @param val change the values of boot in reg CTRL_REG2
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
lps22ch_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)902 int32_t lps22ch_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
903 {
904 lps22ch_ctrl_reg2_t reg;
905 int32_t ret;
906
907 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
908 *val = reg.boot;
909
910 return ret;
911 }
912
913 /**
914 * @}
915 *
916 */
917
918 /**
919 * @defgroup LPS22CH_Filters
920 * @brief This section group all the functions concerning the
921 * filters configuration.
922 * @{
923 *
924 */
925
926 /**
927 * @brief Low-pass bandwidth selection.[set]
928 *
929 * @param ctx read / write interface definitions
930 * @param val change the values of lpfp_cfg in reg CTRL_REG1
931 * @retval interface status (MANDATORY: return 0 -> no Error)
932 *
933 */
lps22ch_lp_bandwidth_set(const stmdev_ctx_t * ctx,lps22ch_lpfp_cfg_t val)934 int32_t lps22ch_lp_bandwidth_set(const stmdev_ctx_t *ctx,
935 lps22ch_lpfp_cfg_t val)
936 {
937 lps22ch_ctrl_reg1_t reg;
938 int32_t ret;
939
940 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
941
942 if (ret == 0)
943 {
944 reg.lpfp_cfg = (uint8_t)val;
945 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
946 }
947
948 return ret;
949 }
950
951 /**
952 * @brief Low-pass bandwidth selection.[get]
953 *
954 * @param ctx read / write interface definitions
955 * @param val Get the values of lpfp_cfg in reg CTRL_REG1
956 * @retval interface status (MANDATORY: return 0 -> no Error)
957 *
958 */
lps22ch_lp_bandwidth_get(const stmdev_ctx_t * ctx,lps22ch_lpfp_cfg_t * val)959 int32_t lps22ch_lp_bandwidth_get(const stmdev_ctx_t *ctx,
960 lps22ch_lpfp_cfg_t *val)
961 {
962 lps22ch_ctrl_reg1_t reg;
963 int32_t ret;
964
965 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
966
967 switch (reg.lpfp_cfg)
968 {
969 case LPS22CH_LPF_ODR_DIV_2:
970 *val = LPS22CH_LPF_ODR_DIV_2;
971 break;
972
973 case LPS22CH_LPF_ODR_DIV_9:
974 *val = LPS22CH_LPF_ODR_DIV_9;
975 break;
976
977 case LPS22CH_LPF_ODR_DIV_20:
978 *val = LPS22CH_LPF_ODR_DIV_20;
979 break;
980
981 default:
982 *val = LPS22CH_LPF_ODR_DIV_2;
983 break;
984 }
985
986 return ret;
987 }
988
989 /**
990 * @}
991 *
992 */
993
994 /**
995 * @defgroup LPS22CH_Serial_Interface
996 * @brief This section groups all the functions concerning serial
997 * interface management
998 * @{
999 *
1000 */
1001
1002 /**
1003 * @brief Enable/Disable I2C interface.[set]
1004 *
1005 * @param ctx read / write interface definitions
1006 * @param val change the values of i2c_disable in reg IF_CTRL
1007 * @retval interface status (MANDATORY: return 0 -> no Error)
1008 *
1009 */
lps22ch_i2c_interface_set(const stmdev_ctx_t * ctx,lps22ch_i2c_disable_t val)1010 int32_t lps22ch_i2c_interface_set(const stmdev_ctx_t *ctx,
1011 lps22ch_i2c_disable_t val)
1012 {
1013 lps22ch_if_ctrl_t reg;
1014 int32_t ret;
1015
1016 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1017
1018 if (ret == 0)
1019 {
1020 reg.i2c_disable = (uint8_t)val;
1021 ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1022 }
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Enable/Disable I2C interface.[get]
1029 *
1030 * @param ctx read / write interface definitions
1031 * @param val Get the values of i2c_disable in reg IF_CTRL
1032 * @retval interface status (MANDATORY: return 0 -> no Error)
1033 *
1034 */
lps22ch_i2c_interface_get(const stmdev_ctx_t * ctx,lps22ch_i2c_disable_t * val)1035 int32_t lps22ch_i2c_interface_get(const stmdev_ctx_t *ctx,
1036 lps22ch_i2c_disable_t *val)
1037 {
1038 lps22ch_if_ctrl_t reg;
1039 int32_t ret;
1040
1041 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1042
1043 switch (reg.i2c_disable)
1044 {
1045 case LPS22CH_I2C_ENABLE:
1046 *val = LPS22CH_I2C_ENABLE;
1047 break;
1048
1049 case LPS22CH_I2C_DISABLE:
1050 *val = LPS22CH_I2C_DISABLE;
1051 break;
1052
1053 default:
1054 *val = LPS22CH_I2C_ENABLE;
1055 break;
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @brief Enable/Disable I3C interface.[set]
1063 *
1064 * @param ctx read / write interface definitions
1065 * @param val change the values of i2c_disable in reg IF_CTRL
1066 * @retval interface status (MANDATORY: return 0 -> no Error)
1067 *
1068 */
lps22ch_i3c_interface_set(const stmdev_ctx_t * ctx,lps22ch_i3c_disable_t val)1069 int32_t lps22ch_i3c_interface_set(const stmdev_ctx_t *ctx,
1070 lps22ch_i3c_disable_t val)
1071 {
1072 lps22ch_if_ctrl_t reg;
1073 int32_t ret;
1074
1075 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
1076
1077 if (ret == 0)
1078 {
1079 reg.i3c_disable = (uint8_t)val;
1080 reg.int_en_i3c = (uint8_t)~val;
1081 ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
1082 }
1083
1084 return ret;
1085 }
1086
1087 /**
1088 * @brief Enable/Disable I3C interface.[get]
1089 *
1090 * @param ctx read / write interface definitions
1091 * @param val Get the values of i2c_disable in reg IF_CTRL
1092 * @retval interface status (MANDATORY: return 0 -> no Error)
1093 *
1094 */
lps22ch_i3c_interface_get(const stmdev_ctx_t * ctx,lps22ch_i3c_disable_t * val)1095 int32_t lps22ch_i3c_interface_get(const stmdev_ctx_t *ctx,
1096 lps22ch_i3c_disable_t *val)
1097 {
1098 lps22ch_if_ctrl_t reg;
1099 int32_t ret;
1100
1101 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1);
1102
1103 switch (reg.i3c_disable)
1104 {
1105 case LPS22CH_I3C_ENABLE:
1106 *val = LPS22CH_I3C_ENABLE;
1107 break;
1108
1109 case LPS22CH_I3C_DISABLE:
1110 *val = LPS22CH_I3C_DISABLE;
1111 break;
1112
1113 default:
1114 *val = LPS22CH_I3C_ENABLE;
1115 break;
1116 }
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief Enable/Disable pull-up on SDO pin.[set]
1123 *
1124 * @param ctx read / write interface definitions
1125 * @param val change the values of sdo_pu_en in reg IF_CTRL
1126 * @retval interface status (MANDATORY: return 0 -> no Error)
1127 *
1128 */
lps22ch_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lps22ch_pu_en_t val)1129 int32_t lps22ch_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
1130 lps22ch_pu_en_t val)
1131 {
1132 lps22ch_if_ctrl_t reg;
1133 int32_t ret;
1134
1135 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1136
1137 if (ret == 0)
1138 {
1139 reg.sdo_pu_en = (uint8_t)val;
1140 ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1141 }
1142
1143 return ret;
1144 }
1145
1146 /**
1147 * @brief Enable/Disable pull-up on SDO pin.[get]
1148 *
1149 * @param ctx read / write interface definitions
1150 * @param val Get the values of sdo_pu_en in reg IF_CTRL
1151 * @retval interface status (MANDATORY: return 0 -> no Error)
1152 *
1153 */
lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lps22ch_pu_en_t * val)1154 int32_t lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
1155 lps22ch_pu_en_t *val)
1156 {
1157 lps22ch_if_ctrl_t reg;
1158 int32_t ret;
1159
1160 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1161
1162 switch (reg.sdo_pu_en)
1163 {
1164 case LPS22CH_PULL_UP_DISCONNECT:
1165 *val = LPS22CH_PULL_UP_DISCONNECT;
1166 break;
1167
1168 case LPS22CH_PULL_UP_CONNECT:
1169 *val = LPS22CH_PULL_UP_CONNECT;
1170 break;
1171
1172 default:
1173 *val = LPS22CH_PULL_UP_DISCONNECT;
1174 break;
1175 }
1176
1177 return ret;
1178 }
1179
1180 /**
1181 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
1182 *
1183 * @param ctx read / write interface definitions
1184 * @param val change the values of sda_pu_en in reg IF_CTRL
1185 * @retval interface status (MANDATORY: return 0 -> no Error)
1186 *
1187 */
lps22ch_sda_mode_set(const stmdev_ctx_t * ctx,lps22ch_pu_en_t val)1188 int32_t lps22ch_sda_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val)
1189 {
1190 lps22ch_if_ctrl_t reg;
1191 int32_t ret;
1192
1193 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1194
1195 if (ret == 0)
1196 {
1197 reg.sda_pu_en = (uint8_t)val;
1198 ret = lps22ch_write_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1199 }
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
1206 *
1207 * @param ctx read / write interface definitions
1208 * @param val Get the values of sda_pu_en in reg IF_CTRL
1209 * @retval interface status (MANDATORY: return 0 -> no Error)
1210 *
1211 */
lps22ch_sda_mode_get(const stmdev_ctx_t * ctx,lps22ch_pu_en_t * val)1212 int32_t lps22ch_sda_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val)
1213 {
1214 lps22ch_if_ctrl_t reg;
1215 int32_t ret;
1216
1217 ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1);
1218
1219 switch (reg.sda_pu_en)
1220 {
1221 case LPS22CH_PULL_UP_DISCONNECT:
1222 *val = LPS22CH_PULL_UP_DISCONNECT;
1223 break;
1224
1225 case LPS22CH_PULL_UP_CONNECT:
1226 *val = LPS22CH_PULL_UP_CONNECT;
1227 break;
1228
1229 default:
1230 *val = LPS22CH_PULL_UP_DISCONNECT;
1231 break;
1232 }
1233
1234 return ret;
1235 }
1236
1237 /**
1238 * @brief SPI Serial Interface Mode selection.[set]
1239 *
1240 * @param ctx read / write interface definitions
1241 * @param val change the values of sim in reg CTRL_REG1
1242 * @retval interface status (MANDATORY: return 0 -> no Error)
1243 *
1244 */
lps22ch_spi_mode_set(const stmdev_ctx_t * ctx,lps22ch_sim_t val)1245 int32_t lps22ch_spi_mode_set(const stmdev_ctx_t *ctx, lps22ch_sim_t val)
1246 {
1247 lps22ch_ctrl_reg1_t reg;
1248 int32_t ret;
1249
1250 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
1251
1252 if (ret == 0)
1253 {
1254 reg.sim = (uint8_t)val;
1255 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
1256 }
1257
1258 return ret;
1259 }
1260
1261 /**
1262 * @brief SPI Serial Interface Mode selection.[get]
1263 *
1264 * @param ctx read / write interface definitions
1265 * @param val Get the values of sim in reg CTRL_REG1
1266 * @retval interface status (MANDATORY: return 0 -> no Error)
1267 *
1268 */
lps22ch_spi_mode_get(const stmdev_ctx_t * ctx,lps22ch_sim_t * val)1269 int32_t lps22ch_spi_mode_get(const stmdev_ctx_t *ctx, lps22ch_sim_t *val)
1270 {
1271 lps22ch_ctrl_reg1_t reg;
1272 int32_t ret;
1273
1274 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1);
1275
1276 switch (reg.sim)
1277 {
1278 case LPS22CH_SPI_4_WIRE:
1279 *val = LPS22CH_SPI_4_WIRE;
1280 break;
1281
1282 case LPS22CH_SPI_3_WIRE:
1283 *val = LPS22CH_SPI_3_WIRE;
1284 break;
1285
1286 default:
1287 *val = LPS22CH_SPI_4_WIRE;
1288 break;
1289 }
1290
1291 return ret;
1292 }
1293
1294 /**
1295 * @}
1296 *
1297 */
1298
1299 /**
1300 * @defgroup LPS22CH_Interrupt_Pins
1301 * @brief This section groups all the functions that manage
1302 * interrupt pins.
1303 * @{
1304 *
1305 */
1306
1307 /**
1308 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set]
1309 *
1310 * @param ctx read / write interface definitions
1311 * @param val change the values of lir in reg INTERRUPT_CFG
1312 * @retval interface status (MANDATORY: return 0 -> no Error)
1313 *
1314 */
lps22ch_int_notification_set(const stmdev_ctx_t * ctx,lps22ch_lir_t val)1315 int32_t lps22ch_int_notification_set(const stmdev_ctx_t *ctx,
1316 lps22ch_lir_t val)
1317 {
1318 lps22ch_interrupt_cfg_t reg;
1319 int32_t ret;
1320
1321 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1322
1323 if (ret == 0)
1324 {
1325 reg.lir = (uint8_t)val;
1326 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1327 }
1328
1329 return ret;
1330 }
1331
1332 /**
1333 * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get]
1334 *
1335 * @param ctx read / write interface definitions
1336 * @param val Get the values of lir in reg INTERRUPT_CFG
1337 * @retval interface status (MANDATORY: return 0 -> no Error)
1338 *
1339 */
lps22ch_int_notification_get(const stmdev_ctx_t * ctx,lps22ch_lir_t * val)1340 int32_t lps22ch_int_notification_get(const stmdev_ctx_t *ctx,
1341 lps22ch_lir_t *val)
1342 {
1343 lps22ch_interrupt_cfg_t reg;
1344 int32_t ret;
1345
1346 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1347
1348 switch (reg.lir)
1349 {
1350 case LPS22CH_INT_PULSED:
1351 *val = LPS22CH_INT_PULSED;
1352 break;
1353
1354 case LPS22CH_INT_LATCHED:
1355 *val = LPS22CH_INT_LATCHED;
1356 break;
1357
1358 default:
1359 *val = LPS22CH_INT_PULSED;
1360 break;
1361 }
1362
1363 return ret;
1364 }
1365
1366 /**
1367 * @brief Push-pull/open drain selection on interrupt pads.[set]
1368 *
1369 * @param ctx read / write interface definitions
1370 * @param val change the values of pp_od in reg CTRL_REG2
1371 * @retval interface status (MANDATORY: return 0 -> no Error)
1372 *
1373 */
lps22ch_pin_mode_set(const stmdev_ctx_t * ctx,lps22ch_pp_od_t val)1374 int32_t lps22ch_pin_mode_set(const stmdev_ctx_t *ctx, lps22ch_pp_od_t val)
1375 {
1376 lps22ch_ctrl_reg2_t reg;
1377 int32_t ret;
1378
1379 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1380
1381 if (ret == 0)
1382 {
1383 reg.pp_od = (uint8_t)val;
1384 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1385 }
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * @brief Push-pull/open drain selection on interrupt pads.[get]
1392 *
1393 * @param ctx read / write interface definitions
1394 * @param val Get the values of pp_od in reg CTRL_REG2
1395 * @retval interface status (MANDATORY: return 0 -> no Error)
1396 *
1397 */
lps22ch_pin_mode_get(const stmdev_ctx_t * ctx,lps22ch_pp_od_t * val)1398 int32_t lps22ch_pin_mode_get(const stmdev_ctx_t *ctx, lps22ch_pp_od_t *val)
1399 {
1400 lps22ch_ctrl_reg2_t reg;
1401 int32_t ret;
1402
1403 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1404
1405 switch (reg.pp_od)
1406 {
1407 case LPS22CH_PUSH_PULL:
1408 *val = LPS22CH_PUSH_PULL;
1409 break;
1410
1411 case LPS22CH_OPEN_DRAIN:
1412 *val = LPS22CH_OPEN_DRAIN;
1413 break;
1414
1415 default:
1416 *val = LPS22CH_PUSH_PULL;
1417 break;
1418 }
1419
1420 return ret;
1421 }
1422
1423 /**
1424 * @brief Interrupt active-high/low.[set]
1425 *
1426 * @param ctx read / write interface definitions
1427 * @param val change the values of int_h_l in reg CTRL_REG2
1428 * @retval interface status (MANDATORY: return 0 -> no Error)
1429 *
1430 */
lps22ch_pin_polarity_set(const stmdev_ctx_t * ctx,lps22ch_int_h_l_t val)1431 int32_t lps22ch_pin_polarity_set(const stmdev_ctx_t *ctx,
1432 lps22ch_int_h_l_t val)
1433 {
1434 lps22ch_ctrl_reg2_t reg;
1435 int32_t ret;
1436
1437 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1438
1439 if (ret == 0)
1440 {
1441 reg.int_h_l = (uint8_t)val;
1442 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1443 }
1444
1445 return ret;
1446 }
1447
1448 /**
1449 * @brief Interrupt active-high/low.[get]
1450 *
1451 * @param ctx read / write interface definitions
1452 * @param val Get the values of int_h_l in reg CTRL_REG2
1453 * @retval interface status (MANDATORY: return 0 -> no Error)
1454 *
1455 */
lps22ch_pin_polarity_get(const stmdev_ctx_t * ctx,lps22ch_int_h_l_t * val)1456 int32_t lps22ch_pin_polarity_get(const stmdev_ctx_t *ctx,
1457 lps22ch_int_h_l_t *val)
1458 {
1459 lps22ch_ctrl_reg2_t reg;
1460 int32_t ret;
1461
1462 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1);
1463
1464 switch (reg.int_h_l)
1465 {
1466 case LPS22CH_ACTIVE_HIGH:
1467 *val = LPS22CH_ACTIVE_HIGH;
1468 break;
1469
1470 case LPS22CH_ACTIVE_LOW:
1471 *val = LPS22CH_ACTIVE_LOW;
1472 break;
1473
1474 default:
1475 *val = LPS22CH_ACTIVE_HIGH;
1476 break;
1477 }
1478
1479 return ret;
1480 }
1481
1482 /**
1483 * @brief Select the signal that need to route on int pad.[set]
1484 *
1485 * @param ctx read / write interface definitions
1486 * @param val registers CTRL_REG3
1487 * @retval interface status (MANDATORY: return 0 -> no Error)
1488 *
1489 */
lps22ch_pin_int_route_set(const stmdev_ctx_t * ctx,lps22ch_ctrl_reg3_t * val)1490 int32_t lps22ch_pin_int_route_set(const stmdev_ctx_t *ctx,
1491 lps22ch_ctrl_reg3_t *val)
1492 {
1493 int32_t ret;
1494
1495 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *) val, 1);
1496
1497 return ret;
1498 }
1499
1500 /**
1501 * @brief Select the signal that need to route on int pad.[get]
1502 *
1503 * @param ctx read / write interface definitions
1504 * @param val registers CTRL_REG3
1505 * @retval interface status (MANDATORY: return 0 -> no Error)
1506 *
1507 */
lps22ch_pin_int_route_get(const stmdev_ctx_t * ctx,lps22ch_ctrl_reg3_t * val)1508 int32_t lps22ch_pin_int_route_get(const stmdev_ctx_t *ctx,
1509 lps22ch_ctrl_reg3_t *val)
1510 {
1511 int32_t ret;
1512
1513 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *) val, 1);
1514
1515 return ret;
1516 }
1517
1518 /**
1519 * @}
1520 *
1521 */
1522
1523 /**
1524 * @defgroup LPS22CH_Interrupt_on_Threshold
1525 * @brief This section groups all the functions that manage the
1526 * interrupt on threshold event generation.
1527 * @{
1528 *
1529 */
1530
1531 /**
1532 * @brief Enable interrupt generation on pressure low/high event.[set]
1533 *
1534 * @param ctx read / write interface definitions
1535 * @param val change the values of pe in reg INTERRUPT_CFG
1536 * @retval interface status (MANDATORY: return 0 -> no Error)
1537 *
1538 */
lps22ch_int_on_threshold_set(const stmdev_ctx_t * ctx,lps22ch_pe_t val)1539 int32_t lps22ch_int_on_threshold_set(const stmdev_ctx_t *ctx,
1540 lps22ch_pe_t val)
1541 {
1542 lps22ch_interrupt_cfg_t reg;
1543 int32_t ret;
1544
1545 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1546
1547 if (ret == 0)
1548 {
1549 reg.pe = (uint8_t)val;
1550
1551 if (val == LPS22CH_NO_THRESHOLD)
1552 {
1553 reg.diff_en = PROPERTY_DISABLE;
1554 }
1555
1556 else
1557 {
1558 reg.diff_en = PROPERTY_ENABLE;
1559 }
1560
1561 ret = lps22ch_write_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1562 }
1563
1564 return ret;
1565 }
1566
1567 /**
1568 * @brief Enable interrupt generation on pressure low/high event.[get]
1569 *
1570 * @param ctx read / write interface definitions
1571 * @param val Get the values of pe in reg INTERRUPT_CFG
1572 * @retval interface status (MANDATORY: return 0 -> no Error)
1573 *
1574 */
lps22ch_int_on_threshold_get(const stmdev_ctx_t * ctx,lps22ch_pe_t * val)1575 int32_t lps22ch_int_on_threshold_get(const stmdev_ctx_t *ctx,
1576 lps22ch_pe_t *val)
1577 {
1578 lps22ch_interrupt_cfg_t reg;
1579 int32_t ret;
1580
1581 ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1);
1582
1583 switch (reg.pe)
1584 {
1585 case LPS22CH_NO_THRESHOLD:
1586 *val = LPS22CH_NO_THRESHOLD;
1587 break;
1588
1589 case LPS22CH_POSITIVE:
1590 *val = LPS22CH_POSITIVE;
1591 break;
1592
1593 case LPS22CH_NEGATIVE:
1594 *val = LPS22CH_NEGATIVE;
1595 break;
1596
1597 case LPS22CH_BOTH:
1598 *val = LPS22CH_BOTH;
1599 break;
1600
1601 default:
1602 *val = LPS22CH_NO_THRESHOLD;
1603 break;
1604 }
1605
1606 return ret;
1607 }
1608
1609 /**
1610 * @brief User-defined threshold value for pressure interrupt event.[set]
1611 *
1612 * @param ctx read / write interface definitions
1613 * @param buff buffer that contains data to write
1614 * @retval interface status (MANDATORY: return 0 -> no Error)
1615 *
1616 */
lps22ch_int_threshold_set(const stmdev_ctx_t * ctx,uint16_t buff)1617 int32_t lps22ch_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff)
1618 {
1619 int32_t ret;
1620
1621 lps22ch_ths_p_l_t ths_p_l;
1622 lps22ch_ths_p_h_t ths_p_h;
1623 ths_p_h.ths = (uint8_t)(buff / 256U);
1624 ths_p_l.ths = (uint8_t)(buff - (ths_p_h.ths * 256U));
1625 ret = lps22ch_write_reg(ctx, LPS22CH_THS_P_L,
1626 (uint8_t *)&ths_p_l, 1);
1627
1628 if (ret == 0)
1629 {
1630 ret = lps22ch_write_reg(ctx, LPS22CH_THS_P_H,
1631 (uint8_t *)&ths_p_h, 1);
1632 }
1633
1634 return ret;
1635 }
1636
1637 /**
1638 * @brief User-defined threshold value for pressure interrupt event.[get]
1639 *
1640 * @param ctx read / write interface definitions
1641 * @param buff buffer that stores data read
1642 * @retval interface status (MANDATORY: return 0 -> no Error)
1643 *
1644 */
lps22ch_int_threshold_get(const stmdev_ctx_t * ctx,uint16_t * buff)1645 int32_t lps22ch_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff)
1646 {
1647 int32_t ret;
1648
1649 lps22ch_ths_p_l_t ths_p_l;
1650 lps22ch_ths_p_h_t ths_p_h;
1651 ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_L,
1652 (uint8_t *)&ths_p_l, 1);
1653
1654 if (ret == 0)
1655 {
1656 ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_H,
1657 (uint8_t *)&ths_p_h, 1);
1658 *buff = (uint16_t)ths_p_h.ths;
1659 *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths;
1660 }
1661
1662 return ret;
1663 }
1664
1665 /**
1666 * @}
1667 *
1668 */
1669
1670 /**
1671 * @defgroup LPS22CH_Fifo
1672 * @brief This section group all the functions concerning the fifo usage.
1673 * @{
1674 *
1675 */
1676
1677 /**
1678 * @brief Fifo Mode selection.[set]
1679 *
1680 * @param ctx read / write interface definitions
1681 * @param val change the values of f_mode in reg FIFO_CTRL
1682 * @retval interface status (MANDATORY: return 0 -> no Error)
1683 *
1684 */
lps22ch_fifo_mode_set(const stmdev_ctx_t * ctx,lps22ch_f_mode_t val)1685 int32_t lps22ch_fifo_mode_set(const stmdev_ctx_t *ctx, lps22ch_f_mode_t val)
1686 {
1687 lps22ch_fifo_ctrl_t reg;
1688 int32_t ret;
1689
1690 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1691
1692 if (ret == 0)
1693 {
1694 reg.f_mode = (uint8_t)val;
1695 ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1696 }
1697
1698 return ret;
1699 }
1700
1701 /**
1702 * @brief Fifo Mode selection.[get]
1703 *
1704 * @param ctx read / write interface definitions
1705 * @param val Get the values of f_mode in reg FIFO_CTRL
1706 * @retval interface status (MANDATORY: return 0 -> no Error)
1707 *
1708 */
lps22ch_fifo_mode_get(const stmdev_ctx_t * ctx,lps22ch_f_mode_t * val)1709 int32_t lps22ch_fifo_mode_get(const stmdev_ctx_t *ctx,
1710 lps22ch_f_mode_t *val)
1711 {
1712 lps22ch_fifo_ctrl_t reg;
1713 int32_t ret;
1714
1715 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1716
1717 switch (reg.f_mode)
1718 {
1719 case LPS22CH_BYPASS_MODE:
1720 *val = LPS22CH_BYPASS_MODE;
1721 break;
1722
1723 case LPS22CH_FIFO_MODE:
1724 *val = LPS22CH_FIFO_MODE;
1725 break;
1726
1727 case LPS22CH_STREAM_MODE:
1728 *val = LPS22CH_STREAM_MODE;
1729 break;
1730
1731 case LPS22CH_DYNAMIC_STREAM_MODE:
1732 *val = LPS22CH_DYNAMIC_STREAM_MODE;
1733 break;
1734
1735 case LPS22CH_BYPASS_TO_FIFO_MODE:
1736 *val = LPS22CH_BYPASS_TO_FIFO_MODE;
1737 break;
1738
1739 case LPS22CH_BYPASS_TO_STREAM_MODE:
1740 *val = LPS22CH_BYPASS_TO_STREAM_MODE;
1741 break;
1742
1743 case LPS22CH_STREAM_TO_FIFO_MODE:
1744 *val = LPS22CH_STREAM_TO_FIFO_MODE;
1745 break;
1746
1747 default:
1748 *val = LPS22CH_BYPASS_MODE;
1749 break;
1750 }
1751
1752 return ret;
1753 }
1754
1755 /**
1756 * @brief Sensing chain FIFO stop values memorization at
1757 * threshold level.[set]
1758 *
1759 * @param ctx read / write interface definitions
1760 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1761 * @retval interface status (MANDATORY: return 0 -> no Error)
1762 *
1763 */
lps22ch_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)1764 int32_t lps22ch_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
1765 {
1766 lps22ch_fifo_ctrl_t reg;
1767 int32_t ret;
1768
1769 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1770
1771 if (ret == 0)
1772 {
1773 reg.stop_on_wtm = val;
1774 ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1775 }
1776
1777 return ret;
1778 }
1779
1780 /**
1781 * @brief Sensing chain FIFO stop values memorization at threshold
1782 * level.[get]
1783 *
1784 * @param ctx read / write interface definitions
1785 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
1786 * @retval interface status (MANDATORY: return 0 -> no Error)
1787 *
1788 */
lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)1789 int32_t lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
1790 {
1791 lps22ch_fifo_ctrl_t reg;
1792 int32_t ret;
1793
1794 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1);
1795 *val = reg.stop_on_wtm;
1796
1797 return ret;
1798 }
1799
1800 /**
1801 * @brief FIFO watermark level selection.[set]
1802 *
1803 * @param ctx read / write interface definitions
1804 * @param val change the values of wtm in reg FIFO_WTM
1805 * @retval interface status (MANDATORY: return 0 -> no Error)
1806 *
1807 */
lps22ch_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1808 int32_t lps22ch_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1809 {
1810 lps22ch_fifo_wtm_t reg;
1811 int32_t ret;
1812
1813 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
1814
1815 if (ret == 0)
1816 {
1817 reg.wtm = val;
1818 ret = lps22ch_write_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
1819 }
1820
1821 return ret;
1822 }
1823
1824 /**
1825 * @brief FIFO watermark level selection.[get]
1826 *
1827 * @param ctx read / write interface definitions
1828 * @param val change the values of wtm in reg FIFO_WTM
1829 * @retval interface status (MANDATORY: return 0 -> no Error)
1830 *
1831 */
lps22ch_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1832 int32_t lps22ch_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1833 {
1834 lps22ch_fifo_wtm_t reg;
1835 int32_t ret;
1836
1837 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1);
1838 *val = reg.wtm;
1839
1840 return ret;
1841 }
1842
1843 /**
1844 * @brief FIFO stored data level.[get]
1845 *
1846 * @param ctx read / write interface definitions
1847 * @param buff buffer that stores data read
1848 * @retval interface status (MANDATORY: return 0 -> no Error)
1849 *
1850 */
lps22ch_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * buff)1851 int32_t lps22ch_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1852 {
1853 int32_t ret;
1854
1855 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS1, buff, 1);
1856
1857 return ret;
1858 }
1859
1860 /**
1861 * @brief Read all the FIFO status flag of the device.[get]
1862 *
1863 * @param ctx read / write interface definitions
1864 * @param val registers FIFO_STATUS2
1865 * @retval interface status (MANDATORY: return 0 -> no Error)
1866 *
1867 */
lps22ch_fifo_src_get(const stmdev_ctx_t * ctx,lps22ch_fifo_status2_t * val)1868 int32_t lps22ch_fifo_src_get(const stmdev_ctx_t *ctx,
1869 lps22ch_fifo_status2_t *val)
1870 {
1871 int32_t ret;
1872
1873 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) val, 1);
1874
1875 return ret;
1876 }
1877
1878 /**
1879 * @brief Smart FIFO full status.[get]
1880 *
1881 * @param ctx read / write interface definitions
1882 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
1883 * @retval interface status (MANDATORY: return 0 -> no Error)
1884 *
1885 */
lps22ch_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1886 int32_t lps22ch_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1887 {
1888 lps22ch_fifo_status2_t reg;
1889 int32_t ret;
1890
1891 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1);
1892 *val = reg.fifo_full_ia;
1893
1894 return ret;
1895 }
1896
1897 /**
1898 * @brief FIFO overrun status.[get]
1899 *
1900 * @param ctx read / write interface definitions
1901 * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
1902 * @retval interface status (MANDATORY: return 0 -> no Error)
1903 *
1904 */
lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1905 int32_t lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1906 {
1907 lps22ch_fifo_status2_t reg;
1908 int32_t ret;
1909
1910 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1);
1911 *val = reg.fifo_ovr_ia;
1912
1913 return ret;
1914 }
1915
1916 /**
1917 * @brief FIFO watermark status.[get]
1918 *
1919 * @param ctx read / write interface definitions
1920 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
1921 * @retval interface status (MANDATORY: return 0 -> no Error)
1922 *
1923 */
lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1924 int32_t lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1925 {
1926 lps22ch_fifo_status2_t reg;
1927 int32_t ret;
1928
1929 ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *)®, 1);
1930 *val = reg.fifo_wtm_ia;
1931
1932 return ret;
1933 }
1934
1935 /**
1936 * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
1937 *
1938 * @param stmdev_ctx_t *ctx: read / write interface definitions
1939 * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
1940 * @retval interface status (MANDATORY: return 0 -> no Error)
1941 *
1942 */
lps22ch_fifo_ovr_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)1943 int32_t lps22ch_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
1944 {
1945 lps22ch_ctrl_reg3_t reg;
1946 int32_t ret;
1947
1948 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
1949
1950 if (ret == 0)
1951 {
1952 reg.int_f_ovr = val;
1953 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
1954 }
1955
1956 return ret;
1957 }
1958
1959 /**
1960 * @brief FIFO overrun interrupt on INT_DRDY pin.[get]
1961 *
1962 * @param stmdev_ctx_t *ctx: read / write interface definitions
1963 * @param uint8_t: change the values of f_ovr in reg CTRL_REG3
1964 * @retval interface status (MANDATORY: return 0 -> no Error)
1965 *
1966 */
lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)1967 int32_t lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val)
1968 {
1969 lps22ch_ctrl_reg3_t reg;
1970 int32_t ret;
1971
1972 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
1973 *val = reg.int_f_ovr;
1974
1975 return ret;
1976 }
1977
1978 /**
1979 * @brief FIFO watermark status on INT_DRDY pin.[set]
1980 *
1981 * @param stmdev_ctx_t *ctx: read / write interface definitions
1982 * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
1983 * @retval interface status (MANDATORY: return 0 -> no Error)
1984 *
1985 */
lps22ch_fifo_threshold_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)1986 int32_t lps22ch_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx,
1987 uint8_t val)
1988 {
1989 lps22ch_ctrl_reg3_t reg;
1990 int32_t ret;
1991
1992 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
1993
1994 if (ret == 0)
1995 {
1996 reg.int_f_wtm = val;
1997 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
1998 }
1999
2000 return ret;
2001 }
2002
2003 /**
2004 * @brief FIFO watermark status on INT_DRDY pin.[get]
2005 *
2006 * @param lps22hb_ctx_t *ctx: read / write interface definitions
2007 * @param uint8_t: change the values of f_fth in reg CTRL_REG3
2008 * @retval interface status (MANDATORY: return 0 -> no Error)
2009 *
2010 */
lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2011 int32_t lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx,
2012 uint8_t *val)
2013 {
2014 lps22ch_ctrl_reg3_t reg;
2015 int32_t ret;
2016
2017 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
2018 *val = reg.int_f_wtm;
2019
2020 return ret;
2021 }
2022
2023 /**
2024 * @brief FIFO full flag on INT_DRDY pin.[set]
2025 *
2026 * @param stmdev_ctx_t *ctx: read / write interface definitions
2027 * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
2028 * @retval interface status (MANDATORY: return 0 -> no Error)
2029 *
2030 */
lps22ch_fifo_full_on_int_set(const stmdev_ctx_t * ctx,uint8_t val)2031 int32_t lps22ch_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val)
2032 {
2033 lps22ch_ctrl_reg3_t reg;
2034 int32_t ret;
2035
2036 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
2037
2038 if (ret == 0)
2039 {
2040 reg.int_f_full = val;
2041 ret = lps22ch_write_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
2042 }
2043
2044 return ret;
2045 }
2046
2047 /**
2048 * @brief FIFO full flag on INT_DRDY pin.[get]
2049 *
2050 * @param stmdev_ctx_t *ctx: read / write interface definitions
2051 * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3
2052 * @retval interface status (MANDATORY: return 0 -> no Error)
2053 *
2054 */
lps22ch_fifo_full_on_int_get(const stmdev_ctx_t * ctx,uint8_t * val)2055 int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val)
2056 {
2057 lps22ch_ctrl_reg3_t reg;
2058 int32_t ret;
2059
2060 ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1);
2061 *val = reg.int_f_full;
2062
2063 return ret;
2064 }
2065
2066 /**
2067 * @}
2068 *
2069 */
2070
2071 /**
2072 * @}
2073 *
2074 */
2075
2076 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2077
