1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: configure_register */ 14 /** Type of lp_clk_conf register 15 * need_des 16 */ 17 typedef union { 18 struct { 19 /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; 20 * need_des 21 */ 22 uint32_t slow_clk_sel:2; 23 /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; 24 * need_des 25 */ 26 uint32_t fast_clk_sel:2; 27 /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; 28 * need_des 29 */ 30 uint32_t lp_peri_div_num:8; 31 uint32_t reserved_12:20; 32 }; 33 uint32_t val; 34 } lp_clkrst_lp_clk_conf_reg_t; 35 36 /** Type of lp_clk_po_en register 37 * need_des 38 */ 39 typedef union { 40 struct { 41 /** aon_slow_oen : R/W; bitpos: [0]; default: 1; 42 * need_des 43 */ 44 uint32_t aon_slow_oen:1; 45 /** aon_fast_oen : R/W; bitpos: [1]; default: 1; 46 * need_des 47 */ 48 uint32_t aon_fast_oen:1; 49 /** sosc_oen : R/W; bitpos: [2]; default: 1; 50 * need_des 51 */ 52 uint32_t sosc_oen:1; 53 /** fosc_oen : R/W; bitpos: [3]; default: 1; 54 * need_des 55 */ 56 uint32_t fosc_oen:1; 57 /** osc32k_oen : R/W; bitpos: [4]; default: 1; 58 * need_des 59 */ 60 uint32_t osc32k_oen:1; 61 /** xtal32k_oen : R/W; bitpos: [5]; default: 1; 62 * need_des 63 */ 64 uint32_t xtal32k_oen:1; 65 /** core_efuse_oen : R/W; bitpos: [6]; default: 1; 66 * need_des 67 */ 68 uint32_t core_efuse_oen:1; 69 /** slow_oen : R/W; bitpos: [7]; default: 1; 70 * need_des 71 */ 72 uint32_t slow_oen:1; 73 /** fast_oen : R/W; bitpos: [8]; default: 1; 74 * need_des 75 */ 76 uint32_t fast_oen:1; 77 /** rng_oen : R/W; bitpos: [9]; default: 1; 78 * need_des 79 */ 80 uint32_t rng_oen:1; 81 /** lpbus_oen : R/W; bitpos: [10]; default: 1; 82 * need_des 83 */ 84 uint32_t lpbus_oen:1; 85 uint32_t reserved_11:21; 86 }; 87 uint32_t val; 88 } lp_clkrst_lp_clk_po_en_reg_t; 89 90 /** Type of lp_clk_en register 91 * need_des 92 */ 93 typedef union { 94 struct { 95 uint32_t reserved_0:31; 96 /** fast_ori_gate : R/W; bitpos: [31]; default: 0; 97 * need_des 98 */ 99 uint32_t fast_ori_gate:1; 100 }; 101 uint32_t val; 102 } lp_clkrst_lp_clk_en_reg_t; 103 104 /** Type of lp_rst_en register 105 * need_des 106 */ 107 typedef union { 108 struct { 109 uint32_t reserved_0:28; 110 /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; 111 * need_des 112 */ 113 uint32_t aon_efuse_core_reset_en:1; 114 /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; 115 * need_des 116 */ 117 uint32_t lp_timer_reset_en:1; 118 /** wdt_reset_en : R/W; bitpos: [30]; default: 0; 119 * need_des 120 */ 121 uint32_t wdt_reset_en:1; 122 /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; 123 * need_des 124 */ 125 uint32_t ana_peri_reset_en:1; 126 }; 127 uint32_t val; 128 } lp_clkrst_lp_rst_en_reg_t; 129 130 /** Type of reset_cause register 131 * need_des 132 */ 133 typedef union { 134 struct { 135 /** reset_cause : RO; bitpos: [4:0]; default: 0; 136 * need_des 137 */ 138 uint32_t reset_cause:5; 139 /** core0_reset_flag : RO; bitpos: [5]; default: 1; 140 * need_des 141 */ 142 uint32_t core0_reset_flag:1; 143 uint32_t reserved_6:23; 144 /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; 145 * need_des 146 */ 147 uint32_t core0_reset_cause_clr:1; 148 /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; 149 * need_des 150 */ 151 uint32_t core0_reset_flag_set:1; 152 /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; 153 * need_des 154 */ 155 uint32_t core0_reset_flag_clr:1; 156 }; 157 uint32_t val; 158 } lp_clkrst_reset_cause_reg_t; 159 160 /** Type of cpu_reset register 161 * need_des 162 */ 163 typedef union { 164 struct { 165 uint32_t reserved_0:22; 166 /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; 167 * need_des 168 */ 169 uint32_t rtc_wdt_cpu_reset_length:3; 170 /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; 171 * need_des 172 */ 173 uint32_t rtc_wdt_cpu_reset_en:1; 174 /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; 175 * need_des 176 */ 177 uint32_t cpu_stall_wait:5; 178 /** cpu_stall_en : R/W; bitpos: [31]; default: 0; 179 * need_des 180 */ 181 uint32_t cpu_stall_en:1; 182 }; 183 uint32_t val; 184 } lp_clkrst_cpu_reset_reg_t; 185 186 /** Type of fosc_cntl register 187 * need_des 188 */ 189 typedef union { 190 struct { 191 uint32_t reserved_0:22; 192 /** fosc_dfreq : R/W; bitpos: [31:22]; default: 600; 193 * need_des 194 */ 195 uint32_t fosc_dfreq:10; 196 }; 197 uint32_t val; 198 } lp_clkrst_fosc_cntl_reg_t; 199 200 /** Type of rc32k_cntl register 201 * need_des 202 */ 203 typedef union { 204 struct { 205 uint32_t reserved_0:22; 206 /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 650; 207 * need_des 208 */ 209 uint32_t rc32k_dfreq:10; 210 }; 211 uint32_t val; 212 } lp_clkrst_rc32k_cntl_reg_t; 213 214 /** Type of clk_to_hp register 215 * need_des 216 */ 217 typedef union { 218 struct { 219 uint32_t reserved_0:28; 220 /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; 221 * need_des 222 */ 223 uint32_t icg_hp_xtal32k:1; 224 /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; 225 * need_des 226 */ 227 uint32_t icg_hp_sosc:1; 228 /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; 229 * need_des 230 */ 231 uint32_t icg_hp_osc32k:1; 232 /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; 233 * need_des 234 */ 235 uint32_t icg_hp_fosc:1; 236 }; 237 uint32_t val; 238 } lp_clkrst_clk_to_hp_reg_t; 239 240 /** Type of lpmem_force register 241 * need_des 242 */ 243 typedef union { 244 struct { 245 uint32_t reserved_0:31; 246 /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; 247 * need_des 248 */ 249 uint32_t lpmem_clk_force_on:1; 250 }; 251 uint32_t val; 252 } lp_clkrst_lpmem_force_reg_t; 253 254 /** Type of lpperi register 255 * need_des 256 */ 257 typedef union { 258 struct { 259 uint32_t reserved_0:12; 260 /** lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0; 261 * need_des 262 */ 263 uint32_t lp_bletimer_div_num:12; 264 /** lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0; 265 * need_des 266 */ 267 uint32_t lp_bletimer_32k_sel:2; 268 /** lp_sel_osc_slow : R/W; bitpos: [26]; default: 0; 269 * need_des 270 */ 271 uint32_t lp_sel_osc_slow:1; 272 /** lp_sel_osc_fast : R/W; bitpos: [27]; default: 0; 273 * need_des 274 */ 275 uint32_t lp_sel_osc_fast:1; 276 /** lp_sel_xtal : R/W; bitpos: [28]; default: 0; 277 * need_des 278 */ 279 uint32_t lp_sel_xtal:1; 280 /** lp_sel_xtal32k : R/W; bitpos: [29]; default: 1; 281 * need_des 282 */ 283 uint32_t lp_sel_xtal32k:1; 284 /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; 285 * need_des 286 */ 287 uint32_t lp_i2c_clk_sel:1; 288 /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; 289 * need_des 290 */ 291 uint32_t lp_uart_clk_sel:1; 292 }; 293 uint32_t val; 294 } lp_clkrst_lpperi_reg_t; 295 296 /** Type of xtal32k register 297 * need_des 298 */ 299 typedef union { 300 struct { 301 uint32_t reserved_0:22; 302 /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; 303 * need_des 304 */ 305 uint32_t dres_xtal32k:3; 306 /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; 307 * need_des 308 */ 309 uint32_t dgm_xtal32k:3; 310 /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; 311 * need_des 312 */ 313 uint32_t dbuf_xtal32k:1; 314 /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; 315 * need_des 316 */ 317 uint32_t dac_xtal32k:3; 318 }; 319 uint32_t val; 320 } lp_clkrst_xtal32k_reg_t; 321 322 /** Type of date register 323 * need_des 324 */ 325 typedef union { 326 struct { 327 /** clkrst_date : R/W; bitpos: [30:0]; default: 35680896; 328 * need_des 329 */ 330 uint32_t clkrst_date:31; 331 /** clk_en : R/W; bitpos: [31]; default: 0; 332 * need_des 333 */ 334 uint32_t clk_en:1; 335 }; 336 uint32_t val; 337 } lp_clkrst_date_reg_t; 338 339 340 typedef struct { 341 volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; 342 volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; 343 volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; 344 volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; 345 volatile lp_clkrst_reset_cause_reg_t reset_cause; 346 volatile lp_clkrst_cpu_reset_reg_t cpu_reset; 347 volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; 348 volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; 349 volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; 350 volatile lp_clkrst_lpmem_force_reg_t lpmem_force; 351 volatile lp_clkrst_lpperi_reg_t lpperi; 352 volatile lp_clkrst_xtal32k_reg_t xtal32k; 353 uint32_t reserved_030[243]; 354 volatile lp_clkrst_date_reg_t date; 355 } lp_clkrst_dev_t; 356 357 extern lp_clkrst_dev_t LP_CLKRST; 358 359 #ifndef __cplusplus 360 _Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); 361 #endif 362 363 #ifdef __cplusplus 364 } 365 #endif 366