1/*
2 * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-m4";
20			reg = <0>;
21		};
22	};
23
24	clocks {
25		mosc: mosc {
26			compatible = "fixed-clock";
27			clock-frequency = <1200000>;
28			status = "disabled";
29			#clock-cells = <0>;
30		};
31
32		sosc: sosc {
33			compatible = "fixed-clock";
34			clock-frequency = <32768>;
35			status = "disabled";
36			#clock-cells = <0>;
37		};
38
39		hoco: hoco {
40			compatible = "fixed-clock";
41			clock-frequency = <24000000>;
42			status = "okay";
43			#clock-cells = <0>;
44		};
45
46		moco: moco {
47			compatible = "fixed-clock";
48			clock-frequency = <8000000>;
49			status = "okay";
50			#clock-cells = <0>;
51		};
52
53		loco: loco {
54			compatible = "fixed-clock";
55			clock-frequency = <32768>;
56			status = "okay";
57			#clock-cells = <0>;
58		};
59
60		pll: pll {
61			compatible = "fixed-factor-clock";
62			status = "disabled";
63			clocks = <&mosc>;
64			clock-div = <2>;
65			clock-mult = <8>;
66			#clock-cells = <0>;
67		};
68	};
69
70	sram0: memory0@20000000 {
71		compatible = "mmio-sram";
72		reg = <0x20000000 DT_SIZE_K(32)>;
73	};
74
75	soc {
76		interrupt-parent = <&icu>;
77		icu: interrupt-controller@40006000 {
78			compatible = "renesas,ra-interrupt-controller-unit";
79			reg = <0x40006000 0x40>;
80			reg-names = "icu";
81			interrupt-controller;
82			#interrupt-cells = <3>;
83		};
84
85		cgc: cgc@4001e000 {
86			compatible = "renesas,ra-clock-generation-circuit";
87			reg = <0x4001e000 0x40 0x40047000 0x10>;
88			reg-names = "system", "mstp";
89			#clock-cells = <1>;
90
91			clock-source = <&moco>;
92			iclk-div = <16>;
93			pclka-div = <16>;
94			pclkb-div = <16>;
95			pclkc-div = <16>;
96			pclkd-div = <16>;
97			fclk-div = <16>;
98		};
99
100		fcu: flash-controller@4001c000 {
101			compatible = "renesas,ra-flash-controller";
102			reg = <0x4001c000 0x44>;
103			reg-names = "fcache";
104
105			#address-cells = <1>;
106			#size-cells = <1>;
107
108			flash0: flash0@0 {
109				compatible = "soc-nv-flash";
110				reg = <0x00000000 DT_SIZE_K(256)>;
111			};
112
113			flash1: flash1@40100000 {
114				compatible = "soc-nv-flash";
115				reg = <0x40100000 DT_SIZE_K(8)>;
116			};
117		};
118
119		ioport0: gpio@40040000 {
120			compatible = "renesas,ra-gpio";
121			reg = <0x40040000 0x20>;
122			gpio-controller;
123			#gpio-cells = <2>;
124			ngpios = <16>;
125			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
126				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
127				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
128				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
129				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ10>,
130				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ15>;
131			interrupt-names = "port-irq2", "port-irq3", "port-irq6",
132					  "port-irq7", "port-irq10", "port-irq15";
133			port-irq2-pins = <2>;
134			port-irq3-pins = <4>;
135			port-irq6-pins = <0>;
136			port-irq7-pins = <1 15>;
137			port-irq10-pins = <5>;
138			port-irq15-pins = <11>;
139			status = "disabled";
140		};
141
142		ioport1: gpio@40040020 {
143			compatible = "renesas,ra-gpio";
144			reg = <0x40040020 0x20>;
145			gpio-controller;
146			#gpio-cells = <2>;
147			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
148				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
149				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
150				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
151				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>;
152			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
153					  "port-irq3", "port-irq4";
154			port-irq0-pins = <5>;
155			port-irq1-pins = <1>;
156			port-irq2-pins = <0>;
157			port-irq3-pins = <10>;
158			port-irq4-pins = <11>;
159			ngpios = <16>;
160			status = "disabled";
161		};
162
163		ioport2: gpio@40040040 {
164			compatible = "renesas,ra-gpio";
165			reg = <0x40040040 0x20>;
166			gpio-controller;
167			#gpio-cells = <2>;
168			ngpios = <16>;
169			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
170				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
171				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
172				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
173				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
174			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
175					  "port-irq3", "port-irq9";
176			port-irq0-pins = <6>;
177			port-irq1-pins = <5>;
178			port-irq2-pins = <13>;
179			port-irq3-pins = <12>;
180			status = "disabled";
181		};
182
183		ioport3: gpio@40040060 {
184			compatible = "renesas,ra-gpio";
185			reg = <0x40040060 0x20>;
186			gpio-controller;
187			#gpio-cells = <2>;
188			ngpios = <16>;
189			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
190				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
191				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
192				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
193			interrupt-names = "port-irq5", "port-irq6", "port-irq8", "port-irq9";
194			port-irq5-pins = <2>;
195			port-irq6-pins = <1>;
196			port-irq8-pins = <5>;
197			port-irq9-pins = <4>;
198			status = "disabled";
199		};
200
201		ioport4: gpio@40040080 {
202			compatible = "renesas,ra-gpio";
203			reg = <0x40040080 0x20>;
204			gpio-controller;
205			#gpio-cells = <2>;
206			ngpios = <16>;
207			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
208				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>,
209				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
210				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
211				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
212				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
213				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
214			interrupt-names = "port-irq0", "port-irq4", "port-irq5", "port-irq6",
215					  "port-irq7", "port-irq8", "port-irq9";
216			port-irq0-pins = <0>;
217			port-irq4-pins = <2 11>;
218			port-irq5-pins = <1 10>;
219			port-irq6-pins = <9>;
220			port-irq7-pins = <8>;
221			port-irq8-pins = <15>;
222			port-irq9-pins = <14>;
223			status = "disabled";
224		};
225
226		ioport5: gpio@400400a0 {
227			compatible = "renesas,ra-gpio";
228			reg = <0x400400a0 0x20>;
229			gpio-controller;
230			#gpio-cells = <2>;
231			ngpios = <16>;
232			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ11>,
233				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ12>,
234				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ14>;
235			interrupt-names = "port-irq11", "port-irq12", "port-irq14";
236			port-irq11-pins = <1>;
237			port-irq12-pins = <2>;
238			port-irq14-pins = <5>;
239			status = "disabled";
240		};
241
242		pinctrl: pinctrl@40040800 {
243			compatible = "renesas,ra-pinctrl";
244			reg = <0x40040800 0x500 0x40040d03 0x1>;
245			reg-names = "pfs", "pmisc_pwpr";
246			status = "okay";
247		};
248
249		sci0: sci@40070000 {
250			compatible = "renesas,ra-sci";
251			reg = <0x40070000 0x20>;
252			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI>,
253				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TXI>,
254				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TEI>,
255				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_ERI>,
256				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_AM>,
257				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI_OR_ERI>;
258			interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri";
259			clocks = <&cgc RA_CLOCK_SCI(0)>;
260			#clock-cells = <1>;
261			status = "disabled";
262			uart {
263				compatible = "renesas,ra-uart-sci";
264				status = "disabled";
265			};
266		};
267
268		sci1: sci@40070020 {
269			compatible = "renesas,ra-sci";
270			reg = <0x40070020 0x20>;
271			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_RXI>,
272				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TXI>,
273				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TEI>,
274				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_ERI>,
275				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_AM>;
276			interrupt-names = "rxi", "txi", "tei", "eri", "am";
277			clocks = <&cgc RA_CLOCK_SCI(1)>;
278			#clock-cells = <1>;
279			status = "disabled";
280			uart {
281				compatible = "renesas,ra-uart-sci";
282				status = "disabled";
283			};
284		};
285
286		sci9: sci@40070120 {
287			compatible = "renesas,ra-sci";
288			reg = <0x40070120 0x20>;
289			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_RXI>,
290				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TXI>,
291				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TEI>,
292				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_ERI>,
293				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_AM>;
294			interrupt-names = "rxi", "txi", "tei", "eri", "am";
295			clocks = <&cgc RA_CLOCK_SCI(9)>;
296			#clock-cells = <1>;
297			status = "disabled";
298			uart {
299				compatible = "renesas,ra-uart-sci";
300				status = "disabled";
301			};
302		};
303	};
304};
305
306&nvic {
307	arm,num-irq-priority-bits = <4>;
308};
309