1 /*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief ADC driver for the LMP90xxx AFE.
10 */
11
12 #include <zephyr/drivers/adc.h>
13 #include <zephyr/drivers/adc/lmp90xxx.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/sys/byteorder.h>
18 #include <zephyr/sys/crc.h>
19
20 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
21 #include <zephyr/logging/log.h>
22 LOG_MODULE_REGISTER(adc_lmp90xxx);
23
24 #define ADC_CONTEXT_USES_KERNEL_TIMER
25 #include "adc_context.h"
26
27 /* LMP90xxx register addresses */
28 #define LMP90XXX_REG_RESETCN 0x00U
29 #define LMP90XXX_REG_SPI_HANDSHAKECN 0x01U
30 #define LMP90XXX_REG_SPI_RESET 0x02U
31 #define LMP90XXX_REG_SPI_STREAMCN 0x03U
32 #define LMP90XXX_REG_PWRCN 0x08U
33 #define LMP90XXX_REG_DATA_ONLY_1 0x09U
34 #define LMP90XXX_REG_DATA_ONLY_2 0x0AU
35 #define LMP90XXX_REG_ADC_RESTART 0x0BU
36 #define LMP90XXX_REG_GPIO_DIRCN 0x0EU
37 #define LMP90XXX_REG_GPIO_DAT 0x0FU
38 #define LMP90XXX_REG_BGCALCN 0x10U
39 #define LMP90XXX_REG_SPI_DRDYBCN 0x11U
40 #define LMP90XXX_REG_ADC_AUXCN 0x12U
41 #define LMP90XXX_REG_SPI_CRC_CN 0x13U
42 #define LMP90XXX_REG_SENDIAG_THLDH 0x14U
43 #define LMP90XXX_REG_SENDIAG_THLDL 0x15U
44 #define LMP90XXX_REG_SCALCN 0x17U
45 #define LMP90XXX_REG_ADC_DONE 0x18U
46 #define LMP90XXX_REG_SENDIAG_FLAGS 0x19U
47 #define LMP90XXX_REG_ADC_DOUT 0x1AU
48 #define LMP90XXX_REG_SPI_CRC_DAT 0x1DU
49 #define LMP90XXX_REG_CH_STS 0x1EU
50 #define LMP90XXX_REG_CH_SCAN 0x1FU
51
52 /* LMP90xxx channel input and configuration registers */
53 #define LMP90XXX_REG_CH_INPUTCN(ch) (0x20U + (2 * ch))
54 #define LMP90XXX_REG_CH_CONFIG(ch) (0x21U + (2 * ch))
55
56 /* LMP90xxx upper (URA) and lower (LRA) register addresses */
57 #define LMP90XXX_URA(addr) ((addr >> 4U) & GENMASK(2, 0))
58 #define LMP90XXX_LRA(addr) (addr & GENMASK(3, 0))
59
60 /* LMP90xxx instruction byte 1 (INST1) */
61 #define LMP90XXX_INST1_WAB 0x10U
62 #define LMP90XXX_INST1_RA 0x90U
63
64 /* LMP90xxx instruction byte 2 (INST2) */
65 #define LMP90XXX_INST2_WB 0U
66 #define LMP90XXX_INST2_R BIT(7)
67 #define LMP90XXX_INST2_SZ_1 (0x0U << 5)
68 #define LMP90XXX_INST2_SZ_2 (0x1U << 5)
69 #define LMP90XXX_INST2_SZ_3 (0x2U << 5)
70 #define LMP90XXX_INST2_SZ_STREAM (0x3U << 5)
71
72 /* LMP90xxx register values/commands */
73 #define LMP90XXX_REG_AND_CNV_RST 0xC3U
74 #define LMP90XXX_SDO_DRDYB_DRIVER(x) ((x & BIT_MASK(3)) << 1)
75 #define LMP90XXX_PWRCN(x) (x & BIT_MASK(2))
76 #define LMP90XXX_RTD_CUR_SEL(x) (x & BIT_MASK(4))
77 #define LMP90XXX_SPI_DRDYB_D6(x) ((x & BIT(0)) << 7)
78 #define LMP90XXX_EN_CRC(x) ((x & BIT(0)) << 4)
79 #define LMP90XXX_DRDYB_AFT_CRC(x) ((x & BIT(0)) << 2)
80 #define LMP90XXX_CH_SCAN_SEL(x) ((x & BIT_MASK(2)) << 6)
81 #define LMP90XXX_LAST_CH(x) ((x & BIT_MASK(3)) << 3)
82 #define LMP90XXX_FIRST_CH(x) (x & BIT_MASK(3))
83 #define LMP90XXX_BURNOUT_EN(x) ((x & BIT(0)) << 7)
84 #define LMP90XXX_VREF_SEL(x) ((x & BIT(0)) << 6)
85 #define LMP90XXX_VINP(x) ((x & BIT_MASK(3)) << 3)
86 #define LMP90XXX_VINN(x) (x & BIT_MASK(3))
87 #define LMP90XXX_BGCALN(x) (x & BIT_MASK(3))
88 #define LMP90XXX_ODR_SEL(x) ((x & BIT_MASK(3)) << 4)
89 #define LMP90XXX_GAIN_SEL(x) ((x & BIT_MASK(3)) << 1)
90 #define LMP90XXX_BUF_EN(x) (x & BIT(0))
91 #define LMP90XXX_GPIO_DAT_MASK BIT_MASK(LMP90XXX_GPIO_MAX)
92
93 /* Invalid (never used) Upper Register Address */
94 #define LMP90XXX_INVALID_URA UINT8_MAX
95
96 /* Maximum number of ADC channels */
97 #define LMP90XXX_MAX_CHANNELS 7
98
99 /* Maximum number of ADC inputs */
100 #define LMP90XXX_MAX_INPUTS 8
101
102 /* Default Output Data Rate (ODR) is 214.65 SPS */
103 #define LMP90XXX_DEFAULT_ODR 7
104
105 /* Macro for checking if Data Ready Bar IRQ is in use */
106 #define LMP90XXX_HAS_DRDYB(config) (config->drdyb.port != NULL)
107
108 struct lmp90xxx_config {
109 struct spi_dt_spec bus;
110 struct gpio_dt_spec drdyb;
111 uint8_t rtd_current;
112 uint8_t resolution;
113 uint8_t channels;
114 };
115
116 struct lmp90xxx_data {
117 struct adc_context ctx;
118 const struct device *dev;
119 struct gpio_callback drdyb_cb;
120 struct k_mutex ura_lock;
121 uint8_t ura;
122 int32_t *buffer;
123 int32_t *repeat_buffer;
124 uint32_t channels;
125 bool calibrate;
126 uint8_t channel_odr[LMP90XXX_MAX_CHANNELS];
127 #ifdef CONFIG_ADC_LMP90XXX_GPIO
128 struct k_mutex gpio_lock;
129 uint8_t gpio_dircn;
130 uint8_t gpio_dat;
131 #endif /* CONFIG_ADC_LMP90XXX_GPIO */
132 struct k_thread thread;
133 struct k_sem acq_sem;
134 struct k_sem drdyb_sem;
135
136 K_KERNEL_STACK_MEMBER(stack,
137 CONFIG_ADC_LMP90XXX_ACQUISITION_THREAD_STACK_SIZE);
138 };
139
140 /*
141 * Approximated LMP90xxx acquisition times in milliseconds. These are
142 * used for the initial delay when polling for data ready.
143 */
144 static const int32_t lmp90xxx_odr_delay_tbl[8] = {
145 596, /* 13.42/8 = 1.6775 SPS */
146 298, /* 13.42/4 = 3.355 SPS */
147 149, /* 13.42/2 = 6.71 SPS */
148 75, /* 13.42 SPS */
149 37, /* 214.65/8 = 26.83125 SPS */
150 19, /* 214.65/4 = 53.6625 SPS */
151 9, /* 214.65/2 = 107.325 SPS */
152 5, /* 214.65 SPS (default) */
153 };
154
lmp90xxx_inst2_sz(size_t len)155 static inline uint8_t lmp90xxx_inst2_sz(size_t len)
156 {
157 if (len == 1) {
158 return LMP90XXX_INST2_SZ_1;
159 } else if (len == 2) {
160 return LMP90XXX_INST2_SZ_2;
161 } else if (len == 3) {
162 return LMP90XXX_INST2_SZ_3;
163 } else {
164 return LMP90XXX_INST2_SZ_STREAM;
165 }
166 }
167
lmp90xxx_read_reg(const struct device * dev,uint8_t addr,uint8_t * dptr,size_t len)168 static int lmp90xxx_read_reg(const struct device *dev, uint8_t addr,
169 uint8_t *dptr,
170 size_t len)
171 {
172 const struct lmp90xxx_config *config = dev->config;
173 struct lmp90xxx_data *data = dev->data;
174 uint8_t ura = LMP90XXX_URA(addr);
175 uint8_t inst1_uab[2] = { LMP90XXX_INST1_WAB, ura };
176 uint8_t inst2 = LMP90XXX_INST2_R | LMP90XXX_LRA(addr);
177 struct spi_buf tx_buf[2];
178 struct spi_buf rx_buf[2];
179 struct spi_buf_set tx;
180 struct spi_buf_set rx;
181 int dummy = 0;
182 int i = 0;
183 int err;
184
185 if (len == 0) {
186 LOG_ERR("attempt to read 0 bytes from register 0x%02x", addr);
187 return -EINVAL;
188 }
189
190 if (k_is_in_isr()) {
191 /* Prevent SPI transactions from an ISR */
192 return -EWOULDBLOCK;
193 }
194
195 k_mutex_lock(&data->ura_lock, K_FOREVER);
196
197 if (ura != data->ura) {
198 /* Instruction Byte 1 + Upper Address Byte */
199 tx_buf[i].buf = inst1_uab;
200 tx_buf[i].len = sizeof(inst1_uab);
201 dummy += sizeof(inst1_uab);
202 i++;
203 }
204
205 /* Instruction Byte 2 */
206 inst2 |= lmp90xxx_inst2_sz(len);
207 tx_buf[i].buf = &inst2;
208 tx_buf[i].len = sizeof(inst2);
209 dummy += sizeof(inst2);
210 i++;
211
212 /* Dummy RX Bytes */
213 rx_buf[0].buf = NULL;
214 rx_buf[0].len = dummy;
215
216 /* Data Byte(s) */
217 rx_buf[1].buf = dptr;
218 rx_buf[1].len = len;
219
220 tx.buffers = tx_buf;
221 tx.count = i;
222 rx.buffers = rx_buf;
223 rx.count = 2;
224
225 err = spi_transceive_dt(&config->bus, &tx, &rx);
226 if (!err) {
227 data->ura = ura;
228 } else {
229 /* Force INST1 + UAB on next access */
230 data->ura = LMP90XXX_INVALID_URA;
231 }
232
233 k_mutex_unlock(&data->ura_lock);
234
235 return err;
236 }
237
lmp90xxx_read_reg8(const struct device * dev,uint8_t addr,uint8_t * val)238 static int lmp90xxx_read_reg8(const struct device *dev, uint8_t addr,
239 uint8_t *val)
240 {
241 return lmp90xxx_read_reg(dev, addr, val, sizeof(*val));
242 }
243
lmp90xxx_write_reg(const struct device * dev,uint8_t addr,uint8_t * dptr,size_t len)244 static int lmp90xxx_write_reg(const struct device *dev, uint8_t addr,
245 uint8_t *dptr,
246 size_t len)
247 {
248 const struct lmp90xxx_config *config = dev->config;
249 struct lmp90xxx_data *data = dev->data;
250 uint8_t ura = LMP90XXX_URA(addr);
251 uint8_t inst1_uab[2] = { LMP90XXX_INST1_WAB, ura };
252 uint8_t inst2 = LMP90XXX_INST2_WB | LMP90XXX_LRA(addr);
253 struct spi_buf tx_buf[3];
254 struct spi_buf_set tx;
255 int i = 0;
256 int err;
257
258 if (len == 0) {
259 LOG_ERR("attempt write 0 bytes to register 0x%02x", addr);
260 return -EINVAL;
261 }
262
263 if (k_is_in_isr()) {
264 /* Prevent SPI transactions from an ISR */
265 return -EWOULDBLOCK;
266 }
267
268 k_mutex_lock(&data->ura_lock, K_FOREVER);
269
270 if (ura != data->ura) {
271 /* Instruction Byte 1 + Upper Address Byte */
272 tx_buf[i].buf = inst1_uab;
273 tx_buf[i].len = sizeof(inst1_uab);
274 i++;
275 }
276
277 /* Instruction Byte 2 */
278 inst2 |= lmp90xxx_inst2_sz(len);
279 tx_buf[i].buf = &inst2;
280 tx_buf[i].len = sizeof(inst2);
281 i++;
282
283 /* Data Byte(s) */
284 tx_buf[i].buf = dptr;
285 tx_buf[i].len = len;
286 i++;
287
288 tx.buffers = tx_buf;
289 tx.count = i;
290
291 err = spi_write_dt(&config->bus, &tx);
292 if (!err) {
293 data->ura = ura;
294 } else {
295 /* Force INST1 + UAB on next access */
296 data->ura = LMP90XXX_INVALID_URA;
297 }
298
299 k_mutex_unlock(&data->ura_lock);
300
301 return err;
302 }
303
lmp90xxx_write_reg8(const struct device * dev,uint8_t addr,uint8_t val)304 static int lmp90xxx_write_reg8(const struct device *dev, uint8_t addr,
305 uint8_t val)
306 {
307 return lmp90xxx_write_reg(dev, addr, &val, sizeof(val));
308 }
309
lmp90xxx_soft_reset(const struct device * dev)310 static int lmp90xxx_soft_reset(const struct device *dev)
311 {
312 int err;
313
314 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_RESETCN,
315 LMP90XXX_REG_AND_CNV_RST);
316 if (err) {
317 return err;
318 }
319
320 /* Write to RESETCN twice in order to reset mode as well as registers */
321 return lmp90xxx_write_reg8(dev, LMP90XXX_REG_RESETCN,
322 LMP90XXX_REG_AND_CNV_RST);
323 }
324
lmp90xxx_has_channel(const struct device * dev,uint8_t channel)325 static inline bool lmp90xxx_has_channel(const struct device *dev,
326 uint8_t channel)
327 {
328 const struct lmp90xxx_config *config = dev->config;
329
330 if (channel >= config->channels) {
331 return false;
332 } else {
333 return true;
334 }
335 }
336
lmp90xxx_has_input(const struct device * dev,uint8_t input)337 static inline bool lmp90xxx_has_input(const struct device *dev, uint8_t input)
338 {
339 const struct lmp90xxx_config *config = dev->config;
340
341 if (input >= LMP90XXX_MAX_INPUTS) {
342 return false;
343 } else if (config->channels < LMP90XXX_MAX_CHANNELS &&
344 (input >= 3 && input <= 5)) {
345 /* This device only has inputs 0, 1, 2, 6, and 7 */
346 return false;
347 } else {
348 return true;
349 }
350 }
351
lmp90xxx_acq_time_to_odr(uint16_t acq_time)352 static inline int lmp90xxx_acq_time_to_odr(uint16_t acq_time)
353 {
354 uint16_t acq_value;
355
356 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
357 return LMP90XXX_DEFAULT_ODR;
358 }
359
360 if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
361 return -EINVAL;
362 }
363
364 /*
365 * The LMP90xxx supports odd (and very slow) output data
366 * rates. Allow the caller to specify the ODR directly using
367 * ADC_ACQ_TIME_TICKS
368 */
369 acq_value = ADC_ACQ_TIME_VALUE(acq_time);
370 if (acq_value <= LMP90XXX_DEFAULT_ODR) {
371 return acq_value;
372 }
373
374 return -EINVAL;
375 }
376
lmp90xxx_adc_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)377 static int lmp90xxx_adc_channel_setup(const struct device *dev,
378 const struct adc_channel_cfg *channel_cfg)
379 {
380 struct lmp90xxx_data *data = dev->data;
381 uint8_t chx_inputcn = LMP90XXX_BURNOUT_EN(0); /* No burnout currents */
382 uint8_t chx_config = LMP90XXX_BUF_EN(0); /* No buffer */
383 uint8_t payload[2];
384 uint8_t addr;
385 int ret;
386
387 switch (channel_cfg->reference) {
388 case ADC_REF_EXTERNAL0:
389 chx_inputcn |= LMP90XXX_VREF_SEL(0);
390 break;
391 case ADC_REF_EXTERNAL1:
392 chx_inputcn |= LMP90XXX_VREF_SEL(1);
393 break;
394 default:
395 LOG_ERR("unsupported channel reference type '%d'",
396 channel_cfg->reference);
397 return -ENOTSUP;
398 }
399
400 if (!lmp90xxx_has_channel(dev, channel_cfg->channel_id)) {
401 LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
402 return -ENOTSUP;
403 }
404
405 if (!lmp90xxx_has_input(dev, channel_cfg->input_positive)) {
406 LOG_ERR("unsupported positive input '%d'",
407 channel_cfg->input_positive);
408 return -ENOTSUP;
409 }
410 chx_inputcn |= LMP90XXX_VINP(channel_cfg->input_positive);
411
412 if (!lmp90xxx_has_input(dev, channel_cfg->input_negative)) {
413 LOG_ERR("unsupported negative input '%d'",
414 channel_cfg->input_negative);
415 return -ENOTSUP;
416 }
417 chx_inputcn |= LMP90XXX_VINN(channel_cfg->input_negative);
418
419 ret = lmp90xxx_acq_time_to_odr(channel_cfg->acquisition_time);
420 if (ret < 0) {
421 LOG_ERR("unsupported channel acquisition time 0x%02x",
422 channel_cfg->acquisition_time);
423 return -ENOTSUP;
424 }
425 chx_config |= LMP90XXX_ODR_SEL(ret);
426 data->channel_odr[channel_cfg->channel_id] = ret;
427
428 switch (channel_cfg->gain) {
429 case ADC_GAIN_1:
430 chx_config |= LMP90XXX_GAIN_SEL(0);
431 break;
432 case ADC_GAIN_2:
433 chx_config |= LMP90XXX_GAIN_SEL(1);
434 break;
435 case ADC_GAIN_4:
436 chx_config |= LMP90XXX_GAIN_SEL(2);
437 break;
438 case ADC_GAIN_8:
439 chx_config |= LMP90XXX_GAIN_SEL(3);
440 break;
441 case ADC_GAIN_16:
442 chx_config |= LMP90XXX_GAIN_SEL(4);
443 break;
444 case ADC_GAIN_32:
445 chx_config |= LMP90XXX_GAIN_SEL(5);
446 break;
447 case ADC_GAIN_64:
448 chx_config |= LMP90XXX_GAIN_SEL(6);
449 break;
450 case ADC_GAIN_128:
451 chx_config |= LMP90XXX_GAIN_SEL(7);
452 break;
453 default:
454 LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
455 return -ENOTSUP;
456 }
457
458 payload[0] = chx_inputcn;
459 payload[1] = chx_config;
460
461 addr = LMP90XXX_REG_CH_INPUTCN(channel_cfg->channel_id);
462 ret = lmp90xxx_write_reg(dev, addr, payload, sizeof(payload));
463 if (ret) {
464 LOG_ERR("failed to configure channel (err %d)", ret);
465 }
466
467 return ret;
468 }
469
lmp90xxx_validate_buffer_size(const struct adc_sequence * sequence)470 static int lmp90xxx_validate_buffer_size(const struct adc_sequence *sequence)
471 {
472 uint8_t channels = 0;
473 size_t needed;
474 uint32_t mask;
475
476 for (mask = BIT(LMP90XXX_MAX_CHANNELS - 1); mask != 0; mask >>= 1) {
477 if (mask & sequence->channels) {
478 channels++;
479 }
480 }
481
482 needed = channels * sizeof(int32_t);
483 if (sequence->options) {
484 needed *= (1 + sequence->options->extra_samplings);
485 }
486
487 if (sequence->buffer_size < needed) {
488 return -ENOMEM;
489 }
490
491 return 0;
492 }
493
lmp90xxx_adc_start_read(const struct device * dev,const struct adc_sequence * sequence)494 static int lmp90xxx_adc_start_read(const struct device *dev,
495 const struct adc_sequence *sequence)
496 {
497 const struct lmp90xxx_config *config = dev->config;
498 struct lmp90xxx_data *data = dev->data;
499 int err;
500
501 if (sequence->resolution != config->resolution) {
502 LOG_ERR("unsupported resolution %d", sequence->resolution);
503 return -ENOTSUP;
504 }
505
506 if (!lmp90xxx_has_channel(dev, find_msb_set(sequence->channels) - 1)) {
507 LOG_ERR("unsupported channels in mask: 0x%08x",
508 sequence->channels);
509 return -ENOTSUP;
510 }
511
512 err = lmp90xxx_validate_buffer_size(sequence);
513 if (err) {
514 LOG_ERR("buffer size too small");
515 return err;
516 }
517
518 data->buffer = sequence->buffer;
519 data->calibrate = sequence->calibrate;
520 adc_context_start_read(&data->ctx, sequence);
521
522 return adc_context_wait_for_completion(&data->ctx);
523 }
524
lmp90xxx_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)525 static int lmp90xxx_adc_read_async(const struct device *dev,
526 const struct adc_sequence *sequence,
527 struct k_poll_signal *async)
528 {
529 struct lmp90xxx_data *data = dev->data;
530 int err;
531
532 adc_context_lock(&data->ctx, async ? true : false, async);
533 err = lmp90xxx_adc_start_read(dev, sequence);
534 adc_context_release(&data->ctx, err);
535
536 return err;
537 }
538
lmp90xxx_adc_read(const struct device * dev,const struct adc_sequence * sequence)539 static int lmp90xxx_adc_read(const struct device *dev,
540 const struct adc_sequence *sequence)
541 {
542 return lmp90xxx_adc_read_async(dev, sequence, NULL);
543 }
544
adc_context_start_sampling(struct adc_context * ctx)545 static void adc_context_start_sampling(struct adc_context *ctx)
546 {
547 struct lmp90xxx_data *data =
548 CONTAINER_OF(ctx, struct lmp90xxx_data, ctx);
549
550 data->channels = ctx->sequence.channels;
551 data->repeat_buffer = data->buffer;
552
553 k_sem_give(&data->acq_sem);
554 }
555
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)556 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
557 bool repeat_sampling)
558 {
559 struct lmp90xxx_data *data =
560 CONTAINER_OF(ctx, struct lmp90xxx_data, ctx);
561
562 if (repeat_sampling) {
563 data->buffer = data->repeat_buffer;
564 }
565 }
566
lmp90xxx_adc_read_channel(const struct device * dev,uint8_t channel,int32_t * result)567 static int lmp90xxx_adc_read_channel(const struct device *dev,
568 uint8_t channel,
569 int32_t *result)
570 {
571 const struct lmp90xxx_config *config = dev->config;
572 struct lmp90xxx_data *data = dev->data;
573 uint8_t adc_done;
574 uint8_t ch_scan;
575 uint8_t buf[4]; /* ADC_DOUT + CRC */
576 int32_t delay;
577 uint8_t odr;
578 int err;
579
580 /* Single channel, single scan mode */
581 ch_scan = LMP90XXX_CH_SCAN_SEL(0x1) | LMP90XXX_FIRST_CH(channel) |
582 LMP90XXX_LAST_CH(channel);
583
584 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_CH_SCAN, ch_scan);
585 if (err) {
586 LOG_ERR("failed to setup scan channels (err %d)", err);
587 return err;
588 }
589
590 /* Start scan */
591 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_PWRCN, LMP90XXX_PWRCN(0));
592 if (err) {
593 LOG_ERR("failed to set active mode (err %d)", err);
594 return err;
595 }
596
597 if (LMP90XXX_HAS_DRDYB(config)) {
598 k_sem_take(&data->drdyb_sem, K_FOREVER);
599 } else {
600 odr = data->channel_odr[channel];
601 delay = lmp90xxx_odr_delay_tbl[odr];
602 LOG_DBG("sleeping for %d ms", delay);
603 k_msleep(delay);
604
605 /* Poll for data ready */
606 do {
607 err = lmp90xxx_read_reg8(dev, LMP90XXX_REG_ADC_DONE,
608 &adc_done);
609 if (err) {
610 LOG_ERR("failed to read done (err %d)", err);
611 return err;
612 }
613
614 if (adc_done == 0xFFU) {
615 LOG_DBG("sleeping for 1 ms");
616 k_msleep(1);
617 } else {
618 break;
619 }
620 } while (true);
621 }
622
623 if (IS_ENABLED(CONFIG_ADC_LMP90XXX_CRC)) {
624 err = lmp90xxx_read_reg(dev, LMP90XXX_REG_ADC_DOUT, buf,
625 sizeof(buf));
626 } else {
627 err = lmp90xxx_read_reg(dev, LMP90XXX_REG_ADC_DOUT, buf,
628 config->resolution / 8);
629 }
630
631 if (err) {
632 LOG_ERR("failed to read ADC DOUT (err %d)", err);
633 return err;
634 }
635
636 if (IS_ENABLED(CONFIG_ADC_LMP90XXX_CRC)) {
637 uint8_t crc = crc8(buf, 3, 0x31, 0, false) ^ 0xFFU;
638
639 if (buf[3] != crc) {
640 LOG_ERR("CRC mismatch (0x%02x vs. 0x%02x)", buf[3],
641 crc);
642 return err;
643 }
644 }
645
646 /* Read result, get rid of CRC, and sign extend result */
647 *result = (int32_t)sys_get_be32(buf);
648 *result >>= (32 - config->resolution);
649
650 return 0;
651 }
652
lmp90xxx_acquisition_thread(struct lmp90xxx_data * data)653 static void lmp90xxx_acquisition_thread(struct lmp90xxx_data *data)
654 {
655 uint8_t bgcalcn = LMP90XXX_BGCALN(0x3); /* Default to BgCalMode3 */
656 int32_t result = 0;
657 uint8_t channel;
658 int err;
659
660 while (true) {
661 k_sem_take(&data->acq_sem, K_FOREVER);
662
663 if (data->calibrate) {
664 /* Use BgCalMode2 */
665 bgcalcn = LMP90XXX_BGCALN(0x2);
666 }
667
668 LOG_DBG("using BGCALCN = 0x%02x", bgcalcn);
669 err = lmp90xxx_write_reg8(data->dev,
670 LMP90XXX_REG_BGCALCN, bgcalcn);
671 if (err) {
672 LOG_ERR("failed to setup background calibration "
673 "(err %d)", err);
674 adc_context_complete(&data->ctx, err);
675 break;
676 }
677
678 while (data->channels) {
679 channel = find_lsb_set(data->channels) - 1;
680
681 LOG_DBG("reading channel %d", channel);
682
683 err = lmp90xxx_adc_read_channel(data->dev,
684 channel, &result);
685 if (err) {
686 adc_context_complete(&data->ctx, err);
687 break;
688 }
689
690 LOG_DBG("finished channel %d, result = %d", channel,
691 result);
692
693 /*
694 * ADC samples are stored as int32_t regardless of the
695 * resolution in order to provide a uniform interface
696 * for the driver.
697 */
698 *data->buffer++ = result;
699 WRITE_BIT(data->channels, channel, 0);
700 }
701
702 adc_context_on_sampling_done(&data->ctx, data->dev);
703 }
704 }
705
lmp90xxx_drdyb_callback(const struct device * port,struct gpio_callback * cb,uint32_t pins)706 static void lmp90xxx_drdyb_callback(const struct device *port,
707 struct gpio_callback *cb, uint32_t pins)
708 {
709 struct lmp90xxx_data *data =
710 CONTAINER_OF(cb, struct lmp90xxx_data, drdyb_cb);
711
712 /* Signal thread that data is now ready */
713 k_sem_give(&data->drdyb_sem);
714 }
715
716 #ifdef CONFIG_ADC_LMP90XXX_GPIO
lmp90xxx_gpio_set_output(const struct device * dev,uint8_t pin)717 int lmp90xxx_gpio_set_output(const struct device *dev, uint8_t pin)
718 {
719 struct lmp90xxx_data *data = dev->data;
720 int err = 0;
721 uint8_t tmp;
722
723 if (pin > LMP90XXX_GPIO_MAX) {
724 return -EINVAL;
725 }
726
727 k_mutex_lock(&data->gpio_lock, K_FOREVER);
728
729 tmp = data->gpio_dircn | BIT(pin);
730 if (tmp != data->gpio_dircn) {
731 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DIRCN, tmp);
732 if (!err) {
733 data->gpio_dircn = tmp;
734 }
735 }
736
737 k_mutex_unlock(&data->gpio_lock);
738
739 return err;
740 }
741
lmp90xxx_gpio_set_input(const struct device * dev,uint8_t pin)742 int lmp90xxx_gpio_set_input(const struct device *dev, uint8_t pin)
743 {
744 struct lmp90xxx_data *data = dev->data;
745 int err = 0;
746 uint8_t tmp;
747
748 if (pin > LMP90XXX_GPIO_MAX) {
749 return -EINVAL;
750 }
751
752 k_mutex_lock(&data->gpio_lock, K_FOREVER);
753
754 tmp = data->gpio_dircn & ~BIT(pin);
755 if (tmp != data->gpio_dircn) {
756 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DIRCN, tmp);
757 if (!err) {
758 data->gpio_dircn = tmp;
759 }
760 }
761
762 k_mutex_unlock(&data->gpio_lock);
763
764 return err;
765 }
766
lmp90xxx_gpio_set_pin_value(const struct device * dev,uint8_t pin,bool value)767 int lmp90xxx_gpio_set_pin_value(const struct device *dev, uint8_t pin,
768 bool value)
769 {
770 struct lmp90xxx_data *data = dev->data;
771 int err = 0;
772 uint8_t tmp;
773
774 if (pin > LMP90XXX_GPIO_MAX) {
775 return -EINVAL;
776 }
777
778 k_mutex_lock(&data->gpio_lock, K_FOREVER);
779
780 tmp = data->gpio_dat;
781 WRITE_BIT(tmp, pin, value);
782
783 if (tmp != data->gpio_dat) {
784 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DAT, tmp);
785 if (!err) {
786 data->gpio_dat = tmp;
787 }
788 }
789
790 k_mutex_unlock(&data->gpio_lock);
791
792 return err;
793 }
794
lmp90xxx_gpio_get_pin_value(const struct device * dev,uint8_t pin,bool * value)795 int lmp90xxx_gpio_get_pin_value(const struct device *dev, uint8_t pin,
796 bool *value)
797 {
798 struct lmp90xxx_data *data = dev->data;
799 int err = 0;
800 uint8_t tmp;
801
802 if (pin > LMP90XXX_GPIO_MAX) {
803 return -EINVAL;
804 }
805
806 k_mutex_lock(&data->gpio_lock, K_FOREVER);
807
808 err = lmp90xxx_read_reg8(dev, LMP90XXX_REG_GPIO_DAT, &tmp);
809 if (!err) {
810 *value = tmp & BIT(pin);
811 }
812
813 k_mutex_unlock(&data->gpio_lock);
814
815 return err;
816 }
817
lmp90xxx_gpio_port_get_raw(const struct device * dev,gpio_port_value_t * value)818 int lmp90xxx_gpio_port_get_raw(const struct device *dev,
819 gpio_port_value_t *value)
820 {
821 struct lmp90xxx_data *data = dev->data;
822 uint8_t tmp;
823 int err;
824
825 k_mutex_lock(&data->gpio_lock, K_FOREVER);
826 err = lmp90xxx_read_reg8(dev, LMP90XXX_REG_GPIO_DAT, &tmp);
827 tmp &= ~(data->gpio_dircn);
828 k_mutex_unlock(&data->gpio_lock);
829
830 *value = tmp;
831
832 return err;
833 }
834
lmp90xxx_gpio_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)835 int lmp90xxx_gpio_port_set_masked_raw(const struct device *dev,
836 gpio_port_pins_t mask,
837 gpio_port_value_t value)
838 {
839 struct lmp90xxx_data *data = dev->data;
840 int err = 0;
841 uint8_t tmp;
842
843 mask &= LMP90XXX_GPIO_DAT_MASK;
844
845 k_mutex_lock(&data->gpio_lock, K_FOREVER);
846 tmp = (data->gpio_dat & ~mask) | (value & mask);
847 if (tmp != data->gpio_dat) {
848 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DAT, tmp);
849 if (!err) {
850 data->gpio_dat = tmp;
851 }
852 }
853 k_mutex_unlock(&data->gpio_lock);
854
855 return err;
856 }
857
lmp90xxx_gpio_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)858 int lmp90xxx_gpio_port_set_bits_raw(const struct device *dev,
859 gpio_port_pins_t pins)
860 {
861 struct lmp90xxx_data *data = dev->data;
862 int err = 0;
863 uint8_t tmp;
864
865 tmp = pins & LMP90XXX_GPIO_DAT_MASK;
866
867 k_mutex_lock(&data->gpio_lock, K_FOREVER);
868 if (tmp != data->gpio_dat) {
869 tmp |= data->gpio_dat;
870 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DAT, tmp);
871 if (!err) {
872 data->gpio_dat = tmp;
873 }
874 }
875 k_mutex_unlock(&data->gpio_lock);
876
877 return err;
878 }
879
lmp90xxx_gpio_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)880 int lmp90xxx_gpio_port_clear_bits_raw(const struct device *dev,
881 gpio_port_pins_t pins)
882 {
883 struct lmp90xxx_data *data = dev->data;
884 int err = 0;
885 uint8_t tmp;
886
887 tmp = pins & LMP90XXX_GPIO_DAT_MASK;
888
889 k_mutex_lock(&data->gpio_lock, K_FOREVER);
890 if ((tmp & data->gpio_dat) != 0) {
891 tmp = data->gpio_dat & ~tmp;
892 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DAT, tmp);
893 if (!err) {
894 data->gpio_dat = tmp;
895 }
896 }
897 k_mutex_unlock(&data->gpio_lock);
898
899 return err;
900 }
901
lmp90xxx_gpio_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)902 int lmp90xxx_gpio_port_toggle_bits(const struct device *dev,
903 gpio_port_pins_t pins)
904 {
905 struct lmp90xxx_data *data = dev->data;
906 uint8_t tmp;
907 int err;
908
909 tmp = pins & LMP90XXX_GPIO_DAT_MASK;
910
911 k_mutex_lock(&data->gpio_lock, K_FOREVER);
912 tmp ^= data->gpio_dat;
913 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_GPIO_DAT, tmp);
914 if (!err) {
915 data->gpio_dat = tmp;
916 }
917 k_mutex_unlock(&data->gpio_lock);
918
919 return err;
920 }
921
922 #endif /* CONFIG_ADC_LMP90XXX_GPIO */
923
lmp90xxx_init(const struct device * dev)924 static int lmp90xxx_init(const struct device *dev)
925 {
926 const struct lmp90xxx_config *config = dev->config;
927 struct lmp90xxx_data *data = dev->data;
928 k_tid_t tid;
929 int err;
930
931 data->dev = dev;
932
933 k_mutex_init(&data->ura_lock);
934 k_sem_init(&data->acq_sem, 0, 1);
935 k_sem_init(&data->drdyb_sem, 0, 1);
936 #ifdef CONFIG_ADC_LMP90XXX_GPIO
937 k_mutex_init(&data->gpio_lock);
938 #endif /* CONFIG_ADC_LMP90XXX_GPIO */
939
940 /* Force INST1 + UAB on first access */
941 data->ura = LMP90XXX_INVALID_URA;
942
943 if (!spi_is_ready_dt(&config->bus)) {
944 LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
945 return -ENODEV;
946 }
947
948 err = lmp90xxx_soft_reset(dev);
949 if (err) {
950 LOG_ERR("failed to request soft reset (err %d)", err);
951 return err;
952 }
953
954 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_SPI_HANDSHAKECN,
955 LMP90XXX_SDO_DRDYB_DRIVER(0x4));
956 if (err) {
957 LOG_ERR("failed to set SPI handshake control (err %d)",
958 err);
959 return err;
960 }
961
962 if (config->rtd_current) {
963 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_ADC_AUXCN,
964 LMP90XXX_RTD_CUR_SEL(config->rtd_current));
965 if (err) {
966 LOG_ERR("failed to set RTD current (err %d)", err);
967 return err;
968 }
969 }
970
971 if (IS_ENABLED(CONFIG_ADC_LMP90XXX_CRC)) {
972 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_SPI_CRC_CN,
973 LMP90XXX_EN_CRC(1) |
974 LMP90XXX_DRDYB_AFT_CRC(1));
975 if (err) {
976 LOG_ERR("failed to enable CRC (err %d)", err);
977 return err;
978 }
979 }
980
981 if (LMP90XXX_HAS_DRDYB(config)) {
982 err = gpio_pin_configure_dt(&config->drdyb, GPIO_INPUT);
983 if (err) {
984 LOG_ERR("failed to configure DRDYB GPIO pin (err %d)",
985 err);
986 return -EINVAL;
987 }
988
989 gpio_init_callback(&data->drdyb_cb, lmp90xxx_drdyb_callback,
990 BIT(config->drdyb.pin));
991
992 err = gpio_add_callback(config->drdyb.port, &data->drdyb_cb);
993 if (err) {
994 LOG_ERR("failed to add DRDYB callback (err %d)", err);
995 return -EINVAL;
996 }
997
998 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_SPI_DRDYBCN,
999 LMP90XXX_SPI_DRDYB_D6(1));
1000 if (err) {
1001 LOG_ERR("failed to configure D6 as DRDYB (err %d)",
1002 err);
1003 return err;
1004 }
1005
1006 err = gpio_pin_interrupt_configure_dt(&config->drdyb,
1007 GPIO_INT_EDGE_TO_ACTIVE);
1008 if (err) {
1009 LOG_ERR("failed to configure DRDBY interrupt (err %d)",
1010 err);
1011 return -EINVAL;
1012 }
1013 }
1014
1015 tid = k_thread_create(&data->thread, data->stack,
1016 CONFIG_ADC_LMP90XXX_ACQUISITION_THREAD_STACK_SIZE,
1017 (k_thread_entry_t)lmp90xxx_acquisition_thread,
1018 data, NULL, NULL,
1019 CONFIG_ADC_LMP90XXX_ACQUISITION_THREAD_PRIO,
1020 0, K_NO_WAIT);
1021 k_thread_name_set(tid, "adc_lmp90xxx");
1022
1023 /* Put device in stand-by to prepare it for single-shot conversion */
1024 err = lmp90xxx_write_reg8(dev, LMP90XXX_REG_PWRCN, LMP90XXX_PWRCN(0x3));
1025 if (err) {
1026 LOG_ERR("failed to request stand-by mode (err %d)", err);
1027 return err;
1028 }
1029
1030 adc_context_unlock_unconditionally(&data->ctx);
1031
1032 return 0;
1033 }
1034
1035 static const struct adc_driver_api lmp90xxx_adc_api = {
1036 .channel_setup = lmp90xxx_adc_channel_setup,
1037 .read = lmp90xxx_adc_read,
1038 #ifdef CONFIG_ADC_ASYNC
1039 .read_async = lmp90xxx_adc_read_async,
1040 #endif
1041 };
1042
1043 #define ASSERT_LMP90XXX_CURRENT_VALID(v) \
1044 BUILD_ASSERT(v == 0 || v == 100 || v == 200 || v == 300 || \
1045 v == 400 || v == 500 || v == 600 || v == 700 || \
1046 v == 800 || v == 900 || v == 1000, \
1047 "unsupported RTD current (" #v ")")
1048
1049 #define LMP90XXX_UAMPS_TO_RTD_CUR_SEL(x) (x / 100)
1050
1051 #define DT_INST_LMP90XXX(inst, t) DT_INST(inst, ti_lmp##t)
1052
1053 #define LMP90XXX_INIT(t, n, res, ch) \
1054 ASSERT_LMP90XXX_CURRENT_VALID(UTIL_AND( \
1055 DT_NODE_HAS_PROP(DT_INST_LMP90XXX(n, t), rtd_current), \
1056 DT_PROP(DT_INST_LMP90XXX(n, t), rtd_current))); \
1057 static struct lmp90xxx_data lmp##t##_data_##n = { \
1058 ADC_CONTEXT_INIT_TIMER(lmp##t##_data_##n, ctx), \
1059 ADC_CONTEXT_INIT_LOCK(lmp##t##_data_##n, ctx), \
1060 ADC_CONTEXT_INIT_SYNC(lmp##t##_data_##n, ctx), \
1061 }; \
1062 static const struct lmp90xxx_config lmp##t##_config_##n = { \
1063 .bus = SPI_DT_SPEC_GET(DT_INST_LMP90XXX(n, t), SPI_OP_MODE_MASTER | \
1064 SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0), \
1065 .drdyb = GPIO_DT_SPEC_GET_OR(DT_INST_LMP90XXX(n, t), drdyb_gpios, {0}), \
1066 .rtd_current = LMP90XXX_UAMPS_TO_RTD_CUR_SEL( \
1067 DT_PROP_OR(DT_INST_LMP90XXX(n, t), rtd_current, 0)), \
1068 .resolution = res, \
1069 .channels = ch, \
1070 }; \
1071 DEVICE_DT_DEFINE(DT_INST_LMP90XXX(n, t), \
1072 &lmp90xxx_init, NULL, \
1073 &lmp##t##_data_##n, \
1074 &lmp##t##_config_##n, POST_KERNEL, \
1075 CONFIG_ADC_INIT_PRIORITY, \
1076 &lmp90xxx_adc_api);
1077
1078 /*
1079 * LMP90077: 16 bit, 2 diff/4 se (4 channels), 0 currents
1080 */
1081 #define LMP90077_INIT(n) LMP90XXX_INIT(90077, n, 16, 4)
1082 #undef DT_DRV_COMPAT
1083 #define DT_DRV_COMPAT ti_lmp90077
1084 DT_INST_FOREACH_STATUS_OKAY(LMP90077_INIT)
1085
1086 /*
1087 * LMP90078: 16 bit, 2 diff/4 se (4 channels), 2 currents
1088 */
1089 #define LMP90078_INIT(n) LMP90XXX_INIT(90078, n, 16, 4)
1090 #undef DT_DRV_COMPAT
1091 #define DT_DRV_COMPAT ti_lmp90078
1092 DT_INST_FOREACH_STATUS_OKAY(LMP90078_INIT)
1093
1094 /*
1095 * LMP90079: 16 bit, 4 diff/7 se (7 channels), 0 currents, has VIN3-5
1096 */
1097 #define LMP90079_INIT(n) LMP90XXX_INIT(90079, n, 16, 7)
1098 #undef DT_DRV_COMPAT
1099 #define DT_DRV_COMPAT ti_lmp90079
1100 DT_INST_FOREACH_STATUS_OKAY(LMP90079_INIT)
1101
1102 /*
1103 * LMP90080: 16 bit, 4 diff/7 se (7 channels), 2 currents, has VIN3-5
1104 */
1105 #define LMP90080_INIT(n) LMP90XXX_INIT(90080, n, 16, 7)
1106 #undef DT_DRV_COMPAT
1107 #define DT_DRV_COMPAT ti_lmp90080
1108 DT_INST_FOREACH_STATUS_OKAY(LMP90080_INIT)
1109
1110 /*
1111 * LMP90097: 24 bit, 2 diff/4 se (4 channels), 0 currents
1112 */
1113 #define LMP90097_INIT(n) LMP90XXX_INIT(90097, n, 24, 4)
1114 #undef DT_DRV_COMPAT
1115 #define DT_DRV_COMPAT ti_lmp90097
1116 DT_INST_FOREACH_STATUS_OKAY(LMP90097_INIT)
1117
1118 /*
1119 * LMP90098: 24 bit, 2 diff/4 se (4 channels), 2 currents
1120 */
1121 #define LMP90098_INIT(n) LMP90XXX_INIT(90098, n, 24, 4)
1122 #undef DT_DRV_COMPAT
1123 #define DT_DRV_COMPAT ti_lmp90098
1124 DT_INST_FOREACH_STATUS_OKAY(LMP90098_INIT)
1125
1126 /*
1127 * LMP90099: 24 bit, 4 diff/7 se (7 channels), 0 currents, has VIN3-5
1128 */
1129 #define LMP90099_INIT(n) LMP90XXX_INIT(90099, n, 24, 7)
1130 #undef DT_DRV_COMPAT
1131 #define DT_DRV_COMPAT ti_lmp90099
1132 DT_INST_FOREACH_STATUS_OKAY(LMP90099_INIT)
1133
1134 /*
1135 * LMP90100: 24 bit, 4 diff/7 se (7 channels), 2 currents, has VIN3-5
1136 */
1137 #define LMP90100_INIT(n) LMP90XXX_INIT(90100, n, 24, 7)
1138 #undef DT_DRV_COMPAT
1139 #define DT_DRV_COMPAT ti_lmp90100
1140 DT_INST_FOREACH_STATUS_OKAY(LMP90100_INIT)
1141
