1 /**
2 ******************************************************************************
3 * @file lis3dh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS3DH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis3dh_reg.h"
21
22 /**
23 * @defgroup LIS3DH
24 * @brief This file provides a set of functions needed to drive the
25 * lis3dh enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS3DH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis3dh_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 ret = ctx->read_reg(ctx->handle, reg, data, len);
55
56 return ret;
57 }
58
59 /**
60 * @brief Write generic device register
61 *
62 * @param ctx read / write interface definitions(ptr)
63 * @param reg register to write
64 * @param data pointer to data to write in register reg(ptr)
65 * @param len number of consecutive register to write
66 * @retval interface status (MANDATORY: return 0 -> no Error)
67 *
68 */
lis3dh_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)69 int32_t __weak lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
70 uint8_t *data,
71 uint16_t len)
72 {
73 int32_t ret;
74
75 ret = ctx->write_reg(ctx->handle, reg, data, len);
76
77 return ret;
78 }
79
80 /**
81 * @}
82 *
83 */
84
85 /**
86 * @defgroup LIS3DH_Sensitivity
87 * @brief These functions convert raw-data into engineering units.
88 * @{
89 *
90 */
91
lis3dh_from_fs2_hr_to_mg(int16_t lsb)92 float_t lis3dh_from_fs2_hr_to_mg(int16_t lsb)
93 {
94 return ((float_t)lsb / 16.0f) * 1.0f;
95 }
96
lis3dh_from_fs4_hr_to_mg(int16_t lsb)97 float_t lis3dh_from_fs4_hr_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb / 16.0f) * 2.0f;
100 }
101
lis3dh_from_fs8_hr_to_mg(int16_t lsb)102 float_t lis3dh_from_fs8_hr_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb / 16.0f) * 4.0f;
105 }
106
lis3dh_from_fs16_hr_to_mg(int16_t lsb)107 float_t lis3dh_from_fs16_hr_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb / 16.0f) * 12.0f;
110 }
111
lis3dh_from_lsb_hr_to_celsius(int16_t lsb)112 float_t lis3dh_from_lsb_hr_to_celsius(int16_t lsb)
113 {
114 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
115 }
116
lis3dh_from_fs2_nm_to_mg(int16_t lsb)117 float_t lis3dh_from_fs2_nm_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb / 64.0f) * 4.0f;
120 }
121
lis3dh_from_fs4_nm_to_mg(int16_t lsb)122 float_t lis3dh_from_fs4_nm_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb / 64.0f) * 8.0f;
125 }
126
lis3dh_from_fs8_nm_to_mg(int16_t lsb)127 float_t lis3dh_from_fs8_nm_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb / 64.0f) * 16.0f;
130 }
131
lis3dh_from_fs16_nm_to_mg(int16_t lsb)132 float_t lis3dh_from_fs16_nm_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb / 64.0f) * 48.0f;
135 }
136
lis3dh_from_lsb_nm_to_celsius(int16_t lsb)137 float_t lis3dh_from_lsb_nm_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
140 }
141
lis3dh_from_fs2_lp_to_mg(int16_t lsb)142 float_t lis3dh_from_fs2_lp_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb / 256.0f) * 16.0f;
145 }
146
lis3dh_from_fs4_lp_to_mg(int16_t lsb)147 float_t lis3dh_from_fs4_lp_to_mg(int16_t lsb)
148 {
149 return ((float_t)lsb / 256.0f) * 32.0f;
150 }
151
lis3dh_from_fs8_lp_to_mg(int16_t lsb)152 float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb)
153 {
154 return ((float_t)lsb / 256.0f) * 64.0f;
155 }
156
lis3dh_from_fs16_lp_to_mg(int16_t lsb)157 float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb)
158 {
159 return ((float_t)lsb / 256.0f) * 192.0f;
160 }
161
lis3dh_from_lsb_lp_to_celsius(int16_t lsb)162 float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
163 {
164 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
165 }
166
167 /**
168 * @}
169 *
170 */
171
172 /**
173 * @defgroup LIS3DH_Data_generation
174 * @brief This section group all the functions concerning data generation.
175 * @{
176 *
177 */
178
179 /**
180 * @brief Temperature status register.[get]
181 *
182 * @param ctx read / write interface definitions
183 * @param buff buffer that stores data read
184 * @retval interface status (MANDATORY: return 0 -> no Error)
185 *
186 */
lis3dh_temp_status_reg_get(stmdev_ctx_t * ctx,uint8_t * buff)187 int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
188 {
189 int32_t ret;
190
191 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, buff, 1);
192
193 return ret;
194 }
195 /**
196 * @brief Temperature data available.[get]
197 *
198 * @param ctx read / write interface definitions
199 * @param val change the values of tda in reg STATUS_REG_AUX
200 * @retval interface status (MANDATORY: return 0 -> no Error)
201 *
202 */
lis3dh_temp_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)203 int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
204 {
205 lis3dh_status_reg_aux_t status_reg_aux;
206 int32_t ret;
207
208 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
209 (uint8_t *)&status_reg_aux, 1);
210 *val = status_reg_aux._3da;
211
212 return ret;
213 }
214 /**
215 * @brief Temperature data overrun.[get]
216 *
217 * @param ctx read / write interface definitions
218 * @param val change the values of tor in reg STATUS_REG_AUX
219 * @retval interface status (MANDATORY: return 0 -> no Error)
220 *
221 */
lis3dh_temp_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)222 int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
223 {
224 lis3dh_status_reg_aux_t status_reg_aux;
225 int32_t ret;
226
227 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
228 (uint8_t *)&status_reg_aux, 1);
229 *val = status_reg_aux._3or;
230
231 return ret;
232 }
233 /**
234 * @brief Temperature output value.[get]
235 *
236 * @param ctx read / write interface definitions
237 * @param buff buffer that stores data read
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
lis3dh_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)241 int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
242 {
243 uint8_t buff[2];
244 int32_t ret;
245
246 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, buff, 2);
247 *val = (int16_t)buff[1];
248 *val = (*val * 256) + (int16_t)buff[0];
249
250 return ret;
251 }
252
253 /**
254 * @brief ADC output value.[get]
255 * Sample frequency: the same as the ODR CTRL_REG1
256 * The resolution:
257 * 10bit if LPen bit in CTRL_REG1 (20h) is clear
258 * 8bit if LPen bit in CTRL_REG1 (20h) is set
259 * Data Format:
260 * Outputs are Left Justified in 2’ complements
261 * range 800mV
262 * code zero means an analogue value of about 1.2V
263 * Voltage values smaller than centre values are positive
264 * (Example: 800mV = 7Fh / 127 dec)
265 * Voltage values bigger than centre values are negative
266 * (Example: 1600mV = 80h / -128 dec)
267 *
268 * @param ctx read / write interface definitions
269 * @param buff buffer that stores data read
270 * @retval interface status (MANDATORY: return 0 -> no Error)
271 *
272 */
lis3dh_adc_raw_get(stmdev_ctx_t * ctx,int16_t * val)273 int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val)
274 {
275 uint8_t buff[6];
276 int32_t ret;
277
278 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC1_L, buff, 6);
279 val[0] = (int16_t)buff[1];
280 val[0] = (val[0] * 256) + (int16_t)buff[0];
281 val[1] = (int16_t)buff[3];
282 val[1] = (val[1] * 256) + (int16_t)buff[2];
283 val[2] = (int16_t)buff[5];
284 val[2] = (val[2] * 256) + (int16_t)buff[4];
285
286 return ret;
287 }
288
289 /**
290 * @brief Auxiliary ADC.[set]
291 *
292 * @param ctx read / write interface definitions
293 * @param val configure the auxiliary ADC
294 * @retval interface status (MANDATORY: return 0 -> no Error)
295 *
296 */
lis3dh_aux_adc_set(stmdev_ctx_t * ctx,lis3dh_temp_en_t val)297 int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val)
298 {
299 lis3dh_temp_cfg_reg_t temp_cfg_reg;
300 int32_t ret;
301
302 ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
303 (uint8_t *)&temp_cfg_reg, 1);
304
305 if (ret == 0)
306 {
307 if (val != LIS3DH_AUX_DISABLE)
308 {
309 /* Required in order to use auxiliary adc */
310 ret = lis3dh_block_data_update_set(ctx, PROPERTY_ENABLE);
311 }
312 }
313
314 if (ret == 0)
315 {
316 temp_cfg_reg.temp_en = ((uint8_t) val & 0x02U) >> 1;
317 temp_cfg_reg.adc_pd = (uint8_t) val & 0x01U;
318 ret = lis3dh_write_reg(ctx, LIS3DH_TEMP_CFG_REG,
319 (uint8_t *)&temp_cfg_reg, 1);
320 }
321
322 return ret;
323 }
324
325 /**
326 * @brief Auxiliary ADC.[get]
327 *
328 * @param ctx read / write interface definitions
329 * @param val configure the auxiliary ADC
330 * @retval interface status (MANDATORY: return 0 -> no Error)
331 *
332 */
lis3dh_aux_adc_get(stmdev_ctx_t * ctx,lis3dh_temp_en_t * val)333 int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val)
334 {
335 lis3dh_temp_cfg_reg_t temp_cfg_reg;
336 int32_t ret;
337
338 ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
339 (uint8_t *)&temp_cfg_reg, 1);
340
341 if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) ==
342 PROPERTY_ENABLE)
343 {
344 *val = LIS3DH_AUX_ON_TEMPERATURE;
345 }
346
347 if ((temp_cfg_reg.temp_en == PROPERTY_DISABLE) &&
348 (temp_cfg_reg.adc_pd == PROPERTY_ENABLE))
349 {
350 *val = LIS3DH_AUX_ON_PADS;
351 }
352
353 else
354 {
355 *val = LIS3DH_AUX_DISABLE;
356 }
357
358 return ret;
359 }
360
361 /**
362 * @brief Operating mode selection.[set]
363 *
364 * @param ctx read / write interface definitions
365 * @param val change the values of lpen in reg CTRL_REG1
366 * and HR in reg CTRL_REG4
367 * @retval interface status (MANDATORY: return 0 -> no Error)
368 *
369 */
lis3dh_operating_mode_set(stmdev_ctx_t * ctx,lis3dh_op_md_t val)370 int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx,
371 lis3dh_op_md_t val)
372 {
373 lis3dh_ctrl_reg1_t ctrl_reg1;
374 lis3dh_ctrl_reg4_t ctrl_reg4;
375 int32_t ret;
376
377 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1,
378 (uint8_t *)&ctrl_reg1, 1);
379
380 if (ret == 0)
381 {
382 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4,
383 (uint8_t *)&ctrl_reg4, 1);
384 }
385
386 if (ret == 0)
387 {
388 if (val == LIS3DH_HR_12bit)
389 {
390 ctrl_reg1.lpen = 0;
391 ctrl_reg4.hr = 1;
392 }
393
394 if (val == LIS3DH_NM_10bit)
395 {
396 ctrl_reg1.lpen = 0;
397 ctrl_reg4.hr = 0;
398 }
399
400 if (val == LIS3DH_LP_8bit)
401 {
402 ctrl_reg1.lpen = 1;
403 ctrl_reg4.hr = 0;
404 }
405
406 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
407 }
408
409 if (ret == 0)
410 {
411 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
412 }
413
414 return ret;
415 }
416
417 /**
418 * @brief Operating mode selection.[get]
419 *
420 * @param ctx read / write interface definitions
421 * @param val change the values of lpen in reg CTRL_REG1
422 * @retval interface status (MANDATORY: return 0 -> no Error)
423 *
424 */
lis3dh_operating_mode_get(stmdev_ctx_t * ctx,lis3dh_op_md_t * val)425 int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx,
426 lis3dh_op_md_t *val)
427 {
428 lis3dh_ctrl_reg1_t ctrl_reg1;
429 lis3dh_ctrl_reg4_t ctrl_reg4;
430 int32_t ret;
431
432 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
433
434 if (ret == 0)
435 {
436 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
437
438 if (ctrl_reg1.lpen == PROPERTY_ENABLE)
439 {
440 *val = LIS3DH_LP_8bit;
441 }
442
443 else if (ctrl_reg4.hr == PROPERTY_ENABLE)
444 {
445 *val = LIS3DH_HR_12bit;
446 }
447
448 else
449 {
450 *val = LIS3DH_NM_10bit;
451 }
452 }
453
454 return ret;
455 }
456
457 /**
458 * @brief Output data rate selection.[set]
459 *
460 * @param ctx read / write interface definitions
461 * @param val change the values of odr in reg CTRL_REG1
462 * @retval interface status (MANDATORY: return 0 -> no Error)
463 *
464 */
lis3dh_data_rate_set(stmdev_ctx_t * ctx,lis3dh_odr_t val)465 int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val)
466 {
467 lis3dh_ctrl_reg1_t ctrl_reg1;
468 int32_t ret;
469
470 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
471
472 if (ret == 0)
473 {
474 ctrl_reg1.odr = (uint8_t)val;
475 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
476 }
477
478 return ret;
479 }
480
481 /**
482 * @brief Output data rate selection.[get]
483 *
484 * @param ctx read / write interface definitions
485 * @param val get the values of odr in reg CTRL_REG1
486 * @retval interface status (MANDATORY: return 0 -> no Error)
487 *
488 */
lis3dh_data_rate_get(stmdev_ctx_t * ctx,lis3dh_odr_t * val)489 int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val)
490 {
491 lis3dh_ctrl_reg1_t ctrl_reg1;
492 int32_t ret;
493
494 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
495
496 switch (ctrl_reg1.odr)
497 {
498 case LIS3DH_POWER_DOWN:
499 *val = LIS3DH_POWER_DOWN;
500 break;
501
502 case LIS3DH_ODR_1Hz:
503 *val = LIS3DH_ODR_1Hz;
504 break;
505
506 case LIS3DH_ODR_10Hz:
507 *val = LIS3DH_ODR_10Hz;
508 break;
509
510 case LIS3DH_ODR_25Hz:
511 *val = LIS3DH_ODR_25Hz;
512 break;
513
514 case LIS3DH_ODR_50Hz:
515 *val = LIS3DH_ODR_50Hz;
516 break;
517
518 case LIS3DH_ODR_100Hz:
519 *val = LIS3DH_ODR_100Hz;
520 break;
521
522 case LIS3DH_ODR_200Hz:
523 *val = LIS3DH_ODR_200Hz;
524 break;
525
526 case LIS3DH_ODR_400Hz:
527 *val = LIS3DH_ODR_400Hz;
528 break;
529
530 case LIS3DH_ODR_1kHz620_LP:
531 *val = LIS3DH_ODR_1kHz620_LP;
532 break;
533
534 case LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP:
535 *val = LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP;
536 break;
537
538 default:
539 *val = LIS3DH_POWER_DOWN;
540 break;
541 }
542
543 return ret;
544 }
545
546 /**
547 * @brief High pass data from internal filter sent to output register
548 * and FIFO.
549 *
550 * @param ctx read / write interface definitions
551 * @param val change the values of fds in reg CTRL_REG2
552 * @retval interface status (MANDATORY: return 0 -> no Error)
553 *
554 */
lis3dh_high_pass_on_outputs_set(stmdev_ctx_t * ctx,uint8_t val)555 int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
556 uint8_t val)
557 {
558 lis3dh_ctrl_reg2_t ctrl_reg2;
559 int32_t ret;
560
561 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
562
563 if (ret == 0)
564 {
565 ctrl_reg2.fds = val;
566 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
567 }
568
569 return ret;
570 }
571
572 /**
573 * @brief High pass data from internal filter sent to output register
574 * and FIFO.[get]
575 *
576 * @param ctx read / write interface definitions
577 * @param val change the values of fds in reg CTRL_REG2
578 * @retval interface status (MANDATORY: return 0 -> no Error)
579 *
580 */
lis3dh_high_pass_on_outputs_get(stmdev_ctx_t * ctx,uint8_t * val)581 int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
582 uint8_t *val)
583 {
584 lis3dh_ctrl_reg2_t ctrl_reg2;
585 int32_t ret;
586
587 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
588 *val = (uint8_t)ctrl_reg2.fds;
589
590 return ret;
591 }
592
593 /**
594 * @brief High-pass filter cutoff frequency selection.[set]
595 *
596 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
597 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
598 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
599 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
600 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
601 *
602 * @param ctx read / write interface definitions
603 * @param val change the values of hpcf in reg CTRL_REG2
604 * @retval interface status (MANDATORY: return 0 -> no Error)
605 *
606 */
lis3dh_high_pass_bandwidth_set(stmdev_ctx_t * ctx,lis3dh_hpcf_t val)607 int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
608 lis3dh_hpcf_t val)
609 {
610 lis3dh_ctrl_reg2_t ctrl_reg2;
611 int32_t ret;
612
613 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
614
615 if (ret == 0)
616 {
617 ctrl_reg2.hpcf = (uint8_t)val;
618 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
619 }
620
621 return ret;
622 }
623
624 /**
625 * @brief High-pass filter cutoff frequency selection.[get]
626 *
627 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
628 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
629 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
630 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
631 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
632 *
633 * @param ctx read / write interface definitions
634 * @param val get the values of hpcf in reg CTRL_REG2
635 * @retval interface status (MANDATORY: return 0 -> no Error)
636 *
637 */
lis3dh_high_pass_bandwidth_get(stmdev_ctx_t * ctx,lis3dh_hpcf_t * val)638 int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
639 lis3dh_hpcf_t *val)
640 {
641 lis3dh_ctrl_reg2_t ctrl_reg2;
642 int32_t ret;
643
644 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
645
646 switch (ctrl_reg2.hpcf)
647 {
648 case LIS3DH_AGGRESSIVE:
649 *val = LIS3DH_AGGRESSIVE;
650 break;
651
652 case LIS3DH_STRONG:
653 *val = LIS3DH_STRONG;
654 break;
655
656 case LIS3DH_MEDIUM:
657 *val = LIS3DH_MEDIUM;
658 break;
659
660 case LIS3DH_LIGHT:
661 *val = LIS3DH_LIGHT;
662 break;
663
664 default:
665 *val = LIS3DH_LIGHT;
666 break;
667 }
668
669 return ret;
670 }
671
672 /**
673 * @brief High-pass filter mode selection.[set]
674 *
675 * @param ctx read / write interface definitions
676 * @param val change the values of hpm in reg CTRL_REG2
677 * @retval interface status (MANDATORY: return 0 -> no Error)
678 *
679 */
lis3dh_high_pass_mode_set(stmdev_ctx_t * ctx,lis3dh_hpm_t val)680 int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val)
681 {
682 lis3dh_ctrl_reg2_t ctrl_reg2;
683 int32_t ret;
684
685 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
686
687 if (ret == 0)
688 {
689 ctrl_reg2.hpm = (uint8_t)val;
690 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
691 }
692
693 return ret;
694 }
695
696 /**
697 * @brief High-pass filter mode selection.[get]
698 *
699 * @param ctx read / write interface definitions
700 * @param val get the values of hpm in reg CTRL_REG2
701 * @retval interface status (MANDATORY: return 0 -> no Error)
702 *
703 */
lis3dh_high_pass_mode_get(stmdev_ctx_t * ctx,lis3dh_hpm_t * val)704 int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx,
705 lis3dh_hpm_t *val)
706 {
707 lis3dh_ctrl_reg2_t ctrl_reg2;
708 int32_t ret;
709
710 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
711
712 switch (ctrl_reg2.hpm)
713 {
714 case LIS3DH_NORMAL_WITH_RST:
715 *val = LIS3DH_NORMAL_WITH_RST;
716 break;
717
718 case LIS3DH_REFERENCE_MODE:
719 *val = LIS3DH_REFERENCE_MODE;
720 break;
721
722 case LIS3DH_NORMAL:
723 *val = LIS3DH_NORMAL;
724 break;
725
726 case LIS3DH_AUTORST_ON_INT:
727 *val = LIS3DH_AUTORST_ON_INT;
728 break;
729
730 default:
731 *val = LIS3DH_NORMAL_WITH_RST;
732 break;
733 }
734
735 return ret;
736 }
737
738 /**
739 * @brief Full-scale configuration.[set]
740 *
741 * @param ctx read / write interface definitions
742 * @param val change the values of fs in reg CTRL_REG4
743 * @retval interface status (MANDATORY: return 0 -> no Error)
744 *
745 */
lis3dh_full_scale_set(stmdev_ctx_t * ctx,lis3dh_fs_t val)746 int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val)
747 {
748 lis3dh_ctrl_reg4_t ctrl_reg4;
749 int32_t ret;
750
751 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
752
753 if (ret == 0)
754 {
755 ctrl_reg4.fs = (uint8_t)val;
756 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
757 }
758
759 return ret;
760 }
761
762 /**
763 * @brief Full-scale configuration.[get]
764 *
765 * @param ctx read / write interface definitions
766 * @param val get the values of fs in reg CTRL_REG4
767 * @retval interface status (MANDATORY: return 0 -> no Error)
768 *
769 */
lis3dh_full_scale_get(stmdev_ctx_t * ctx,lis3dh_fs_t * val)770 int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val)
771 {
772 lis3dh_ctrl_reg4_t ctrl_reg4;
773 int32_t ret;
774
775 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
776
777 switch (ctrl_reg4.fs)
778 {
779 case LIS3DH_2g:
780 *val = LIS3DH_2g;
781 break;
782
783 case LIS3DH_4g:
784 *val = LIS3DH_4g;
785 break;
786
787 case LIS3DH_8g:
788 *val = LIS3DH_8g;
789 break;
790
791 case LIS3DH_16g:
792 *val = LIS3DH_16g;
793 break;
794
795 default:
796 *val = LIS3DH_2g;
797 break;
798 }
799
800 return ret;
801 }
802
803 /**
804 * @brief Block Data Update.[set]
805 *
806 * @param ctx read / write interface definitions
807 * @param val change the values of bdu in reg CTRL_REG4
808 * @retval interface status (MANDATORY: return 0 -> no Error)
809 *
810 */
lis3dh_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)811 int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
812 {
813 lis3dh_ctrl_reg4_t ctrl_reg4;
814 int32_t ret;
815
816 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
817
818 if (ret == 0)
819 {
820 ctrl_reg4.bdu = val;
821 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
822 }
823
824 return ret;
825 }
826
827 /**
828 * @brief Block Data Update.[get]
829 *
830 * @param ctx read / write interface definitions
831 * @param val change the values of bdu in reg CTRL_REG4
832 * @retval interface status (MANDATORY: return 0 -> no Error)
833 *
834 */
lis3dh_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)835 int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
836 {
837 lis3dh_ctrl_reg4_t ctrl_reg4;
838 int32_t ret;
839
840 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
841 *val = (uint8_t)ctrl_reg4.bdu;
842
843 return ret;
844 }
845
846 /**
847 * @brief Reference value for interrupt generation.[set]
848 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
849 *
850 * @param ctx read / write interface definitions
851 * @param buff buffer that contains data to write
852 * @retval interface status (MANDATORY: return 0 -> no Error)
853 *
854 */
lis3dh_filter_reference_set(stmdev_ctx_t * ctx,uint8_t * buff)855 int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
856 {
857 int32_t ret;
858
859 ret = lis3dh_write_reg(ctx, LIS3DH_REFERENCE, buff, 1);
860
861 return ret;
862 }
863
864 /**
865 * @brief Reference value for interrupt generation.[get]
866 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
867 *
868 * @param ctx read / write interface definitions
869 * @param buff buffer that stores data read
870 * @retval interface status (MANDATORY: return 0 -> no Error)
871 *
872 */
lis3dh_filter_reference_get(stmdev_ctx_t * ctx,uint8_t * buff)873 int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
874 {
875 int32_t ret;
876
877 ret = lis3dh_read_reg(ctx, LIS3DH_REFERENCE, buff, 1);
878
879 return ret;
880 }
881 /**
882 * @brief Acceleration set of data available.[get]
883 *
884 * @param ctx read / write interface definitions
885 * @param val change the values of zyxda in reg STATUS_REG
886 * @retval interface status (MANDATORY: return 0 -> no Error)
887 *
888 */
lis3dh_xl_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)889 int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
890 {
891 lis3dh_status_reg_t status_reg;
892 int32_t ret;
893
894 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
895 *val = status_reg.zyxda;
896
897 return ret;
898 }
899 /**
900 * @brief Acceleration set of data overrun.[get]
901 *
902 * @param ctx read / write interface definitions
903 * @param val change the values of zyxor in reg STATUS_REG
904 * @retval interface status (MANDATORY: return 0 -> no Error)
905 *
906 */
lis3dh_xl_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)907 int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
908 {
909 lis3dh_status_reg_t status_reg;
910 int32_t ret;
911
912 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
913 *val = status_reg.zyxor;
914
915 return ret;
916 }
917 /**
918 * @brief Acceleration output value.[get]
919 *
920 * @param ctx read / write interface definitions
921 * @param buff buffer that stores data read
922 * @retval interface status (MANDATORY: return 0 -> no Error)
923 *
924 */
lis3dh_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)925 int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
926 {
927 uint8_t buff[6];
928 int32_t ret;
929
930 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_X_L, buff, 6);
931 val[0] = (int16_t)buff[1];
932 val[0] = (val[0] * 256) + (int16_t)buff[0];
933 val[1] = (int16_t)buff[3];
934 val[1] = (val[1] * 256) + (int16_t)buff[2];
935 val[2] = (int16_t)buff[5];
936 val[2] = (val[2] * 256) + (int16_t)buff[4];
937
938 return ret;
939 }
940 /**
941 * @}
942 *
943 */
944
945 /**
946 * @defgroup LIS3DH_Common
947 * @brief This section group common useful functions
948 * @{
949 *
950 */
951
952 /**
953 * @brief DeviceWhoamI .[get]
954 *
955 * @param ctx read / write interface definitions
956 * @param buff buffer that stores data read
957 * @retval interface status (MANDATORY: return 0 -> no Error)
958 *
959 */
lis3dh_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)960 int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
961 {
962 int32_t ret;
963
964 ret = lis3dh_read_reg(ctx, LIS3DH_WHO_AM_I, buff, 1);
965
966 return ret;
967 }
968 /**
969 * @brief Self Test.[set]
970 *
971 * @param ctx read / write interface definitions
972 * @param val change the values of st in reg CTRL_REG4
973 * @retval interface status (MANDATORY: return 0 -> no Error)
974 *
975 */
lis3dh_self_test_set(stmdev_ctx_t * ctx,lis3dh_st_t val)976 int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val)
977 {
978 lis3dh_ctrl_reg4_t ctrl_reg4;
979 int32_t ret;
980
981 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
982
983 if (ret == 0)
984 {
985 ctrl_reg4.st = (uint8_t)val;
986 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
987 }
988
989 return ret;
990 }
991
992 /**
993 * @brief Self Test.[get]
994 *
995 * @param ctx read / write interface definitions
996 * @param val Get the values of st in reg CTRL_REG4
997 * @retval interface status (MANDATORY: return 0 -> no Error)
998 *
999 */
lis3dh_self_test_get(stmdev_ctx_t * ctx,lis3dh_st_t * val)1000 int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val)
1001 {
1002 lis3dh_ctrl_reg4_t ctrl_reg4;
1003 int32_t ret;
1004
1005 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1006
1007 switch (ctrl_reg4.st)
1008 {
1009 case LIS3DH_ST_DISABLE:
1010 *val = LIS3DH_ST_DISABLE;
1011 break;
1012
1013 case LIS3DH_ST_POSITIVE:
1014 *val = LIS3DH_ST_POSITIVE;
1015 break;
1016
1017 case LIS3DH_ST_NEGATIVE:
1018 *val = LIS3DH_ST_NEGATIVE;
1019 break;
1020
1021 default:
1022 *val = LIS3DH_ST_DISABLE;
1023 break;
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Big/Little Endian data selection.[set]
1031 *
1032 * @param ctx read / write interface definitions
1033 * @param val change the values of ble in reg CTRL_REG4
1034 * @retval interface status (MANDATORY: return 0 -> no Error)
1035 *
1036 */
lis3dh_data_format_set(stmdev_ctx_t * ctx,lis3dh_ble_t val)1037 int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val)
1038 {
1039 lis3dh_ctrl_reg4_t ctrl_reg4;
1040 int32_t ret;
1041
1042 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1043
1044 if (ret == 0)
1045 {
1046 ctrl_reg4.ble = (uint8_t)val;
1047 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1048 }
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief Big/Little Endian data selection.[get]
1055 *
1056 * @param ctx read / write interface definitions
1057 * @param val get the values of ble in reg CTRL_REG4
1058 * @retval interface status (MANDATORY: return 0 -> no Error)
1059 *
1060 */
lis3dh_data_format_get(stmdev_ctx_t * ctx,lis3dh_ble_t * val)1061 int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val)
1062 {
1063 lis3dh_ctrl_reg4_t ctrl_reg4;
1064 int32_t ret;
1065
1066 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1067
1068 switch (ctrl_reg4.ble)
1069 {
1070 case LIS3DH_LSB_AT_LOW_ADD:
1071 *val = LIS3DH_LSB_AT_LOW_ADD;
1072 break;
1073
1074 case LIS3DH_MSB_AT_LOW_ADD:
1075 *val = LIS3DH_MSB_AT_LOW_ADD;
1076 break;
1077
1078 default:
1079 *val = LIS3DH_LSB_AT_LOW_ADD;
1080 break;
1081 }
1082
1083 return ret;
1084 }
1085
1086 /**
1087 * @brief Reboot memory content. Reload the calibration parameters.[set]
1088 *
1089 * @param ctx read / write interface definitions
1090 * @param val change the values of boot in reg CTRL_REG5
1091 * @retval interface status (MANDATORY: return 0 -> no Error)
1092 *
1093 */
lis3dh_boot_set(stmdev_ctx_t * ctx,uint8_t val)1094 int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1095 {
1096 lis3dh_ctrl_reg5_t ctrl_reg5;
1097 int32_t ret;
1098
1099 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1100
1101 if (ret == 0)
1102 {
1103 ctrl_reg5.boot = val;
1104 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1105 }
1106
1107 return ret;
1108 }
1109
1110 /**
1111 * @brief Reboot memory content. Reload the calibration parameters.[get]
1112 *
1113 * @param ctx read / write interface definitions
1114 * @param val change the values of boot in reg CTRL_REG5
1115 * @retval interface status (MANDATORY: return 0 -> no Error)
1116 *
1117 */
lis3dh_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1118 int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1119 {
1120 lis3dh_ctrl_reg5_t ctrl_reg5;
1121 int32_t ret;
1122
1123 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1124 *val = (uint8_t)ctrl_reg5.boot;
1125
1126 return ret;
1127 }
1128
1129 /**
1130 * @brief Info about device status.[get]
1131 *
1132 * @param ctx read / write interface definitions
1133 * @param val register STATUS_REG
1134 * @retval interface status (MANDATORY: return 0 -> no Error)
1135 *
1136 */
lis3dh_status_get(stmdev_ctx_t * ctx,lis3dh_status_reg_t * val)1137 int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val)
1138 {
1139 int32_t ret;
1140
1141 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *) val, 1);
1142
1143 return ret;
1144 }
1145 /**
1146 * @}
1147 *
1148 */
1149
1150 /**
1151 * @defgroup LIS3DH_Interrupts_generator_1
1152 * @brief This section group all the functions that manage the first
1153 * interrupts generator
1154 * @{
1155 *
1156 */
1157
1158 /**
1159 * @brief Interrupt generator 1 configuration register.[set]
1160 *
1161 * @param ctx read / write interface definitions
1162 * @param val register INT1_CFG
1163 * @retval interface status (MANDATORY: return 0 -> no Error)
1164 *
1165 */
lis3dh_int1_gen_conf_set(stmdev_ctx_t * ctx,lis3dh_int1_cfg_t * val)1166 int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
1167 lis3dh_int1_cfg_t *val)
1168 {
1169 int32_t ret;
1170
1171 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
1172
1173 return ret;
1174 }
1175
1176 /**
1177 * @brief Interrupt generator 1 configuration register.[get]
1178 *
1179 * @param ctx read / write interface definitions
1180 * @param val register INT1_CFG
1181 * @retval interface status (MANDATORY: return 0 -> no Error)
1182 *
1183 */
lis3dh_int1_gen_conf_get(stmdev_ctx_t * ctx,lis3dh_int1_cfg_t * val)1184 int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
1185 lis3dh_int1_cfg_t *val)
1186 {
1187 int32_t ret;
1188
1189 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
1190
1191 return ret;
1192 }
1193
1194 /**
1195 * @brief Interrupt generator 1 source register.[get]
1196 *
1197 * @param ctx read / write interface definitions
1198 * @param val Registers INT1_SRC
1199 * @retval interface status (MANDATORY: return 0 -> no Error)
1200 *
1201 */
lis3dh_int1_gen_source_get(stmdev_ctx_t * ctx,lis3dh_int1_src_t * val)1202 int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx,
1203 lis3dh_int1_src_t *val)
1204 {
1205 int32_t ret;
1206
1207 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_SRC, (uint8_t *) val, 1);
1208
1209 return ret;
1210 }
1211 /**
1212 * @brief User-defined threshold value for xl interrupt event on
1213 * generator 1.[set]
1214 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1215 *
1216 * @param ctx read / write interface definitions
1217 * @param val change the values of ths in reg INT1_THS
1218 * @retval interface status (MANDATORY: return 0 -> no Error)
1219 *
1220 */
lis3dh_int1_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1221 int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1222 {
1223 lis3dh_int1_ths_t int1_ths;
1224 int32_t ret;
1225
1226 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1227
1228 if (ret == 0)
1229 {
1230 int1_ths.ths = val;
1231 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1232 }
1233
1234 return ret;
1235 }
1236
1237 /**
1238 * @brief User-defined threshold value for xl interrupt event on
1239 * generator 1.[get]
1240 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1241 *
1242 * @param ctx read / write interface definitions
1243 * @param val change the values of ths in reg INT1_THS
1244 * @retval interface status (MANDATORY: return 0 -> no Error)
1245 *
1246 */
lis3dh_int1_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1247 int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1248 {
1249 lis3dh_int1_ths_t int1_ths;
1250 int32_t ret;
1251
1252 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1253 *val = (uint8_t)int1_ths.ths;
1254
1255 return ret;
1256 }
1257
1258 /**
1259 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1260 * recognized.[set]
1261 *
1262 * @param ctx read / write interface definitions
1263 * @param val change the values of d in reg INT1_DURATION
1264 * @retval interface status (MANDATORY: return 0 -> no Error)
1265 *
1266 */
lis3dh_int1_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1267 int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1268 {
1269 lis3dh_int1_duration_t int1_duration;
1270 int32_t ret;
1271
1272 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
1273 (uint8_t *)&int1_duration, 1);
1274
1275 if (ret == 0)
1276 {
1277 int1_duration.d = val;
1278 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_DURATION,
1279 (uint8_t *)&int1_duration, 1);
1280 }
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1287 * recognized.[get]
1288 *
1289 * @param ctx read / write interface definitions
1290 * @param val change the values of d in reg INT1_DURATION
1291 * @retval interface status (MANDATORY: return 0 -> no Error)
1292 *
1293 */
lis3dh_int1_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1294 int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
1295 {
1296 lis3dh_int1_duration_t int1_duration;
1297 int32_t ret;
1298
1299 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
1300 (uint8_t *)&int1_duration, 1);
1301 *val = (uint8_t)int1_duration.d;
1302
1303 return ret;
1304 }
1305
1306 /**
1307 * @}
1308 *
1309 */
1310
1311 /**
1312 * @defgroup LIS3DH_Interrupts_generator_2
1313 * @brief This section group all the functions that manage the second
1314 * interrupts generator
1315 * @{
1316 *
1317 */
1318
1319 /**
1320 * @brief Interrupt generator 2 configuration register.[set]
1321 *
1322 * @param ctx read / write interface definitions
1323 * @param val registers INT2_CFG
1324 * @retval interface status (MANDATORY: return 0 -> no Error)
1325 *
1326 */
lis3dh_int2_gen_conf_set(stmdev_ctx_t * ctx,lis3dh_int2_cfg_t * val)1327 int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
1328 lis3dh_int2_cfg_t *val)
1329 {
1330 int32_t ret;
1331
1332 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
1333
1334 return ret;
1335 }
1336
1337 /**
1338 * @brief Interrupt generator 2 configuration register.[get]
1339 *
1340 * @param ctx read / write interface definitions
1341 * @param val registers INT2_CFG
1342 * @retval interface status (MANDATORY: return 0 -> no Error)
1343 *
1344 */
lis3dh_int2_gen_conf_get(stmdev_ctx_t * ctx,lis3dh_int2_cfg_t * val)1345 int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
1346 lis3dh_int2_cfg_t *val)
1347 {
1348 int32_t ret;
1349
1350 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
1351
1352 return ret;
1353 }
1354 /**
1355 * @brief Interrupt generator 2 source register.[get]
1356 *
1357 * @param ctx read / write interface definitions
1358 * @param val registers INT2_SRC
1359 * @retval interface status (MANDATORY: return 0 -> no Error)
1360 *
1361 */
lis3dh_int2_gen_source_get(stmdev_ctx_t * ctx,lis3dh_int2_src_t * val)1362 int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx,
1363 lis3dh_int2_src_t *val)
1364 {
1365 int32_t ret;
1366
1367 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_SRC, (uint8_t *) val, 1);
1368
1369 return ret;
1370 }
1371 /**
1372 * @brief User-defined threshold value for xl interrupt event on
1373 * generator 2.[set]
1374 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1375 *
1376 * @param ctx read / write interface definitions
1377 * @param val change the values of ths in reg INT2_THS
1378 * @retval interface status (MANDATORY: return 0 -> no Error)
1379 *
1380 */
lis3dh_int2_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1381 int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1382 {
1383 lis3dh_int2_ths_t int2_ths;
1384 int32_t ret;
1385
1386 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1387
1388 if (ret == 0)
1389 {
1390 int2_ths.ths = val;
1391 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1392 }
1393
1394 return ret;
1395 }
1396
1397 /**
1398 * @brief User-defined threshold value for xl interrupt event on
1399 * generator 2.[get]
1400 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1401 *
1402 * @param ctx read / write interface definitions
1403 * @param val change the values of ths in reg INT2_THS
1404 * @retval interface status (MANDATORY: return 0 -> no Error)
1405 *
1406 */
lis3dh_int2_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1407 int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1408 {
1409 lis3dh_int2_ths_t int2_ths;
1410 int32_t ret;
1411
1412 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1413 *val = (uint8_t)int2_ths.ths;
1414
1415 return ret;
1416 }
1417
1418 /**
1419 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1420 * recognized .[set]
1421 *
1422 * @param ctx read / write interface definitions
1423 * @param val change the values of d in reg INT2_DURATION
1424 * @retval interface status (MANDATORY: return 0 -> no Error)
1425 *
1426 */
lis3dh_int2_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1427 int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1428 {
1429 lis3dh_int2_duration_t int2_duration;
1430 int32_t ret;
1431
1432 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
1433 (uint8_t *)&int2_duration, 1);
1434
1435 if (ret == 0)
1436 {
1437 int2_duration.d = val;
1438 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_DURATION,
1439 (uint8_t *)&int2_duration, 1);
1440 }
1441
1442 return ret;
1443 }
1444
1445 /**
1446 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1447 * recognized.[get]
1448 *
1449 * @param ctx read / write interface definitions
1450 * @param val change the values of d in reg INT2_DURATION
1451 * @retval interface status (MANDATORY: return 0 -> no Error)
1452 *
1453 */
lis3dh_int2_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1454 int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
1455 {
1456 lis3dh_int2_duration_t int2_duration;
1457 int32_t ret;
1458
1459 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
1460 (uint8_t *)&int2_duration, 1);
1461 *val = (uint8_t)int2_duration.d;
1462
1463 return ret;
1464 }
1465
1466 /**
1467 * @}
1468 *
1469 */
1470
1471 /**
1472 * @defgroup LIS3DH_Interrupt_pins
1473 * @brief This section group all the functions that manage interrupt pins
1474 * @{
1475 *
1476 */
1477
1478 /**
1479 * @brief High-pass filter on interrupts/tap generator.[set]
1480 *
1481 * @param ctx read / write interface definitions
1482 * @param val change the values of hp in reg CTRL_REG2
1483 * @retval interface status (MANDATORY: return 0 -> no Error)
1484 *
1485 */
lis3dh_high_pass_int_conf_set(stmdev_ctx_t * ctx,lis3dh_hp_t val)1486 int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
1487 lis3dh_hp_t val)
1488 {
1489 lis3dh_ctrl_reg2_t ctrl_reg2;
1490 int32_t ret;
1491
1492 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1493
1494 if (ret == 0)
1495 {
1496 ctrl_reg2.hp = (uint8_t)val;
1497 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1498 }
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * @brief High-pass filter on interrupts/tap generator.[get]
1505 *
1506 * @param ctx read / write interface definitions
1507 * @param val Get the values of hp in reg CTRL_REG2
1508 * @retval interface status (MANDATORY: return 0 -> no Error)
1509 *
1510 */
lis3dh_high_pass_int_conf_get(stmdev_ctx_t * ctx,lis3dh_hp_t * val)1511 int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
1512 lis3dh_hp_t *val)
1513 {
1514 lis3dh_ctrl_reg2_t ctrl_reg2;
1515 int32_t ret;
1516
1517 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1518
1519 switch (ctrl_reg2.hp)
1520 {
1521 case LIS3DH_DISC_FROM_INT_GENERATOR:
1522 *val = LIS3DH_DISC_FROM_INT_GENERATOR;
1523 break;
1524
1525 case LIS3DH_ON_INT1_GEN:
1526 *val = LIS3DH_ON_INT1_GEN;
1527 break;
1528
1529 case LIS3DH_ON_INT2_GEN:
1530 *val = LIS3DH_ON_INT2_GEN;
1531 break;
1532
1533 case LIS3DH_ON_TAP_GEN:
1534 *val = LIS3DH_ON_TAP_GEN;
1535 break;
1536
1537 case LIS3DH_ON_INT1_INT2_GEN:
1538 *val = LIS3DH_ON_INT1_INT2_GEN;
1539 break;
1540
1541 case LIS3DH_ON_INT1_TAP_GEN:
1542 *val = LIS3DH_ON_INT1_TAP_GEN;
1543 break;
1544
1545 case LIS3DH_ON_INT2_TAP_GEN:
1546 *val = LIS3DH_ON_INT2_TAP_GEN;
1547 break;
1548
1549 case LIS3DH_ON_INT1_INT2_TAP_GEN:
1550 *val = LIS3DH_ON_INT1_INT2_TAP_GEN;
1551 break;
1552
1553 default:
1554 *val = LIS3DH_DISC_FROM_INT_GENERATOR;
1555 break;
1556 }
1557
1558 return ret;
1559 }
1560
1561 /**
1562 * @brief Int1 pin routing configuration register.[set]
1563 *
1564 * @param ctx read / write interface definitions
1565 * @param val registers CTRL_REG3
1566 * @retval interface status (MANDATORY: return 0 -> no Error)
1567 *
1568 */
lis3dh_pin_int1_config_set(stmdev_ctx_t * ctx,lis3dh_ctrl_reg3_t * val)1569 int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
1570 lis3dh_ctrl_reg3_t *val)
1571 {
1572 int32_t ret;
1573
1574 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
1575
1576 return ret;
1577 }
1578
1579 /**
1580 * @brief Int1 pin routing configuration register.[get]
1581 *
1582 * @param ctx read / write interface definitions
1583 * @param val registers CTRL_REG3
1584 * @retval interface status (MANDATORY: return 0 -> no Error)
1585 *
1586 */
lis3dh_pin_int1_config_get(stmdev_ctx_t * ctx,lis3dh_ctrl_reg3_t * val)1587 int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx,
1588 lis3dh_ctrl_reg3_t *val)
1589 {
1590 int32_t ret;
1591
1592 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
1593
1594 return ret;
1595 }
1596 /**
1597 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1598 * on INT2 pin when 6D bit on
1599 * INT2_CFG (34h) is set to 1.
1600 *
1601 * @param ctx read / write interface definitions
1602 * @param val change the values of d4d_int2 in reg CTRL_REG5
1603 * @retval interface status (MANDATORY: return 0 -> no Error)
1604 *
1605 */
lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1606 int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
1607 {
1608 lis3dh_ctrl_reg5_t ctrl_reg5;
1609 int32_t ret;
1610
1611 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1612
1613 if (ret == 0)
1614 {
1615 ctrl_reg5.d4d_int2 = val;
1616 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1617 }
1618
1619 return ret;
1620 }
1621
1622 /**
1623 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1624 * INT2_CFG (34h) is set to 1.[get]
1625 *
1626 * @param ctx read / write interface definitions
1627 * @param val change the values of d4d_int2 in reg CTRL_REG5
1628 * @retval interface status (MANDATORY: return 0 -> no Error)
1629 *
1630 */
lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1631 int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
1632 {
1633 lis3dh_ctrl_reg5_t ctrl_reg5;
1634 int32_t ret;
1635
1636 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1637 *val = (uint8_t)ctrl_reg5.d4d_int2;
1638
1639 return ret;
1640 }
1641
1642 /**
1643 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1644 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1645 * itself.[set]
1646 *
1647 * @param ctx read / write interface definitions
1648 * @param val change the values of lir_int2 in reg CTRL_REG5
1649 * @retval interface status (MANDATORY: return 0 -> no Error)
1650 *
1651 */
lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t * ctx,lis3dh_lir_int2_t val)1652 int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
1653 lis3dh_lir_int2_t val)
1654 {
1655 lis3dh_ctrl_reg5_t ctrl_reg5;
1656 int32_t ret;
1657
1658 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1659
1660 if (ret == 0)
1661 {
1662 ctrl_reg5.lir_int2 = (uint8_t)val;
1663 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1664 }
1665
1666 return ret;
1667 }
1668
1669 /**
1670 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1671 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1672 * itself.[get]
1673 *
1674 * @param ctx read / write interface definitions
1675 * @param val Get the values of lir_int2 in reg CTRL_REG5
1676 * @retval interface status (MANDATORY: return 0 -> no Error)
1677 *
1678 */
lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t * ctx,lis3dh_lir_int2_t * val)1679 int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
1680 lis3dh_lir_int2_t *val)
1681 {
1682 lis3dh_ctrl_reg5_t ctrl_reg5;
1683 int32_t ret;
1684
1685 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1686
1687 switch (ctrl_reg5.lir_int2)
1688 {
1689 case LIS3DH_INT2_PULSED:
1690 *val = LIS3DH_INT2_PULSED;
1691 break;
1692
1693 case LIS3DH_INT2_LATCHED:
1694 *val = LIS3DH_INT2_LATCHED;
1695 break;
1696
1697 default:
1698 *val = LIS3DH_INT2_PULSED;
1699 break;
1700 }
1701
1702 return ret;
1703 }
1704
1705 /**
1706 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1707 * on INT1_CFG(30h) is set to 1.[set]
1708 *
1709 * @param ctx read / write interface definitions
1710 * @param val change the values of d4d_int1 in reg CTRL_REG5
1711 * @retval interface status (MANDATORY: return 0 -> no Error)
1712 *
1713 */
lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1714 int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
1715 {
1716 lis3dh_ctrl_reg5_t ctrl_reg5;
1717 int32_t ret;
1718
1719 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1720
1721 if (ret == 0)
1722 {
1723 ctrl_reg5.d4d_int1 = val;
1724 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1725 }
1726
1727 return ret;
1728 }
1729
1730 /**
1731 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1732 * INT1_CFG(30h) is set to 1.[get]
1733 *
1734 * @param ctx read / write interface definitions
1735 * @param val change the values of d4d_int1 in reg CTRL_REG5
1736 * @retval interface status (MANDATORY: return 0 -> no Error)
1737 *
1738 */
lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1739 int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
1740 {
1741 lis3dh_ctrl_reg5_t ctrl_reg5;
1742 int32_t ret;
1743
1744 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1745 *val = (uint8_t)ctrl_reg5.d4d_int1;
1746
1747 return ret;
1748 }
1749
1750 /**
1751 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1752 * register cleared by reading INT1_SRC (31h) itself.[set]
1753 *
1754 * @param ctx read / write interface definitions
1755 * @param val change the values of lir_int1 in reg CTRL_REG5
1756 * @retval interface status (MANDATORY: return 0 -> no Error)
1757 *
1758 */
lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t * ctx,lis3dh_lir_int1_t val)1759 int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
1760 lis3dh_lir_int1_t val)
1761 {
1762 lis3dh_ctrl_reg5_t ctrl_reg5;
1763 int32_t ret;
1764
1765 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1766
1767 if (ret == 0)
1768 {
1769 ctrl_reg5.lir_int1 = (uint8_t)val;
1770 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1771 }
1772
1773 return ret;
1774 }
1775
1776 /**
1777 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1778 * register cleared by reading INT1_SRC (31h) itself.[get]
1779 *
1780 * @param ctx read / write interface definitions
1781 * @param val Get the values of lir_int1 in reg CTRL_REG5
1782 * @retval interface status (MANDATORY: return 0 -> no Error)
1783 *
1784 */
lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t * ctx,lis3dh_lir_int1_t * val)1785 int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
1786 lis3dh_lir_int1_t *val)
1787 {
1788 lis3dh_ctrl_reg5_t ctrl_reg5;
1789 int32_t ret;
1790
1791 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1792
1793 switch (ctrl_reg5.lir_int1)
1794 {
1795 case LIS3DH_INT1_PULSED:
1796 *val = LIS3DH_INT1_PULSED;
1797 break;
1798
1799 case LIS3DH_INT1_LATCHED:
1800 *val = LIS3DH_INT1_LATCHED;
1801 break;
1802
1803 default:
1804 *val = LIS3DH_INT1_PULSED;
1805 break;
1806 }
1807
1808 return ret;
1809 }
1810
1811 /**
1812 * @brief Int2 pin routing configuration register.[set]
1813 *
1814 * @param ctx read / write interface definitions
1815 * @param val registers CTRL_REG6
1816 * @retval interface status (MANDATORY: return 0 -> no Error)
1817 *
1818 */
lis3dh_pin_int2_config_set(stmdev_ctx_t * ctx,lis3dh_ctrl_reg6_t * val)1819 int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
1820 lis3dh_ctrl_reg6_t *val)
1821 {
1822 int32_t ret;
1823
1824 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
1825
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief Int2 pin routing configuration register.[get]
1831 *
1832 * @param ctx read / write interface definitions
1833 * @param val registers CTRL_REG6
1834 * @retval interface status (MANDATORY: return 0 -> no Error)
1835 *
1836 */
lis3dh_pin_int2_config_get(stmdev_ctx_t * ctx,lis3dh_ctrl_reg6_t * val)1837 int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx,
1838 lis3dh_ctrl_reg6_t *val)
1839 {
1840 int32_t ret;
1841
1842 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
1843
1844 return ret;
1845 }
1846 /**
1847 * @}
1848 *
1849 */
1850
1851 /**
1852 * @defgroup LIS3DH_Fifo
1853 * @brief This section group all the functions concerning the fifo usage
1854 * @{
1855 *
1856 */
1857
1858 /**
1859 * @brief FIFO enable.[set]
1860 *
1861 * @param ctx read / write interface definitions
1862 * @param val change the values of fifo_en in reg CTRL_REG5
1863 * @retval interface status (MANDATORY: return 0 -> no Error)
1864 *
1865 */
lis3dh_fifo_set(stmdev_ctx_t * ctx,uint8_t val)1866 int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
1867 {
1868 lis3dh_ctrl_reg5_t ctrl_reg5;
1869 int32_t ret;
1870
1871 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1872
1873 if (ret == 0)
1874 {
1875 ctrl_reg5.fifo_en = val;
1876 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1877 }
1878
1879 return ret;
1880 }
1881
1882 /**
1883 * @brief FIFO enable.[get]
1884 *
1885 * @param ctx read / write interface definitions
1886 * @param val change the values of fifo_en in reg CTRL_REG5
1887 * @retval interface status (MANDATORY: return 0 -> no Error)
1888 *
1889 */
lis3dh_fifo_get(stmdev_ctx_t * ctx,uint8_t * val)1890 int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
1891 {
1892 lis3dh_ctrl_reg5_t ctrl_reg5;
1893 int32_t ret;
1894
1895 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1896 *val = (uint8_t)ctrl_reg5.fifo_en;
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @brief FIFO watermark level selection.[set]
1903 *
1904 * @param ctx read / write interface definitions
1905 * @param val change the values of fth in reg FIFO_CTRL_REG
1906 * @retval interface status (MANDATORY: return 0 -> no Error)
1907 *
1908 */
lis3dh_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)1909 int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
1910 {
1911 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1912 int32_t ret;
1913
1914 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1915 (uint8_t *)&fifo_ctrl_reg, 1);
1916
1917 if (ret == 0)
1918 {
1919 fifo_ctrl_reg.fth = val;
1920 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1921 (uint8_t *)&fifo_ctrl_reg, 1);
1922 }
1923
1924 return ret;
1925 }
1926
1927 /**
1928 * @brief FIFO watermark level selection.[get]
1929 *
1930 * @param ctx read / write interface definitions
1931 * @param val change the values of fth in reg FIFO_CTRL_REG
1932 * @retval interface status (MANDATORY: return 0 -> no Error)
1933 *
1934 */
lis3dh_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)1935 int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
1936 {
1937 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1938 int32_t ret;
1939
1940 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1941 (uint8_t *)&fifo_ctrl_reg, 1);
1942 *val = (uint8_t)fifo_ctrl_reg.fth;
1943
1944 return ret;
1945 }
1946
1947 /**
1948 * @brief Trigger FIFO selection.[set]
1949 *
1950 * @param ctx read / write interface definitions
1951 * @param val change the values of tr in reg FIFO_CTRL_REG
1952 * @retval interface status (MANDATORY: return 0 -> no Error)
1953 *
1954 */
lis3dh_fifo_trigger_event_set(stmdev_ctx_t * ctx,lis3dh_tr_t val)1955 int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
1956 lis3dh_tr_t val)
1957 {
1958 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1959 int32_t ret;
1960
1961 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1962 (uint8_t *)&fifo_ctrl_reg, 1);
1963
1964 if (ret == 0)
1965 {
1966 fifo_ctrl_reg.tr = (uint8_t)val;
1967 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1968 (uint8_t *)&fifo_ctrl_reg, 1);
1969 }
1970
1971 return ret;
1972 }
1973
1974 /**
1975 * @brief Trigger FIFO selection.[get]
1976 *
1977 * @param ctx read / write interface definitions
1978 * @param val Get the values of tr in reg FIFO_CTRL_REG
1979 * @retval interface status (MANDATORY: return 0 -> no Error)
1980 *
1981 */
lis3dh_fifo_trigger_event_get(stmdev_ctx_t * ctx,lis3dh_tr_t * val)1982 int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
1983 lis3dh_tr_t *val)
1984 {
1985 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1986 int32_t ret;
1987
1988 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1989 (uint8_t *)&fifo_ctrl_reg, 1);
1990
1991 switch (fifo_ctrl_reg.tr)
1992 {
1993 case LIS3DH_INT1_GEN:
1994 *val = LIS3DH_INT1_GEN;
1995 break;
1996
1997 case LIS3DH_INT2_GEN:
1998 *val = LIS3DH_INT2_GEN;
1999 break;
2000
2001 default:
2002 *val = LIS3DH_INT1_GEN;
2003 break;
2004 }
2005
2006 return ret;
2007 }
2008
2009 /**
2010 * @brief FIFO mode selection.[set]
2011 *
2012 * @param ctx read / write interface definitions
2013 * @param val change the values of fm in reg FIFO_CTRL_REG
2014 * @retval interface status (MANDATORY: return 0 -> no Error)
2015 *
2016 */
lis3dh_fifo_mode_set(stmdev_ctx_t * ctx,lis3dh_fm_t val)2017 int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val)
2018 {
2019 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2020 int32_t ret;
2021
2022 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2023 (uint8_t *)&fifo_ctrl_reg, 1);
2024
2025 if (ret == 0)
2026 {
2027 fifo_ctrl_reg.fm = (uint8_t)val;
2028 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2029 (uint8_t *)&fifo_ctrl_reg, 1);
2030 }
2031
2032 return ret;
2033 }
2034
2035 /**
2036 * @brief FIFO mode selection.[get]
2037 *
2038 * @param ctx read / write interface definitions
2039 * @param val Get the values of fm in reg FIFO_CTRL_REG
2040 * @retval interface status (MANDATORY: return 0 -> no Error)
2041 *
2042 */
lis3dh_fifo_mode_get(stmdev_ctx_t * ctx,lis3dh_fm_t * val)2043 int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val)
2044 {
2045 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2046 int32_t ret;
2047
2048 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2049 (uint8_t *)&fifo_ctrl_reg, 1);
2050
2051 switch (fifo_ctrl_reg.fm)
2052 {
2053 case LIS3DH_BYPASS_MODE:
2054 *val = LIS3DH_BYPASS_MODE;
2055 break;
2056
2057 case LIS3DH_FIFO_MODE:
2058 *val = LIS3DH_FIFO_MODE;
2059 break;
2060
2061 case LIS3DH_DYNAMIC_STREAM_MODE:
2062 *val = LIS3DH_DYNAMIC_STREAM_MODE;
2063 break;
2064
2065 case LIS3DH_STREAM_TO_FIFO_MODE:
2066 *val = LIS3DH_STREAM_TO_FIFO_MODE;
2067 break;
2068
2069 default:
2070 *val = LIS3DH_BYPASS_MODE;
2071 break;
2072 }
2073
2074 return ret;
2075 }
2076
2077 /**
2078 * @brief FIFO status register.[get]
2079 *
2080 * @param ctx read / write interface definitions
2081 * @param val registers FIFO_SRC_REG
2082 * @retval interface status (MANDATORY: return 0 -> no Error)
2083 *
2084 */
lis3dh_fifo_status_get(stmdev_ctx_t * ctx,lis3dh_fifo_src_reg_t * val)2085 int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx,
2086 lis3dh_fifo_src_reg_t *val)
2087 {
2088 int32_t ret;
2089
2090 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *) val, 1);
2091
2092 return ret;
2093 }
2094 /**
2095 * @brief FIFO stored data level.[get]
2096 *
2097 * @param ctx read / write interface definitions
2098 * @param val change the values of fss in reg FIFO_SRC_REG
2099 * @retval interface status (MANDATORY: return 0 -> no Error)
2100 *
2101 */
lis3dh_fifo_data_level_get(stmdev_ctx_t * ctx,uint8_t * val)2102 int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
2103 {
2104 lis3dh_fifo_src_reg_t fifo_src_reg;
2105 int32_t ret;
2106
2107 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2108 (uint8_t *)&fifo_src_reg, 1);
2109 *val = (uint8_t)fifo_src_reg.fss;
2110
2111 return ret;
2112 }
2113 /**
2114 * @brief Empty FIFO status flag.[get]
2115 *
2116 * @param ctx read / write interface definitions
2117 * @param val change the values of empty in reg FIFO_SRC_REG
2118 * @retval interface status (MANDATORY: return 0 -> no Error)
2119 *
2120 */
lis3dh_fifo_empty_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2121 int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2122 {
2123 lis3dh_fifo_src_reg_t fifo_src_reg;
2124 int32_t ret;
2125
2126 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2127 (uint8_t *)&fifo_src_reg, 1);
2128 *val = (uint8_t)fifo_src_reg.empty;
2129
2130 return ret;
2131 }
2132 /**
2133 * @brief FIFO overrun status flag.[get]
2134 *
2135 * @param ctx read / write interface definitions
2136 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
2137 * @retval interface status (MANDATORY: return 0 -> no Error)
2138 *
2139 */
lis3dh_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2140 int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2141 {
2142 lis3dh_fifo_src_reg_t fifo_src_reg;
2143 int32_t ret;
2144
2145 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2146 (uint8_t *)&fifo_src_reg, 1);
2147 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
2148
2149 return ret;
2150 }
2151 /**
2152 * @brief FIFO watermark status.[get]
2153 *
2154 * @param ctx read / write interface definitions
2155 * @param val change the values of wtm in reg FIFO_SRC_REG
2156 * @retval interface status (MANDATORY: return 0 -> no Error)
2157 *
2158 */
lis3dh_fifo_fth_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2159 int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2160 {
2161 lis3dh_fifo_src_reg_t fifo_src_reg;
2162 int32_t ret;
2163
2164 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2165 (uint8_t *)&fifo_src_reg, 1);
2166 *val = (uint8_t)fifo_src_reg.wtm;
2167
2168 return ret;
2169 }
2170 /**
2171 * @}
2172 *
2173 */
2174
2175 /**
2176 * @defgroup LIS3DH_Tap_generator
2177 * @brief This section group all the functions that manage the tap and
2178 * double tap event generation
2179 * @{
2180 *
2181 */
2182
2183 /**
2184 * @brief Tap/Double Tap generator configuration register.[set]
2185 *
2186 * @param ctx read / write interface definitions
2187 * @param val registers CLICK_CFG
2188 * @retval interface status (MANDATORY: return 0 -> no Error)
2189 *
2190 */
lis3dh_tap_conf_set(stmdev_ctx_t * ctx,lis3dh_click_cfg_t * val)2191 int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx,
2192 lis3dh_click_cfg_t *val)
2193 {
2194 int32_t ret;
2195
2196 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
2197
2198 return ret;
2199 }
2200
2201 /**
2202 * @brief Tap/Double Tap generator configuration register.[get]
2203 *
2204 * @param ctx read / write interface definitions
2205 * @param val registers CLICK_CFG
2206 * @retval interface status (MANDATORY: return 0 -> no Error)
2207 *
2208 */
lis3dh_tap_conf_get(stmdev_ctx_t * ctx,lis3dh_click_cfg_t * val)2209 int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx,
2210 lis3dh_click_cfg_t *val)
2211 {
2212 int32_t ret;
2213
2214 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
2215
2216 return ret;
2217 }
2218 /**
2219 * @brief Tap/Double Tap generator source register.[get]
2220 *
2221 * @param ctx read / write interface definitions
2222 * @param val registers CLICK_SRC
2223 * @retval interface status (MANDATORY: return 0 -> no Error)
2224 *
2225 */
lis3dh_tap_source_get(stmdev_ctx_t * ctx,lis3dh_click_src_t * val)2226 int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx,
2227 lis3dh_click_src_t *val)
2228 {
2229 int32_t ret;
2230
2231 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_SRC, (uint8_t *) val, 1);
2232
2233 return ret;
2234 }
2235 /**
2236 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2237 * 1 LSB = full scale/128
2238 *
2239 * @param ctx read / write interface definitions
2240 * @param val change the values of ths in reg CLICK_THS
2241 * @retval interface status (MANDATORY: return 0 -> no Error)
2242 *
2243 */
lis3dh_tap_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2244 int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2245 {
2246 lis3dh_click_ths_t click_ths;
2247 int32_t ret;
2248
2249 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2250
2251 if (ret == 0)
2252 {
2253 click_ths.ths = val;
2254 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2255 }
2256
2257 return ret;
2258 }
2259
2260 /**
2261 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2262 * 1 LSB = full scale/128
2263 *
2264 * @param ctx read / write interface definitions
2265 * @param val change the values of ths in reg CLICK_THS
2266 * @retval interface status (MANDATORY: return 0 -> no Error)
2267 *
2268 */
lis3dh_tap_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2269 int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2270 {
2271 lis3dh_click_ths_t click_ths;
2272 int32_t ret;
2273
2274 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2275 *val = (uint8_t)click_ths.ths;
2276
2277 return ret;
2278 }
2279
2280 /**
2281 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2282 * for the duration of the latency window.
2283 * If the LIR_Click bit is set, the interrupt is kept high until the
2284 * CLICK_SRC(39h) register is read.[set]
2285 *
2286 * @param ctx read / write interface definitions
2287 * @param val change the values of lir_click in reg CLICK_THS
2288 * @retval interface status (MANDATORY: return 0 -> no Error)
2289 *
2290 */
lis3dh_tap_notification_mode_set(stmdev_ctx_t * ctx,lis3dh_lir_click_t val)2291 int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
2292 lis3dh_lir_click_t val)
2293 {
2294 lis3dh_click_ths_t click_ths;
2295 int32_t ret;
2296
2297 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2298
2299 if (ret == 0)
2300 {
2301 click_ths.lir_click = (uint8_t)val;
2302 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2303 }
2304
2305 return ret;
2306 }
2307
2308 /**
2309 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2310 * for the duration of the latency window.
2311 * If the LIR_Click bit is set, the interrupt is kept high until the
2312 * CLICK_SRC(39h) register is read.[get]
2313 *
2314 * @param ctx read / write interface definitions
2315 * @param val Get the values of lir_click in reg CLICK_THS
2316 * @retval interface status (MANDATORY: return 0 -> no Error)
2317 *
2318 */
lis3dh_tap_notification_mode_get(stmdev_ctx_t * ctx,lis3dh_lir_click_t * val)2319 int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx,
2320 lis3dh_lir_click_t *val)
2321 {
2322 lis3dh_click_ths_t click_ths;
2323 int32_t ret;
2324
2325 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2326
2327 switch (click_ths.lir_click)
2328 {
2329 case LIS3DH_TAP_PULSED:
2330 *val = LIS3DH_TAP_PULSED;
2331 break;
2332
2333 case LIS3DH_TAP_LATCHED:
2334 *val = LIS3DH_TAP_LATCHED;
2335 break;
2336
2337 default:
2338 *val = LIS3DH_TAP_PULSED;
2339 break;
2340 }
2341
2342 return ret;
2343 }
2344
2345 /**
2346 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2347 * between the start of the click-detection procedure and when the
2348 * acceleration falls back below the threshold.[set]
2349 *
2350 * @param ctx read / write interface definitions
2351 * @param val change the values of tli in reg TIME_LIMIT
2352 * @retval interface status (MANDATORY: return 0 -> no Error)
2353 *
2354 */
lis3dh_shock_dur_set(stmdev_ctx_t * ctx,uint8_t val)2355 int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2356 {
2357 lis3dh_time_limit_t time_limit;
2358 int32_t ret;
2359
2360 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2361
2362 if (ret == 0)
2363 {
2364 time_limit.tli = val;
2365 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2366 }
2367
2368 return ret;
2369 }
2370
2371 /**
2372 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2373 * the start of the click-detection procedure and when the
2374 * acceleration falls back below the threshold.[get]
2375 *
2376 * @param ctx read / write interface definitions
2377 * @param val change the values of tli in reg TIME_LIMIT
2378 * @retval interface status (MANDATORY: return 0 -> no Error)
2379 *
2380 */
lis3dh_shock_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2381 int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2382 {
2383 lis3dh_time_limit_t time_limit;
2384 int32_t ret;
2385
2386 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2387 *val = (uint8_t)time_limit.tli;
2388
2389 return ret;
2390 }
2391
2392 /**
2393 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2394 * click detection where the click-detection procedure is
2395 * disabled, in cases where the device is configured for
2396 * double-click detection.[set]
2397 *
2398 * @param ctx read / write interface definitions
2399 * @param val change the values of tla in reg TIME_LATENCY
2400 * @retval interface status (MANDATORY: return 0 -> no Error)
2401 *
2402 */
lis3dh_quiet_dur_set(stmdev_ctx_t * ctx,uint8_t val)2403 int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2404 {
2405 lis3dh_time_latency_t time_latency;
2406 int32_t ret;
2407
2408 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
2409 (uint8_t *)&time_latency, 1);
2410
2411 if (ret == 0)
2412 {
2413 time_latency.tla = val;
2414 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LATENCY,
2415 (uint8_t *)&time_latency, 1);
2416 }
2417
2418 return ret;
2419 }
2420
2421 /**
2422 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2423 * click detection where the click-detection procedure is
2424 * disabled, in cases where the device is configured for
2425 * double-click detection.[get]
2426 *
2427 * @param ctx read / write interface definitions
2428 * @param val change the values of tla in reg TIME_LATENCY
2429 * @retval interface status (MANDATORY: return 0 -> no Error)
2430 *
2431 */
lis3dh_quiet_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2432 int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2433 {
2434 lis3dh_time_latency_t time_latency;
2435 int32_t ret;
2436
2437 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
2438 (uint8_t *)&time_latency, 1);
2439 *val = (uint8_t)time_latency.tla;
2440
2441 return ret;
2442 }
2443
2444 /**
2445 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2446 * after the end of the latency interval in which the click-detection
2447 * procedure can start, in cases where the device is configured
2448 * for double-click detection.[set]
2449 *
2450 * @param ctx read / write interface definitions
2451 * @param val change the values of tw in reg TIME_WINDOW
2452 * @retval interface status (MANDATORY: return 0 -> no Error)
2453 *
2454 */
lis3dh_double_tap_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2455 int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2456 {
2457 lis3dh_time_window_t time_window;
2458 int32_t ret;
2459
2460 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
2461 (uint8_t *)&time_window, 1);
2462
2463 if (ret == 0)
2464 {
2465 time_window.tw = val;
2466 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_WINDOW,
2467 (uint8_t *)&time_window, 1);
2468 }
2469
2470 return ret;
2471 }
2472
2473 /**
2474 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2475 * after the end of the latency interval in which the
2476 * click-detection procedure can start, in cases where the device
2477 * is configured for double-click detection.[get]
2478 *
2479 * @param ctx read / write interface definitions
2480 * @param val change the values of tw in reg TIME_WINDOW
2481 * @retval interface status (MANDATORY: return 0 -> no Error)
2482 *
2483 */
lis3dh_double_tap_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2484 int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2485 {
2486 lis3dh_time_window_t time_window;
2487 int32_t ret;
2488
2489 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
2490 (uint8_t *)&time_window, 1);
2491 *val = (uint8_t)time_window.tw;
2492
2493 return ret;
2494 }
2495
2496 /**
2497 * @}
2498 *
2499 */
2500
2501 /**
2502 * @defgroup LIS3DH_Activity_inactivity
2503 * @brief This section group all the functions concerning activity
2504 * inactivity functionality
2505 * @{
2506 *
2507 */
2508
2509 /**
2510 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2511 * low-power mode.[set]
2512 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2513 *
2514 * @param ctx read / write interface definitions
2515 * @param val change the values of acth in reg ACT_THS
2516 * @retval interface status (MANDATORY: return 0 -> no Error)
2517 *
2518 */
lis3dh_act_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2519 int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2520 {
2521 lis3dh_act_ths_t act_ths;
2522 int32_t ret;
2523
2524 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2525
2526 if (ret == 0)
2527 {
2528 act_ths.acth = val;
2529 ret = lis3dh_write_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2530 }
2531
2532 return ret;
2533 }
2534
2535 /**
2536 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2537 * mode.[get]
2538 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2539 *
2540 * @param ctx read / write interface definitions
2541 * @param val change the values of acth in reg ACT_THS
2542 * @retval interface status (MANDATORY: return 0 -> no Error)
2543 *
2544 */
lis3dh_act_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2545 int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2546 {
2547 lis3dh_act_ths_t act_ths;
2548 int32_t ret;
2549
2550 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2551 *val = (uint8_t)act_ths.acth;
2552
2553 return ret;
2554 }
2555
2556 /**
2557 * @brief Sleep-to-wake, return-to-sleep.[set]
2558 * duration = (8*1[LSb]+1)/ODR
2559 *
2560 * @param ctx read / write interface definitions
2561 * @param val change the values of actd in reg ACT_DUR
2562 * @retval interface status (MANDATORY: return 0 -> no Error)
2563 *
2564 */
lis3dh_act_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2565 int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2566 {
2567 lis3dh_act_dur_t act_dur;
2568 int32_t ret;
2569
2570 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2571
2572 if (ret == 0)
2573 {
2574 act_dur.actd = val;
2575 ret = lis3dh_write_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2576 }
2577
2578 return ret;
2579 }
2580
2581 /**
2582 * @brief Sleep-to-wake, return-to-sleep.[get]
2583 * duration = (8*1[LSb]+1)/ODR
2584 *
2585 * @param ctx read / write interface definitions
2586 * @param val change the values of actd in reg ACT_DUR
2587 * @retval interface status (MANDATORY: return 0 -> no Error)
2588 *
2589 */
lis3dh_act_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2590 int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2591 {
2592 lis3dh_act_dur_t act_dur;
2593 int32_t ret;
2594
2595 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2596 *val = (uint8_t)act_dur.actd;
2597
2598 return ret;
2599 }
2600
2601 /**
2602 * @}
2603 *
2604 */
2605
2606 /**
2607 * @defgroup LIS3DH_Serial_interface
2608 * @brief This section group all the functions concerning serial
2609 * interface management
2610 * @{
2611 *
2612 */
2613
2614 /**
2615 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2616 *
2617 * @param ctx read / write interface definitions
2618 * @param val change the values of sdo_pu_disc in reg CTRL_REG0
2619 * @retval interface status (MANDATORY: return 0 -> no Error)
2620 *
2621 */
lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lis3dh_sdo_pu_disc_t val)2622 int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
2623 lis3dh_sdo_pu_disc_t val)
2624 {
2625 lis3dh_ctrl_reg0_t ctrl_reg0;
2626 int32_t ret;
2627
2628 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2629
2630 if (ret == 0)
2631 {
2632 ctrl_reg0.sdo_pu_disc = (uint8_t)val;
2633 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2634 }
2635
2636 return ret;
2637 }
2638
2639 /**
2640 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2641 *
2642 * @param ctx read / write interface definitions
2643 * @param val Get the values of sdo_pu_disc in reg CTRL_REG0
2644 * @retval interface status (MANDATORY: return 0 -> no Error)
2645 *
2646 */
lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lis3dh_sdo_pu_disc_t * val)2647 int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
2648 lis3dh_sdo_pu_disc_t *val)
2649 {
2650 lis3dh_ctrl_reg0_t ctrl_reg0;
2651 int32_t ret;
2652
2653 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2654
2655 switch (ctrl_reg0.sdo_pu_disc)
2656 {
2657 case LIS3DH_PULL_UP_DISCONNECT:
2658 *val = LIS3DH_PULL_UP_DISCONNECT;
2659 break;
2660
2661 case LIS3DH_PULL_UP_CONNECT:
2662 *val = LIS3DH_PULL_UP_CONNECT;
2663 break;
2664
2665 default:
2666 *val = LIS3DH_PULL_UP_DISCONNECT;
2667 break;
2668 }
2669
2670 return ret;
2671 }
2672
2673 /**
2674 * @brief SPI Serial Interface Mode selection.[set]
2675 *
2676 * @param ctx read / write interface definitions
2677 * @param val change the values of sim in reg CTRL_REG4
2678 * @retval interface status (MANDATORY: return 0 -> no Error)
2679 *
2680 */
lis3dh_spi_mode_set(stmdev_ctx_t * ctx,lis3dh_sim_t val)2681 int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val)
2682 {
2683 lis3dh_ctrl_reg4_t ctrl_reg4;
2684 int32_t ret;
2685
2686 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2687
2688 if (ret == 0)
2689 {
2690 ctrl_reg4.sim = (uint8_t)val;
2691 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2692 }
2693
2694 return ret;
2695 }
2696
2697 /**
2698 * @brief SPI Serial Interface Mode selection.[get]
2699 *
2700 * @param ctx read / write interface definitions
2701 * @param val Get the values of sim in reg CTRL_REG4
2702 * @retval interface status (MANDATORY: return 0 -> no Error)
2703 *
2704 */
lis3dh_spi_mode_get(stmdev_ctx_t * ctx,lis3dh_sim_t * val)2705 int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val)
2706 {
2707 lis3dh_ctrl_reg4_t ctrl_reg4;
2708 int32_t ret;
2709
2710 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2711
2712 switch (ctrl_reg4.sim)
2713 {
2714 case LIS3DH_SPI_4_WIRE:
2715 *val = LIS3DH_SPI_4_WIRE;
2716 break;
2717
2718 case LIS3DH_SPI_3_WIRE:
2719 *val = LIS3DH_SPI_3_WIRE;
2720 break;
2721
2722 default:
2723 *val = LIS3DH_SPI_4_WIRE;
2724 break;
2725 }
2726
2727 return ret;
2728 }
2729
2730 /**
2731 * @}
2732 *
2733 */
2734
2735 /**
2736 * @}
2737 *
2738 */
2739
2740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2741
