1 /**
2 ******************************************************************************
3 * @file lis331dlh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS331DLH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis331dlh_reg.h"
21
22 /**
23 * @defgroup LIS331DLH
24 * @brief This file provides a set of functions needed to drive the
25 * lis331dlh enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS331DLH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis331dlh_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis331dlh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis331dlh_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis331dlh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS331DLH_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lis331dlh_from_fs2_to_mg(int16_t lsb)103 float_t lis331dlh_from_fs2_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb / 16.0f);
106 }
107
lis331dlh_from_fs4_to_mg(int16_t lsb)108 float_t lis331dlh_from_fs4_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 2.0f / 16.0f);
111 }
112
lis331dlh_from_fs8_to_mg(int16_t lsb)113 float_t lis331dlh_from_fs8_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 3.9f / 16.0f);
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup LIS331DLH_Data_Generation
125 * @brief This section group all the functions concerning
126 * data generation
127 * @{
128 *
129 */
130
131 /**
132 * @brief X axis enable/disable.[set]
133 *
134 * @param ctx read / write interface definitions(ptr)
135 * @param val change the values of xen in reg CTRL_REG1
136 * @retval interface status (MANDATORY: return 0 -> no Error)
137 *
138 */
lis331dlh_axis_x_data_set(const stmdev_ctx_t * ctx,uint8_t val)139 int32_t lis331dlh_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val)
140 {
141 lis331dlh_ctrl_reg1_t ctrl_reg1;
142 int32_t ret;
143
144 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
145 (uint8_t *)&ctrl_reg1, 1);
146
147 if (ret == 0)
148 {
149 ctrl_reg1.xen = val;
150 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
151 (uint8_t *)&ctrl_reg1, 1);
152 }
153
154 return ret;
155 }
156
157 /**
158 * @brief X axis enable/disable.[get]
159 *
160 * @param ctx read / write interface definitions(ptr)
161 * @param val change the values of xen in reg CTRL_REG1
162 * @retval interface status (MANDATORY: return 0 -> no Error)
163 *
164 */
lis331dlh_axis_x_data_get(const stmdev_ctx_t * ctx,uint8_t * val)165 int32_t lis331dlh_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
166 {
167 lis331dlh_ctrl_reg1_t ctrl_reg1;
168 int32_t ret;
169
170 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
171 (uint8_t *)&ctrl_reg1, 1);
172 *val = ctrl_reg1.xen;
173
174 return ret;
175 }
176
177 /**
178 * @brief Y axis enable/disable.[set]
179 *
180 * @param ctx read / write interface definitions(ptr)
181 * @param val change the values of yen in reg CTRL_REG1
182 * @retval interface status (MANDATORY: return 0 -> no Error)
183 *
184 */
lis331dlh_axis_y_data_set(const stmdev_ctx_t * ctx,uint8_t val)185 int32_t lis331dlh_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val)
186 {
187 lis331dlh_ctrl_reg1_t ctrl_reg1;
188 int32_t ret;
189
190 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
191 (uint8_t *)&ctrl_reg1, 1);
192
193 if (ret == 0)
194 {
195 ctrl_reg1.yen = val;
196 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
197 (uint8_t *)&ctrl_reg1, 1);
198 }
199
200 return ret;
201 }
202
203 /**
204 * @brief Y axis enable/disable.[get]
205 *
206 * @param ctx read / write interface definitions(ptr)
207 * @param val change the values of yen in reg CTRL_REG1
208 * @retval interface status (MANDATORY: return 0 -> no Error)
209 *
210 */
lis331dlh_axis_y_data_get(const stmdev_ctx_t * ctx,uint8_t * val)211 int32_t lis331dlh_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
212 {
213 lis331dlh_ctrl_reg1_t ctrl_reg1;
214 int32_t ret;
215
216 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
217 (uint8_t *)&ctrl_reg1, 1);
218 *val = ctrl_reg1.yen;
219
220 return ret;
221 }
222
223 /**
224 * @brief Z axis enable/disable.[set]
225 *
226 * @param ctx read / write interface definitions(ptr)
227 * @param val change the values of zen in reg CTRL_REG1
228 * @retval interface status (MANDATORY: return 0 -> no Error)
229 *
230 */
lis331dlh_axis_z_data_set(const stmdev_ctx_t * ctx,uint8_t val)231 int32_t lis331dlh_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val)
232 {
233 lis331dlh_ctrl_reg1_t ctrl_reg1;
234 int32_t ret;
235
236 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
237 (uint8_t *)&ctrl_reg1, 1);
238
239 if (ret == 0)
240 {
241 ctrl_reg1.zen = val;
242 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
243 (uint8_t *)&ctrl_reg1, 1);
244 }
245
246 return ret;
247 }
248
249 /**
250 * @brief Z axis enable/disable.[get]
251 *
252 * @param ctx read / write interface definitions(ptr)
253 * @param val change the values of zen in reg CTRL_REG1
254 * @retval interface status (MANDATORY: return 0 -> no Error)
255 *
256 */
lis331dlh_axis_z_data_get(const stmdev_ctx_t * ctx,uint8_t * val)257 int32_t lis331dlh_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
258 {
259 lis331dlh_ctrl_reg1_t ctrl_reg1;
260 int32_t ret;
261
262 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
263 (uint8_t *)&ctrl_reg1, 1);
264 *val = ctrl_reg1.zen;
265
266 return ret;
267 }
268
269 /**
270 * @brief Accelerometer data rate selection.[set]
271 *
272 * @param ctx read / write interface definitions(ptr)
273 * @param val change the values of dr in reg CTRL_REG1
274 * @retval interface status (MANDATORY: return 0 -> no Error)
275 *
276 */
lis331dlh_data_rate_set(const stmdev_ctx_t * ctx,lis331dlh_dr_t val)277 int32_t lis331dlh_data_rate_set(const stmdev_ctx_t *ctx, lis331dlh_dr_t val)
278 {
279 lis331dlh_ctrl_reg1_t ctrl_reg1;
280 int32_t ret;
281
282 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
283 (uint8_t *)&ctrl_reg1, 1);
284
285 if (ret == 0)
286 {
287 ctrl_reg1.pm = (uint8_t)val & 0x07U;
288 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
289 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
290 (uint8_t *)&ctrl_reg1, 1);
291 }
292
293 return ret;
294 }
295
296 /**
297 * @brief Accelerometer data rate selection.[get]
298 *
299 * @param ctx read / write interface definitions(ptr)
300 * @param val Get the values of dr in reg CTRL_REG1
301 * @retval interface status (MANDATORY: return 0 -> no Error)
302 *
303 */
lis331dlh_data_rate_get(const stmdev_ctx_t * ctx,lis331dlh_dr_t * val)304 int32_t lis331dlh_data_rate_get(const stmdev_ctx_t *ctx,
305 lis331dlh_dr_t *val)
306 {
307 lis331dlh_ctrl_reg1_t ctrl_reg1;
308 int32_t ret;
309
310 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
311 (uint8_t *)&ctrl_reg1, 1);
312
313 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
314 {
315 case LIS331DLH_ODR_OFF:
316 *val = LIS331DLH_ODR_OFF;
317 break;
318
319 case LIS331DLH_ODR_Hz5:
320 *val = LIS331DLH_ODR_Hz5;
321 break;
322
323 case LIS331DLH_ODR_1Hz:
324 *val = LIS331DLH_ODR_1Hz;
325 break;
326
327 case LIS331DLH_ODR_2Hz:
328 *val = LIS331DLH_ODR_2Hz;
329 break;
330
331 case LIS331DLH_ODR_5Hz:
332 *val = LIS331DLH_ODR_5Hz;
333 break;
334
335 case LIS331DLH_ODR_10Hz:
336 *val = LIS331DLH_ODR_10Hz;
337 break;
338
339 case LIS331DLH_ODR_50Hz:
340 *val = LIS331DLH_ODR_50Hz;
341 break;
342
343 case LIS331DLH_ODR_100Hz:
344 *val = LIS331DLH_ODR_100Hz;
345 break;
346
347 case LIS331DLH_ODR_400Hz:
348 *val = LIS331DLH_ODR_400Hz;
349 break;
350
351 case LIS331DLH_ODR_1kHz:
352 *val = LIS331DLH_ODR_1kHz;
353 break;
354
355 default:
356 *val = LIS331DLH_ODR_OFF;
357 break;
358 }
359
360 return ret;
361 }
362
363 /**
364 * @brief High pass filter mode selection.[set]
365 *
366 * @param ctx read / write interface definitions(ptr)
367 * @param val change the values of hpm in reg CTRL_REG2
368 * @retval interface status (MANDATORY: return 0 -> no Error)
369 *
370 */
lis331dlh_reference_mode_set(const stmdev_ctx_t * ctx,lis331dlh_hpm_t val)371 int32_t lis331dlh_reference_mode_set(const stmdev_ctx_t *ctx,
372 lis331dlh_hpm_t val)
373 {
374 lis331dlh_ctrl_reg2_t ctrl_reg2;
375 int32_t ret;
376
377 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
378 (uint8_t *)&ctrl_reg2, 1);
379
380 if (ret == 0)
381 {
382 ctrl_reg2.hpm = (uint8_t)val;
383 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
384 (uint8_t *)&ctrl_reg2, 1);
385 }
386
387 return ret;
388 }
389
390 /**
391 * @brief High pass filter mode selection.[get]
392 *
393 * @param ctx read / write interface definitions(ptr)
394 * @param val Get the values of hpm in reg CTRL_REG2
395 * @retval interface status (MANDATORY: return 0 -> no Error)
396 *
397 */
lis331dlh_reference_mode_get(const stmdev_ctx_t * ctx,lis331dlh_hpm_t * val)398 int32_t lis331dlh_reference_mode_get(const stmdev_ctx_t *ctx,
399 lis331dlh_hpm_t *val)
400 {
401 lis331dlh_ctrl_reg2_t ctrl_reg2;
402 int32_t ret;
403
404 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
405 (uint8_t *)&ctrl_reg2, 1);
406
407 switch (ctrl_reg2.hpm)
408 {
409 case LIS331DLH_NORMAL_MODE:
410 *val = LIS331DLH_NORMAL_MODE;
411 break;
412
413 case LIS331DLH_REF_MODE_ENABLE:
414 *val = LIS331DLH_REF_MODE_ENABLE;
415 break;
416
417 default:
418 *val = LIS331DLH_NORMAL_MODE;
419 break;
420 }
421
422 return ret;
423 }
424
425 /**
426 * @brief Accelerometer full-scale selection.[set]
427 *
428 * @param ctx read / write interface definitions(ptr)
429 * @param val change the values of fs in reg CTRL_REG4
430 * @retval interface status (MANDATORY: return 0 -> no Error)
431 *
432 */
lis331dlh_full_scale_set(const stmdev_ctx_t * ctx,lis331dlh_fs_t val)433 int32_t lis331dlh_full_scale_set(const stmdev_ctx_t *ctx,
434 lis331dlh_fs_t val)
435 {
436 lis331dlh_ctrl_reg4_t ctrl_reg4;
437 int32_t ret;
438
439 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
440 (uint8_t *)&ctrl_reg4, 1);
441
442 if (ret == 0)
443 {
444 ctrl_reg4.fs = (uint8_t)val;
445 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
446 (uint8_t *)&ctrl_reg4, 1);
447 }
448
449 return ret;
450 }
451
452 /**
453 * @brief Accelerometer full-scale selection.[get]
454 *
455 * @param ctx read / write interface definitions(ptr)
456 * @param val Get the values of fs in reg CTRL_REG4
457 * @retval interface status (MANDATORY: return 0 -> no Error)
458 *
459 */
lis331dlh_full_scale_get(const stmdev_ctx_t * ctx,lis331dlh_fs_t * val)460 int32_t lis331dlh_full_scale_get(const stmdev_ctx_t *ctx,
461 lis331dlh_fs_t *val)
462 {
463 lis331dlh_ctrl_reg4_t ctrl_reg4;
464 int32_t ret;
465
466 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
467 (uint8_t *)&ctrl_reg4, 1);
468
469 switch (ctrl_reg4.fs)
470 {
471 case LIS331DLH_2g:
472 *val = LIS331DLH_2g;
473 break;
474
475 case LIS331DLH_4g:
476 *val = LIS331DLH_4g;
477 break;
478
479 case LIS331DLH_8g:
480 *val = LIS331DLH_8g;
481 break;
482
483 default:
484 *val = LIS331DLH_2g;
485 break;
486 }
487
488 return ret;
489 }
490
491 /**
492 * @brief Block data update.[set]
493 *
494 * @param ctx read / write interface definitions(ptr)
495 * @param val change the values of bdu in reg CTRL_REG4
496 * @retval interface status (MANDATORY: return 0 -> no Error)
497 *
498 */
lis331dlh_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)499 int32_t lis331dlh_block_data_update_set(const stmdev_ctx_t *ctx,
500 uint8_t val)
501 {
502 lis331dlh_ctrl_reg4_t ctrl_reg4;
503 int32_t ret;
504
505 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
506 (uint8_t *)&ctrl_reg4, 1);
507
508 if (ret == 0)
509 {
510 ctrl_reg4.bdu = val;
511 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
512 (uint8_t *)&ctrl_reg4, 1);
513 }
514
515 return ret;
516 }
517
518 /**
519 * @brief Block data update.[get]
520 *
521 * @param ctx read / write interface definitions(ptr)
522 * @param val change the values of bdu in reg CTRL_REG4
523 * @retval interface status (MANDATORY: return 0 -> no Error)
524 *
525 */
lis331dlh_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)526 int32_t lis331dlh_block_data_update_get(const stmdev_ctx_t *ctx,
527 uint8_t *val)
528 {
529 lis331dlh_ctrl_reg4_t ctrl_reg4;
530 int32_t ret;
531
532 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
533 (uint8_t *)&ctrl_reg4, 1);
534 *val = ctrl_reg4.bdu;
535
536 return ret;
537 }
538
539 /**
540 * @brief The STATUS_REG register is read by the interface.[get]
541 *
542 * @param ctx read / write interface definitions(ptr)
543 * @param val registers STATUS_REG
544 * @retval interface status (MANDATORY: return 0 -> no Error)
545 *
546 */
lis331dlh_status_reg_get(const stmdev_ctx_t * ctx,lis331dlh_status_reg_t * val)547 int32_t lis331dlh_status_reg_get(const stmdev_ctx_t *ctx,
548 lis331dlh_status_reg_t *val)
549 {
550 int32_t ret;
551
552 ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG, (uint8_t *) val, 1);
553
554 return ret;
555 }
556
557 /**
558 * @brief Accelerometer new data available.[get]
559 *
560 * @param ctx read / write interface definitions(ptr)
561 * @param val change the values of zyxda in reg STATUS_REG
562 * @retval interface status (MANDATORY: return 0 -> no Error)
563 *
564 */
lis331dlh_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)565 int32_t lis331dlh_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
566 {
567 lis331dlh_status_reg_t status_reg;
568 int32_t ret;
569
570 ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG,
571 (uint8_t *)&status_reg, 1);
572 *val = status_reg.zyxda;
573
574 return ret;
575 }
576
577 /**
578 * @}
579 *
580 */
581
582 /**
583 * @defgroup LIS331DLH_Data_Output
584 * @brief This section groups all the data output functions.
585 * @{
586 *
587 */
588
589 /**
590 * @brief Linear acceleration output register. The value is expressed
591 * as a 16-bit word in two’s complement.[get]
592 *
593 * @param ctx read / write interface definitions(ptr)
594 * @param buff buffer that stores data read
595 * @retval interface status (MANDATORY: return 0 -> no Error)
596 *
597 */
lis331dlh_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)598 int32_t lis331dlh_acceleration_raw_get(const stmdev_ctx_t *ctx,
599 int16_t *val)
600 {
601 uint8_t buff[6];
602 int32_t ret;
603
604 ret = lis331dlh_read_reg(ctx, LIS331DLH_OUT_X_L, buff, 6);
605 val[0] = (int16_t)buff[1];
606 val[0] = (val[0] * 256) + (int16_t)buff[0];
607 val[1] = (int16_t)buff[3];
608 val[1] = (val[1] * 256) + (int16_t)buff[2];
609 val[2] = (int16_t)buff[5];
610 val[2] = (val[2] * 256) + (int16_t)buff[4];
611
612 return ret;
613 }
614
615 /**
616 * @}
617 *
618 */
619
620 /**
621 * @defgroup LIS331DLH_Common
622 * @brief This section groups common useful functions.
623 * @{
624 *
625 */
626
627 /**
628 * @brief Device Who am I.[get]
629 *
630 * @param ctx read / write interface definitions(ptr)
631 * @param buff buffer that stores data read
632 * @retval interface status (MANDATORY: return 0 -> no Error)
633 *
634 */
lis331dlh_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)635 int32_t lis331dlh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
636 {
637 int32_t ret;
638
639 ret = lis331dlh_read_reg(ctx, LIS331DLH_WHO_AM_I, buff, 1);
640
641 return ret;
642 }
643
644 /**
645 * @brief Reboot memory content. Reload the calibration parameters.[set]
646 *
647 * @param ctx read / write interface definitions(ptr)
648 * @param val change the values of boot in reg CTRL_REG2
649 * @retval interface status (MANDATORY: return 0 -> no Error)
650 *
651 */
lis331dlh_boot_set(const stmdev_ctx_t * ctx,uint8_t val)652 int32_t lis331dlh_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
653 {
654 lis331dlh_ctrl_reg2_t ctrl_reg2;
655 int32_t ret;
656
657 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
658 (uint8_t *)&ctrl_reg2, 1);
659
660 if (ret == 0)
661 {
662 ctrl_reg2.boot = val;
663 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
664 (uint8_t *)&ctrl_reg2, 1);
665 }
666
667 return ret;
668 }
669
670 /**
671 * @brief Reboot memory content. Reload the calibration parameters.[get]
672 *
673 * @param ctx read / write interface definitions(ptr)
674 * @param val change the values of boot in reg CTRL_REG2
675 * @retval interface status (MANDATORY: return 0 -> no Error)
676 *
677 */
lis331dlh_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)678 int32_t lis331dlh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
679 {
680 lis331dlh_ctrl_reg2_t ctrl_reg2;
681 int32_t ret;
682
683 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
684 (uint8_t *)&ctrl_reg2, 1);
685 *val = ctrl_reg2.boot;
686
687 return ret;
688 }
689
690 /**
691 * @brief Linear acceleration sensor self-test enable.[set]
692 *
693 * @param ctx read / write interface definitions(ptr)
694 * @param val change the values of st in reg CTRL_REG4
695 * @retval interface status (MANDATORY: return 0 -> no Error)
696 *
697 */
lis331dlh_self_test_set(const stmdev_ctx_t * ctx,lis331dlh_st_t val)698 int32_t lis331dlh_self_test_set(const stmdev_ctx_t *ctx, lis331dlh_st_t val)
699 {
700 lis331dlh_ctrl_reg4_t ctrl_reg4;
701 int32_t ret;
702
703 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
704 (uint8_t *)&ctrl_reg4, 1);
705
706 if (ret == 0)
707 {
708 ctrl_reg4.st = (uint8_t)val;
709 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
710 (uint8_t *)&ctrl_reg4, 1);
711 }
712
713 return ret;
714 }
715
716 /**
717 * @brief Linear acceleration sensor self-test enable.[get]
718 *
719 * @param ctx read / write interface definitions(ptr)
720 * @param val Get the values of st in reg CTRL_REG4
721 * @retval interface status (MANDATORY: return 0 -> no Error)
722 *
723 */
lis331dlh_self_test_get(const stmdev_ctx_t * ctx,lis331dlh_st_t * val)724 int32_t lis331dlh_self_test_get(const stmdev_ctx_t *ctx,
725 lis331dlh_st_t *val)
726 {
727 lis331dlh_ctrl_reg4_t ctrl_reg4;
728 int32_t ret;
729
730 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
731 (uint8_t *)&ctrl_reg4, 1);
732
733 switch (ctrl_reg4.st)
734 {
735 case LIS331DLH_ST_DISABLE:
736 *val = LIS331DLH_ST_DISABLE;
737 break;
738
739 case LIS331DLH_ST_POSITIVE:
740 *val = LIS331DLH_ST_POSITIVE;
741 break;
742
743 case LIS331DLH_ST_NEGATIVE:
744 *val = LIS331DLH_ST_NEGATIVE;
745 break;
746
747 default:
748 *val = LIS331DLH_ST_DISABLE;
749 break;
750 }
751
752 return ret;
753 }
754
755 /**
756 * @brief Big/Little Endian Data selection.[set]
757 *
758 * @param ctx read / write interface definitions(ptr)
759 * @param val change the values of ble in reg CTRL_REG4
760 * @retval interface status (MANDATORY: return 0 -> no Error)
761 *
762 */
lis331dlh_data_format_set(const stmdev_ctx_t * ctx,lis331dlh_ble_t val)763 int32_t lis331dlh_data_format_set(const stmdev_ctx_t *ctx,
764 lis331dlh_ble_t val)
765 {
766 lis331dlh_ctrl_reg4_t ctrl_reg4;
767 int32_t ret;
768
769 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
770 (uint8_t *)&ctrl_reg4, 1);
771
772 if (ret == 0)
773 {
774 ctrl_reg4.ble = (uint8_t)val;
775 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
776 (uint8_t *)&ctrl_reg4, 1);
777 }
778
779 return ret;
780 }
781
782 /**
783 * @brief Big/Little Endian Data selection.[get]
784 *
785 * @param ctx read / write interface definitions(ptr)
786 * @param val Get the values of ble in reg CTRL_REG4
787 * @retval interface status (MANDATORY: return 0 -> no Error)
788 *
789 */
lis331dlh_data_format_get(const stmdev_ctx_t * ctx,lis331dlh_ble_t * val)790 int32_t lis331dlh_data_format_get(const stmdev_ctx_t *ctx,
791 lis331dlh_ble_t *val)
792 {
793 lis331dlh_ctrl_reg4_t ctrl_reg4;
794 int32_t ret;
795
796 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
797 (uint8_t *)&ctrl_reg4, 1);
798
799 switch (ctrl_reg4.ble)
800 {
801 case LIS331DLH_LSB_AT_LOW_ADD:
802 *val = LIS331DLH_LSB_AT_LOW_ADD;
803 break;
804
805 case LIS331DLH_MSB_AT_LOW_ADD:
806 *val = LIS331DLH_MSB_AT_LOW_ADD;
807 break;
808
809 default:
810 *val = LIS331DLH_LSB_AT_LOW_ADD;
811 break;
812 }
813
814 return ret;
815 }
816
817 /**
818 * @}
819 *
820 */
821
822 /**
823 * @defgroup LIS331DLH_Filters
824 * @brief This section group all the functions concerning the
825 * filters configuration.
826 * @{
827 *
828 */
829
830 /**
831 * @brief High pass filter cut-off frequency configuration.[set]
832 *
833 * @param ctx read / write interface definitions(ptr)
834 * @param val change the values of hpcf in reg CTRL_REG2
835 * @retval interface status (MANDATORY: return 0 -> no Error)
836 *
837 */
lis331dlh_hp_bandwidth_set(const stmdev_ctx_t * ctx,lis331dlh_hpcf_t val)838 int32_t lis331dlh_hp_bandwidth_set(const stmdev_ctx_t *ctx,
839 lis331dlh_hpcf_t val)
840 {
841 lis331dlh_ctrl_reg2_t ctrl_reg2;
842 int32_t ret;
843
844 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
845 (uint8_t *)&ctrl_reg2, 1);
846
847 if (ret == 0)
848 {
849 ctrl_reg2.hpcf = (uint8_t)val;
850 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
851 (uint8_t *)&ctrl_reg2, 1);
852 }
853
854 return ret;
855 }
856
857 /**
858 * @brief High pass filter cut-off frequency configuration.[get]
859 *
860 * @param ctx read / write interface definitions(ptr)
861 * @param val Get the values of hpcf in reg CTRL_REG2
862 * @retval interface status (MANDATORY: return 0 -> no Error)
863 *
864 */
lis331dlh_hp_bandwidth_get(const stmdev_ctx_t * ctx,lis331dlh_hpcf_t * val)865 int32_t lis331dlh_hp_bandwidth_get(const stmdev_ctx_t *ctx,
866 lis331dlh_hpcf_t *val)
867 {
868 lis331dlh_ctrl_reg2_t ctrl_reg2;
869 int32_t ret;
870
871 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
872 (uint8_t *)&ctrl_reg2, 1);
873
874 switch (ctrl_reg2.hpcf)
875 {
876 case LIS331DLH_CUT_OFF_8Hz:
877 *val = LIS331DLH_CUT_OFF_8Hz;
878 break;
879
880 case LIS331DLH_CUT_OFF_16Hz:
881 *val = LIS331DLH_CUT_OFF_16Hz;
882 break;
883
884 case LIS331DLH_CUT_OFF_32Hz:
885 *val = LIS331DLH_CUT_OFF_32Hz;
886 break;
887
888 case LIS331DLH_CUT_OFF_64Hz:
889 *val = LIS331DLH_CUT_OFF_64Hz;
890 break;
891
892 default:
893 *val = LIS331DLH_CUT_OFF_8Hz;
894 break;
895 }
896
897 return ret;
898 }
899
900 /**
901 * @brief Select High Pass filter path.[set]
902 *
903 * @param ctx read / write interface definitions(ptr)
904 * @param val change the values of hpen in reg CTRL_REG2
905 * @retval interface status (MANDATORY: return 0 -> no Error)
906 *
907 */
lis331dlh_hp_path_set(const stmdev_ctx_t * ctx,lis331dlh_hpen_t val)908 int32_t lis331dlh_hp_path_set(const stmdev_ctx_t *ctx, lis331dlh_hpen_t val)
909 {
910 lis331dlh_ctrl_reg2_t ctrl_reg2;
911 int32_t ret;
912
913 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
914 (uint8_t *)&ctrl_reg2, 1);
915
916 if (ret == 0)
917 {
918 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
919 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
920 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
921 (uint8_t *)&ctrl_reg2, 1);
922 }
923
924 return ret;
925 }
926
927 /**
928 * @brief Select High Pass filter path.[get]
929 *
930 * @param ctx read / write interface definitions(ptr)
931 * @param val Get the values of hpen in reg CTRL_REG2
932 * @retval interface status (MANDATORY: return 0 -> no Error)
933 *
934 */
lis331dlh_hp_path_get(const stmdev_ctx_t * ctx,lis331dlh_hpen_t * val)935 int32_t lis331dlh_hp_path_get(const stmdev_ctx_t *ctx,
936 lis331dlh_hpen_t *val)
937 {
938 lis331dlh_ctrl_reg2_t ctrl_reg2;
939 int32_t ret;
940
941 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
942 (uint8_t *)&ctrl_reg2, 1);
943
944 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
945 {
946 case LIS331DLH_HP_DISABLE:
947 *val = LIS331DLH_HP_DISABLE;
948 break;
949
950 case LIS331DLH_HP_ON_OUT:
951 *val = LIS331DLH_HP_ON_OUT;
952 break;
953
954 case LIS331DLH_HP_ON_INT1:
955 *val = LIS331DLH_HP_ON_INT1;
956 break;
957
958 case LIS331DLH_HP_ON_INT2:
959 *val = LIS331DLH_HP_ON_INT2;
960 break;
961
962 case LIS331DLH_HP_ON_INT1_INT2:
963 *val = LIS331DLH_HP_ON_INT1_INT2;
964 break;
965
966 case LIS331DLH_HP_ON_INT1_INT2_OUT:
967 *val = LIS331DLH_HP_ON_INT1_INT2_OUT;
968 break;
969
970 case LIS331DLH_HP_ON_INT2_OUT:
971 *val = LIS331DLH_HP_ON_INT2_OUT;
972 break;
973
974 case LIS331DLH_HP_ON_INT1_OUT:
975 *val = LIS331DLH_HP_ON_INT1_OUT;
976 break;
977
978 default:
979 *val = LIS331DLH_HP_DISABLE;
980 break;
981 }
982
983 return ret;
984 }
985
986 /**
987 * @brief Reading at this address zeroes instantaneously
988 * the content of the internal high pass-filter.
989 * If the high pass filter is enabled all three axes
990 * are instantaneously set to 0g. This allows to
991 * overcome the settling time of the high pass
992 * filter.[get]
993 *
994 * @param ctx read / write interface definitions(ptr)
995 * @retval interface status (MANDATORY: return 0 -> no Error)
996 *
997 */
lis331dlh_hp_reset_get(const stmdev_ctx_t * ctx)998 int32_t lis331dlh_hp_reset_get(const stmdev_ctx_t *ctx)
999 {
1000 uint8_t dummy;
1001 int32_t ret;
1002
1003 ret = lis331dlh_read_reg(ctx, LIS331DLH_HP_FILTER_RESET,
1004 (uint8_t *)&dummy, 1);
1005
1006 return ret;
1007 }
1008
1009 /**
1010 * @brief Reference value for high-pass filter.[set]
1011 *
1012 * @param ctx read / write interface definitions(ptr)
1013 * @param val change the values of ref in reg REFERENCE
1014 * @retval interface status (MANDATORY: return 0 -> no Error)
1015 *
1016 */
lis331dlh_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)1017 int32_t lis331dlh_hp_reference_value_set(const stmdev_ctx_t *ctx,
1018 uint8_t val)
1019 {
1020 int32_t ret;
1021
1022 ret = lis331dlh_write_reg(ctx, LIS331DLH_REFERENCE, (uint8_t *)&val, 1);
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Reference value for high-pass filter.[get]
1029 *
1030 * @param ctx read / write interface definitions(ptr)
1031 * @param val change the values of ref in reg REFERENCE
1032 * @retval interface status (MANDATORY: return 0 -> no Error)
1033 *
1034 */
lis331dlh_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)1035 int32_t lis331dlh_hp_reference_value_get(const stmdev_ctx_t *ctx,
1036 uint8_t *val)
1037 {
1038 int32_t ret;
1039
1040 ret = lis331dlh_read_reg(ctx, LIS331DLH_REFERENCE, val, 1);
1041
1042 return ret;
1043 }
1044
1045 /**
1046 * @}
1047 *
1048 */
1049
1050 /**
1051 * @defgroup LIS331DLH_Serial_Interface
1052 * @brief This section groups all the functions concerning serial
1053 * interface management.
1054 * @{
1055 *
1056 */
1057
1058 /**
1059 * @brief SPI 3- or 4-wire interface.[set]
1060 *
1061 * @param ctx read / write interface definitions(ptr)
1062 * @param val change the values of sim in reg CTRL_REG4
1063 * @retval interface status (MANDATORY: return 0 -> no Error)
1064 *
1065 */
lis331dlh_spi_mode_set(const stmdev_ctx_t * ctx,lis331dlh_sim_t val)1066 int32_t lis331dlh_spi_mode_set(const stmdev_ctx_t *ctx, lis331dlh_sim_t val)
1067 {
1068 lis331dlh_ctrl_reg4_t ctrl_reg4;
1069 int32_t ret;
1070
1071 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
1072 (uint8_t *)&ctrl_reg4, 1);
1073
1074 if (ret == 0)
1075 {
1076 ctrl_reg4.sim = (uint8_t)val;
1077 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
1078 (uint8_t *)&ctrl_reg4, 1);
1079 }
1080
1081 return ret;
1082 }
1083
1084 /**
1085 * @brief SPI 3- or 4-wire interface.[get]
1086 *
1087 * @param ctx read / write interface definitions(ptr)
1088 * @param val Get the values of sim in reg CTRL_REG4
1089 * @retval interface status (MANDATORY: return 0 -> no Error)
1090 *
1091 */
lis331dlh_spi_mode_get(const stmdev_ctx_t * ctx,lis331dlh_sim_t * val)1092 int32_t lis331dlh_spi_mode_get(const stmdev_ctx_t *ctx,
1093 lis331dlh_sim_t *val)
1094 {
1095 lis331dlh_ctrl_reg4_t ctrl_reg4;
1096 int32_t ret;
1097
1098 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
1099 (uint8_t *)&ctrl_reg4, 1);
1100
1101 switch (ctrl_reg4.sim)
1102 {
1103 case LIS331DLH_SPI_4_WIRE:
1104 *val = LIS331DLH_SPI_4_WIRE;
1105 break;
1106
1107 case LIS331DLH_SPI_3_WIRE:
1108 *val = LIS331DLH_SPI_3_WIRE;
1109 break;
1110
1111 default:
1112 *val = LIS331DLH_SPI_4_WIRE;
1113 break;
1114 }
1115
1116 return ret;
1117 }
1118
1119 /**
1120 * @}
1121 *
1122 */
1123
1124 /**
1125 * @defgroup LIS331DLH_Interrupt_Pins
1126 * @brief This section groups all the functions that manage
1127 * interrupt pins.
1128 * @{
1129 *
1130 */
1131
1132 /**
1133 * @brief Data signal on INT 1 pad control bits.[set]
1134 *
1135 * @param ctx read / write interface definitions(ptr)
1136 * @param val change the values of i1_cfg in reg CTRL_REG3
1137 * @retval interface status (MANDATORY: return 0 -> no Error)
1138 *
1139 */
lis331dlh_pin_int1_route_set(const stmdev_ctx_t * ctx,lis331dlh_i1_cfg_t val)1140 int32_t lis331dlh_pin_int1_route_set(const stmdev_ctx_t *ctx,
1141 lis331dlh_i1_cfg_t val)
1142 {
1143 lis331dlh_ctrl_reg3_t ctrl_reg3;
1144 int32_t ret;
1145
1146 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1147 (uint8_t *)&ctrl_reg3, 1);
1148
1149 if (ret == 0)
1150 {
1151 ctrl_reg3.i1_cfg = (uint8_t)val;
1152 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1153 (uint8_t *)&ctrl_reg3, 1);
1154 }
1155
1156 return ret;
1157 }
1158
1159 /**
1160 * @brief Data signal on INT 1 pad control bits.[get]
1161 *
1162 * @param ctx read / write interface definitions(ptr)
1163 * @param val Get the values of i1_cfg in reg CTRL_REG3
1164 * @retval interface status (MANDATORY: return 0 -> no Error)
1165 *
1166 */
lis331dlh_pin_int1_route_get(const stmdev_ctx_t * ctx,lis331dlh_i1_cfg_t * val)1167 int32_t lis331dlh_pin_int1_route_get(const stmdev_ctx_t *ctx,
1168 lis331dlh_i1_cfg_t *val)
1169 {
1170 lis331dlh_ctrl_reg3_t ctrl_reg3;
1171 int32_t ret;
1172
1173 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1174 (uint8_t *)&ctrl_reg3, 1);
1175
1176 switch (ctrl_reg3.i1_cfg)
1177 {
1178 case LIS331DLH_PAD1_INT1_SRC:
1179 *val = LIS331DLH_PAD1_INT1_SRC;
1180 break;
1181
1182 case LIS331DLH_PAD1_INT1_OR_INT2_SRC:
1183 *val = LIS331DLH_PAD1_INT1_OR_INT2_SRC;
1184 break;
1185
1186 case LIS331DLH_PAD1_DRDY:
1187 *val = LIS331DLH_PAD1_DRDY;
1188 break;
1189
1190 case LIS331DLH_PAD1_BOOT:
1191 *val = LIS331DLH_PAD1_BOOT;
1192 break;
1193
1194 default:
1195 *val = LIS331DLH_PAD1_INT1_SRC;
1196 break;
1197 }
1198
1199 return ret;
1200 }
1201
1202 /**
1203 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1204 * register cleared by reading INT1_SRC register.[set]
1205 *
1206 * @param ctx read / write interface definitions(ptr)
1207 * @param val change the values of lir1 in reg CTRL_REG3
1208 * @retval interface status (MANDATORY: return 0 -> no Error)
1209 *
1210 */
lis331dlh_int1_notification_set(const stmdev_ctx_t * ctx,lis331dlh_lir1_t val)1211 int32_t lis331dlh_int1_notification_set(const stmdev_ctx_t *ctx,
1212 lis331dlh_lir1_t val)
1213 {
1214 lis331dlh_ctrl_reg3_t ctrl_reg3;
1215 int32_t ret;
1216
1217 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1218 (uint8_t *)&ctrl_reg3, 1);
1219
1220 if (ret == 0)
1221 {
1222 ctrl_reg3.lir1 = (uint8_t)val;
1223 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1224 (uint8_t *)&ctrl_reg3, 1);
1225 }
1226
1227 return ret;
1228 }
1229
1230 /**
1231 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1232 * register cleared by reading INT1_SRC register.[get]
1233 *
1234 * @param ctx read / write interface definitions(ptr)
1235 * @param val Get the values of lir1 in reg CTRL_REG3
1236 * @retval interface status (MANDATORY: return 0 -> no Error)
1237 *
1238 */
lis331dlh_int1_notification_get(const stmdev_ctx_t * ctx,lis331dlh_lir1_t * val)1239 int32_t lis331dlh_int1_notification_get(const stmdev_ctx_t *ctx,
1240 lis331dlh_lir1_t *val)
1241 {
1242 lis331dlh_ctrl_reg3_t ctrl_reg3;
1243 int32_t ret;
1244
1245 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1246 (uint8_t *)&ctrl_reg3, 1);
1247
1248 switch (ctrl_reg3.lir1)
1249 {
1250 case LIS331DLH_INT1_PULSED:
1251 *val = LIS331DLH_INT1_PULSED;
1252 break;
1253
1254 case LIS331DLH_INT1_LATCHED:
1255 *val = LIS331DLH_INT1_LATCHED;
1256 break;
1257
1258 default:
1259 *val = LIS331DLH_INT1_PULSED;
1260 break;
1261 }
1262
1263 return ret;
1264 }
1265
1266 /**
1267 * @brief Data signal on INT 2 pad control bits.[set]
1268 *
1269 * @param ctx read / write interface definitions(ptr)
1270 * @param val change the values of i2_cfg in reg CTRL_REG3
1271 * @retval interface status (MANDATORY: return 0 -> no Error)
1272 *
1273 */
lis331dlh_pin_int2_route_set(const stmdev_ctx_t * ctx,lis331dlh_i2_cfg_t val)1274 int32_t lis331dlh_pin_int2_route_set(const stmdev_ctx_t *ctx,
1275 lis331dlh_i2_cfg_t val)
1276 {
1277 lis331dlh_ctrl_reg3_t ctrl_reg3;
1278 int32_t ret;
1279
1280 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1281 (uint8_t *)&ctrl_reg3, 1);
1282
1283 if (ret == 0)
1284 {
1285 ctrl_reg3.i2_cfg = (uint8_t)val;
1286 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1287 (uint8_t *)&ctrl_reg3, 1);
1288 }
1289
1290 return ret;
1291 }
1292
1293 /**
1294 * @brief Data signal on INT 2 pad control bits.[get]
1295 *
1296 * @param ctx read / write interface definitions(ptr)
1297 * @param val Get the values of i2_cfg in reg CTRL_REG3
1298 * @retval interface status (MANDATORY: return 0 -> no Error)
1299 *
1300 */
lis331dlh_pin_int2_route_get(const stmdev_ctx_t * ctx,lis331dlh_i2_cfg_t * val)1301 int32_t lis331dlh_pin_int2_route_get(const stmdev_ctx_t *ctx,
1302 lis331dlh_i2_cfg_t *val)
1303 {
1304 lis331dlh_ctrl_reg3_t ctrl_reg3;
1305 int32_t ret;
1306
1307 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1308 (uint8_t *)&ctrl_reg3, 1);
1309
1310 switch (ctrl_reg3.i2_cfg)
1311 {
1312 case LIS331DLH_PAD2_INT2_SRC:
1313 *val = LIS331DLH_PAD2_INT2_SRC;
1314 break;
1315
1316 case LIS331DLH_PAD2_INT1_OR_INT2_SRC:
1317 *val = LIS331DLH_PAD2_INT1_OR_INT2_SRC;
1318 break;
1319
1320 case LIS331DLH_PAD2_DRDY:
1321 *val = LIS331DLH_PAD2_DRDY;
1322 break;
1323
1324 case LIS331DLH_PAD2_BOOT:
1325 *val = LIS331DLH_PAD2_BOOT;
1326 break;
1327
1328 default:
1329 *val = LIS331DLH_PAD2_INT2_SRC;
1330 break;
1331 }
1332
1333 return ret;
1334 }
1335
1336 /**
1337 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1338 * register cleared by reading INT2_SRC itself.[set]
1339 *
1340 * @param ctx read / write interface definitions(ptr)
1341 * @param val change the values of lir2 in reg CTRL_REG3
1342 * @retval interface status (MANDATORY: return 0 -> no Error)
1343 *
1344 */
lis331dlh_int2_notification_set(const stmdev_ctx_t * ctx,lis331dlh_lir2_t val)1345 int32_t lis331dlh_int2_notification_set(const stmdev_ctx_t *ctx,
1346 lis331dlh_lir2_t val)
1347 {
1348 lis331dlh_ctrl_reg3_t ctrl_reg3;
1349 int32_t ret;
1350
1351 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1352 (uint8_t *)&ctrl_reg3, 1);
1353
1354 if (ret == 0)
1355 {
1356 ctrl_reg3.lir2 = (uint8_t)val;
1357 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1358 (uint8_t *)&ctrl_reg3, 1);
1359 }
1360
1361 return ret;
1362 }
1363
1364 /**
1365 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1366 * register cleared by reading INT2_SRC itself.[get]
1367 *
1368 * @param ctx read / write interface definitions(ptr)
1369 * @param val Get the values of lir2 in reg CTRL_REG3
1370 * @retval interface status (MANDATORY: return 0 -> no Error)
1371 *
1372 */
lis331dlh_int2_notification_get(const stmdev_ctx_t * ctx,lis331dlh_lir2_t * val)1373 int32_t lis331dlh_int2_notification_get(const stmdev_ctx_t *ctx,
1374 lis331dlh_lir2_t *val)
1375 {
1376 lis331dlh_ctrl_reg3_t ctrl_reg3;
1377 int32_t ret;
1378
1379 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1380 (uint8_t *)&ctrl_reg3, 1);
1381
1382 switch (ctrl_reg3.lir2)
1383 {
1384 case LIS331DLH_INT2_PULSED:
1385 *val = LIS331DLH_INT2_PULSED;
1386 break;
1387
1388 case LIS331DLH_INT2_LATCHED:
1389 *val = LIS331DLH_INT2_LATCHED;
1390 break;
1391
1392 default:
1393 *val = LIS331DLH_INT2_PULSED;
1394 break;
1395 }
1396
1397 return ret;
1398 }
1399
1400 /**
1401 * @brief Push-pull/open drain selection on interrupt pads.[set]
1402 *
1403 * @param ctx read / write interface definitions(ptr)
1404 * @param val change the values of pp_od in reg CTRL_REG3
1405 * @retval interface status (MANDATORY: return 0 -> no Error)
1406 *
1407 */
lis331dlh_pin_mode_set(const stmdev_ctx_t * ctx,lis331dlh_pp_od_t val)1408 int32_t lis331dlh_pin_mode_set(const stmdev_ctx_t *ctx,
1409 lis331dlh_pp_od_t val)
1410 {
1411 lis331dlh_ctrl_reg3_t ctrl_reg3;
1412 int32_t ret;
1413
1414 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1415 (uint8_t *)&ctrl_reg3, 1);
1416
1417 if (ret == 0)
1418 {
1419 ctrl_reg3.pp_od = (uint8_t)val;
1420 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1421 (uint8_t *)&ctrl_reg3, 1);
1422 }
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief Push-pull/open drain selection on interrupt pads.[get]
1429 *
1430 * @param ctx read / write interface definitions(ptr)
1431 * @param val Get the values of pp_od in reg CTRL_REG3
1432 * @retval interface status (MANDATORY: return 0 -> no Error)
1433 *
1434 */
lis331dlh_pin_mode_get(const stmdev_ctx_t * ctx,lis331dlh_pp_od_t * val)1435 int32_t lis331dlh_pin_mode_get(const stmdev_ctx_t *ctx,
1436 lis331dlh_pp_od_t *val)
1437 {
1438 lis331dlh_ctrl_reg3_t ctrl_reg3;
1439 int32_t ret;
1440
1441 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1442 (uint8_t *)&ctrl_reg3, 1);
1443
1444 switch (ctrl_reg3.pp_od)
1445 {
1446 case LIS331DLH_PUSH_PULL:
1447 *val = LIS331DLH_PUSH_PULL;
1448 break;
1449
1450 case LIS331DLH_OPEN_DRAIN:
1451 *val = LIS331DLH_OPEN_DRAIN;
1452 break;
1453
1454 default:
1455 *val = LIS331DLH_PUSH_PULL;
1456 break;
1457 }
1458
1459 return ret;
1460 }
1461
1462 /**
1463 * @brief Interrupt active-high/low.[set]
1464 *
1465 * @param ctx read / write interface definitions(ptr)
1466 * @param val change the values of ihl in reg CTRL_REG3
1467 * @retval interface status (MANDATORY: return 0 -> no Error)
1468 *
1469 */
lis331dlh_pin_polarity_set(const stmdev_ctx_t * ctx,lis331dlh_ihl_t val)1470 int32_t lis331dlh_pin_polarity_set(const stmdev_ctx_t *ctx,
1471 lis331dlh_ihl_t val)
1472 {
1473 lis331dlh_ctrl_reg3_t ctrl_reg3;
1474 int32_t ret;
1475
1476 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1477 (uint8_t *)&ctrl_reg3, 1);
1478
1479 if (ret == 0)
1480 {
1481 ctrl_reg3.ihl = (uint8_t)val;
1482 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1483 (uint8_t *)&ctrl_reg3, 1);
1484 }
1485
1486 return ret;
1487 }
1488
1489 /**
1490 * @brief Interrupt active-high/low.[get]
1491 *
1492 * @param ctx read / write interface definitions(ptr)
1493 * @param val Get the values of ihl in reg CTRL_REG3
1494 * @retval interface status (MANDATORY: return 0 -> no Error)
1495 *
1496 */
lis331dlh_pin_polarity_get(const stmdev_ctx_t * ctx,lis331dlh_ihl_t * val)1497 int32_t lis331dlh_pin_polarity_get(const stmdev_ctx_t *ctx,
1498 lis331dlh_ihl_t *val)
1499 {
1500 lis331dlh_ctrl_reg3_t ctrl_reg3;
1501 int32_t ret;
1502
1503 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1504 (uint8_t *)&ctrl_reg3, 1);
1505
1506 switch (ctrl_reg3.ihl)
1507 {
1508 case LIS331DLH_ACTIVE_HIGH:
1509 *val = LIS331DLH_ACTIVE_HIGH;
1510 break;
1511
1512 case LIS331DLH_ACTIVE_LOW:
1513 *val = LIS331DLH_ACTIVE_LOW;
1514 break;
1515
1516 default:
1517 *val = LIS331DLH_ACTIVE_HIGH;
1518 break;
1519 }
1520
1521 return ret;
1522 }
1523
1524 /**
1525 * @}
1526 *
1527 */
1528
1529 /**
1530 * @defgroup LIS331DLH_interrupt_on_threshold
1531 * @brief This section groups all the functions that manage
1532 * the interrupt on threshold event generation.
1533 * @{
1534 *
1535 */
1536
1537 /**
1538 * @brief Configure the interrupt 1 threshold sign.[set]
1539 *
1540 * @param ctx read / write interface definitions(ptr)
1541 * @param val enable sign and axis for interrupt on threshold
1542 * @retval interface status (MANDATORY: return 0 -> no Error)
1543 *
1544 */
lis331dlh_int1_on_threshold_conf_set(const stmdev_ctx_t * ctx,int1_on_th_conf_t val)1545 int32_t lis331dlh_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1546 int1_on_th_conf_t val)
1547 {
1548 lis331dlh_int1_cfg_t int1_cfg;
1549 int32_t ret;
1550
1551 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1552 (uint8_t *)&int1_cfg, 1);
1553
1554 if (ret == 0)
1555 {
1556 int1_cfg.xlie = val.int1_xlie;
1557 int1_cfg.xhie = val.int1_xhie;
1558 int1_cfg.ylie = val.int1_ylie;
1559 int1_cfg.yhie = val.int1_yhie;
1560 int1_cfg.zlie = val.int1_zlie;
1561 int1_cfg.zhie = val.int1_zhie;
1562 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
1563 (uint8_t *)&int1_cfg, 1);
1564 }
1565
1566 return ret;
1567 }
1568
1569 /**
1570 * @brief Configure the interrupt 1 threshold sign.[get]
1571 *
1572 * @param ctx read / write interface definitions(ptr)
1573 * @param val enable sign and axis for interrupt on threshold
1574 * @retval interface status (MANDATORY: return 0 -> no Error)
1575 *
1576 */
lis331dlh_int1_on_threshold_conf_get(const stmdev_ctx_t * ctx,int1_on_th_conf_t * val)1577 int32_t lis331dlh_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1578 int1_on_th_conf_t *val)
1579 {
1580 lis331dlh_int1_cfg_t int1_cfg;
1581 int32_t ret;
1582
1583 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1584 (uint8_t *)&int1_cfg, 1);
1585 val->int1_xlie = int1_cfg.xlie;
1586 val->int1_xhie = int1_cfg.xhie;
1587 val->int1_ylie = int1_cfg.ylie;
1588 val->int1_yhie = int1_cfg.yhie;
1589 val->int1_zlie = int1_cfg.zlie;
1590 val->int1_zhie = int1_cfg.zhie;
1591
1592 return ret;
1593 }
1594
1595 /**
1596 * @brief AND/OR combination of Interrupt 1 events.[set]
1597 *
1598 * @param ctx read / write interface definitions(ptr)
1599 * @param val change the values of aoi in reg INT1_CFG
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
lis331dlh_int1_on_threshold_mode_set(const stmdev_ctx_t * ctx,lis331dlh_int1_aoi_t val)1603 int32_t lis331dlh_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1604 lis331dlh_int1_aoi_t val)
1605 {
1606 lis331dlh_int1_cfg_t int1_cfg;
1607 int32_t ret;
1608
1609 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1610 (uint8_t *)&int1_cfg, 1);
1611
1612 if (ret == 0)
1613 {
1614 int1_cfg.aoi = (uint8_t) val;
1615 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
1616 (uint8_t *)&int1_cfg, 1);
1617 }
1618
1619 return ret;
1620 }
1621
1622 /**
1623 * @brief AND/OR combination of Interrupt 1 events.[get]
1624 *
1625 * @param ctx read / write interface definitions(ptr)
1626 * @param val Get the values of aoi in reg INT1_CFG
1627 * @retval interface status (MANDATORY: return 0 -> no Error)
1628 *
1629 */
lis331dlh_int1_on_threshold_mode_get(const stmdev_ctx_t * ctx,lis331dlh_int1_aoi_t * val)1630 int32_t lis331dlh_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1631 lis331dlh_int1_aoi_t *val)
1632 {
1633 lis331dlh_int1_cfg_t int1_cfg;
1634 int32_t ret;
1635
1636 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1637 (uint8_t *)&int1_cfg, 1);
1638
1639 switch (int1_cfg.aoi)
1640 {
1641 case LIS331DLH_INT1_ON_THRESHOLD_OR:
1642 *val = LIS331DLH_INT1_ON_THRESHOLD_OR;
1643 break;
1644
1645 case LIS331DLH_INT1_ON_THRESHOLD_AND:
1646 *val = LIS331DLH_INT1_ON_THRESHOLD_AND;
1647 break;
1648
1649 default:
1650 *val = LIS331DLH_INT1_ON_THRESHOLD_OR;
1651 break;
1652 }
1653
1654 return ret;
1655 }
1656
1657 /**
1658 * @brief Interrupt generator 1 on threshold source register.[get]
1659 *
1660 * @param ctx read / write interface definitions(ptr)
1661 * @param val registers INT1_SRC
1662 * @retval interface status (MANDATORY: return 0 -> no Error)
1663 *
1664 */
lis331dlh_int1_src_get(const stmdev_ctx_t * ctx,lis331dlh_int1_src_t * val)1665 int32_t lis331dlh_int1_src_get(const stmdev_ctx_t *ctx,
1666 lis331dlh_int1_src_t *val)
1667 {
1668 int32_t ret;
1669
1670 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
1671
1672 return ret;
1673 }
1674
1675 /**
1676 * @brief Interrupt 1 threshold.[set]
1677 *
1678 * @param ctx read / write interface definitions(ptr)
1679 * @param val change the values of ths in reg INT1_THS
1680 * @retval interface status (MANDATORY: return 0 -> no Error)
1681 *
1682 */
lis331dlh_int1_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1683 int32_t lis331dlh_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1684 {
1685 lis331dlh_int1_ths_t int1_ths;
1686 int32_t ret;
1687
1688 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
1689 (uint8_t *)&int1_ths, 1);
1690
1691 if (ret == 0)
1692 {
1693 int1_ths.ths = val;
1694 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
1695 (uint8_t *)&int1_ths, 1);
1696 }
1697
1698 return ret;
1699 }
1700
1701 /**
1702 * @brief Interrupt 1 threshold.[get]
1703 *
1704 * @param ctx read / write interface definitions(ptr)
1705 * @param val change the values of ths in reg INT1_THS
1706 * @retval interface status (MANDATORY: return 0 -> no Error)
1707 *
1708 */
lis331dlh_int1_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1709 int32_t lis331dlh_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1710 {
1711 lis331dlh_int1_ths_t int1_ths;
1712 int32_t ret;
1713
1714 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
1715 (uint8_t *)&int1_ths, 1);
1716 *val = int1_ths.ths;
1717
1718 return ret;
1719 }
1720
1721 /**
1722 * @brief Duration value for interrupt 1 generator.[set]
1723 *
1724 * @param ctx read / write interface definitions(ptr)
1725 * @param val change the values of d in reg INT1_DURATION
1726 * @retval interface status (MANDATORY: return 0 -> no Error)
1727 *
1728 */
lis331dlh_int1_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1729 int32_t lis331dlh_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1730 {
1731 lis331dlh_int1_duration_t int1_duration;
1732 int32_t ret;
1733
1734 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
1735 (uint8_t *)&int1_duration, 1);
1736
1737 if (ret == 0)
1738 {
1739 int1_duration.d = val;
1740 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_DURATION,
1741 (uint8_t *)&int1_duration, 1);
1742 }
1743
1744 return ret;
1745 }
1746
1747 /**
1748 * @brief Duration value for interrupt 1 generator.[get]
1749 *
1750 * @param ctx read / write interface definitions(ptr)
1751 * @param val change the values of d in reg INT1_DURATION
1752 * @retval interface status (MANDATORY: return 0 -> no Error)
1753 *
1754 */
lis331dlh_int1_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1755 int32_t lis331dlh_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1756 {
1757 lis331dlh_int1_duration_t int1_duration;
1758 int32_t ret;
1759
1760 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
1761 (uint8_t *)&int1_duration, 1);
1762 *val = int1_duration.d;
1763
1764 return ret;
1765 }
1766
1767 /**
1768 * @brief Configure the interrupt 2 threshold sign.[set]
1769 *
1770 * @param ctx read / write interface definitions(ptr)
1771 * @param val enable sign and axis for interrupt on threshold
1772 * @retval interface status (MANDATORY: return 0 -> no Error)
1773 *
1774 */
lis331dlh_int2_on_threshold_conf_set(const stmdev_ctx_t * ctx,int2_on_th_conf_t val)1775 int32_t lis331dlh_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1776 int2_on_th_conf_t val)
1777 {
1778 lis331dlh_int2_cfg_t int2_cfg;
1779 int32_t ret;
1780
1781 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1782 (uint8_t *)&int2_cfg, 1);
1783
1784 if (ret == 0)
1785 {
1786 int2_cfg.xlie = val.int2_xlie;
1787 int2_cfg.xhie = val.int2_xhie;
1788 int2_cfg.ylie = val.int2_ylie;
1789 int2_cfg.yhie = val.int2_yhie;
1790 int2_cfg.zlie = val.int2_zlie;
1791 int2_cfg.zhie = val.int2_zhie;
1792 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
1793 (uint8_t *)&int2_cfg, 1);
1794 }
1795
1796 return ret;
1797 }
1798
1799 /**
1800 * @brief Configure the interrupt 2 threshold sign.[get]
1801 *
1802 * @param ctx read / write interface definitions(ptr)
1803 * @param val enable sign and axis for interrupt on threshold
1804 * @retval interface status (MANDATORY: return 0 -> no Error)
1805 *
1806 */
lis331dlh_int2_on_threshold_conf_get(const stmdev_ctx_t * ctx,int2_on_th_conf_t * val)1807 int32_t lis331dlh_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1808 int2_on_th_conf_t *val)
1809 {
1810 lis331dlh_int2_cfg_t int2_cfg;
1811 int32_t ret;
1812
1813 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1814 (uint8_t *)&int2_cfg, 1);
1815 val->int2_xlie = int2_cfg.xlie;
1816 val->int2_xhie = int2_cfg.xhie;
1817 val->int2_ylie = int2_cfg.ylie;
1818 val->int2_yhie = int2_cfg.yhie;
1819 val->int2_zlie = int2_cfg.zlie;
1820 val->int2_zhie = int2_cfg.zhie;
1821
1822 return ret;
1823 }
1824
1825 /**
1826 * @brief AND/OR combination of Interrupt 2 events.[set]
1827 *
1828 * @param ctx read / write interface definitions(ptr)
1829 * @param val change the values of aoi in reg INT2_CFG
1830 * @retval interface status (MANDATORY: return 0 -> no Error)
1831 *
1832 */
lis331dlh_int2_on_threshold_mode_set(const stmdev_ctx_t * ctx,lis331dlh_int2_aoi_t val)1833 int32_t lis331dlh_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1834 lis331dlh_int2_aoi_t val)
1835 {
1836 lis331dlh_int2_cfg_t int2_cfg;
1837 int32_t ret;
1838
1839 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1840 (uint8_t *)&int2_cfg, 1);
1841
1842 if (ret == 0)
1843 {
1844 int2_cfg.aoi = (uint8_t) val;
1845 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
1846 (uint8_t *)&int2_cfg, 1);
1847 }
1848
1849 return ret;
1850 }
1851
1852 /**
1853 * @brief AND/OR combination of Interrupt 2 events.[get]
1854 *
1855 * @param ctx read / write interface definitions(ptr)
1856 * @param val Get the values of aoi in reg INT2_CFG
1857 * @retval interface status (MANDATORY: return 0 -> no Error)
1858 *
1859 */
lis331dlh_int2_on_threshold_mode_get(const stmdev_ctx_t * ctx,lis331dlh_int2_aoi_t * val)1860 int32_t lis331dlh_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1861 lis331dlh_int2_aoi_t *val)
1862 {
1863 lis331dlh_int2_cfg_t int2_cfg;
1864 int32_t ret;
1865
1866 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1867 (uint8_t *)&int2_cfg, 1);
1868
1869 switch (int2_cfg.aoi)
1870 {
1871 case LIS331DLH_INT2_ON_THRESHOLD_OR:
1872 *val = LIS331DLH_INT2_ON_THRESHOLD_OR;
1873 break;
1874
1875 case LIS331DLH_INT2_ON_THRESHOLD_AND:
1876 *val = LIS331DLH_INT2_ON_THRESHOLD_AND;
1877 break;
1878
1879 default:
1880 *val = LIS331DLH_INT2_ON_THRESHOLD_OR;
1881 break;
1882 }
1883
1884 return ret;
1885 }
1886
1887 /**
1888 * @brief Interrupt generator 1 on threshold source register.[get]
1889 *
1890 * @param ctx read / write interface definitions(ptr)
1891 * @param val registers INT2_SRC
1892 * @retval interface status (MANDATORY: return 0 -> no Error)
1893 *
1894 */
lis331dlh_int2_src_get(const stmdev_ctx_t * ctx,lis331dlh_int2_src_t * val)1895 int32_t lis331dlh_int2_src_get(const stmdev_ctx_t *ctx,
1896 lis331dlh_int2_src_t *val)
1897 {
1898 int32_t ret;
1899
1900 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
1901
1902 return ret;
1903 }
1904
1905 /**
1906 * @brief Interrupt 2 threshold.[set]
1907 *
1908 * @param ctx read / write interface definitions(ptr)
1909 * @param val change the values of ths in reg INT2_THS
1910 * @retval interface status (MANDATORY: return 0 -> no Error)
1911 *
1912 */
lis331dlh_int2_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1913 int32_t lis331dlh_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1914 {
1915 lis331dlh_int2_ths_t int2_ths;
1916 int32_t ret;
1917
1918 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
1919 (uint8_t *)&int2_ths, 1);
1920
1921 if (ret == 0)
1922 {
1923 int2_ths.ths = val;
1924 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
1925 (uint8_t *)&int2_ths, 1);
1926 }
1927
1928 return ret;
1929 }
1930
1931 /**
1932 * @brief Interrupt 2 threshold.[get]
1933 *
1934 * @param ctx read / write interface definitions(ptr)
1935 * @param val change the values of ths in reg INT2_THS
1936 * @retval interface status (MANDATORY: return 0 -> no Error)
1937 *
1938 */
lis331dlh_int2_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1939 int32_t lis331dlh_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1940 {
1941 lis331dlh_int2_ths_t int2_ths;
1942 int32_t ret;
1943
1944 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
1945 (uint8_t *)&int2_ths, 1);
1946 *val = int2_ths.ths;
1947
1948 return ret;
1949 }
1950
1951 /**
1952 * @brief Duration value for interrupt 2 generator.[set]
1953 *
1954 * @param ctx read / write interface definitions(ptr)
1955 * @param val change the values of d in reg INT2_DURATION
1956 * @retval interface status (MANDATORY: return 0 -> no Error)
1957 *
1958 */
lis331dlh_int2_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1959 int32_t lis331dlh_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1960 {
1961 lis331dlh_int2_duration_t int2_duration;
1962 int32_t ret;
1963
1964 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
1965 (uint8_t *)&int2_duration, 1);
1966
1967 if (ret == 0)
1968 {
1969 int2_duration.d = val;
1970 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_DURATION,
1971 (uint8_t *)&int2_duration, 1);
1972 }
1973
1974 return ret;
1975 }
1976
1977 /**
1978 * @brief Duration value for interrupt 2 generator.[get]
1979 *
1980 * @param ctx read / write interface definitions(ptr)
1981 * @param val change the values of d in reg INT2_DURATION
1982 * @retval interface status (MANDATORY: return 0 -> no Error)
1983 *
1984 */
lis331dlh_int2_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1985 int32_t lis331dlh_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1986 {
1987 lis331dlh_int2_duration_t int2_duration;
1988 int32_t ret;
1989
1990 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
1991 (uint8_t *)&int2_duration, 1);
1992 *val = int2_duration.d;
1993
1994 return ret;
1995 }
1996
1997 /**
1998 * @}
1999 *
2000 */
2001
2002 /**
2003 * @defgroup LIS331DLH_Wake_Up_Event
2004 * @brief This section groups all the functions that manage the
2005 * Wake Up event generation.
2006 * @{
2007 *
2008 */
2009
2010 /**
2011 * @brief Turn-on mode selection for sleep to wake function.[set]
2012 *
2013 * @param ctx read / write interface definitions(ptr)
2014 * @param val change the values of turnon in reg CTRL_REG5
2015 * @retval interface status (MANDATORY: return 0 -> no Error)
2016 *
2017 */
lis331dlh_wkup_to_sleep_set(const stmdev_ctx_t * ctx,uint8_t val)2018 int32_t lis331dlh_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val)
2019 {
2020 lis331dlh_ctrl_reg5_t ctrl_reg5;
2021 int32_t ret;
2022
2023 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
2024 (uint8_t *)&ctrl_reg5, 1);
2025
2026 if (ret == 0)
2027 {
2028 ctrl_reg5.turnon = val;
2029 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG5,
2030 (uint8_t *)&ctrl_reg5, 1);
2031 }
2032
2033 return ret;
2034 }
2035
2036 /**
2037 * @brief Turn-on mode selection for sleep to wake function.[get]
2038 *
2039 * @param ctx read / write interface definitions(ptr)
2040 * @param val change the values of turnon in reg CTRL_REG5
2041 * @retval interface status (MANDATORY: return 0 -> no Error)
2042 *
2043 */
lis331dlh_wkup_to_sleep_get(const stmdev_ctx_t * ctx,uint8_t * val)2044 int32_t lis331dlh_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val)
2045 {
2046 lis331dlh_ctrl_reg5_t ctrl_reg5;
2047 int32_t ret;
2048
2049 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
2050 (uint8_t *)&ctrl_reg5, 1);
2051 *val = ctrl_reg5.turnon;
2052
2053 return ret;
2054 }
2055
2056 /**
2057 * @}
2058 *
2059 */
2060
2061 /**
2062 * @defgroup LIS331DLH_Six_Position_Detection
2063 * @brief This section groups all the functions concerning six
2064 * position detection (6D).
2065 * @{
2066 *
2067 */
2068
2069 /**
2070 * @brief Configure the 6d on interrupt 1 generator.[set]
2071 *
2072 * @param ctx read / write interface definitions(ptr)
2073 * @param val change the values of 6d in reg INT1_CFG
2074 * @retval interface status (MANDATORY: return 0 -> no Error)
2075 *
2076 */
lis331dlh_int1_6d_mode_set(const stmdev_ctx_t * ctx,lis331dlh_int1_6d_t val)2077 int32_t lis331dlh_int1_6d_mode_set(const stmdev_ctx_t *ctx,
2078 lis331dlh_int1_6d_t val)
2079 {
2080 lis331dlh_int1_cfg_t int1_cfg;
2081 int32_t ret;
2082
2083 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
2084 (uint8_t *)&int1_cfg, 1);
2085
2086 if (ret == 0)
2087 {
2088 int1_cfg._6d = (uint8_t)val & 0x01U;
2089 int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2090 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
2091 (uint8_t *)&int1_cfg, 1);
2092 }
2093
2094 return ret;
2095 }
2096
2097 /**
2098 * @brief Configure the 6d on interrupt 1 generator.[get]
2099 *
2100 * @param ctx read / write interface definitions(ptr)
2101 * @param val Get the values of 6d in reg INT1_CFG
2102 * @retval interface status (MANDATORY: return 0 -> no Error)
2103 *
2104 */
lis331dlh_int1_6d_mode_get(const stmdev_ctx_t * ctx,lis331dlh_int1_6d_t * val)2105 int32_t lis331dlh_int1_6d_mode_get(const stmdev_ctx_t *ctx,
2106 lis331dlh_int1_6d_t *val)
2107 {
2108 lis331dlh_int1_cfg_t int1_cfg;
2109 int32_t ret;
2110
2111 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
2112 (uint8_t *)&int1_cfg, 1);
2113
2114 switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
2115 {
2116 case LIS331DLH_6D_INT1_DISABLE:
2117 *val = LIS331DLH_6D_INT1_DISABLE;
2118 break;
2119
2120 case LIS331DLH_6D_INT1_MOVEMENT:
2121 *val = LIS331DLH_6D_INT1_MOVEMENT;
2122 break;
2123
2124 case LIS331DLH_6D_INT1_POSITION:
2125 *val = LIS331DLH_6D_INT1_POSITION;
2126 break;
2127
2128 default:
2129 *val = LIS331DLH_6D_INT1_DISABLE;
2130 break;
2131 }
2132
2133 return ret;
2134 }
2135
2136 /**
2137 * @brief 6D on interrupt generator 1 source register.[get]
2138 *
2139 * @param ctx read / write interface definitions(ptr)
2140 * @param val registers INT1_SRC
2141 * @retval interface status (MANDATORY: return 0 -> no Error)
2142 *
2143 */
lis331dlh_int1_6d_src_get(const stmdev_ctx_t * ctx,lis331dlh_int1_src_t * val)2144 int32_t lis331dlh_int1_6d_src_get(const stmdev_ctx_t *ctx,
2145 lis331dlh_int1_src_t *val)
2146 {
2147 int32_t ret;
2148
2149 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
2150
2151 return ret;
2152 }
2153
2154 /**
2155 * @brief Interrupt 1 threshold.[set]
2156 *
2157 * @param ctx read / write interface definitions(ptr)
2158 * @param val change the values of ths in reg INT1_THS
2159 * @retval interface status (MANDATORY: return 0 -> no Error)
2160 *
2161 */
lis331dlh_int1_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2162 int32_t lis331dlh_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2163 {
2164 lis331dlh_int1_ths_t int1_ths;
2165 int32_t ret;
2166
2167 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
2168 (uint8_t *)&int1_ths, 1);
2169
2170 if (ret == 0)
2171 {
2172 int1_ths.ths = val;
2173 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
2174 (uint8_t *)&int1_ths, 1);
2175 }
2176
2177 return ret;
2178 }
2179
2180 /**
2181 * @brief Interrupt 1 threshold.[get]
2182 *
2183 * @param ctx read / write interface definitions(ptr)
2184 * @param val change the values of ths in reg INT1_THS
2185 * @retval interface status (MANDATORY: return 0 -> no Error)
2186 *
2187 */
lis331dlh_int1_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2188 int32_t lis331dlh_int1_6d_threshold_get(const stmdev_ctx_t *ctx,
2189 uint8_t *val)
2190 {
2191 lis331dlh_int1_ths_t int1_ths;
2192 int32_t ret;
2193
2194 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
2195 (uint8_t *)&int1_ths, 1);
2196 *val = int1_ths.ths;
2197
2198 return ret;
2199 }
2200
2201 /**
2202 * @brief Configure the 6d on interrupt 2 generator.[set]
2203 *
2204 * @param ctx read / write interface definitions(ptr)
2205 * @param val change the values of 6d in reg INT2_CFG
2206 * @retval interface status (MANDATORY: return 0 -> no Error)
2207 *
2208 */
lis331dlh_int2_6d_mode_set(const stmdev_ctx_t * ctx,lis331dlh_int2_6d_t val)2209 int32_t lis331dlh_int2_6d_mode_set(const stmdev_ctx_t *ctx,
2210 lis331dlh_int2_6d_t val)
2211 {
2212 lis331dlh_int2_cfg_t int2_cfg;
2213 int32_t ret;
2214
2215 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
2216 (uint8_t *)&int2_cfg, 1);
2217
2218 if (ret == 0)
2219 {
2220 int2_cfg._6d = (uint8_t)val & 0x01U;
2221 int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2222 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
2223 (uint8_t *)&int2_cfg, 1);
2224 }
2225
2226 return ret;
2227 }
2228
2229 /**
2230 * @brief Configure the 6d on interrupt 2 generator.[get]
2231 *
2232 * @param ctx read / write interface definitions(ptr)
2233 * @param val Get the values of 6d in reg INT2_CFG
2234 * @retval interface status (MANDATORY: return 0 -> no Error)
2235 *
2236 */
lis331dlh_int2_6d_mode_get(const stmdev_ctx_t * ctx,lis331dlh_int2_6d_t * val)2237 int32_t lis331dlh_int2_6d_mode_get(const stmdev_ctx_t *ctx,
2238 lis331dlh_int2_6d_t *val)
2239 {
2240 lis331dlh_int2_cfg_t int2_cfg;
2241 int32_t ret;
2242
2243 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
2244 (uint8_t *)&int2_cfg, 1);
2245
2246 switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
2247 {
2248 case LIS331DLH_6D_INT2_DISABLE:
2249 *val = LIS331DLH_6D_INT2_DISABLE;
2250 break;
2251
2252 case LIS331DLH_6D_INT2_MOVEMENT:
2253 *val = LIS331DLH_6D_INT2_MOVEMENT;
2254 break;
2255
2256 case LIS331DLH_6D_INT2_POSITION:
2257 *val = LIS331DLH_6D_INT2_POSITION;
2258 break;
2259
2260 default:
2261 *val = LIS331DLH_6D_INT2_DISABLE;
2262 break;
2263 }
2264
2265 return ret;
2266 }
2267
2268 /**
2269 * @brief 6D on interrupt generator 2 source register.[get]
2270 *
2271 * @param ctx read / write interface definitions(ptr)
2272 * @param val registers INT2_SRC
2273 * @retval interface status (MANDATORY: return 0 -> no Error)
2274 *
2275 */
lis331dlh_int2_6d_src_get(const stmdev_ctx_t * ctx,lis331dlh_int2_src_t * val)2276 int32_t lis331dlh_int2_6d_src_get(const stmdev_ctx_t *ctx,
2277 lis331dlh_int2_src_t *val)
2278 {
2279 int32_t ret;
2280
2281 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
2282
2283 return ret;
2284 }
2285
2286 /**
2287 * @brief Interrupt 2 threshold.[set]
2288 *
2289 * @param ctx read / write interface definitions(ptr)
2290 * @param val change the values of ths in reg INT2_THS
2291 * @retval interface status (MANDATORY: return 0 -> no Error)
2292 *
2293 */
lis331dlh_int2_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2294 int32_t lis331dlh_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2295 {
2296 lis331dlh_int2_ths_t int2_ths;
2297 int32_t ret;
2298
2299 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
2300 (uint8_t *)&int2_ths, 1);
2301
2302 if (ret == 0)
2303 {
2304 int2_ths.ths = val;
2305 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
2306 (uint8_t *)&int2_ths, 1);
2307 }
2308
2309 return ret;
2310 }
2311
2312 /**
2313 * @brief Interrupt 2 threshold.[get]
2314 *
2315 * @param ctx read / write interface definitions(ptr)
2316 * @param val change the values of ths in reg INT2_THS
2317 * @retval interface status (MANDATORY: return 0 -> no Error)
2318 *
2319 */
lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2320 int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx,
2321 uint8_t *val)
2322 {
2323 lis331dlh_int2_ths_t int2_ths;
2324 int32_t ret;
2325
2326 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
2327 (uint8_t *)&int2_ths, 1);
2328 *val = int2_ths.ths;
2329
2330 return ret;
2331 }
2332
2333 /**
2334 * @}
2335 *
2336 */
2337
2338 /**
2339 * @}
2340 *
2341 */
2342
2343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2344
