1 /**
2 ******************************************************************************
3 * @file lis331dlh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS331DLH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis331dlh_reg.h"
21
22 /**
23 * @defgroup LIS331DLH
24 * @brief This file provides a set of functions needed to drive the
25 * lis331dlh enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS331DLH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis331dlh_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis331dlh_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS331DLH_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis331dlh_from_fs2_to_mg(int16_t lsb)93 float_t lis331dlh_from_fs2_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb / 16.0f);
96 }
97
lis331dlh_from_fs4_to_mg(int16_t lsb)98 float_t lis331dlh_from_fs4_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 2.0f / 16.0f);
101 }
102
lis331dlh_from_fs8_to_mg(int16_t lsb)103 float_t lis331dlh_from_fs8_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 3.9f / 16.0f);
106 }
107
108 /**
109 * @}
110 *
111 */
112
113 /**
114 * @defgroup LIS331DLH_Data_Generation
115 * @brief This section group all the functions concerning
116 * data generation
117 * @{
118 *
119 */
120
121 /**
122 * @brief X axis enable/disable.[set]
123 *
124 * @param ctx read / write interface definitions(ptr)
125 * @param val change the values of xen in reg CTRL_REG1
126 * @retval interface status (MANDATORY: return 0 -> no Error)
127 *
128 */
lis331dlh_axis_x_data_set(stmdev_ctx_t * ctx,uint8_t val)129 int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
130 {
131 lis331dlh_ctrl_reg1_t ctrl_reg1;
132 int32_t ret;
133
134 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
135 (uint8_t *)&ctrl_reg1, 1);
136
137 if (ret == 0)
138 {
139 ctrl_reg1.xen = val;
140 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
141 (uint8_t *)&ctrl_reg1, 1);
142 }
143
144 return ret;
145 }
146
147 /**
148 * @brief X axis enable/disable.[get]
149 *
150 * @param ctx read / write interface definitions(ptr)
151 * @param val change the values of xen in reg CTRL_REG1
152 * @retval interface status (MANDATORY: return 0 -> no Error)
153 *
154 */
lis331dlh_axis_x_data_get(stmdev_ctx_t * ctx,uint8_t * val)155 int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
156 {
157 lis331dlh_ctrl_reg1_t ctrl_reg1;
158 int32_t ret;
159
160 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
161 (uint8_t *)&ctrl_reg1, 1);
162 *val = ctrl_reg1.xen;
163
164 return ret;
165 }
166
167 /**
168 * @brief Y axis enable/disable.[set]
169 *
170 * @param ctx read / write interface definitions(ptr)
171 * @param val change the values of yen in reg CTRL_REG1
172 * @retval interface status (MANDATORY: return 0 -> no Error)
173 *
174 */
lis331dlh_axis_y_data_set(stmdev_ctx_t * ctx,uint8_t val)175 int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
176 {
177 lis331dlh_ctrl_reg1_t ctrl_reg1;
178 int32_t ret;
179
180 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
181 (uint8_t *)&ctrl_reg1, 1);
182
183 if (ret == 0)
184 {
185 ctrl_reg1.yen = val;
186 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
187 (uint8_t *)&ctrl_reg1, 1);
188 }
189
190 return ret;
191 }
192
193 /**
194 * @brief Y axis enable/disable.[get]
195 *
196 * @param ctx read / write interface definitions(ptr)
197 * @param val change the values of yen in reg CTRL_REG1
198 * @retval interface status (MANDATORY: return 0 -> no Error)
199 *
200 */
lis331dlh_axis_y_data_get(stmdev_ctx_t * ctx,uint8_t * val)201 int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
202 {
203 lis331dlh_ctrl_reg1_t ctrl_reg1;
204 int32_t ret;
205
206 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
207 (uint8_t *)&ctrl_reg1, 1);
208 *val = ctrl_reg1.yen;
209
210 return ret;
211 }
212
213 /**
214 * @brief Z axis enable/disable.[set]
215 *
216 * @param ctx read / write interface definitions(ptr)
217 * @param val change the values of zen in reg CTRL_REG1
218 * @retval interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
lis331dlh_axis_z_data_set(stmdev_ctx_t * ctx,uint8_t val)221 int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
222 {
223 lis331dlh_ctrl_reg1_t ctrl_reg1;
224 int32_t ret;
225
226 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
227 (uint8_t *)&ctrl_reg1, 1);
228
229 if (ret == 0)
230 {
231 ctrl_reg1.zen = val;
232 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
233 (uint8_t *)&ctrl_reg1, 1);
234 }
235
236 return ret;
237 }
238
239 /**
240 * @brief Z axis enable/disable.[get]
241 *
242 * @param ctx read / write interface definitions(ptr)
243 * @param val change the values of zen in reg CTRL_REG1
244 * @retval interface status (MANDATORY: return 0 -> no Error)
245 *
246 */
lis331dlh_axis_z_data_get(stmdev_ctx_t * ctx,uint8_t * val)247 int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
248 {
249 lis331dlh_ctrl_reg1_t ctrl_reg1;
250 int32_t ret;
251
252 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
253 (uint8_t *)&ctrl_reg1, 1);
254 *val = ctrl_reg1.zen;
255
256 return ret;
257 }
258
259 /**
260 * @brief Accelerometer data rate selection.[set]
261 *
262 * @param ctx read / write interface definitions(ptr)
263 * @param val change the values of dr in reg CTRL_REG1
264 * @retval interface status (MANDATORY: return 0 -> no Error)
265 *
266 */
lis331dlh_data_rate_set(stmdev_ctx_t * ctx,lis331dlh_dr_t val)267 int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val)
268 {
269 lis331dlh_ctrl_reg1_t ctrl_reg1;
270 int32_t ret;
271
272 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
273 (uint8_t *)&ctrl_reg1, 1);
274
275 if (ret == 0)
276 {
277 ctrl_reg1.pm = (uint8_t)val & 0x07U;
278 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
279 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG1,
280 (uint8_t *)&ctrl_reg1, 1);
281 }
282
283 return ret;
284 }
285
286 /**
287 * @brief Accelerometer data rate selection.[get]
288 *
289 * @param ctx read / write interface definitions(ptr)
290 * @param val Get the values of dr in reg CTRL_REG1
291 * @retval interface status (MANDATORY: return 0 -> no Error)
292 *
293 */
lis331dlh_data_rate_get(stmdev_ctx_t * ctx,lis331dlh_dr_t * val)294 int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx,
295 lis331dlh_dr_t *val)
296 {
297 lis331dlh_ctrl_reg1_t ctrl_reg1;
298 int32_t ret;
299
300 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1,
301 (uint8_t *)&ctrl_reg1, 1);
302
303 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
304 {
305 case LIS331DLH_ODR_OFF:
306 *val = LIS331DLH_ODR_OFF;
307 break;
308
309 case LIS331DLH_ODR_Hz5:
310 *val = LIS331DLH_ODR_Hz5;
311 break;
312
313 case LIS331DLH_ODR_1Hz:
314 *val = LIS331DLH_ODR_1Hz;
315 break;
316
317 case LIS331DLH_ODR_2Hz:
318 *val = LIS331DLH_ODR_2Hz;
319 break;
320
321 case LIS331DLH_ODR_5Hz:
322 *val = LIS331DLH_ODR_5Hz;
323 break;
324
325 case LIS331DLH_ODR_10Hz:
326 *val = LIS331DLH_ODR_10Hz;
327 break;
328
329 case LIS331DLH_ODR_50Hz:
330 *val = LIS331DLH_ODR_50Hz;
331 break;
332
333 case LIS331DLH_ODR_100Hz:
334 *val = LIS331DLH_ODR_100Hz;
335 break;
336
337 case LIS331DLH_ODR_400Hz:
338 *val = LIS331DLH_ODR_400Hz;
339 break;
340
341 case LIS331DLH_ODR_1kHz:
342 *val = LIS331DLH_ODR_1kHz;
343 break;
344
345 default:
346 *val = LIS331DLH_ODR_OFF;
347 break;
348 }
349
350 return ret;
351 }
352
353 /**
354 * @brief High pass filter mode selection.[set]
355 *
356 * @param ctx read / write interface definitions(ptr)
357 * @param val change the values of hpm in reg CTRL_REG2
358 * @retval interface status (MANDATORY: return 0 -> no Error)
359 *
360 */
lis331dlh_reference_mode_set(stmdev_ctx_t * ctx,lis331dlh_hpm_t val)361 int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx,
362 lis331dlh_hpm_t val)
363 {
364 lis331dlh_ctrl_reg2_t ctrl_reg2;
365 int32_t ret;
366
367 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
368 (uint8_t *)&ctrl_reg2, 1);
369
370 if (ret == 0)
371 {
372 ctrl_reg2.hpm = (uint8_t)val;
373 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
374 (uint8_t *)&ctrl_reg2, 1);
375 }
376
377 return ret;
378 }
379
380 /**
381 * @brief High pass filter mode selection.[get]
382 *
383 * @param ctx read / write interface definitions(ptr)
384 * @param val Get the values of hpm in reg CTRL_REG2
385 * @retval interface status (MANDATORY: return 0 -> no Error)
386 *
387 */
lis331dlh_reference_mode_get(stmdev_ctx_t * ctx,lis331dlh_hpm_t * val)388 int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx,
389 lis331dlh_hpm_t *val)
390 {
391 lis331dlh_ctrl_reg2_t ctrl_reg2;
392 int32_t ret;
393
394 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
395 (uint8_t *)&ctrl_reg2, 1);
396
397 switch (ctrl_reg2.hpm)
398 {
399 case LIS331DLH_NORMAL_MODE:
400 *val = LIS331DLH_NORMAL_MODE;
401 break;
402
403 case LIS331DLH_REF_MODE_ENABLE:
404 *val = LIS331DLH_REF_MODE_ENABLE;
405 break;
406
407 default:
408 *val = LIS331DLH_NORMAL_MODE;
409 break;
410 }
411
412 return ret;
413 }
414
415 /**
416 * @brief Accelerometer full-scale selection.[set]
417 *
418 * @param ctx read / write interface definitions(ptr)
419 * @param val change the values of fs in reg CTRL_REG4
420 * @retval interface status (MANDATORY: return 0 -> no Error)
421 *
422 */
lis331dlh_full_scale_set(stmdev_ctx_t * ctx,lis331dlh_fs_t val)423 int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx,
424 lis331dlh_fs_t val)
425 {
426 lis331dlh_ctrl_reg4_t ctrl_reg4;
427 int32_t ret;
428
429 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
430 (uint8_t *)&ctrl_reg4, 1);
431
432 if (ret == 0)
433 {
434 ctrl_reg4.fs = (uint8_t)val;
435 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
436 (uint8_t *)&ctrl_reg4, 1);
437 }
438
439 return ret;
440 }
441
442 /**
443 * @brief Accelerometer full-scale selection.[get]
444 *
445 * @param ctx read / write interface definitions(ptr)
446 * @param val Get the values of fs in reg CTRL_REG4
447 * @retval interface status (MANDATORY: return 0 -> no Error)
448 *
449 */
lis331dlh_full_scale_get(stmdev_ctx_t * ctx,lis331dlh_fs_t * val)450 int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx,
451 lis331dlh_fs_t *val)
452 {
453 lis331dlh_ctrl_reg4_t ctrl_reg4;
454 int32_t ret;
455
456 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
457 (uint8_t *)&ctrl_reg4, 1);
458
459 switch (ctrl_reg4.fs)
460 {
461 case LIS331DLH_2g:
462 *val = LIS331DLH_2g;
463 break;
464
465 case LIS331DLH_4g:
466 *val = LIS331DLH_4g;
467 break;
468
469 case LIS331DLH_8g:
470 *val = LIS331DLH_8g;
471 break;
472
473 default:
474 *val = LIS331DLH_2g;
475 break;
476 }
477
478 return ret;
479 }
480
481 /**
482 * @brief Block data update.[set]
483 *
484 * @param ctx read / write interface definitions(ptr)
485 * @param val change the values of bdu in reg CTRL_REG4
486 * @retval interface status (MANDATORY: return 0 -> no Error)
487 *
488 */
lis331dlh_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)489 int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx,
490 uint8_t val)
491 {
492 lis331dlh_ctrl_reg4_t ctrl_reg4;
493 int32_t ret;
494
495 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
496 (uint8_t *)&ctrl_reg4, 1);
497
498 if (ret == 0)
499 {
500 ctrl_reg4.bdu = val;
501 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
502 (uint8_t *)&ctrl_reg4, 1);
503 }
504
505 return ret;
506 }
507
508 /**
509 * @brief Block data update.[get]
510 *
511 * @param ctx read / write interface definitions(ptr)
512 * @param val change the values of bdu in reg CTRL_REG4
513 * @retval interface status (MANDATORY: return 0 -> no Error)
514 *
515 */
lis331dlh_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)516 int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx,
517 uint8_t *val)
518 {
519 lis331dlh_ctrl_reg4_t ctrl_reg4;
520 int32_t ret;
521
522 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
523 (uint8_t *)&ctrl_reg4, 1);
524 *val = ctrl_reg4.bdu;
525
526 return ret;
527 }
528
529 /**
530 * @brief The STATUS_REG register is read by the interface.[get]
531 *
532 * @param ctx read / write interface definitions(ptr)
533 * @param val registers STATUS_REG
534 * @retval interface status (MANDATORY: return 0 -> no Error)
535 *
536 */
lis331dlh_status_reg_get(stmdev_ctx_t * ctx,lis331dlh_status_reg_t * val)537 int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx,
538 lis331dlh_status_reg_t *val)
539 {
540 int32_t ret;
541
542 ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG, (uint8_t *) val, 1);
543
544 return ret;
545 }
546
547 /**
548 * @brief Accelerometer new data available.[get]
549 *
550 * @param ctx read / write interface definitions(ptr)
551 * @param val change the values of zyxda in reg STATUS_REG
552 * @retval interface status (MANDATORY: return 0 -> no Error)
553 *
554 */
lis331dlh_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)555 int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
556 {
557 lis331dlh_status_reg_t status_reg;
558 int32_t ret;
559
560 ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG,
561 (uint8_t *)&status_reg, 1);
562 *val = status_reg.zyxda;
563
564 return ret;
565 }
566
567 /**
568 * @}
569 *
570 */
571
572 /**
573 * @defgroup LIS331DLH_Data_Output
574 * @brief This section groups all the data output functions.
575 * @{
576 *
577 */
578
579 /**
580 * @brief Linear acceleration output register. The value is expressed
581 * as a 16-bit word in two’s complement.[get]
582 *
583 * @param ctx read / write interface definitions(ptr)
584 * @param buff buffer that stores data read
585 * @retval interface status (MANDATORY: return 0 -> no Error)
586 *
587 */
lis331dlh_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)588 int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx,
589 int16_t *val)
590 {
591 uint8_t buff[6];
592 int32_t ret;
593
594 ret = lis331dlh_read_reg(ctx, LIS331DLH_OUT_X_L, buff, 6);
595 val[0] = (int16_t)buff[1];
596 val[0] = (val[0] * 256) + (int16_t)buff[0];
597 val[1] = (int16_t)buff[3];
598 val[1] = (val[1] * 256) + (int16_t)buff[2];
599 val[2] = (int16_t)buff[5];
600 val[2] = (val[2] * 256) + (int16_t)buff[4];
601
602 return ret;
603 }
604
605 /**
606 * @}
607 *
608 */
609
610 /**
611 * @defgroup LIS331DLH_Common
612 * @brief This section groups common useful functions.
613 * @{
614 *
615 */
616
617 /**
618 * @brief Device Who am I.[get]
619 *
620 * @param ctx read / write interface definitions(ptr)
621 * @param buff buffer that stores data read
622 * @retval interface status (MANDATORY: return 0 -> no Error)
623 *
624 */
lis331dlh_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)625 int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
626 {
627 int32_t ret;
628
629 ret = lis331dlh_read_reg(ctx, LIS331DLH_WHO_AM_I, buff, 1);
630
631 return ret;
632 }
633
634 /**
635 * @brief Reboot memory content. Reload the calibration parameters.[set]
636 *
637 * @param ctx read / write interface definitions(ptr)
638 * @param val change the values of boot in reg CTRL_REG2
639 * @retval interface status (MANDATORY: return 0 -> no Error)
640 *
641 */
lis331dlh_boot_set(stmdev_ctx_t * ctx,uint8_t val)642 int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
643 {
644 lis331dlh_ctrl_reg2_t ctrl_reg2;
645 int32_t ret;
646
647 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
648 (uint8_t *)&ctrl_reg2, 1);
649
650 if (ret == 0)
651 {
652 ctrl_reg2.boot = val;
653 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
654 (uint8_t *)&ctrl_reg2, 1);
655 }
656
657 return ret;
658 }
659
660 /**
661 * @brief Reboot memory content. Reload the calibration parameters.[get]
662 *
663 * @param ctx read / write interface definitions(ptr)
664 * @param val change the values of boot in reg CTRL_REG2
665 * @retval interface status (MANDATORY: return 0 -> no Error)
666 *
667 */
lis331dlh_boot_get(stmdev_ctx_t * ctx,uint8_t * val)668 int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
669 {
670 lis331dlh_ctrl_reg2_t ctrl_reg2;
671 int32_t ret;
672
673 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
674 (uint8_t *)&ctrl_reg2, 1);
675 *val = ctrl_reg2.boot;
676
677 return ret;
678 }
679
680 /**
681 * @brief Linear acceleration sensor self-test enable.[set]
682 *
683 * @param ctx read / write interface definitions(ptr)
684 * @param val change the values of st in reg CTRL_REG4
685 * @retval interface status (MANDATORY: return 0 -> no Error)
686 *
687 */
lis331dlh_self_test_set(stmdev_ctx_t * ctx,lis331dlh_st_t val)688 int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val)
689 {
690 lis331dlh_ctrl_reg4_t ctrl_reg4;
691 int32_t ret;
692
693 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
694 (uint8_t *)&ctrl_reg4, 1);
695
696 if (ret == 0)
697 {
698 ctrl_reg4.st = (uint8_t)val;
699 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
700 (uint8_t *)&ctrl_reg4, 1);
701 }
702
703 return ret;
704 }
705
706 /**
707 * @brief Linear acceleration sensor self-test enable.[get]
708 *
709 * @param ctx read / write interface definitions(ptr)
710 * @param val Get the values of st in reg CTRL_REG4
711 * @retval interface status (MANDATORY: return 0 -> no Error)
712 *
713 */
lis331dlh_self_test_get(stmdev_ctx_t * ctx,lis331dlh_st_t * val)714 int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx,
715 lis331dlh_st_t *val)
716 {
717 lis331dlh_ctrl_reg4_t ctrl_reg4;
718 int32_t ret;
719
720 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
721 (uint8_t *)&ctrl_reg4, 1);
722
723 switch (ctrl_reg4.st)
724 {
725 case LIS331DLH_ST_DISABLE:
726 *val = LIS331DLH_ST_DISABLE;
727 break;
728
729 case LIS331DLH_ST_POSITIVE:
730 *val = LIS331DLH_ST_POSITIVE;
731 break;
732
733 case LIS331DLH_ST_NEGATIVE:
734 *val = LIS331DLH_ST_NEGATIVE;
735 break;
736
737 default:
738 *val = LIS331DLH_ST_DISABLE;
739 break;
740 }
741
742 return ret;
743 }
744
745 /**
746 * @brief Big/Little Endian Data selection.[set]
747 *
748 * @param ctx read / write interface definitions(ptr)
749 * @param val change the values of ble in reg CTRL_REG4
750 * @retval interface status (MANDATORY: return 0 -> no Error)
751 *
752 */
lis331dlh_data_format_set(stmdev_ctx_t * ctx,lis331dlh_ble_t val)753 int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx,
754 lis331dlh_ble_t val)
755 {
756 lis331dlh_ctrl_reg4_t ctrl_reg4;
757 int32_t ret;
758
759 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
760 (uint8_t *)&ctrl_reg4, 1);
761
762 if (ret == 0)
763 {
764 ctrl_reg4.ble = (uint8_t)val;
765 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
766 (uint8_t *)&ctrl_reg4, 1);
767 }
768
769 return ret;
770 }
771
772 /**
773 * @brief Big/Little Endian Data selection.[get]
774 *
775 * @param ctx read / write interface definitions(ptr)
776 * @param val Get the values of ble in reg CTRL_REG4
777 * @retval interface status (MANDATORY: return 0 -> no Error)
778 *
779 */
lis331dlh_data_format_get(stmdev_ctx_t * ctx,lis331dlh_ble_t * val)780 int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx,
781 lis331dlh_ble_t *val)
782 {
783 lis331dlh_ctrl_reg4_t ctrl_reg4;
784 int32_t ret;
785
786 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
787 (uint8_t *)&ctrl_reg4, 1);
788
789 switch (ctrl_reg4.ble)
790 {
791 case LIS331DLH_LSB_AT_LOW_ADD:
792 *val = LIS331DLH_LSB_AT_LOW_ADD;
793 break;
794
795 case LIS331DLH_MSB_AT_LOW_ADD:
796 *val = LIS331DLH_MSB_AT_LOW_ADD;
797 break;
798
799 default:
800 *val = LIS331DLH_LSB_AT_LOW_ADD;
801 break;
802 }
803
804 return ret;
805 }
806
807 /**
808 * @}
809 *
810 */
811
812 /**
813 * @defgroup LIS331DLH_Filters
814 * @brief This section group all the functions concerning the
815 * filters configuration.
816 * @{
817 *
818 */
819
820 /**
821 * @brief High pass filter cut-off frequency configuration.[set]
822 *
823 * @param ctx read / write interface definitions(ptr)
824 * @param val change the values of hpcf in reg CTRL_REG2
825 * @retval interface status (MANDATORY: return 0 -> no Error)
826 *
827 */
lis331dlh_hp_bandwidth_set(stmdev_ctx_t * ctx,lis331dlh_hpcf_t val)828 int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx,
829 lis331dlh_hpcf_t val)
830 {
831 lis331dlh_ctrl_reg2_t ctrl_reg2;
832 int32_t ret;
833
834 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
835 (uint8_t *)&ctrl_reg2, 1);
836
837 if (ret == 0)
838 {
839 ctrl_reg2.hpcf = (uint8_t)val;
840 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
841 (uint8_t *)&ctrl_reg2, 1);
842 }
843
844 return ret;
845 }
846
847 /**
848 * @brief High pass filter cut-off frequency configuration.[get]
849 *
850 * @param ctx read / write interface definitions(ptr)
851 * @param val Get the values of hpcf in reg CTRL_REG2
852 * @retval interface status (MANDATORY: return 0 -> no Error)
853 *
854 */
lis331dlh_hp_bandwidth_get(stmdev_ctx_t * ctx,lis331dlh_hpcf_t * val)855 int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx,
856 lis331dlh_hpcf_t *val)
857 {
858 lis331dlh_ctrl_reg2_t ctrl_reg2;
859 int32_t ret;
860
861 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
862 (uint8_t *)&ctrl_reg2, 1);
863
864 switch (ctrl_reg2.hpcf)
865 {
866 case LIS331DLH_CUT_OFF_8Hz:
867 *val = LIS331DLH_CUT_OFF_8Hz;
868 break;
869
870 case LIS331DLH_CUT_OFF_16Hz:
871 *val = LIS331DLH_CUT_OFF_16Hz;
872 break;
873
874 case LIS331DLH_CUT_OFF_32Hz:
875 *val = LIS331DLH_CUT_OFF_32Hz;
876 break;
877
878 case LIS331DLH_CUT_OFF_64Hz:
879 *val = LIS331DLH_CUT_OFF_64Hz;
880 break;
881
882 default:
883 *val = LIS331DLH_CUT_OFF_8Hz;
884 break;
885 }
886
887 return ret;
888 }
889
890 /**
891 * @brief Select High Pass filter path.[set]
892 *
893 * @param ctx read / write interface definitions(ptr)
894 * @param val change the values of hpen in reg CTRL_REG2
895 * @retval interface status (MANDATORY: return 0 -> no Error)
896 *
897 */
lis331dlh_hp_path_set(stmdev_ctx_t * ctx,lis331dlh_hpen_t val)898 int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val)
899 {
900 lis331dlh_ctrl_reg2_t ctrl_reg2;
901 int32_t ret;
902
903 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
904 (uint8_t *)&ctrl_reg2, 1);
905
906 if (ret == 0)
907 {
908 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
909 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
910 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG2,
911 (uint8_t *)&ctrl_reg2, 1);
912 }
913
914 return ret;
915 }
916
917 /**
918 * @brief Select High Pass filter path.[get]
919 *
920 * @param ctx read / write interface definitions(ptr)
921 * @param val Get the values of hpen in reg CTRL_REG2
922 * @retval interface status (MANDATORY: return 0 -> no Error)
923 *
924 */
lis331dlh_hp_path_get(stmdev_ctx_t * ctx,lis331dlh_hpen_t * val)925 int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx,
926 lis331dlh_hpen_t *val)
927 {
928 lis331dlh_ctrl_reg2_t ctrl_reg2;
929 int32_t ret;
930
931 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2,
932 (uint8_t *)&ctrl_reg2, 1);
933
934 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
935 {
936 case LIS331DLH_HP_DISABLE:
937 *val = LIS331DLH_HP_DISABLE;
938 break;
939
940 case LIS331DLH_HP_ON_OUT:
941 *val = LIS331DLH_HP_ON_OUT;
942 break;
943
944 case LIS331DLH_HP_ON_INT1:
945 *val = LIS331DLH_HP_ON_INT1;
946 break;
947
948 case LIS331DLH_HP_ON_INT2:
949 *val = LIS331DLH_HP_ON_INT2;
950 break;
951
952 case LIS331DLH_HP_ON_INT1_INT2:
953 *val = LIS331DLH_HP_ON_INT1_INT2;
954 break;
955
956 case LIS331DLH_HP_ON_INT1_INT2_OUT:
957 *val = LIS331DLH_HP_ON_INT1_INT2_OUT;
958 break;
959
960 case LIS331DLH_HP_ON_INT2_OUT:
961 *val = LIS331DLH_HP_ON_INT2_OUT;
962 break;
963
964 case LIS331DLH_HP_ON_INT1_OUT:
965 *val = LIS331DLH_HP_ON_INT1_OUT;
966 break;
967
968 default:
969 *val = LIS331DLH_HP_DISABLE;
970 break;
971 }
972
973 return ret;
974 }
975
976 /**
977 * @brief Reading at this address zeroes instantaneously
978 * the content of the internal high pass-filter.
979 * If the high pass filter is enabled all three axes
980 * are instantaneously set to 0g. This allows to
981 * overcome the settling time of the high pass
982 * filter.[get]
983 *
984 * @param ctx read / write interface definitions(ptr)
985 * @retval interface status (MANDATORY: return 0 -> no Error)
986 *
987 */
lis331dlh_hp_reset_get(stmdev_ctx_t * ctx)988 int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx)
989 {
990 uint8_t dummy;
991 int32_t ret;
992
993 ret = lis331dlh_read_reg(ctx, LIS331DLH_HP_FILTER_RESET,
994 (uint8_t *)&dummy, 1);
995
996 return ret;
997 }
998
999 /**
1000 * @brief Reference value for high-pass filter.[set]
1001 *
1002 * @param ctx read / write interface definitions(ptr)
1003 * @param val change the values of ref in reg REFERENCE
1004 * @retval interface status (MANDATORY: return 0 -> no Error)
1005 *
1006 */
lis331dlh_hp_reference_value_set(stmdev_ctx_t * ctx,uint8_t val)1007 int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx,
1008 uint8_t val)
1009 {
1010 int32_t ret;
1011
1012 ret = lis331dlh_write_reg(ctx, LIS331DLH_REFERENCE, (uint8_t *)&val, 1);
1013
1014 return ret;
1015 }
1016
1017 /**
1018 * @brief Reference value for high-pass filter.[get]
1019 *
1020 * @param ctx read / write interface definitions(ptr)
1021 * @param val change the values of ref in reg REFERENCE
1022 * @retval interface status (MANDATORY: return 0 -> no Error)
1023 *
1024 */
lis331dlh_hp_reference_value_get(stmdev_ctx_t * ctx,uint8_t * val)1025 int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx,
1026 uint8_t *val)
1027 {
1028 int32_t ret;
1029
1030 ret = lis331dlh_read_reg(ctx, LIS331DLH_REFERENCE, val, 1);
1031
1032 return ret;
1033 }
1034
1035 /**
1036 * @}
1037 *
1038 */
1039
1040 /**
1041 * @defgroup LIS331DLH_Serial_Interface
1042 * @brief This section groups all the functions concerning serial
1043 * interface management.
1044 * @{
1045 *
1046 */
1047
1048 /**
1049 * @brief SPI 3- or 4-wire interface.[set]
1050 *
1051 * @param ctx read / write interface definitions(ptr)
1052 * @param val change the values of sim in reg CTRL_REG4
1053 * @retval interface status (MANDATORY: return 0 -> no Error)
1054 *
1055 */
lis331dlh_spi_mode_set(stmdev_ctx_t * ctx,lis331dlh_sim_t val)1056 int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val)
1057 {
1058 lis331dlh_ctrl_reg4_t ctrl_reg4;
1059 int32_t ret;
1060
1061 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
1062 (uint8_t *)&ctrl_reg4, 1);
1063
1064 if (ret == 0)
1065 {
1066 ctrl_reg4.sim = (uint8_t)val;
1067 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG4,
1068 (uint8_t *)&ctrl_reg4, 1);
1069 }
1070
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief SPI 3- or 4-wire interface.[get]
1076 *
1077 * @param ctx read / write interface definitions(ptr)
1078 * @param val Get the values of sim in reg CTRL_REG4
1079 * @retval interface status (MANDATORY: return 0 -> no Error)
1080 *
1081 */
lis331dlh_spi_mode_get(stmdev_ctx_t * ctx,lis331dlh_sim_t * val)1082 int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx,
1083 lis331dlh_sim_t *val)
1084 {
1085 lis331dlh_ctrl_reg4_t ctrl_reg4;
1086 int32_t ret;
1087
1088 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4,
1089 (uint8_t *)&ctrl_reg4, 1);
1090
1091 switch (ctrl_reg4.sim)
1092 {
1093 case LIS331DLH_SPI_4_WIRE:
1094 *val = LIS331DLH_SPI_4_WIRE;
1095 break;
1096
1097 case LIS331DLH_SPI_3_WIRE:
1098 *val = LIS331DLH_SPI_3_WIRE;
1099 break;
1100
1101 default:
1102 *val = LIS331DLH_SPI_4_WIRE;
1103 break;
1104 }
1105
1106 return ret;
1107 }
1108
1109 /**
1110 * @}
1111 *
1112 */
1113
1114 /**
1115 * @defgroup LIS331DLH_Interrupt_Pins
1116 * @brief This section groups all the functions that manage
1117 * interrupt pins.
1118 * @{
1119 *
1120 */
1121
1122 /**
1123 * @brief Data signal on INT 1 pad control bits.[set]
1124 *
1125 * @param ctx read / write interface definitions(ptr)
1126 * @param val change the values of i1_cfg in reg CTRL_REG3
1127 * @retval interface status (MANDATORY: return 0 -> no Error)
1128 *
1129 */
lis331dlh_pin_int1_route_set(stmdev_ctx_t * ctx,lis331dlh_i1_cfg_t val)1130 int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx,
1131 lis331dlh_i1_cfg_t val)
1132 {
1133 lis331dlh_ctrl_reg3_t ctrl_reg3;
1134 int32_t ret;
1135
1136 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1137 (uint8_t *)&ctrl_reg3, 1);
1138
1139 if (ret == 0)
1140 {
1141 ctrl_reg3.i1_cfg = (uint8_t)val;
1142 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1143 (uint8_t *)&ctrl_reg3, 1);
1144 }
1145
1146 return ret;
1147 }
1148
1149 /**
1150 * @brief Data signal on INT 1 pad control bits.[get]
1151 *
1152 * @param ctx read / write interface definitions(ptr)
1153 * @param val Get the values of i1_cfg in reg CTRL_REG3
1154 * @retval interface status (MANDATORY: return 0 -> no Error)
1155 *
1156 */
lis331dlh_pin_int1_route_get(stmdev_ctx_t * ctx,lis331dlh_i1_cfg_t * val)1157 int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx,
1158 lis331dlh_i1_cfg_t *val)
1159 {
1160 lis331dlh_ctrl_reg3_t ctrl_reg3;
1161 int32_t ret;
1162
1163 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1164 (uint8_t *)&ctrl_reg3, 1);
1165
1166 switch (ctrl_reg3.i1_cfg)
1167 {
1168 case LIS331DLH_PAD1_INT1_SRC:
1169 *val = LIS331DLH_PAD1_INT1_SRC;
1170 break;
1171
1172 case LIS331DLH_PAD1_INT1_OR_INT2_SRC:
1173 *val = LIS331DLH_PAD1_INT1_OR_INT2_SRC;
1174 break;
1175
1176 case LIS331DLH_PAD1_DRDY:
1177 *val = LIS331DLH_PAD1_DRDY;
1178 break;
1179
1180 case LIS331DLH_PAD1_BOOT:
1181 *val = LIS331DLH_PAD1_BOOT;
1182 break;
1183
1184 default:
1185 *val = LIS331DLH_PAD1_INT1_SRC;
1186 break;
1187 }
1188
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1194 * register cleared by reading INT1_SRC register.[set]
1195 *
1196 * @param ctx read / write interface definitions(ptr)
1197 * @param val change the values of lir1 in reg CTRL_REG3
1198 * @retval interface status (MANDATORY: return 0 -> no Error)
1199 *
1200 */
lis331dlh_int1_notification_set(stmdev_ctx_t * ctx,lis331dlh_lir1_t val)1201 int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx,
1202 lis331dlh_lir1_t val)
1203 {
1204 lis331dlh_ctrl_reg3_t ctrl_reg3;
1205 int32_t ret;
1206
1207 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1208 (uint8_t *)&ctrl_reg3, 1);
1209
1210 if (ret == 0)
1211 {
1212 ctrl_reg3.lir1 = (uint8_t)val;
1213 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1214 (uint8_t *)&ctrl_reg3, 1);
1215 }
1216
1217 return ret;
1218 }
1219
1220 /**
1221 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1222 * register cleared by reading INT1_SRC register.[get]
1223 *
1224 * @param ctx read / write interface definitions(ptr)
1225 * @param val Get the values of lir1 in reg CTRL_REG3
1226 * @retval interface status (MANDATORY: return 0 -> no Error)
1227 *
1228 */
lis331dlh_int1_notification_get(stmdev_ctx_t * ctx,lis331dlh_lir1_t * val)1229 int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx,
1230 lis331dlh_lir1_t *val)
1231 {
1232 lis331dlh_ctrl_reg3_t ctrl_reg3;
1233 int32_t ret;
1234
1235 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1236 (uint8_t *)&ctrl_reg3, 1);
1237
1238 switch (ctrl_reg3.lir1)
1239 {
1240 case LIS331DLH_INT1_PULSED:
1241 *val = LIS331DLH_INT1_PULSED;
1242 break;
1243
1244 case LIS331DLH_INT1_LATCHED:
1245 *val = LIS331DLH_INT1_LATCHED;
1246 break;
1247
1248 default:
1249 *val = LIS331DLH_INT1_PULSED;
1250 break;
1251 }
1252
1253 return ret;
1254 }
1255
1256 /**
1257 * @brief Data signal on INT 2 pad control bits.[set]
1258 *
1259 * @param ctx read / write interface definitions(ptr)
1260 * @param val change the values of i2_cfg in reg CTRL_REG3
1261 * @retval interface status (MANDATORY: return 0 -> no Error)
1262 *
1263 */
lis331dlh_pin_int2_route_set(stmdev_ctx_t * ctx,lis331dlh_i2_cfg_t val)1264 int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx,
1265 lis331dlh_i2_cfg_t val)
1266 {
1267 lis331dlh_ctrl_reg3_t ctrl_reg3;
1268 int32_t ret;
1269
1270 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1271 (uint8_t *)&ctrl_reg3, 1);
1272
1273 if (ret == 0)
1274 {
1275 ctrl_reg3.i2_cfg = (uint8_t)val;
1276 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1277 (uint8_t *)&ctrl_reg3, 1);
1278 }
1279
1280 return ret;
1281 }
1282
1283 /**
1284 * @brief Data signal on INT 2 pad control bits.[get]
1285 *
1286 * @param ctx read / write interface definitions(ptr)
1287 * @param val Get the values of i2_cfg in reg CTRL_REG3
1288 * @retval interface status (MANDATORY: return 0 -> no Error)
1289 *
1290 */
lis331dlh_pin_int2_route_get(stmdev_ctx_t * ctx,lis331dlh_i2_cfg_t * val)1291 int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx,
1292 lis331dlh_i2_cfg_t *val)
1293 {
1294 lis331dlh_ctrl_reg3_t ctrl_reg3;
1295 int32_t ret;
1296
1297 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1298 (uint8_t *)&ctrl_reg3, 1);
1299
1300 switch (ctrl_reg3.i2_cfg)
1301 {
1302 case LIS331DLH_PAD2_INT2_SRC:
1303 *val = LIS331DLH_PAD2_INT2_SRC;
1304 break;
1305
1306 case LIS331DLH_PAD2_INT1_OR_INT2_SRC:
1307 *val = LIS331DLH_PAD2_INT1_OR_INT2_SRC;
1308 break;
1309
1310 case LIS331DLH_PAD2_DRDY:
1311 *val = LIS331DLH_PAD2_DRDY;
1312 break;
1313
1314 case LIS331DLH_PAD2_BOOT:
1315 *val = LIS331DLH_PAD2_BOOT;
1316 break;
1317
1318 default:
1319 *val = LIS331DLH_PAD2_INT2_SRC;
1320 break;
1321 }
1322
1323 return ret;
1324 }
1325
1326 /**
1327 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1328 * register cleared by reading INT2_SRC itself.[set]
1329 *
1330 * @param ctx read / write interface definitions(ptr)
1331 * @param val change the values of lir2 in reg CTRL_REG3
1332 * @retval interface status (MANDATORY: return 0 -> no Error)
1333 *
1334 */
lis331dlh_int2_notification_set(stmdev_ctx_t * ctx,lis331dlh_lir2_t val)1335 int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx,
1336 lis331dlh_lir2_t val)
1337 {
1338 lis331dlh_ctrl_reg3_t ctrl_reg3;
1339 int32_t ret;
1340
1341 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1342 (uint8_t *)&ctrl_reg3, 1);
1343
1344 if (ret == 0)
1345 {
1346 ctrl_reg3.lir2 = (uint8_t)val;
1347 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1348 (uint8_t *)&ctrl_reg3, 1);
1349 }
1350
1351 return ret;
1352 }
1353
1354 /**
1355 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1356 * register cleared by reading INT2_SRC itself.[get]
1357 *
1358 * @param ctx read / write interface definitions(ptr)
1359 * @param val Get the values of lir2 in reg CTRL_REG3
1360 * @retval interface status (MANDATORY: return 0 -> no Error)
1361 *
1362 */
lis331dlh_int2_notification_get(stmdev_ctx_t * ctx,lis331dlh_lir2_t * val)1363 int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx,
1364 lis331dlh_lir2_t *val)
1365 {
1366 lis331dlh_ctrl_reg3_t ctrl_reg3;
1367 int32_t ret;
1368
1369 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1370 (uint8_t *)&ctrl_reg3, 1);
1371
1372 switch (ctrl_reg3.lir2)
1373 {
1374 case LIS331DLH_INT2_PULSED:
1375 *val = LIS331DLH_INT2_PULSED;
1376 break;
1377
1378 case LIS331DLH_INT2_LATCHED:
1379 *val = LIS331DLH_INT2_LATCHED;
1380 break;
1381
1382 default:
1383 *val = LIS331DLH_INT2_PULSED;
1384 break;
1385 }
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * @brief Push-pull/open drain selection on interrupt pads.[set]
1392 *
1393 * @param ctx read / write interface definitions(ptr)
1394 * @param val change the values of pp_od in reg CTRL_REG3
1395 * @retval interface status (MANDATORY: return 0 -> no Error)
1396 *
1397 */
lis331dlh_pin_mode_set(stmdev_ctx_t * ctx,lis331dlh_pp_od_t val)1398 int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx,
1399 lis331dlh_pp_od_t val)
1400 {
1401 lis331dlh_ctrl_reg3_t ctrl_reg3;
1402 int32_t ret;
1403
1404 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1405 (uint8_t *)&ctrl_reg3, 1);
1406
1407 if (ret == 0)
1408 {
1409 ctrl_reg3.pp_od = (uint8_t)val;
1410 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1411 (uint8_t *)&ctrl_reg3, 1);
1412 }
1413
1414 return ret;
1415 }
1416
1417 /**
1418 * @brief Push-pull/open drain selection on interrupt pads.[get]
1419 *
1420 * @param ctx read / write interface definitions(ptr)
1421 * @param val Get the values of pp_od in reg CTRL_REG3
1422 * @retval interface status (MANDATORY: return 0 -> no Error)
1423 *
1424 */
lis331dlh_pin_mode_get(stmdev_ctx_t * ctx,lis331dlh_pp_od_t * val)1425 int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx,
1426 lis331dlh_pp_od_t *val)
1427 {
1428 lis331dlh_ctrl_reg3_t ctrl_reg3;
1429 int32_t ret;
1430
1431 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1432 (uint8_t *)&ctrl_reg3, 1);
1433
1434 switch (ctrl_reg3.pp_od)
1435 {
1436 case LIS331DLH_PUSH_PULL:
1437 *val = LIS331DLH_PUSH_PULL;
1438 break;
1439
1440 case LIS331DLH_OPEN_DRAIN:
1441 *val = LIS331DLH_OPEN_DRAIN;
1442 break;
1443
1444 default:
1445 *val = LIS331DLH_PUSH_PULL;
1446 break;
1447 }
1448
1449 return ret;
1450 }
1451
1452 /**
1453 * @brief Interrupt active-high/low.[set]
1454 *
1455 * @param ctx read / write interface definitions(ptr)
1456 * @param val change the values of ihl in reg CTRL_REG3
1457 * @retval interface status (MANDATORY: return 0 -> no Error)
1458 *
1459 */
lis331dlh_pin_polarity_set(stmdev_ctx_t * ctx,lis331dlh_ihl_t val)1460 int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx,
1461 lis331dlh_ihl_t val)
1462 {
1463 lis331dlh_ctrl_reg3_t ctrl_reg3;
1464 int32_t ret;
1465
1466 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1467 (uint8_t *)&ctrl_reg3, 1);
1468
1469 if (ret == 0)
1470 {
1471 ctrl_reg3.ihl = (uint8_t)val;
1472 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG3,
1473 (uint8_t *)&ctrl_reg3, 1);
1474 }
1475
1476 return ret;
1477 }
1478
1479 /**
1480 * @brief Interrupt active-high/low.[get]
1481 *
1482 * @param ctx read / write interface definitions(ptr)
1483 * @param val Get the values of ihl in reg CTRL_REG3
1484 * @retval interface status (MANDATORY: return 0 -> no Error)
1485 *
1486 */
lis331dlh_pin_polarity_get(stmdev_ctx_t * ctx,lis331dlh_ihl_t * val)1487 int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx,
1488 lis331dlh_ihl_t *val)
1489 {
1490 lis331dlh_ctrl_reg3_t ctrl_reg3;
1491 int32_t ret;
1492
1493 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3,
1494 (uint8_t *)&ctrl_reg3, 1);
1495
1496 switch (ctrl_reg3.ihl)
1497 {
1498 case LIS331DLH_ACTIVE_HIGH:
1499 *val = LIS331DLH_ACTIVE_HIGH;
1500 break;
1501
1502 case LIS331DLH_ACTIVE_LOW:
1503 *val = LIS331DLH_ACTIVE_LOW;
1504 break;
1505
1506 default:
1507 *val = LIS331DLH_ACTIVE_HIGH;
1508 break;
1509 }
1510
1511 return ret;
1512 }
1513
1514 /**
1515 * @}
1516 *
1517 */
1518
1519 /**
1520 * @defgroup LIS331DLH_interrupt_on_threshold
1521 * @brief This section groups all the functions that manage
1522 * the interrupt on threshold event generation.
1523 * @{
1524 *
1525 */
1526
1527 /**
1528 * @brief Configure the interrupt 1 threshold sign.[set]
1529 *
1530 * @param ctx read / write interface definitions(ptr)
1531 * @param val enable sign and axis for interrupt on threshold
1532 * @retval interface status (MANDATORY: return 0 -> no Error)
1533 *
1534 */
lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t * ctx,int1_on_th_conf_t val)1535 int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
1536 int1_on_th_conf_t val)
1537 {
1538 lis331dlh_int1_cfg_t int1_cfg;
1539 int32_t ret;
1540
1541 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1542 (uint8_t *)&int1_cfg, 1);
1543
1544 if (ret == 0)
1545 {
1546 int1_cfg.xlie = val.int1_xlie;
1547 int1_cfg.xhie = val.int1_xhie;
1548 int1_cfg.ylie = val.int1_ylie;
1549 int1_cfg.yhie = val.int1_yhie;
1550 int1_cfg.zlie = val.int1_zlie;
1551 int1_cfg.zhie = val.int1_zhie;
1552 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
1553 (uint8_t *)&int1_cfg, 1);
1554 }
1555
1556 return ret;
1557 }
1558
1559 /**
1560 * @brief Configure the interrupt 1 threshold sign.[get]
1561 *
1562 * @param ctx read / write interface definitions(ptr)
1563 * @param val enable sign and axis for interrupt on threshold
1564 * @retval interface status (MANDATORY: return 0 -> no Error)
1565 *
1566 */
lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t * ctx,int1_on_th_conf_t * val)1567 int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
1568 int1_on_th_conf_t *val)
1569 {
1570 lis331dlh_int1_cfg_t int1_cfg;
1571 int32_t ret;
1572
1573 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1574 (uint8_t *)&int1_cfg, 1);
1575 val->int1_xlie = int1_cfg.xlie;
1576 val->int1_xhie = int1_cfg.xhie;
1577 val->int1_ylie = int1_cfg.ylie;
1578 val->int1_yhie = int1_cfg.yhie;
1579 val->int1_zlie = int1_cfg.zlie;
1580 val->int1_zhie = int1_cfg.zhie;
1581
1582 return ret;
1583 }
1584
1585 /**
1586 * @brief AND/OR combination of Interrupt 1 events.[set]
1587 *
1588 * @param ctx read / write interface definitions(ptr)
1589 * @param val change the values of aoi in reg INT1_CFG
1590 * @retval interface status (MANDATORY: return 0 -> no Error)
1591 *
1592 */
lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t * ctx,lis331dlh_int1_aoi_t val)1593 int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
1594 lis331dlh_int1_aoi_t val)
1595 {
1596 lis331dlh_int1_cfg_t int1_cfg;
1597 int32_t ret;
1598
1599 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1600 (uint8_t *)&int1_cfg, 1);
1601
1602 if (ret == 0)
1603 {
1604 int1_cfg.aoi = (uint8_t) val;
1605 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
1606 (uint8_t *)&int1_cfg, 1);
1607 }
1608
1609 return ret;
1610 }
1611
1612 /**
1613 * @brief AND/OR combination of Interrupt 1 events.[get]
1614 *
1615 * @param ctx read / write interface definitions(ptr)
1616 * @param val Get the values of aoi in reg INT1_CFG
1617 * @retval interface status (MANDATORY: return 0 -> no Error)
1618 *
1619 */
lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t * ctx,lis331dlh_int1_aoi_t * val)1620 int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
1621 lis331dlh_int1_aoi_t *val)
1622 {
1623 lis331dlh_int1_cfg_t int1_cfg;
1624 int32_t ret;
1625
1626 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
1627 (uint8_t *)&int1_cfg, 1);
1628
1629 switch (int1_cfg.aoi)
1630 {
1631 case LIS331DLH_INT1_ON_THRESHOLD_OR:
1632 *val = LIS331DLH_INT1_ON_THRESHOLD_OR;
1633 break;
1634
1635 case LIS331DLH_INT1_ON_THRESHOLD_AND:
1636 *val = LIS331DLH_INT1_ON_THRESHOLD_AND;
1637 break;
1638
1639 default:
1640 *val = LIS331DLH_INT1_ON_THRESHOLD_OR;
1641 break;
1642 }
1643
1644 return ret;
1645 }
1646
1647 /**
1648 * @brief Interrupt generator 1 on threshold source register.[get]
1649 *
1650 * @param ctx read / write interface definitions(ptr)
1651 * @param val registers INT1_SRC
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lis331dlh_int1_src_get(stmdev_ctx_t * ctx,lis331dlh_int1_src_t * val)1655 int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx,
1656 lis331dlh_int1_src_t *val)
1657 {
1658 int32_t ret;
1659
1660 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
1661
1662 return ret;
1663 }
1664
1665 /**
1666 * @brief Interrupt 1 threshold.[set]
1667 *
1668 * @param ctx read / write interface definitions(ptr)
1669 * @param val change the values of ths in reg INT1_THS
1670 * @retval interface status (MANDATORY: return 0 -> no Error)
1671 *
1672 */
lis331dlh_int1_treshold_set(stmdev_ctx_t * ctx,uint8_t val)1673 int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
1674 {
1675 lis331dlh_int1_ths_t int1_ths;
1676 int32_t ret;
1677
1678 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
1679 (uint8_t *)&int1_ths, 1);
1680
1681 if (ret == 0)
1682 {
1683 int1_ths.ths = val;
1684 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
1685 (uint8_t *)&int1_ths, 1);
1686 }
1687
1688 return ret;
1689 }
1690
1691 /**
1692 * @brief Interrupt 1 threshold.[get]
1693 *
1694 * @param ctx read / write interface definitions(ptr)
1695 * @param val change the values of ths in reg INT1_THS
1696 * @retval interface status (MANDATORY: return 0 -> no Error)
1697 *
1698 */
lis331dlh_int1_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)1699 int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1700 {
1701 lis331dlh_int1_ths_t int1_ths;
1702 int32_t ret;
1703
1704 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
1705 (uint8_t *)&int1_ths, 1);
1706 *val = int1_ths.ths;
1707
1708 return ret;
1709 }
1710
1711 /**
1712 * @brief Duration value for interrupt 1 generator.[set]
1713 *
1714 * @param ctx read / write interface definitions(ptr)
1715 * @param val change the values of d in reg INT1_DURATION
1716 * @retval interface status (MANDATORY: return 0 -> no Error)
1717 *
1718 */
lis331dlh_int1_dur_set(stmdev_ctx_t * ctx,uint8_t val)1719 int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1720 {
1721 lis331dlh_int1_duration_t int1_duration;
1722 int32_t ret;
1723
1724 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
1725 (uint8_t *)&int1_duration, 1);
1726
1727 if (ret == 0)
1728 {
1729 int1_duration.d = val;
1730 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_DURATION,
1731 (uint8_t *)&int1_duration, 1);
1732 }
1733
1734 return ret;
1735 }
1736
1737 /**
1738 * @brief Duration value for interrupt 1 generator.[get]
1739 *
1740 * @param ctx read / write interface definitions(ptr)
1741 * @param val change the values of d in reg INT1_DURATION
1742 * @retval interface status (MANDATORY: return 0 -> no Error)
1743 *
1744 */
lis331dlh_int1_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1745 int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1746 {
1747 lis331dlh_int1_duration_t int1_duration;
1748 int32_t ret;
1749
1750 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION,
1751 (uint8_t *)&int1_duration, 1);
1752 *val = int1_duration.d;
1753
1754 return ret;
1755 }
1756
1757 /**
1758 * @brief Configure the interrupt 2 threshold sign.[set]
1759 *
1760 * @param ctx read / write interface definitions(ptr)
1761 * @param val enable sign and axis for interrupt on threshold
1762 * @retval interface status (MANDATORY: return 0 -> no Error)
1763 *
1764 */
lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t * ctx,int2_on_th_conf_t val)1765 int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
1766 int2_on_th_conf_t val)
1767 {
1768 lis331dlh_int2_cfg_t int2_cfg;
1769 int32_t ret;
1770
1771 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1772 (uint8_t *)&int2_cfg, 1);
1773
1774 if (ret == 0)
1775 {
1776 int2_cfg.xlie = val.int2_xlie;
1777 int2_cfg.xhie = val.int2_xhie;
1778 int2_cfg.ylie = val.int2_ylie;
1779 int2_cfg.yhie = val.int2_yhie;
1780 int2_cfg.zlie = val.int2_zlie;
1781 int2_cfg.zhie = val.int2_zhie;
1782 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
1783 (uint8_t *)&int2_cfg, 1);
1784 }
1785
1786 return ret;
1787 }
1788
1789 /**
1790 * @brief Configure the interrupt 2 threshold sign.[get]
1791 *
1792 * @param ctx read / write interface definitions(ptr)
1793 * @param val enable sign and axis for interrupt on threshold
1794 * @retval interface status (MANDATORY: return 0 -> no Error)
1795 *
1796 */
lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t * ctx,int2_on_th_conf_t * val)1797 int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
1798 int2_on_th_conf_t *val)
1799 {
1800 lis331dlh_int2_cfg_t int2_cfg;
1801 int32_t ret;
1802
1803 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1804 (uint8_t *)&int2_cfg, 1);
1805 val->int2_xlie = int2_cfg.xlie;
1806 val->int2_xhie = int2_cfg.xhie;
1807 val->int2_ylie = int2_cfg.ylie;
1808 val->int2_yhie = int2_cfg.yhie;
1809 val->int2_zlie = int2_cfg.zlie;
1810 val->int2_zhie = int2_cfg.zhie;
1811
1812 return ret;
1813 }
1814
1815 /**
1816 * @brief AND/OR combination of Interrupt 2 events.[set]
1817 *
1818 * @param ctx read / write interface definitions(ptr)
1819 * @param val change the values of aoi in reg INT2_CFG
1820 * @retval interface status (MANDATORY: return 0 -> no Error)
1821 *
1822 */
lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t * ctx,lis331dlh_int2_aoi_t val)1823 int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
1824 lis331dlh_int2_aoi_t val)
1825 {
1826 lis331dlh_int2_cfg_t int2_cfg;
1827 int32_t ret;
1828
1829 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1830 (uint8_t *)&int2_cfg, 1);
1831
1832 if (ret == 0)
1833 {
1834 int2_cfg.aoi = (uint8_t) val;
1835 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
1836 (uint8_t *)&int2_cfg, 1);
1837 }
1838
1839 return ret;
1840 }
1841
1842 /**
1843 * @brief AND/OR combination of Interrupt 2 events.[get]
1844 *
1845 * @param ctx read / write interface definitions(ptr)
1846 * @param val Get the values of aoi in reg INT2_CFG
1847 * @retval interface status (MANDATORY: return 0 -> no Error)
1848 *
1849 */
lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t * ctx,lis331dlh_int2_aoi_t * val)1850 int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
1851 lis331dlh_int2_aoi_t *val)
1852 {
1853 lis331dlh_int2_cfg_t int2_cfg;
1854 int32_t ret;
1855
1856 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
1857 (uint8_t *)&int2_cfg, 1);
1858
1859 switch (int2_cfg.aoi)
1860 {
1861 case LIS331DLH_INT2_ON_THRESHOLD_OR:
1862 *val = LIS331DLH_INT2_ON_THRESHOLD_OR;
1863 break;
1864
1865 case LIS331DLH_INT2_ON_THRESHOLD_AND:
1866 *val = LIS331DLH_INT2_ON_THRESHOLD_AND;
1867 break;
1868
1869 default:
1870 *val = LIS331DLH_INT2_ON_THRESHOLD_OR;
1871 break;
1872 }
1873
1874 return ret;
1875 }
1876
1877 /**
1878 * @brief Interrupt generator 1 on threshold source register.[get]
1879 *
1880 * @param ctx read / write interface definitions(ptr)
1881 * @param val registers INT2_SRC
1882 * @retval interface status (MANDATORY: return 0 -> no Error)
1883 *
1884 */
lis331dlh_int2_src_get(stmdev_ctx_t * ctx,lis331dlh_int2_src_t * val)1885 int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx,
1886 lis331dlh_int2_src_t *val)
1887 {
1888 int32_t ret;
1889
1890 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
1891
1892 return ret;
1893 }
1894
1895 /**
1896 * @brief Interrupt 2 threshold.[set]
1897 *
1898 * @param ctx read / write interface definitions(ptr)
1899 * @param val change the values of ths in reg INT2_THS
1900 * @retval interface status (MANDATORY: return 0 -> no Error)
1901 *
1902 */
lis331dlh_int2_treshold_set(stmdev_ctx_t * ctx,uint8_t val)1903 int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
1904 {
1905 lis331dlh_int2_ths_t int2_ths;
1906 int32_t ret;
1907
1908 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
1909 (uint8_t *)&int2_ths, 1);
1910
1911 if (ret == 0)
1912 {
1913 int2_ths.ths = val;
1914 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
1915 (uint8_t *)&int2_ths, 1);
1916 }
1917
1918 return ret;
1919 }
1920
1921 /**
1922 * @brief Interrupt 2 threshold.[get]
1923 *
1924 * @param ctx read / write interface definitions(ptr)
1925 * @param val change the values of ths in reg INT2_THS
1926 * @retval interface status (MANDATORY: return 0 -> no Error)
1927 *
1928 */
lis331dlh_int2_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)1929 int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1930 {
1931 lis331dlh_int2_ths_t int2_ths;
1932 int32_t ret;
1933
1934 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
1935 (uint8_t *)&int2_ths, 1);
1936 *val = int2_ths.ths;
1937
1938 return ret;
1939 }
1940
1941 /**
1942 * @brief Duration value for interrupt 2 generator.[set]
1943 *
1944 * @param ctx read / write interface definitions(ptr)
1945 * @param val change the values of d in reg INT2_DURATION
1946 * @retval interface status (MANDATORY: return 0 -> no Error)
1947 *
1948 */
lis331dlh_int2_dur_set(stmdev_ctx_t * ctx,uint8_t val)1949 int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1950 {
1951 lis331dlh_int2_duration_t int2_duration;
1952 int32_t ret;
1953
1954 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
1955 (uint8_t *)&int2_duration, 1);
1956
1957 if (ret == 0)
1958 {
1959 int2_duration.d = val;
1960 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_DURATION,
1961 (uint8_t *)&int2_duration, 1);
1962 }
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @brief Duration value for interrupt 2 generator.[get]
1969 *
1970 * @param ctx read / write interface definitions(ptr)
1971 * @param val change the values of d in reg INT2_DURATION
1972 * @retval interface status (MANDATORY: return 0 -> no Error)
1973 *
1974 */
lis331dlh_int2_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1975 int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1976 {
1977 lis331dlh_int2_duration_t int2_duration;
1978 int32_t ret;
1979
1980 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION,
1981 (uint8_t *)&int2_duration, 1);
1982 *val = int2_duration.d;
1983
1984 return ret;
1985 }
1986
1987 /**
1988 * @}
1989 *
1990 */
1991
1992 /**
1993 * @defgroup LIS331DLH_Wake_Up_Event
1994 * @brief This section groups all the functions that manage the
1995 * Wake Up event generation.
1996 * @{
1997 *
1998 */
1999
2000 /**
2001 * @brief Turn-on mode selection for sleep to wake function.[set]
2002 *
2003 * @param ctx read / write interface definitions(ptr)
2004 * @param val change the values of turnon in reg CTRL_REG5
2005 * @retval interface status (MANDATORY: return 0 -> no Error)
2006 *
2007 */
lis331dlh_wkup_to_sleep_set(stmdev_ctx_t * ctx,uint8_t val)2008 int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
2009 {
2010 lis331dlh_ctrl_reg5_t ctrl_reg5;
2011 int32_t ret;
2012
2013 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
2014 (uint8_t *)&ctrl_reg5, 1);
2015
2016 if (ret == 0)
2017 {
2018 ctrl_reg5.turnon = val;
2019 ret = lis331dlh_write_reg(ctx, LIS331DLH_CTRL_REG5,
2020 (uint8_t *)&ctrl_reg5, 1);
2021 }
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @brief Turn-on mode selection for sleep to wake function.[get]
2028 *
2029 * @param ctx read / write interface definitions(ptr)
2030 * @param val change the values of turnon in reg CTRL_REG5
2031 * @retval interface status (MANDATORY: return 0 -> no Error)
2032 *
2033 */
lis331dlh_wkup_to_sleep_get(stmdev_ctx_t * ctx,uint8_t * val)2034 int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
2035 {
2036 lis331dlh_ctrl_reg5_t ctrl_reg5;
2037 int32_t ret;
2038
2039 ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5,
2040 (uint8_t *)&ctrl_reg5, 1);
2041 *val = ctrl_reg5.turnon;
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @}
2048 *
2049 */
2050
2051 /**
2052 * @defgroup LIS331DLH_Six_Position_Detection
2053 * @brief This section groups all the functions concerning six
2054 * position detection (6D).
2055 * @{
2056 *
2057 */
2058
2059 /**
2060 * @brief Configure the 6d on interrupt 1 generator.[set]
2061 *
2062 * @param ctx read / write interface definitions(ptr)
2063 * @param val change the values of 6d in reg INT1_CFG
2064 * @retval interface status (MANDATORY: return 0 -> no Error)
2065 *
2066 */
lis331dlh_int1_6d_mode_set(stmdev_ctx_t * ctx,lis331dlh_int1_6d_t val)2067 int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx,
2068 lis331dlh_int1_6d_t val)
2069 {
2070 lis331dlh_int1_cfg_t int1_cfg;
2071 int32_t ret;
2072
2073 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
2074 (uint8_t *)&int1_cfg, 1);
2075
2076 if (ret == 0)
2077 {
2078 int1_cfg._6d = (uint8_t)val & 0x01U;
2079 int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2080 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_CFG,
2081 (uint8_t *)&int1_cfg, 1);
2082 }
2083
2084 return ret;
2085 }
2086
2087 /**
2088 * @brief Configure the 6d on interrupt 1 generator.[get]
2089 *
2090 * @param ctx read / write interface definitions(ptr)
2091 * @param val Get the values of 6d in reg INT1_CFG
2092 * @retval interface status (MANDATORY: return 0 -> no Error)
2093 *
2094 */
lis331dlh_int1_6d_mode_get(stmdev_ctx_t * ctx,lis331dlh_int1_6d_t * val)2095 int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx,
2096 lis331dlh_int1_6d_t *val)
2097 {
2098 lis331dlh_int1_cfg_t int1_cfg;
2099 int32_t ret;
2100
2101 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG,
2102 (uint8_t *)&int1_cfg, 1);
2103
2104 switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
2105 {
2106 case LIS331DLH_6D_INT1_DISABLE:
2107 *val = LIS331DLH_6D_INT1_DISABLE;
2108 break;
2109
2110 case LIS331DLH_6D_INT1_MOVEMENT:
2111 *val = LIS331DLH_6D_INT1_MOVEMENT;
2112 break;
2113
2114 case LIS331DLH_6D_INT1_POSITION:
2115 *val = LIS331DLH_6D_INT1_POSITION;
2116 break;
2117
2118 default:
2119 *val = LIS331DLH_6D_INT1_DISABLE;
2120 break;
2121 }
2122
2123 return ret;
2124 }
2125
2126 /**
2127 * @brief 6D on interrupt generator 1 source register.[get]
2128 *
2129 * @param ctx read / write interface definitions(ptr)
2130 * @param val registers INT1_SRC
2131 * @retval interface status (MANDATORY: return 0 -> no Error)
2132 *
2133 */
lis331dlh_int1_6d_src_get(stmdev_ctx_t * ctx,lis331dlh_int1_src_t * val)2134 int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx,
2135 lis331dlh_int1_src_t *val)
2136 {
2137 int32_t ret;
2138
2139 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_SRC, (uint8_t *) val, 1);
2140
2141 return ret;
2142 }
2143
2144 /**
2145 * @brief Interrupt 1 threshold.[set]
2146 *
2147 * @param ctx read / write interface definitions(ptr)
2148 * @param val change the values of ths in reg INT1_THS
2149 * @retval interface status (MANDATORY: return 0 -> no Error)
2150 *
2151 */
lis331dlh_int1_6d_treshold_set(stmdev_ctx_t * ctx,uint8_t val)2152 int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
2153 {
2154 lis331dlh_int1_ths_t int1_ths;
2155 int32_t ret;
2156
2157 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
2158 (uint8_t *)&int1_ths, 1);
2159
2160 if (ret == 0)
2161 {
2162 int1_ths.ths = val;
2163 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT1_THS,
2164 (uint8_t *)&int1_ths, 1);
2165 }
2166
2167 return ret;
2168 }
2169
2170 /**
2171 * @brief Interrupt 1 threshold.[get]
2172 *
2173 * @param ctx read / write interface definitions(ptr)
2174 * @param val change the values of ths in reg INT1_THS
2175 * @retval interface status (MANDATORY: return 0 -> no Error)
2176 *
2177 */
lis331dlh_int1_6d_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)2178 int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx,
2179 uint8_t *val)
2180 {
2181 lis331dlh_int1_ths_t int1_ths;
2182 int32_t ret;
2183
2184 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS,
2185 (uint8_t *)&int1_ths, 1);
2186 *val = int1_ths.ths;
2187
2188 return ret;
2189 }
2190
2191 /**
2192 * @brief Configure the 6d on interrupt 2 generator.[set]
2193 *
2194 * @param ctx read / write interface definitions(ptr)
2195 * @param val change the values of 6d in reg INT2_CFG
2196 * @retval interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
lis331dlh_int2_6d_mode_set(stmdev_ctx_t * ctx,lis331dlh_int2_6d_t val)2199 int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx,
2200 lis331dlh_int2_6d_t val)
2201 {
2202 lis331dlh_int2_cfg_t int2_cfg;
2203 int32_t ret;
2204
2205 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
2206 (uint8_t *)&int2_cfg, 1);
2207
2208 if (ret == 0)
2209 {
2210 int2_cfg._6d = (uint8_t)val & 0x01U;
2211 int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2212 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_CFG,
2213 (uint8_t *)&int2_cfg, 1);
2214 }
2215
2216 return ret;
2217 }
2218
2219 /**
2220 * @brief Configure the 6d on interrupt 2 generator.[get]
2221 *
2222 * @param ctx read / write interface definitions(ptr)
2223 * @param val Get the values of 6d in reg INT2_CFG
2224 * @retval interface status (MANDATORY: return 0 -> no Error)
2225 *
2226 */
lis331dlh_int2_6d_mode_get(stmdev_ctx_t * ctx,lis331dlh_int2_6d_t * val)2227 int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx,
2228 lis331dlh_int2_6d_t *val)
2229 {
2230 lis331dlh_int2_cfg_t int2_cfg;
2231 int32_t ret;
2232
2233 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG,
2234 (uint8_t *)&int2_cfg, 1);
2235
2236 switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
2237 {
2238 case LIS331DLH_6D_INT2_DISABLE:
2239 *val = LIS331DLH_6D_INT2_DISABLE;
2240 break;
2241
2242 case LIS331DLH_6D_INT2_MOVEMENT:
2243 *val = LIS331DLH_6D_INT2_MOVEMENT;
2244 break;
2245
2246 case LIS331DLH_6D_INT2_POSITION:
2247 *val = LIS331DLH_6D_INT2_POSITION;
2248 break;
2249
2250 default:
2251 *val = LIS331DLH_6D_INT2_DISABLE;
2252 break;
2253 }
2254
2255 return ret;
2256 }
2257
2258 /**
2259 * @brief 6D on interrupt generator 2 source register.[get]
2260 *
2261 * @param ctx read / write interface definitions(ptr)
2262 * @param val registers INT2_SRC
2263 * @retval interface status (MANDATORY: return 0 -> no Error)
2264 *
2265 */
lis331dlh_int2_6d_src_get(stmdev_ctx_t * ctx,lis331dlh_int2_src_t * val)2266 int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx,
2267 lis331dlh_int2_src_t *val)
2268 {
2269 int32_t ret;
2270
2271 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_SRC, (uint8_t *) val, 1);
2272
2273 return ret;
2274 }
2275
2276 /**
2277 * @brief Interrupt 2 threshold.[set]
2278 *
2279 * @param ctx read / write interface definitions(ptr)
2280 * @param val change the values of ths in reg INT2_THS
2281 * @retval interface status (MANDATORY: return 0 -> no Error)
2282 *
2283 */
lis331dlh_int2_6d_treshold_set(stmdev_ctx_t * ctx,uint8_t val)2284 int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
2285 {
2286 lis331dlh_int2_ths_t int2_ths;
2287 int32_t ret;
2288
2289 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
2290 (uint8_t *)&int2_ths, 1);
2291
2292 if (ret == 0)
2293 {
2294 int2_ths.ths = val;
2295 ret = lis331dlh_write_reg(ctx, LIS331DLH_INT2_THS,
2296 (uint8_t *)&int2_ths, 1);
2297 }
2298
2299 return ret;
2300 }
2301
2302 /**
2303 * @brief Interrupt 2 threshold.[get]
2304 *
2305 * @param ctx read / write interface definitions(ptr)
2306 * @param val change the values of ths in reg INT2_THS
2307 * @retval interface status (MANDATORY: return 0 -> no Error)
2308 *
2309 */
lis331dlh_int2_6d_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)2310 int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx,
2311 uint8_t *val)
2312 {
2313 lis331dlh_int2_ths_t int2_ths;
2314 int32_t ret;
2315
2316 ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS,
2317 (uint8_t *)&int2_ths, 1);
2318 *val = int2_ths.ths;
2319
2320 return ret;
2321 }
2322
2323 /**
2324 * @}
2325 *
2326 */
2327
2328 /**
2329 * @}
2330 *
2331 */
2332
2333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2334
