1 /** 2 ****************************************************************************** 3 * @file lis331dlh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis331dlh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS331DLH_REGS_H 23 #define LIS331DLH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS331DLH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 167 /** @defgroup LIS331DLH_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 173 #define LIS331DLH_I2C_ADD_L 0x31U 174 #define LIS331DLH_I2C_ADD_H 0x33U 175 176 /** Device Identification (Who am I) **/ 177 #define LIS331DLH_ID 0x32U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LIS331DLH_WHO_AM_I 0x0FU 185 #define LIS331DLH_CTRL_REG1 0x20U 186 typedef struct 187 { 188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 189 uint8_t xen : 1; 190 uint8_t yen : 1; 191 uint8_t zen : 1; 192 uint8_t dr : 2; 193 uint8_t pm : 3; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t pm : 3; 196 uint8_t dr : 2; 197 uint8_t zen : 1; 198 uint8_t yen : 1; 199 uint8_t xen : 1; 200 #endif /* DRV_BYTE_ORDER */ 201 } lis331dlh_ctrl_reg1_t; 202 203 #define LIS331DLH_CTRL_REG2 0x21U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t hpcf : 2; 208 uint8_t hpen : 2; 209 uint8_t fds : 1; 210 uint8_t hpm : 2; 211 uint8_t boot : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t boot : 1; 214 uint8_t hpm : 2; 215 uint8_t fds : 1; 216 uint8_t hpen : 2; 217 uint8_t hpcf : 2; 218 #endif /* DRV_BYTE_ORDER */ 219 } lis331dlh_ctrl_reg2_t; 220 221 #define LIS331DLH_CTRL_REG3 0x22U 222 typedef struct 223 { 224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 225 uint8_t i1_cfg : 2; 226 uint8_t lir1 : 1; 227 uint8_t i2_cfg : 2; 228 uint8_t lir2 : 1; 229 uint8_t pp_od : 1; 230 uint8_t ihl : 1; 231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 232 uint8_t ihl : 1; 233 uint8_t pp_od : 1; 234 uint8_t lir2 : 1; 235 uint8_t i2_cfg : 2; 236 uint8_t lir1 : 1; 237 uint8_t i1_cfg : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } lis331dlh_ctrl_reg3_t; 240 241 #define LIS331DLH_CTRL_REG4 0x23U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t sim : 1; 246 uint8_t st : 3; /* STsign + ST */ 247 uint8_t fs : 2; 248 uint8_t ble : 1; 249 uint8_t bdu : 1; 250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 251 uint8_t bdu : 1; 252 uint8_t ble : 1; 253 uint8_t fs : 2; 254 uint8_t st : 3; /* STsign + ST */ 255 uint8_t sim : 1; 256 #endif /* DRV_BYTE_ORDER */ 257 } lis331dlh_ctrl_reg4_t; 258 259 #define LIS331DLH_CTRL_REG5 0x24U 260 typedef struct 261 { 262 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 263 uint8_t turnon : 2; 264 uint8_t not_used_01 : 6; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t not_used_01 : 6; 267 uint8_t turnon : 2; 268 #endif /* DRV_BYTE_ORDER */ 269 } lis331dlh_ctrl_reg5_t; 270 271 #define LIS331DLH_HP_FILTER_RESET 0x25U 272 #define LIS331DLH_REFERENCE 0x26U 273 #define LIS331DLH_STATUS_REG 0x27U 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t xda : 1; 278 uint8_t yda : 1; 279 uint8_t zda : 1; 280 uint8_t zyxda : 1; 281 uint8_t _xor : 1; 282 uint8_t yor : 1; 283 uint8_t zor : 1; 284 uint8_t zyxor : 1; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t zyxor : 1; 287 uint8_t zor : 1; 288 uint8_t yor : 1; 289 uint8_t _xor : 1; 290 uint8_t zyxda : 1; 291 uint8_t zda : 1; 292 uint8_t yda : 1; 293 uint8_t xda : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 } lis331dlh_status_reg_t; 296 297 #define LIS331DLH_OUT_X_L 0x28U 298 #define LIS331DLH_OUT_X_H 0x29U 299 #define LIS331DLH_OUT_Y_L 0x2AU 300 #define LIS331DLH_OUT_Y_H 0x2BU 301 #define LIS331DLH_OUT_Z_L 0x2CU 302 #define LIS331DLH_OUT_Z_H 0x2DU 303 #define LIS331DLH_INT1_CFG 0x30U 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t xlie : 1; 308 uint8_t xhie : 1; 309 uint8_t ylie : 1; 310 uint8_t yhie : 1; 311 uint8_t zlie : 1; 312 uint8_t zhie : 1; 313 uint8_t _6d : 1; 314 uint8_t aoi : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t aoi : 1; 317 uint8_t _6d : 1; 318 uint8_t zhie : 1; 319 uint8_t zlie : 1; 320 uint8_t yhie : 1; 321 uint8_t ylie : 1; 322 uint8_t xhie : 1; 323 uint8_t xlie : 1; 324 #endif /* DRV_BYTE_ORDER */ 325 } lis331dlh_int1_cfg_t; 326 327 #define LIS331DLH_INT1_SRC 0x31U 328 typedef struct 329 { 330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 331 uint8_t xl : 1; 332 uint8_t xh : 1; 333 uint8_t yl : 1; 334 uint8_t yh : 1; 335 uint8_t zl : 1; 336 uint8_t zh : 1; 337 uint8_t ia : 1; 338 uint8_t not_used_01 : 1; 339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 340 uint8_t not_used_01 : 1; 341 uint8_t ia : 1; 342 uint8_t zh : 1; 343 uint8_t zl : 1; 344 uint8_t yh : 1; 345 uint8_t yl : 1; 346 uint8_t xh : 1; 347 uint8_t xl : 1; 348 #endif /* DRV_BYTE_ORDER */ 349 } lis331dlh_int1_src_t; 350 351 #define LIS331DLH_INT1_THS 0x32U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t ths : 7; 356 uint8_t not_used_01 : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used_01 : 1; 359 uint8_t ths : 7; 360 #endif /* DRV_BYTE_ORDER */ 361 } lis331dlh_int1_ths_t; 362 363 #define LIS331DLH_INT1_DURATION 0x33U 364 typedef struct 365 { 366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 367 uint8_t d : 7; 368 uint8_t not_used_01 : 1; 369 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 370 uint8_t not_used_01 : 1; 371 uint8_t d : 7; 372 #endif /* DRV_BYTE_ORDER */ 373 374 } lis331dlh_int1_duration_t; 375 376 #define LIS331DLH_INT2_CFG 0x34U 377 typedef struct 378 { 379 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 380 uint8_t xlie : 1; 381 uint8_t xhie : 1; 382 uint8_t ylie : 1; 383 uint8_t yhie : 1; 384 uint8_t zlie : 1; 385 uint8_t zhie : 1; 386 uint8_t _6d : 1; 387 uint8_t aoi : 1; 388 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 389 uint8_t aoi : 1; 390 uint8_t _6d : 1; 391 uint8_t zhie : 1; 392 uint8_t zlie : 1; 393 uint8_t yhie : 1; 394 uint8_t ylie : 1; 395 uint8_t xhie : 1; 396 uint8_t xlie : 1; 397 #endif /* DRV_BYTE_ORDER */ 398 399 } lis331dlh_int2_cfg_t; 400 401 #define LIS331DLH_INT2_SRC 0x35U 402 typedef struct 403 { 404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 405 uint8_t xl : 1; 406 uint8_t xh : 1; 407 uint8_t yl : 1; 408 uint8_t yh : 1; 409 uint8_t zl : 1; 410 uint8_t zh : 1; 411 uint8_t ia : 1; 412 uint8_t not_used_01 : 1; 413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 414 uint8_t not_used_01 : 1; 415 uint8_t ia : 1; 416 uint8_t zh : 1; 417 uint8_t zl : 1; 418 uint8_t yh : 1; 419 uint8_t yl : 1; 420 uint8_t xh : 1; 421 uint8_t xl : 1; 422 #endif /* DRV_BYTE_ORDER */ 423 424 } lis331dlh_int2_src_t; 425 426 #define LIS331DLH_INT2_THS 0x36U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t ths : 7; 431 uint8_t not_used_01 : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t not_used_01 : 1; 434 uint8_t ths : 7; 435 #endif /* DRV_BYTE_ORDER */ 436 } lis331dlh_int2_ths_t; 437 438 #define LIS331DLH_INT2_DURATION 0x37U 439 typedef struct 440 { 441 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 442 uint8_t d : 7; 443 uint8_t not_used_01 : 1; 444 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 445 uint8_t not_used_01 : 1; 446 uint8_t d : 7; 447 #endif /* DRV_BYTE_ORDER */ 448 } lis331dlh_int2_duration_t; 449 450 /** 451 * @defgroup LIS331DLH_Register_Union 452 * @brief This union group all the registers having a bit-field 453 * description. 454 * This union is useful but it's not needed by the driver. 455 * 456 * REMOVING this union you are compliant with: 457 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 458 * 459 * @{ 460 * 461 */ 462 typedef union 463 { 464 lis331dlh_ctrl_reg1_t ctrl_reg1; 465 lis331dlh_ctrl_reg2_t ctrl_reg2; 466 lis331dlh_ctrl_reg3_t ctrl_reg3; 467 lis331dlh_ctrl_reg4_t ctrl_reg4; 468 lis331dlh_ctrl_reg5_t ctrl_reg5; 469 lis331dlh_status_reg_t status_reg; 470 lis331dlh_int1_cfg_t int1_cfg; 471 lis331dlh_int1_src_t int1_src; 472 lis331dlh_int1_ths_t int1_ths; 473 lis331dlh_int1_duration_t int1_duration; 474 lis331dlh_int2_cfg_t int2_cfg; 475 lis331dlh_int2_src_t int2_src; 476 lis331dlh_int2_ths_t int2_ths; 477 lis331dlh_int2_duration_t int2_duration; 478 bitwise_t bitwise; 479 uint8_t byte; 480 } lis331dlh_reg_t; 481 482 /** 483 * @} 484 * 485 */ 486 487 #ifndef __weak 488 #define __weak __attribute__((weak)) 489 #endif /* __weak */ 490 491 /* 492 * These are the basic platform dependent I/O routines to read 493 * and write device registers connected on a standard bus. 494 * The driver keeps offering a default implementation based on function 495 * pointers to read/write routines for backward compatibility. 496 * The __weak directive allows the final application to overwrite 497 * them with a custom implementation. 498 */ 499 500 int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 501 uint8_t *data, 502 uint16_t len); 503 int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 504 uint8_t *data, 505 uint16_t len); 506 507 float_t lis331dlh_from_fs2_to_mg(int16_t lsb); 508 float_t lis331dlh_from_fs4_to_mg(int16_t lsb); 509 float_t lis331dlh_from_fs8_to_mg(int16_t lsb); 510 511 int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); 512 int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); 513 514 int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); 515 int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); 516 517 int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); 518 int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); 519 520 typedef enum 521 { 522 LIS331DLH_ODR_OFF = 0x00, 523 LIS331DLH_ODR_Hz5 = 0x02, 524 LIS331DLH_ODR_1Hz = 0x03, 525 LIS331DLH_ODR_2Hz = 0x04, 526 LIS331DLH_ODR_5Hz = 0x05, 527 LIS331DLH_ODR_10Hz = 0x06, 528 LIS331DLH_ODR_50Hz = 0x01, 529 LIS331DLH_ODR_100Hz = 0x11, 530 LIS331DLH_ODR_400Hz = 0x21, 531 LIS331DLH_ODR_1kHz = 0x31, 532 } lis331dlh_dr_t; 533 int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, 534 lis331dlh_dr_t val); 535 int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, 536 lis331dlh_dr_t *val); 537 538 typedef enum 539 { 540 LIS331DLH_NORMAL_MODE = 0, 541 LIS331DLH_REF_MODE_ENABLE = 1, 542 } lis331dlh_hpm_t; 543 int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx, 544 lis331dlh_hpm_t val); 545 int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx, 546 lis331dlh_hpm_t *val); 547 548 typedef enum 549 { 550 LIS331DLH_2g = 0, 551 LIS331DLH_4g = 1, 552 LIS331DLH_8g = 3, 553 } lis331dlh_fs_t; 554 int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, 555 lis331dlh_fs_t val); 556 int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, 557 lis331dlh_fs_t *val); 558 559 int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, 560 uint8_t val); 561 int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, 562 uint8_t *val); 563 564 int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx, 565 lis331dlh_status_reg_t *val); 566 567 int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, 568 uint8_t *val); 569 570 int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, 571 int16_t *val); 572 573 int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 574 575 int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val); 576 int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 577 578 typedef enum 579 { 580 LIS331DLH_ST_DISABLE = 0, 581 LIS331DLH_ST_POSITIVE = 1, 582 LIS331DLH_ST_NEGATIVE = 5, 583 } lis331dlh_st_t; 584 int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, 585 lis331dlh_st_t val); 586 int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, 587 lis331dlh_st_t *val); 588 589 typedef enum 590 { 591 LIS331DLH_LSB_AT_LOW_ADD = 0, 592 LIS331DLH_MSB_AT_LOW_ADD = 1, 593 } lis331dlh_ble_t; 594 int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, 595 lis331dlh_ble_t val); 596 int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, 597 lis331dlh_ble_t *val); 598 599 typedef enum 600 { 601 LIS331DLH_CUT_OFF_8Hz = 0, 602 LIS331DLH_CUT_OFF_16Hz = 1, 603 LIS331DLH_CUT_OFF_32Hz = 2, 604 LIS331DLH_CUT_OFF_64Hz = 3, 605 } lis331dlh_hpcf_t; 606 int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, 607 lis331dlh_hpcf_t val); 608 int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx, 609 lis331dlh_hpcf_t *val); 610 611 typedef enum 612 { 613 LIS331DLH_HP_DISABLE = 0, 614 LIS331DLH_HP_ON_OUT = 4, 615 LIS331DLH_HP_ON_INT1 = 1, 616 LIS331DLH_HP_ON_INT2 = 2, 617 LIS331DLH_HP_ON_INT1_INT2 = 3, 618 LIS331DLH_HP_ON_INT1_INT2_OUT = 7, 619 LIS331DLH_HP_ON_INT2_OUT = 6, 620 LIS331DLH_HP_ON_INT1_OUT = 5, 621 } lis331dlh_hpen_t; 622 int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, 623 lis331dlh_hpen_t val); 624 int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, 625 lis331dlh_hpen_t *val); 626 627 int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx); 628 629 int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, 630 uint8_t val); 631 int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, 632 uint8_t *val); 633 634 typedef enum 635 { 636 LIS331DLH_SPI_4_WIRE = 0, 637 LIS331DLH_SPI_3_WIRE = 1, 638 } lis331dlh_sim_t; 639 int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, 640 lis331dlh_sim_t val); 641 int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, 642 lis331dlh_sim_t *val); 643 644 typedef enum 645 { 646 LIS331DLH_PAD1_INT1_SRC = 0, 647 LIS331DLH_PAD1_INT1_OR_INT2_SRC = 1, 648 LIS331DLH_PAD1_DRDY = 2, 649 LIS331DLH_PAD1_BOOT = 3, 650 } lis331dlh_i1_cfg_t; 651 int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx, 652 lis331dlh_i1_cfg_t val); 653 int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx, 654 lis331dlh_i1_cfg_t *val); 655 656 typedef enum 657 { 658 LIS331DLH_INT1_PULSED = 0, 659 LIS331DLH_INT1_LATCHED = 1, 660 } lis331dlh_lir1_t; 661 int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx, 662 lis331dlh_lir1_t val); 663 int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx, 664 lis331dlh_lir1_t *val); 665 666 typedef enum 667 { 668 LIS331DLH_PAD2_INT2_SRC = 0, 669 LIS331DLH_PAD2_INT1_OR_INT2_SRC = 1, 670 LIS331DLH_PAD2_DRDY = 2, 671 LIS331DLH_PAD2_BOOT = 3, 672 } lis331dlh_i2_cfg_t; 673 int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx, 674 lis331dlh_i2_cfg_t val); 675 int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx, 676 lis331dlh_i2_cfg_t *val); 677 678 typedef enum 679 { 680 LIS331DLH_INT2_PULSED = 0, 681 LIS331DLH_INT2_LATCHED = 1, 682 } lis331dlh_lir2_t; 683 int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx, 684 lis331dlh_lir2_t val); 685 int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx, 686 lis331dlh_lir2_t *val); 687 688 typedef enum 689 { 690 LIS331DLH_PUSH_PULL = 0, 691 LIS331DLH_OPEN_DRAIN = 1, 692 } lis331dlh_pp_od_t; 693 int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, 694 lis331dlh_pp_od_t val); 695 int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, 696 lis331dlh_pp_od_t *val); 697 698 typedef enum 699 { 700 LIS331DLH_ACTIVE_HIGH = 0, 701 LIS331DLH_ACTIVE_LOW = 1, 702 } lis331dlh_ihl_t; 703 int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, 704 lis331dlh_ihl_t val); 705 int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, 706 lis331dlh_ihl_t *val); 707 708 typedef struct 709 { 710 uint8_t int1_xlie : 1; 711 uint8_t int1_xhie : 1; 712 uint8_t int1_ylie : 1; 713 uint8_t int1_yhie : 1; 714 uint8_t int1_zlie : 1; 715 uint8_t int1_zhie : 1; 716 } int1_on_th_conf_t; 717 int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, 718 int1_on_th_conf_t val); 719 int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, 720 int1_on_th_conf_t *val); 721 722 typedef enum 723 { 724 LIS331DLH_INT1_ON_THRESHOLD_OR = 0, 725 LIS331DLH_INT1_ON_THRESHOLD_AND = 1, 726 } lis331dlh_int1_aoi_t; 727 int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, 728 lis331dlh_int1_aoi_t val); 729 int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, 730 lis331dlh_int1_aoi_t *val); 731 732 int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx, 733 lis331dlh_int1_src_t *val); 734 735 int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 736 int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); 737 738 int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); 739 int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 740 741 typedef struct 742 { 743 uint8_t int2_xlie : 1; 744 uint8_t int2_xhie : 1; 745 uint8_t int2_ylie : 1; 746 uint8_t int2_yhie : 1; 747 uint8_t int2_zlie : 1; 748 uint8_t int2_zhie : 1; 749 } int2_on_th_conf_t; 750 int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, 751 int2_on_th_conf_t val); 752 int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, 753 int2_on_th_conf_t *val); 754 755 typedef enum 756 { 757 LIS331DLH_INT2_ON_THRESHOLD_OR = 0, 758 LIS331DLH_INT2_ON_THRESHOLD_AND = 1, 759 } lis331dlh_int2_aoi_t; 760 int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, 761 lis331dlh_int2_aoi_t val); 762 int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, 763 lis331dlh_int2_aoi_t *val); 764 765 int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx, 766 lis331dlh_int2_src_t *val); 767 768 int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 769 int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); 770 771 int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); 772 int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 773 774 int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); 775 int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); 776 777 typedef enum 778 { 779 LIS331DLH_6D_INT1_DISABLE = 0, 780 LIS331DLH_6D_INT1_MOVEMENT = 1, 781 LIS331DLH_6D_INT1_POSITION = 3, 782 } lis331dlh_int1_6d_t; 783 int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx, 784 lis331dlh_int1_6d_t val); 785 int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx, 786 lis331dlh_int1_6d_t *val); 787 788 int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx, 789 lis331dlh_int1_src_t *val); 790 791 int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, 792 uint8_t val); 793 int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, 794 uint8_t *val); 795 796 typedef enum 797 { 798 LIS331DLH_6D_INT2_DISABLE = 0, 799 LIS331DLH_6D_INT2_MOVEMENT = 1, 800 LIS331DLH_6D_INT2_POSITION = 3, 801 } lis331dlh_int2_6d_t; 802 int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx, 803 lis331dlh_int2_6d_t val); 804 int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx, 805 lis331dlh_int2_6d_t *val); 806 807 int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx, 808 lis331dlh_int2_src_t *val); 809 810 int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, 811 uint8_t val); 812 int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx, 813 uint8_t *val); 814 815 /** 816 *@} 817 * 818 */ 819 820 #ifdef __cplusplus 821 } 822 #endif 823 824 #endif /* LIS331DLH_REGS_H */ 825 826 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 827
