1 /**
2 ******************************************************************************
3 * @file lis2mdl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2MDL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2mdl_reg.h"
21
22 /**
23 * @defgroup LIS2MDL
24 * @brief This file provides a set of functions needed to drive the
25 * lis2mdl enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2MDL_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2mdl_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2mdl_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2MDL_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
lis2mdl_from_lsb_to_mgauss(int16_t lsb)92 float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb)
93 {
94 return ((float_t)lsb * 1.5f);
95 }
96
lis2mdl_from_lsb_to_celsius(int16_t lsb)97 float_t lis2mdl_from_lsb_to_celsius(int16_t lsb)
98 {
99 return (((float_t)lsb / 8.0f) + 25.0f);
100 }
101
102 /**
103 * @}
104 *
105 */
106
107 /**
108 * @defgroup LIS2MDL_data_generation
109 * @brief This section group all the functions concerning
110 * data generation
111 * @{
112 *
113 */
114
115 /**
116 * @brief These registers comprise a 3 group of 16-bit number and represent
117 * hard-iron offset in order to compensate environmental effects.
118 * Data format is the same of output data raw: two’s complement
119 * with 1LSb = 1.5mG. These values act on the magnetic output data
120 * value in order to delete the environmental offset.[set]
121 *
122 * @param ctx read / write interface definitions.(ptr)
123 * @param buff buffer that contains data to write
124 * @retval interface status.(MANDATORY: return 0 -> no Error)
125 *
126 */
lis2mdl_mag_user_offset_set(stmdev_ctx_t * ctx,int16_t * val)127 int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val)
128 {
129 uint8_t buff[6];
130 int32_t ret;
131
132 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
133 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
134 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
135 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
136 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
137 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
138 ret = lis2mdl_write_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
139
140 return ret;
141 }
142
143 /**
144 * @brief These registers comprise a 3 group of 16-bit number and represent
145 * hard-iron offset in order to compensate environmental effects.
146 * Data format is the same of output data raw: two’s complement
147 * with 1LSb = 1.5mG. These values act on the magnetic output data
148 * value in order to delete the environmental offset.[get]
149 *
150 * @param ctx read / write interface definitions.(ptr)
151 * @param buff that stores data read
152 * @retval interface status.(MANDATORY: return 0 -> no Error)
153 *
154 */
lis2mdl_mag_user_offset_get(stmdev_ctx_t * ctx,int16_t * val)155 int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val)
156 {
157 uint8_t buff[6];
158 int32_t ret;
159
160 ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
161 val[0] = (int16_t)buff[1];
162 val[0] = (val[0] * 256) + (int16_t)buff[0];
163 val[1] = (int16_t)buff[3];
164 val[1] = (val[1] * 256) + (int16_t)buff[2];
165 val[2] = (int16_t)buff[5];
166 val[2] = (val[2] * 256) + (int16_t)buff[4];
167
168 return ret;
169 }
170
171 /**
172 * @brief Operating mode selection.[set]
173 *
174 * @param ctx read / write interface definitions.(ptr)
175 * @param val change the values of md in reg CFG_REG_A
176 * @retval interface status.(MANDATORY: return 0 -> no Error)
177 *
178 */
lis2mdl_operating_mode_set(stmdev_ctx_t * ctx,lis2mdl_md_t val)179 int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx,
180 lis2mdl_md_t val)
181 {
182 lis2mdl_cfg_reg_a_t reg;
183 int32_t ret;
184
185 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
186
187 if (ret == 0)
188 {
189 reg.md = (uint8_t)val;
190 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
191 }
192
193 return ret;
194 }
195
196 /**
197 * @brief Operating mode selection.[get]
198 *
199 * @param ctx read / write interface definitions.(ptr)
200 * @param val Get the values of md in reg CFG_REG_A.(ptr)
201 * @retval interface status.(MANDATORY: return 0 -> no Error)
202 *
203 */
lis2mdl_operating_mode_get(stmdev_ctx_t * ctx,lis2mdl_md_t * val)204 int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx,
205 lis2mdl_md_t *val)
206 {
207 lis2mdl_cfg_reg_a_t reg;
208 int32_t ret;
209
210 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
211
212 switch (reg.md)
213 {
214 case LIS2MDL_POWER_DOWN:
215 *val = LIS2MDL_POWER_DOWN;
216 break;
217
218 case LIS2MDL_CONTINUOUS_MODE:
219 *val = LIS2MDL_CONTINUOUS_MODE;
220 break;
221
222 case LIS2MDL_SINGLE_TRIGGER:
223 *val = LIS2MDL_SINGLE_TRIGGER;
224 break;
225
226 default:
227 *val = LIS2MDL_POWER_DOWN;
228 break;
229 }
230
231 return ret;
232 }
233
234 /**
235 * @brief Output data rate selection.[set]
236 *
237 * @param ctx read / write interface definitions.(ptr)
238 * @param val change the values of odr in reg CFG_REG_A
239 * @retval interface status.(MANDATORY: return 0 -> no Error)
240 *
241 */
lis2mdl_data_rate_set(stmdev_ctx_t * ctx,lis2mdl_odr_t val)242 int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val)
243 {
244 lis2mdl_cfg_reg_a_t reg;
245 int32_t ret;
246
247 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
248
249 if (ret == 0)
250 {
251 reg.odr = (uint8_t)val;
252 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
253 }
254
255 return ret;
256 }
257
258 /**
259 * @brief Output data rate selection.[get]
260 *
261 * @param ctx read / write interface definitions.(ptr)
262 * @param val Get the values of odr in reg CFG_REG_A.(ptr)
263 * @retval interface status.(MANDATORY: return 0 -> no Error)
264 *
265 */
lis2mdl_data_rate_get(stmdev_ctx_t * ctx,lis2mdl_odr_t * val)266 int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val)
267 {
268 lis2mdl_cfg_reg_a_t reg;
269 int32_t ret;
270
271 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
272
273 switch (reg.odr)
274 {
275 case LIS2MDL_ODR_10Hz:
276 *val = LIS2MDL_ODR_10Hz;
277 break;
278
279 case LIS2MDL_ODR_20Hz:
280 *val = LIS2MDL_ODR_20Hz;
281 break;
282
283 case LIS2MDL_ODR_50Hz:
284 *val = LIS2MDL_ODR_50Hz;
285 break;
286
287 case LIS2MDL_ODR_100Hz:
288 *val = LIS2MDL_ODR_100Hz;
289 break;
290
291 default:
292 *val = LIS2MDL_ODR_10Hz;
293 break;
294 }
295
296 return ret;
297 }
298
299 /**
300 * @brief Enables high-resolution/low-power mode.[set]
301 *
302 * @param ctx read / write interface definitions.(ptr)
303 * @param val change the values of lp in reg CFG_REG_A
304 * @retval interface status.(MANDATORY: return 0 -> no Error)
305 *
306 */
lis2mdl_power_mode_set(stmdev_ctx_t * ctx,lis2mdl_lp_t val)307 int32_t lis2mdl_power_mode_set(stmdev_ctx_t *ctx, lis2mdl_lp_t val)
308 {
309 lis2mdl_cfg_reg_a_t reg;
310 int32_t ret;
311
312 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
313
314 if (ret == 0)
315 {
316 reg.lp = (uint8_t)val;
317 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
318 }
319
320 return ret;
321 }
322
323 /**
324 * @brief Enables high-resolution/low-power mode.[get]
325 *
326 * @param ctx read / write interface definitions.(ptr)
327 * @param val Get the values of lp in reg CFG_REG_A.(ptr)
328 * @retval interface status.(MANDATORY: return 0 -> no Error)
329 *
330 */
lis2mdl_power_mode_get(stmdev_ctx_t * ctx,lis2mdl_lp_t * val)331 int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val)
332 {
333 lis2mdl_cfg_reg_a_t reg;
334 int32_t ret;
335
336 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
337
338 switch (reg.lp)
339 {
340 case LIS2MDL_HIGH_RESOLUTION:
341 *val = LIS2MDL_HIGH_RESOLUTION;
342 break;
343
344 case LIS2MDL_LOW_POWER:
345 *val = LIS2MDL_LOW_POWER;
346 break;
347
348 default:
349 *val = LIS2MDL_HIGH_RESOLUTION;
350 break;
351 }
352
353 return ret;
354 }
355
356 /**
357 * @brief Enables the magnetometer temperature compensation.[set]
358 *
359 * @param ctx read / write interface definitions.(ptr)
360 * @param val change the values of comp_temp_en in reg CFG_REG_A
361 * @retval interface status.(MANDATORY: return 0 -> no Error)
362 *
363 */
lis2mdl_offset_temp_comp_set(stmdev_ctx_t * ctx,uint8_t val)364 int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val)
365 {
366 lis2mdl_cfg_reg_a_t reg;
367 int32_t ret;
368
369 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
370
371 if (ret == 0)
372 {
373 reg.comp_temp_en = val;
374 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
375 }
376
377 return ret;
378 }
379
380 /**
381 * @brief Enables the magnetometer temperature compensation.[get]
382 *
383 * @param ctx read / write interface definitions.(ptr)
384 * @param val change the values of comp_temp_en in reg CFG_REG_A.(ptr)
385 * @retval interface status.(MANDATORY: return 0 -> no Error)
386 *
387 */
lis2mdl_offset_temp_comp_get(stmdev_ctx_t * ctx,uint8_t * val)388 int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val)
389 {
390 lis2mdl_cfg_reg_a_t reg;
391 int32_t ret;
392
393 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
394 *val = reg.comp_temp_en;
395
396 return ret;
397 }
398
399 /**
400 * @brief Low-pass bandwidth selection.[set]
401 *
402 * @param ctx read / write interface definitions.(ptr)
403 * @param val change the values of lpf in reg CFG_REG_B
404 * @retval interface status.(MANDATORY: return 0 -> no Error)
405 *
406 */
lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t * ctx,lis2mdl_lpf_t val)407 int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx,
408 lis2mdl_lpf_t val)
409 {
410 lis2mdl_cfg_reg_b_t reg;
411 int32_t ret;
412
413 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
414
415 if (ret == 0)
416 {
417 reg.lpf = (uint8_t)val;
418 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
419 }
420
421 return ret;
422 }
423
424 /**
425 * @brief Low-pass bandwidth selection.[get]
426 *
427 * @param ctx read / write interface definitions.(ptr)
428 * @param val Get the values of lpf in reg CFG_REG_B.(ptr)
429 * @retval interface status.(MANDATORY: return 0 -> no Error)
430 *
431 */
lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t * ctx,lis2mdl_lpf_t * val)432 int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx,
433 lis2mdl_lpf_t *val)
434 {
435 lis2mdl_cfg_reg_b_t reg;
436 int32_t ret;
437
438 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
439
440 switch (reg.lpf)
441 {
442 case LIS2MDL_ODR_DIV_2:
443 *val = LIS2MDL_ODR_DIV_2;
444 break;
445
446 case LIS2MDL_ODR_DIV_4:
447 *val = LIS2MDL_ODR_DIV_4;
448 break;
449
450 default:
451 *val = LIS2MDL_ODR_DIV_2;
452 break;
453 }
454
455 return ret;
456 }
457
458 /**
459 * @brief Reset mode.[set]
460 *
461 * @param ctx read / write interface definitions.(ptr)
462 * @param val change the values of set_rst in reg CFG_REG_B
463 * @retval interface status.(MANDATORY: return 0 -> no Error)
464 *
465 */
lis2mdl_set_rst_mode_set(stmdev_ctx_t * ctx,lis2mdl_set_rst_t val)466 int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx,
467 lis2mdl_set_rst_t val)
468 {
469 lis2mdl_cfg_reg_b_t reg;
470 int32_t ret;
471
472 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
473
474 if (ret == 0)
475 {
476 reg.set_rst = (uint8_t)val;
477 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
478 }
479
480 return ret;
481 }
482
483 /**
484 * @brief Reset mode.[get]
485 *
486 * @param ctx read / write interface definitions.(ptr)
487 * @param val Get the values of set_rst in reg CFG_REG_B.(ptr)
488 * @retval interface status.(MANDATORY: return 0 -> no Error)
489 *
490 */
lis2mdl_set_rst_mode_get(stmdev_ctx_t * ctx,lis2mdl_set_rst_t * val)491 int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx,
492 lis2mdl_set_rst_t *val)
493 {
494 lis2mdl_cfg_reg_b_t reg;
495 int32_t ret;
496
497 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
498
499 switch (reg.set_rst)
500 {
501 case LIS2MDL_SET_SENS_ODR_DIV_63:
502 *val = LIS2MDL_SET_SENS_ODR_DIV_63;
503 break;
504
505 case LIS2MDL_SENS_OFF_CANC_EVERY_ODR:
506 *val = LIS2MDL_SENS_OFF_CANC_EVERY_ODR;
507 break;
508
509 case LIS2MDL_SET_SENS_ONLY_AT_POWER_ON:
510 *val = LIS2MDL_SET_SENS_ONLY_AT_POWER_ON;
511 break;
512
513 default:
514 *val = LIS2MDL_SET_SENS_ODR_DIV_63;
515 break;
516 }
517
518 return ret;
519 }
520
521 /**
522 * @brief Enables offset cancellation in single measurement mode.
523 * The OFF_CANC bit must be set to 1 when enabling offset
524 * cancellation in single measurement mode this means a
525 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR)
526 * is need.[set]
527 *
528 * @param ctx read / write interface definitions.(ptr)
529 * @param val change the values of off_canc_one_shot in reg CFG_REG_B
530 * @retval interface status.(MANDATORY: return 0 -> no Error)
531 *
532 */
lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t * ctx,uint8_t val)533 int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx,
534 uint8_t val)
535 {
536 lis2mdl_cfg_reg_b_t reg;
537 int32_t ret;
538
539 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
540
541 if (ret == 0)
542 {
543 reg.off_canc_one_shot = val;
544 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
545 }
546
547 return ret;
548 }
549
550 /**
551 * @brief Enables offset cancellation in single measurement mode.
552 * The OFF_CANC bit must be set to 1 when enabling offset
553 * cancellation in single measurement mode this means a
554 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR)
555 * is need.[get]
556 *
557 * @param ctx read / write interface definitions.(ptr)
558 * @param val change the values of off_canc_one_shot in reg CFG_REG_B.(ptr)
559 * @retval interface status.(MANDATORY: return 0 -> no Error)
560 *
561 */
lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t * ctx,uint8_t * val)562 int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx,
563 uint8_t *val)
564 {
565 lis2mdl_cfg_reg_b_t reg;
566 int32_t ret;
567
568 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
569 *val = reg.off_canc_one_shot;
570
571 return ret;
572 }
573
574 /**
575 * @brief Blockdataupdate.[set]
576 *
577 * @param ctx read / write interface definitions.(ptr)
578 * @param val change the values of bdu in reg CFG_REG_C
579 * @retval interface status.(MANDATORY: return 0 -> no Error)
580 *
581 */
lis2mdl_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)582 int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
583 {
584 lis2mdl_cfg_reg_c_t reg;
585 int32_t ret;
586
587 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
588
589 if (ret == 0)
590 {
591 reg.bdu = val;
592 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
593 }
594
595 return ret;
596 }
597
598 /**
599 * @brief Blockdataupdate.[get]
600 *
601 * @param ctx read / write interface definitions.(ptr)
602 * @param val change the values of bdu in reg CFG_REG_C.(ptr)
603 * @retval interface status.(MANDATORY: return 0 -> no Error)
604 *
605 */
lis2mdl_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)606 int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
607 {
608 lis2mdl_cfg_reg_c_t reg;
609 int32_t ret;
610
611 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
612 *val = reg.bdu;
613
614 return ret;
615 }
616
617 /**
618 * @brief Magnetic set of data available.[get]
619 *
620 * @param ctx read / write interface definitions.(ptr)
621 * @param val change the values of zyxda in reg STATUS_REG.(ptr)
622 * @retval interface status.(MANDATORY: return 0 -> no Error)
623 *
624 */
lis2mdl_mag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)625 int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
626 {
627 lis2mdl_status_reg_t reg;
628 int32_t ret;
629
630 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
631 *val = reg.zyxda;
632
633 return ret;
634 }
635
636 /**
637 * @brief Magnetic set of data overrun.[get]
638 *
639 * @param ctx read / write interface definitions.(ptr)
640 * @param val change the values of zyxor in reg STATUS_REG.(ptr)
641 * @retval interface status.(MANDATORY: return 0 -> no Error)
642 *
643 */
lis2mdl_mag_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)644 int32_t lis2mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
645 {
646 lis2mdl_status_reg_t reg;
647 int32_t ret;
648
649 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
650 *val = reg.zyxor;
651
652 return ret;
653 }
654
655 /**
656 * @brief Magnetic output value.[get]
657 *
658 * @param ctx read / write interface definitions.(ptr)
659 * @param buff that stores data read
660 * @retval interface status.(MANDATORY: return 0 -> no Error)
661 *
662 */
lis2mdl_magnetic_raw_get(stmdev_ctx_t * ctx,int16_t * val)663 int32_t lis2mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val)
664 {
665 uint8_t buff[6];
666 int32_t ret;
667
668 ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6);
669 val[0] = (int16_t)buff[1];
670 val[0] = (val[0] * 256) + (int16_t)buff[0];
671 val[1] = (int16_t)buff[3];
672 val[1] = (val[1] * 256) + (int16_t)buff[2];
673 val[2] = (int16_t)buff[5];
674 val[2] = (val[2] * 256) + (int16_t)buff[4];
675
676 return ret;
677 }
678
679 /**
680 * @brief Temperature output value.[get]
681 *
682 * @param ctx read / write interface definitions.(ptr)
683 * @param buff that stores data read
684 * @retval interface status.(MANDATORY: return 0 -> no Error)
685 *
686 */
lis2mdl_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)687 int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
688 {
689 uint8_t buff[2];
690 int32_t ret;
691
692 ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2);
693 *val = (int16_t)buff[1];
694 *val = (*val * 256) + (int16_t)buff[0];
695
696 return ret;
697 }
698
699 /**
700 * @}
701 *
702 */
703
704 /**
705 * @defgroup LIS2MDL_common
706 * @brief This section group common useful functions
707 * @{
708 *
709 */
710
711 /**
712 * @brief DeviceWhoamI.[get]
713 *
714 * @param ctx read / write interface definitions.(ptr)
715 * @param buff that stores data read
716 * @retval interface status.(MANDATORY: return 0 -> no Error)
717 *
718 */
lis2mdl_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)719 int32_t lis2mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
720 {
721 int32_t ret;
722
723 ret = lis2mdl_read_reg(ctx, LIS2MDL_WHO_AM_I, buff, 1);
724
725 return ret;
726 }
727
728 /**
729 * @brief Software reset. Restore the default values in user registers.[set]
730 *
731 * @param ctx read / write interface definitions.(ptr)
732 * @param val change the values of soft_rst in reg CFG_REG_A
733 * @retval interface status.(MANDATORY: return 0 -> no Error)
734 *
735 */
lis2mdl_reset_set(stmdev_ctx_t * ctx,uint8_t val)736 int32_t lis2mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
737 {
738 lis2mdl_cfg_reg_a_t reg;
739 int32_t ret;
740
741 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
742
743 if (ret == 0)
744 {
745 reg.soft_rst = val;
746 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
747 }
748
749 return ret;
750 }
751
752 /**
753 * @brief Software reset. Restore the default values in user registers.[get]
754 *
755 * @param ctx read / write interface definitions.(ptr)
756 * @param val change the values of soft_rst in reg CFG_REG_A.(ptr)
757 * @retval interface status.(MANDATORY: return 0 -> no Error)
758 *
759 */
lis2mdl_reset_get(stmdev_ctx_t * ctx,uint8_t * val)760 int32_t lis2mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
761 {
762 lis2mdl_cfg_reg_a_t reg;
763 int32_t ret;
764
765 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
766 *val = reg.soft_rst;
767
768 return ret;
769 }
770
771 /**
772 * @brief Reboot memory content. Reload the calibration parameters.[set]
773 *
774 * @param ctx read / write interface definitions.(ptr)
775 * @param val change the values of reboot in reg CFG_REG_A
776 * @retval interface status.(MANDATORY: return 0 -> no Error)
777 *
778 */
lis2mdl_boot_set(stmdev_ctx_t * ctx,uint8_t val)779 int32_t lis2mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
780 {
781 lis2mdl_cfg_reg_a_t reg;
782 int32_t ret;
783
784 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
785
786 if (ret == 0)
787 {
788 reg.reboot = val;
789 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
790 }
791
792 return ret;
793 }
794
795 /**
796 * @brief Reboot memory content. Reload the calibration parameters.[get]
797 *
798 * @param ctx read / write interface definitions.(ptr)
799 * @param val change the values of reboot in reg CFG_REG_A.(ptr)
800 * @retval interface status.(MANDATORY: return 0 -> no Error)
801 *
802 */
lis2mdl_boot_get(stmdev_ctx_t * ctx,uint8_t * val)803 int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
804 {
805 lis2mdl_cfg_reg_a_t reg;
806 int32_t ret;
807
808 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
809 *val = reg.reboot;
810
811 return ret;
812 }
813
814 /**
815 * @brief Selftest.[set]
816 *
817 * @param ctx read / write interface definitions.(ptr)
818 * @param val change the values of self_test in reg CFG_REG_C
819 * @retval interface status.(MANDATORY: return 0 -> no Error)
820 *
821 */
lis2mdl_self_test_set(stmdev_ctx_t * ctx,uint8_t val)822 int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val)
823 {
824 lis2mdl_cfg_reg_c_t reg;
825 int32_t ret;
826
827 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
828
829 if (ret == 0)
830 {
831 reg.self_test = val;
832 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
833 }
834
835 return ret;
836 }
837
838 /**
839 * @brief Selftest.[get]
840 *
841 * @param ctx read / write interface definitions.(ptr)
842 * @param val change the values of self_test in reg CFG_REG_C.(ptr)
843 * @retval interface status.(MANDATORY: return 0 -> no Error)
844 *
845 */
lis2mdl_self_test_get(stmdev_ctx_t * ctx,uint8_t * val)846 int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val)
847 {
848 lis2mdl_cfg_reg_c_t reg;
849 int32_t ret;
850
851 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
852 *val = reg.self_test;
853
854 return ret;
855 }
856
857 /**
858 * @brief Big/Little Endian data selection.[set]
859 *
860 * @param ctx read / write interface definitions.(ptr)
861 * @param val change the values of ble in reg CFG_REG_C
862 * @retval interface status.(MANDATORY: return 0 -> no Error)
863 *
864 */
lis2mdl_data_format_set(stmdev_ctx_t * ctx,lis2mdl_ble_t val)865 int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val)
866 {
867 lis2mdl_cfg_reg_c_t reg;
868 int32_t ret;
869
870 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
871
872 if (ret == 0)
873 {
874 reg.ble = (uint8_t)val;
875 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
876 }
877
878 return ret;
879 }
880
881 /**
882 * @brief Big/Little Endian data selection.[get]
883 *
884 * @param ctx read / write interface definitions.(ptr)
885 * @param val Get the values of ble in reg CFG_REG_C.(ptr)
886 * @retval interface status.(MANDATORY: return 0 -> no Error)
887 *
888 */
lis2mdl_data_format_get(stmdev_ctx_t * ctx,lis2mdl_ble_t * val)889 int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val)
890 {
891 lis2mdl_cfg_reg_c_t reg;
892 int32_t ret;
893
894 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
895
896 switch (reg.ble)
897 {
898 case LIS2MDL_LSB_AT_LOW_ADD:
899 *val = LIS2MDL_LSB_AT_LOW_ADD;
900 break;
901
902 case LIS2MDL_MSB_AT_LOW_ADD:
903 *val = LIS2MDL_MSB_AT_LOW_ADD;
904 break;
905
906 default:
907 *val = LIS2MDL_LSB_AT_LOW_ADD;
908 break;
909 }
910
911 return ret;
912 }
913
914 /**
915 * @brief Info about device status.[get]
916 *
917 * @param ctx read / write interface definitions.(ptr)
918 * @param val registers STATUS_REG.(ptr)
919 * @retval interface status.(MANDATORY: return 0 -> no Error)
920 *
921 */
lis2mdl_status_get(stmdev_ctx_t * ctx,lis2mdl_status_reg_t * val)922 int32_t lis2mdl_status_get(stmdev_ctx_t *ctx,
923 lis2mdl_status_reg_t *val)
924 {
925 int32_t ret;
926
927 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *) val, 1);
928
929 return ret;
930 }
931
932 /**
933 * @}
934 *
935 */
936
937 /**
938 * @defgroup LIS2MDL_interrupts
939 * @brief This section group all the functions that manage interrupts
940 * @{
941 *
942 */
943
944 /**
945 * @brief The interrupt block recognition checks data after/before the
946 * hard-iron correction to discover the interrupt.[set]
947 *
948 * @param ctx read / write interface definitions.(ptr)
949 * @param val change the values of int_on_dataoff in reg CFG_REG_B
950 * @retval interface status.(MANDATORY: return 0 -> no Error)
951 *
952 */
lis2mdl_offset_int_conf_set(stmdev_ctx_t * ctx,lis2mdl_int_on_dataoff_t val)953 int32_t lis2mdl_offset_int_conf_set(stmdev_ctx_t *ctx,
954 lis2mdl_int_on_dataoff_t val)
955 {
956 lis2mdl_cfg_reg_b_t reg;
957 int32_t ret;
958
959 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
960
961 if (ret == 0)
962 {
963 reg.int_on_dataoff = (uint8_t)val;
964 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
965 }
966
967 return ret;
968 }
969
970 /**
971 * @brief The interrupt block recognition checks data after/before the
972 * hard-iron correction to discover the interrupt.[get]
973 *
974 * @param ctx read / write interface definitions.(ptr)
975 * @param val Get the values of int_on_dataoff in reg CFG_REG_B.(ptr)
976 * @retval interface status.(MANDATORY: return 0 -> no Error)
977 *
978 */
lis2mdl_offset_int_conf_get(stmdev_ctx_t * ctx,lis2mdl_int_on_dataoff_t * val)979 int32_t lis2mdl_offset_int_conf_get(stmdev_ctx_t *ctx,
980 lis2mdl_int_on_dataoff_t *val)
981 {
982 lis2mdl_cfg_reg_b_t reg;
983 int32_t ret;
984
985 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
986
987 switch (reg.int_on_dataoff)
988 {
989 case LIS2MDL_CHECK_BEFORE:
990 *val = LIS2MDL_CHECK_BEFORE;
991 break;
992
993 case LIS2MDL_CHECK_AFTER:
994 *val = LIS2MDL_CHECK_AFTER;
995 break;
996
997 default:
998 *val = LIS2MDL_CHECK_BEFORE;
999 break;
1000 }
1001
1002 return ret;
1003 }
1004
1005 /**
1006 * @brief Data-ready signal on INT_DRDY pin.[set]
1007 *
1008 * @param ctx read / write interface definitions.(ptr)
1009 * @param val change the values of drdy_on_pin in reg CFG_REG_C
1010 * @retval interface status.(MANDATORY: return 0 -> no Error)
1011 *
1012 */
lis2mdl_drdy_on_pin_set(stmdev_ctx_t * ctx,uint8_t val)1013 int32_t lis2mdl_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
1014 {
1015 lis2mdl_cfg_reg_c_t reg;
1016 int32_t ret;
1017
1018 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1019
1020 if (ret == 0)
1021 {
1022 reg.drdy_on_pin = val;
1023 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Data-ready signal on INT_DRDY pin.[get]
1031 *
1032 * @param ctx read / write interface definitions.(ptr)
1033 * @param val change the values of drdy_on_pin in reg CFG_REG_C.(ptr)
1034 * @retval interface status.(MANDATORY: return 0 -> no Error)
1035 *
1036 */
lis2mdl_drdy_on_pin_get(stmdev_ctx_t * ctx,uint8_t * val)1037 int32_t lis2mdl_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
1038 {
1039 lis2mdl_cfg_reg_c_t reg;
1040 int32_t ret;
1041
1042 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1043 *val = reg.drdy_on_pin;
1044
1045 return ret;
1046 }
1047
1048 /**
1049 * @brief Interrupt signal on INT_DRDY pin.[set]
1050 *
1051 * @param ctx read / write interface definitions.(ptr)
1052 * @param val change the values of int_on_pin in reg CFG_REG_C
1053 * @retval interface status.(MANDATORY: return 0 -> no Error)
1054 *
1055 */
lis2mdl_int_on_pin_set(stmdev_ctx_t * ctx,uint8_t val)1056 int32_t lis2mdl_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val)
1057 {
1058 lis2mdl_cfg_reg_c_t reg;
1059 int32_t ret;
1060
1061 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1062
1063 if (ret == 0)
1064 {
1065 reg.int_on_pin = val;
1066 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1067 }
1068
1069 return ret;
1070 }
1071
1072 /**
1073 * @brief Interrupt signal on INT_DRDY pin.[get]
1074 *
1075 * @param ctx read / write interface definitions.(ptr)
1076 * @param val change the values of int_on_pin in reg CFG_REG_C.(ptr)
1077 * @retval interface status.(MANDATORY: return 0 -> no Error)
1078 *
1079 */
lis2mdl_int_on_pin_get(stmdev_ctx_t * ctx,uint8_t * val)1080 int32_t lis2mdl_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val)
1081 {
1082 lis2mdl_cfg_reg_c_t reg;
1083 int32_t ret;
1084
1085 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1086 *val = reg.int_on_pin;
1087
1088 return ret;
1089 }
1090
1091 /**
1092 * @brief Interrupt generator configuration register.[set]
1093 *
1094 * @param ctx read / write interface definitions.(ptr)
1095 * @param val registers INT_CRTL_REG.(ptr)
1096 * @retval interface status.(MANDATORY: return 0 -> no Error)
1097 *
1098 */
lis2mdl_int_gen_conf_set(stmdev_ctx_t * ctx,lis2mdl_int_crtl_reg_t * val)1099 int32_t lis2mdl_int_gen_conf_set(stmdev_ctx_t *ctx,
1100 lis2mdl_int_crtl_reg_t *val)
1101 {
1102 int32_t ret;
1103
1104 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
1105
1106 return ret;
1107 }
1108
1109 /**
1110 * @brief Interrupt generator configuration register.[get]
1111 *
1112 * @param ctx read / write interface definitions.(ptr)
1113 * @param val registers INT_CRTL_REG.(ptr)
1114 * @retval interface status.(MANDATORY: return 0 -> no Error)
1115 *
1116 */
lis2mdl_int_gen_conf_get(stmdev_ctx_t * ctx,lis2mdl_int_crtl_reg_t * val)1117 int32_t lis2mdl_int_gen_conf_get(stmdev_ctx_t *ctx,
1118 lis2mdl_int_crtl_reg_t *val)
1119 {
1120 int32_t ret;
1121
1122 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
1123
1124 return ret;
1125 }
1126
1127 /**
1128 * @brief Interrupt generator source register.[get]
1129 *
1130 * @param ctx read / write interface definitions.(ptr)
1131 * @param val registers INT_SOURCE_REG.(ptr)
1132 * @retval interface status.(MANDATORY: return 0 -> no Error)
1133 *
1134 */
lis2mdl_int_gen_source_get(stmdev_ctx_t * ctx,lis2mdl_int_source_reg_t * val)1135 int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx,
1136 lis2mdl_int_source_reg_t *val)
1137 {
1138 int32_t ret;
1139
1140 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t *) val, 1);
1141
1142 return ret;
1143 }
1144
1145 /**
1146 * @brief User-defined threshold value for xl interrupt event on generator.
1147 * Data format is the same of output data raw: two’s complement with
1148 * 1LSb = 1.5mG.[set]
1149 *
1150 * @param ctx read / write interface definitions.(ptr)
1151 * @param buff that contains data to write
1152 * @retval interface status.(MANDATORY: return 0 -> no Error)
1153 *
1154 */
lis2mdl_int_gen_treshold_set(stmdev_ctx_t * ctx,uint16_t val)1155 int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val)
1156 {
1157 uint8_t buff[2];
1158 int32_t ret;
1159
1160 buff[1] = (uint8_t)(val / 256U);
1161 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1162 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
1163
1164 return ret;
1165 }
1166
1167 /**
1168 * @brief User-defined threshold value for xl interrupt event on generator.
1169 * Data format is the same of output data raw: two’s complement with
1170 * 1LSb = 1.5mG.[get]
1171 *
1172 * @param ctx read / write interface definitions.(ptr)
1173 * @param buff that stores data read
1174 * @retval interface status.(MANDATORY: return 0 -> no Error)
1175 *
1176 */
lis2mdl_int_gen_treshold_get(stmdev_ctx_t * ctx,uint16_t * val)1177 int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val)
1178 {
1179 uint8_t buff[2];
1180 int32_t ret;
1181
1182 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
1183 *val = buff[1];
1184 *val = (*val * 256U) + buff[0];
1185
1186 return ret;
1187 }
1188
1189 /**
1190 * @}
1191 *
1192 */
1193
1194 /**
1195 * @defgroup LIS2MDL_serial_interface
1196 * @brief This section group all the functions concerning serial
1197 * interface management
1198 * @{
1199 *
1200 */
1201
1202 /**
1203 * @brief SPI Serial Interface Mode selection.[set]
1204 *
1205 * @param ctx read / write interface definitions
1206 * @param val change the values of 4wspi in reg CFG_REG_C
1207 * @retval interface status (MANDATORY: return 0 -> no Error)
1208 *
1209 */
lis2mdl_spi_mode_set(stmdev_ctx_t * ctx,lis2mdl_sim_t val)1210 int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val)
1211 {
1212 lis2mdl_cfg_reg_c_t reg;
1213 int32_t ret;
1214
1215 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1216
1217 if (ret == 0)
1218 {
1219 reg._4wspi = (uint8_t)val;
1220 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1221 }
1222
1223 return ret;
1224 }
1225
1226 /**
1227 * @brief SPI Serial Interface Mode selection.[get]
1228 *
1229 * @param ctx read / write interface definitions
1230 * @param val Get the values of 4wspi in reg CFG_REG_C
1231 * @retval interface status (MANDATORY: return 0 -> no Error)
1232 *
1233 */
lis2mdl_spi_mode_get(stmdev_ctx_t * ctx,lis2mdl_sim_t * val)1234 int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val)
1235 {
1236 lis2mdl_cfg_reg_c_t reg;
1237 int32_t ret;
1238
1239 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1240
1241 switch (reg._4wspi)
1242 {
1243 case LIS2MDL_SPI_4_WIRE:
1244 *val = LIS2MDL_SPI_4_WIRE;
1245 break;
1246
1247 case LIS2MDL_SPI_3_WIRE:
1248 *val = LIS2MDL_SPI_3_WIRE;
1249 break;
1250
1251 default:
1252 *val = LIS2MDL_SPI_3_WIRE;
1253 break;
1254 }
1255
1256 return ret;
1257 }
1258
1259 /**
1260 * @brief Enable/Disable I2C interface.[set]
1261 *
1262 * @param ctx read / write interface definitions.(ptr)
1263 * @param val change the values of i2c_dis in reg CFG_REG_C
1264 * @retval interface status.(MANDATORY: return 0 -> no Error)
1265 *
1266 */
lis2mdl_i2c_interface_set(stmdev_ctx_t * ctx,lis2mdl_i2c_dis_t val)1267 int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx,
1268 lis2mdl_i2c_dis_t val)
1269 {
1270 lis2mdl_cfg_reg_c_t reg;
1271 int32_t ret;
1272
1273 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1274
1275 if (ret == 0)
1276 {
1277 reg.i2c_dis = (uint8_t)val;
1278 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1279 }
1280
1281 return ret;
1282 }
1283
1284 /**
1285 * @brief Enable/Disable I2C interface.[get]
1286 *
1287 * @param ctx read / write interface definitions.(ptr)
1288 * @param val Get the values of i2c_dis in reg CFG_REG_C.(ptr)
1289 * @retval interface status.(MANDATORY: return 0 -> no Error)
1290 *
1291 */
lis2mdl_i2c_interface_get(stmdev_ctx_t * ctx,lis2mdl_i2c_dis_t * val)1292 int32_t lis2mdl_i2c_interface_get(stmdev_ctx_t *ctx,
1293 lis2mdl_i2c_dis_t *val)
1294 {
1295 lis2mdl_cfg_reg_c_t reg;
1296 int32_t ret;
1297
1298 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1299
1300 switch (reg.i2c_dis)
1301 {
1302 case LIS2MDL_I2C_ENABLE:
1303 *val = LIS2MDL_I2C_ENABLE;
1304 break;
1305
1306 case LIS2MDL_I2C_DISABLE:
1307 *val = LIS2MDL_I2C_DISABLE;
1308 break;
1309
1310 default:
1311 *val = LIS2MDL_I2C_ENABLE;
1312 break;
1313 }
1314
1315 return ret;
1316 }
1317
1318 /**
1319 * @}
1320 *
1321 */
1322
1323 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1324
