1 /*
2  ******************************************************************************
3  * @file    lis2duxs12_reg.h
4  * @author  Sensors Software Solution Team
5  * @brief   This file contains all the functions prototypes for the
6  *          lis2duxs12_reg.c driver.
7  ******************************************************************************
8  * @attention
9  *
10  * <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
11  * All rights reserved.</center></h2>
12  *
13  * This software component is licensed by ST under BSD 3-Clause license,
14  * the "License"; You may not use this file except in compliance with the
15  * License. You may obtain a copy of the License at:
16  *                        opensource.org/licenses/BSD-3-Clause
17  *
18  ******************************************************************************
19  */
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef LIS2DUXS12_REGS_H
23 #define LIS2DUXS12_REGS_H
24 
25 #ifdef __cplusplus
26   extern "C" {
27 #endif
28 
29 /* Includes ------------------------------------------------------------------*/
30 #include <stdint.h>
31 #include <stddef.h>
32 #include <math.h>
33 
34 /** @addtogroup LIS2DUXS12
35   * @{
36   *
37   */
38 
39 /** @defgroup  Endianness definitions
40   * @{
41   *
42   */
43 
44 #ifndef DRV_BYTE_ORDER
45 #ifndef __BYTE_ORDER__
46 
47 #define DRV_LITTLE_ENDIAN 1234
48 #define DRV_BIG_ENDIAN    4321
49 
50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture
51   * by uncommenting the define which fits your platform endianness
52   */
53 //#define DRV_BYTE_ORDER    DRV_BIG_ENDIAN
54 #define DRV_BYTE_ORDER    DRV_LITTLE_ENDIAN
55 
56 #else /* defined __BYTE_ORDER__ */
57 
58 #define DRV_LITTLE_ENDIAN  __ORDER_LITTLE_ENDIAN__
59 #define DRV_BIG_ENDIAN     __ORDER_BIG_ENDIAN__
60 #define DRV_BYTE_ORDER     __BYTE_ORDER__
61 
62 #endif /* __BYTE_ORDER__*/
63 #endif /* DRV_BYTE_ORDER */
64 
65 /**
66   * @}
67   *
68   */
69 
70 /** @defgroup STMicroelectronics sensors common types
71   * @{
72   *
73   */
74 
75 #ifndef MEMS_SHARED_TYPES
76 #define MEMS_SHARED_TYPES
77 
78 typedef struct{
79 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
80   uint8_t bit0                         : 1;
81   uint8_t bit1                         : 1;
82   uint8_t bit2                         : 1;
83   uint8_t bit3                         : 1;
84   uint8_t bit4                         : 1;
85   uint8_t bit5                         : 1;
86   uint8_t bit6                         : 1;
87   uint8_t bit7                         : 1;
88 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
89   uint8_t bit7                         : 1;
90   uint8_t bit6                         : 1;
91   uint8_t bit5                         : 1;
92   uint8_t bit4                         : 1;
93   uint8_t bit3                         : 1;
94   uint8_t bit2                         : 1;
95   uint8_t bit1                         : 1;
96   uint8_t bit0                         : 1;
97 #endif /* DRV_BYTE_ORDER */
98 } bitwise_t;
99 
100 #define PROPERTY_DISABLE                (0U)
101 #define PROPERTY_ENABLE                 (1U)
102 
103 /** @addtogroup  Interfaces_Functions
104   * @brief       This section provide a set of functions used to read and
105   *              write a generic register of the device.
106   *              MANDATORY: return 0 -> no Error.
107   * @{
108   *
109   */
110 
111 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
112 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
113 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
114 
115 typedef struct
116 {
117   /** Component mandatory fields **/
118   stmdev_write_ptr  write_reg;
119   stmdev_read_ptr   read_reg;
120   /** Component optional fields **/
121   stmdev_mdelay_ptr   mdelay;
122   /** Customizable optional pointer **/
123   void *handle;
124 } stmdev_ctx_t;
125 
126 /**
127   * @}
128   *
129   */
130 
131 #endif /* MEMS_SHARED_TYPES */
132 
133 #ifndef MEMS_UCF_SHARED_TYPES
134 #define MEMS_UCF_SHARED_TYPES
135 
136 /** @defgroup    Generic address-data structure definition
137   * @brief       This structure is useful to load a predefined configuration
138   *              of a sensor.
139   *              You can create a sensor configuration by your own or using
140   *              Unico / Unicleo tools available on STMicroelectronics
141   *              web site.
142   *
143   * @{
144   *
145   */
146 
147 typedef struct {
148   uint8_t address;
149   uint8_t data;
150 } ucf_line_t;
151 
152 /**
153   * @}
154   *
155   */
156 
157 #endif /* MEMS_UCF_SHARED_TYPES */
158 
159 /**
160   * @}
161   *
162   */
163 
164 /** @defgroup LIS2DUXS12_Infos
165   * @{
166   *
167   */
168 
169 /** I2C Device Address 8 bit format  if SA0=0 -> 0x if SA0=1 -> 0x **/
170 #define LIS2DUXS12_I2C_ADD_L                            0x31U
171 #define LIS2DUXS12_I2C_ADD_H                            0x33U
172 
173 /** Device Identification (Who am I) **/
174 #define LIS2DUXS12_ID                                   0x47U
175 
176 /**
177   * @}
178   *
179   */
180 
181 #define LIS2DUXS12_PIN_CTRL                             0x0CU
182 typedef struct
183 {
184 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
185   uint8_t sim                          : 1;
186   uint8_t pp_od                        : 1;
187   uint8_t cs_pu_dis                    : 1;
188   uint8_t h_lactive                    : 1;
189   uint8_t pd_dis_int1                  : 1;
190   uint8_t pd_dis_int2                  : 1;
191   uint8_t sda_pu_en                    : 1;
192   uint8_t sdo_pu_en                    : 1;
193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
194   uint8_t sdo_pu_en                    : 1;
195   uint8_t sda_pu_en                    : 1;
196   uint8_t pd_dis_int2                  : 1;
197   uint8_t pd_dis_int1                  : 1;
198   uint8_t h_lactive                    : 1;
199   uint8_t cs_pu_dis                    : 1;
200   uint8_t pp_od                        : 1;
201   uint8_t sim                          : 1;
202 #endif /* DRV_BYTE_ORDER */
203 } lis2duxs12_pin_ctrl_t;
204 
205 #define LIS2DUXS12_WAKE_UP_DUR_EXT                      0x0EU
206 typedef struct
207 {
208 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
209   uint8_t not_used0                    : 4;
210   uint8_t wu_dur_extended              : 1;
211   uint8_t not_used1                    : 3;
212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
213   uint8_t not_used1                    : 3;
214   uint8_t wu_dur_extended              : 1;
215   uint8_t not_used0                    : 4;
216 #endif /* DRV_BYTE_ORDER */
217 } lis2duxs12_wake_up_dur_ext_t;
218 
219 #define LIS2DUXS12_WHO_AM_I                             0x0FU
220 typedef struct
221 {
222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
223   uint8_t id                           : 8;
224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
225   uint8_t id                           : 8;
226 #endif /* DRV_BYTE_ORDER */
227 } lis2duxs12_who_am_i_t;
228 
229 #define LIS2DUXS12_CTRL1                                0x10U
230 typedef struct
231 {
232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
233   uint8_t wu_z_en                      : 1;
234   uint8_t wu_y_en                      : 1;
235   uint8_t wu_x_en                      : 1;
236   uint8_t drdy_pulsed                  : 1;
237   uint8_t if_add_inc                   : 1;
238   uint8_t sw_reset                     : 1;
239   uint8_t int1_on_res                  : 1;
240   uint8_t not_used0                    : 1;
241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
242   uint8_t not_used0                    : 1;
243   uint8_t int1_on_res                  : 1;
244   uint8_t sw_reset                     : 1;
245   uint8_t if_add_inc                   : 1;
246   uint8_t drdy_pulsed                  : 1;
247   uint8_t wu_x_en                      : 1;
248   uint8_t wu_y_en                      : 1;
249   uint8_t wu_z_en                      : 1;
250 #endif /* DRV_BYTE_ORDER */
251 } lis2duxs12_ctrl1_t;
252 
253 #define LIS2DUXS12_CTRL2                                0x11U
254 typedef struct
255 {
256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
257   uint8_t not_used0                    : 3;
258   uint8_t int1_drdy                    : 1;
259   uint8_t int1_fifo_ovr                : 1;
260   uint8_t int1_fifo_th                 : 1;
261   uint8_t int1_fifo_full               : 1;
262   uint8_t int1_boot                    : 1;
263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
264   uint8_t int1_boot                    : 1;
265   uint8_t int1_fifo_full               : 1;
266   uint8_t int1_fifo_th                 : 1;
267   uint8_t int1_fifo_ovr                : 1;
268   uint8_t int1_drdy                    : 1;
269   uint8_t not_used0                    : 3;
270 #endif /* DRV_BYTE_ORDER */
271 } lis2duxs12_ctrl2_t;
272 
273 #define LIS2DUXS12_CTRL3                                0x12U
274 typedef struct
275 {
276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
277   uint8_t st_sign_x                    : 1;
278   uint8_t st_sign_y                    : 1;
279   uint8_t hp_en                        : 1;
280   uint8_t int2_drdy                    : 1;
281   uint8_t int2_fifo_ovr                : 1;
282   uint8_t int2_fifo_th                 : 1;
283   uint8_t int2_fifo_full               : 1;
284   uint8_t int2_boot                    : 1;
285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
286   uint8_t int2_boot                    : 1;
287   uint8_t int2_fifo_full               : 1;
288   uint8_t int2_fifo_th                 : 1;
289   uint8_t int2_fifo_ovr                : 1;
290   uint8_t int2_drdy                    : 1;
291   uint8_t hp_en                        : 1;
292   uint8_t st_sign_y                    : 1;
293   uint8_t st_sign_x                    : 1;
294 #endif /* DRV_BYTE_ORDER */
295 } lis2duxs12_ctrl3_t;
296 
297 #define LIS2DUXS12_CTRL4                                0x13U
298 typedef struct
299 {
300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
301   uint8_t boot                         : 1;
302   uint8_t soc                          : 1;
303   uint8_t not_used0                    : 1;
304   uint8_t fifo_en                      : 1;
305   uint8_t emb_func_en                  : 1;
306   uint8_t bdu                          : 1;
307   uint8_t inact_odr                    : 2;
308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
309   uint8_t inact_odr                    : 2;
310   uint8_t bdu                          : 1;
311   uint8_t emb_func_en                  : 1;
312   uint8_t fifo_en                      : 1;
313   uint8_t not_used0                    : 1;
314   uint8_t soc                          : 1;
315   uint8_t boot                         : 1;
316 #endif /* DRV_BYTE_ORDER */
317 } lis2duxs12_ctrl4_t;
318 
319 #define LIS2DUXS12_CTRL5                                0x14U
320 typedef struct
321 {
322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
323   uint8_t fs                           : 2;
324   uint8_t bw                           : 2;
325   uint8_t odr                          : 4;
326 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
327   uint8_t odr                          : 4;
328   uint8_t bw                           : 2;
329   uint8_t fs                           : 2;
330 #endif /* DRV_BYTE_ORDER */
331 } lis2duxs12_ctrl5_t;
332 
333 #define LIS2DUXS12_FIFO_CTRL                            0x15U
334 typedef struct
335 {
336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
337   uint8_t fifo_mode                    : 3;
338   uint8_t stop_on_fth                  : 1;
339   uint8_t not_used0                    : 2;
340   uint8_t fifo_depth                   : 1;
341   uint8_t cfg_chg_en                   : 1;
342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
343   uint8_t cfg_chg_en                   : 1;
344   uint8_t fifo_depth                   : 1;
345   uint8_t not_used0                    : 2;
346   uint8_t stop_on_fth                  : 1;
347   uint8_t fifo_mode                    : 3;
348 #endif /* DRV_BYTE_ORDER */
349 } lis2duxs12_fifo_ctrl_t;
350 
351 #define LIS2DUXS12_FIFO_WTM                             0x16U
352 typedef struct
353 {
354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
355   uint8_t fth                          : 7;
356   uint8_t xl_only_fifo                 : 1;
357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
358   uint8_t xl_only_fifo                 : 1;
359   uint8_t fth                          : 7;
360 #endif /* DRV_BYTE_ORDER */
361 } lis2duxs12_fifo_wtm_t;
362 
363 #define LIS2DUXS12_INTERRUPT_CFG                        0x17U
364 typedef struct
365 {
366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
367   uint8_t interrupts_enable            : 1;
368   uint8_t lir                          : 1;
369   uint8_t dis_rst_lir_all_int          : 1;
370   uint8_t sleep_status_on_int          : 1;
371   uint8_t not_used0                    : 1;
372   uint8_t wake_ths_w                   : 1;
373   uint8_t not_used1                    : 1;
374   uint8_t timestamp_en                 : 1;
375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
376   uint8_t timestamp_en                 : 1;
377   uint8_t not_used1                    : 1;
378   uint8_t wake_ths_w                   : 1;
379   uint8_t not_used0                    : 1;
380   uint8_t sleep_status_on_int          : 1;
381   uint8_t dis_rst_lir_all_int          : 1;
382   uint8_t lir                          : 1;
383   uint8_t interrupts_enable            : 1;
384 #endif /* DRV_BYTE_ORDER */
385 } lis2duxs12_interrupt_cfg_t;
386 
387 #define LIS2DUXS12_SIXD                                 0x18U
388 typedef struct
389 {
390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
391   uint8_t not_used0                    : 5;
392   uint8_t d6d_ths                      : 2;
393   uint8_t d4d_en                       : 1;
394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
395   uint8_t d4d_en                       : 1;
396   uint8_t d6d_ths                      : 2;
397   uint8_t not_used0                    : 5;
398 #endif /* DRV_BYTE_ORDER */
399 } lis2duxs12_sixd_t;
400 
401 #define LIS2DUXS12_WAKE_UP_THS                          0x1CU
402 typedef struct
403 {
404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
405   uint8_t wk_ths                       : 6;
406   uint8_t sleep_on                     : 1;
407   uint8_t not_used0                    : 1;
408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
409   uint8_t not_used0                    : 1;
410   uint8_t sleep_on                     : 1;
411   uint8_t wk_ths                       : 6;
412 #endif /* DRV_BYTE_ORDER */
413 } lis2duxs12_wake_up_ths_t;
414 
415 #define LIS2DUXS12_WAKE_UP_DUR                          0x1DU
416 typedef struct
417 {
418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
419   uint8_t sleep_dur                    : 4;
420   uint8_t st_sign_z                    : 1;
421   uint8_t wake_dur                     : 2;
422   uint8_t ff_dur                       : 1;
423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
424   uint8_t ff_dur                       : 1;
425   uint8_t wake_dur                     : 2;
426   uint8_t st_sign_z                    : 1;
427   uint8_t sleep_dur                    : 4;
428 #endif /* DRV_BYTE_ORDER */
429 } lis2duxs12_wake_up_dur_t;
430 
431 #define LIS2DUXS12_FREE_FALL                            0x1EU
432 typedef struct
433 {
434 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
435   uint8_t ff_ths                       : 3;
436   uint8_t ff_dur                       : 5;
437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
438   uint8_t ff_dur                       : 5;
439   uint8_t ff_ths                       : 3;
440 #endif /* DRV_BYTE_ORDER */
441 } lis2duxs12_free_fall_t;
442 
443 #define LIS2DUXS12_MD1_CFG                              0x1FU
444 typedef struct
445 {
446 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
447   uint8_t int1_emb_func                : 1;
448   uint8_t int1_timestamp               : 1;
449   uint8_t int1_6d                      : 1;
450   uint8_t int1_tap                     : 1;
451   uint8_t int1_ff                      : 1;
452   uint8_t int1_wu                      : 1;
453   uint8_t not_used0                    : 1;
454   uint8_t int1_sleep_change            : 1;
455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
456   uint8_t int1_sleep_change            : 1;
457   uint8_t not_used0                    : 1;
458   uint8_t int1_wu                      : 1;
459   uint8_t int1_ff                      : 1;
460   uint8_t int1_tap                     : 1;
461   uint8_t int1_6d                      : 1;
462   uint8_t int1_timestamp               : 1;
463   uint8_t int1_emb_func                : 1;
464 #endif /* DRV_BYTE_ORDER */
465 } lis2duxs12_md1_cfg_t;
466 
467 #define LIS2DUXS12_MD2_CFG                              0x20U
468 typedef struct
469 {
470 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
471   uint8_t int2_emb_func                : 1;
472   uint8_t int2_timestamp               : 1;
473   uint8_t int2_6d                      : 1;
474   uint8_t int2_tap                     : 1;
475   uint8_t int2_ff                      : 1;
476   uint8_t int2_wu                      : 1;
477   uint8_t not_used0                    : 1;
478   uint8_t int2_sleep_change            : 1;
479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
480   uint8_t int2_sleep_change            : 1;
481   uint8_t not_used0                    : 1;
482   uint8_t int2_wu                      : 1;
483   uint8_t int2_ff                      : 1;
484   uint8_t int2_tap                     : 1;
485   uint8_t int2_6d                      : 1;
486   uint8_t int2_timestamp               : 1;
487   uint8_t int2_emb_func                : 1;
488 #endif /* DRV_BYTE_ORDER */
489 } lis2duxs12_md2_cfg_t;
490 
491 #define LIS2DUXS12_WAKE_UP_SRC                          0x21U
492 typedef struct
493 {
494 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
495   uint8_t z_wu                         : 1;
496   uint8_t y_wu                         : 1;
497   uint8_t x_wu                         : 1;
498   uint8_t wu_ia                        : 1;
499   uint8_t sleep_state                  : 1;
500   uint8_t ff_ia                        : 1;
501   uint8_t sleep_change_ia              : 1;
502   uint8_t not_used0                    : 1;
503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
504   uint8_t not_used0                    : 1;
505   uint8_t sleep_change_ia              : 1;
506   uint8_t ff_ia                        : 1;
507   uint8_t sleep_state                  : 1;
508   uint8_t wu_ia                        : 1;
509   uint8_t x_wu                         : 1;
510   uint8_t y_wu                         : 1;
511   uint8_t z_wu                         : 1;
512 #endif /* DRV_BYTE_ORDER */
513 } lis2duxs12_wake_up_src_t;
514 
515 #define LIS2DUXS12_TAP_SRC                              0x22U
516 typedef struct
517 {
518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
519   uint8_t not_used0                    : 4;
520   uint8_t triple_tap_ia                : 1;
521   uint8_t double_tap_ia                : 1;
522   uint8_t single_tap_ia                : 1;
523   uint8_t tap_ia                       : 1;
524 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
525   uint8_t tap_ia                       : 1;
526   uint8_t single_tap_ia                : 1;
527   uint8_t double_tap_ia                : 1;
528   uint8_t triple_tap_ia                : 1;
529   uint8_t not_used0                    : 4;
530 #endif /* DRV_BYTE_ORDER */
531 } lis2duxs12_tap_src_t;
532 
533 #define LIS2DUXS12_SIXD_SRC                             0x23U
534 typedef struct
535 {
536 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
537   uint8_t xl                           : 1;
538   uint8_t xh                           : 1;
539   uint8_t yl                           : 1;
540   uint8_t yh                           : 1;
541   uint8_t zl                           : 1;
542   uint8_t zh                           : 1;
543   uint8_t d6d_ia                       : 1;
544   uint8_t not_used0                    : 1;
545 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
546   uint8_t not_used0                    : 1;
547   uint8_t d6d_ia                       : 1;
548   uint8_t zh                           : 1;
549   uint8_t zl                           : 1;
550   uint8_t yh                           : 1;
551   uint8_t yl                           : 1;
552   uint8_t xh                           : 1;
553   uint8_t xl                           : 1;
554 #endif /* DRV_BYTE_ORDER */
555 } lis2duxs12_sixd_src_t;
556 
557 #define LIS2DUXS12_ALL_INT_SRC                          0x24U
558 typedef struct
559 {
560 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
561   uint8_t ff_ia_all                    : 1;
562   uint8_t wu_ia_all                    : 1;
563   uint8_t single_tap_all               : 1;
564   uint8_t double_tap_all               : 1;
565   uint8_t triple_tap_all               : 1;
566   uint8_t d6d_ia_all                   : 1;
567   uint8_t sleep_change_ia_all          : 1;
568   uint8_t not_used0                    : 1;
569 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
570   uint8_t not_used0                    : 1;
571   uint8_t sleep_change_ia_all          : 1;
572   uint8_t d6d_ia_all                   : 1;
573   uint8_t triple_tap_all               : 1;
574   uint8_t double_tap_all               : 1;
575   uint8_t single_tap_all               : 1;
576   uint8_t wu_ia_all                    : 1;
577   uint8_t ff_ia_all                    : 1;
578 #endif /* DRV_BYTE_ORDER */
579 } lis2duxs12_all_int_src_t;
580 
581 #define LIS2DUXS12_STATUS                               0x25U
582 typedef struct
583 {
584 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
585   uint8_t drdy                         : 1;
586   uint8_t not_used0                    : 4;
587   uint8_t int_global                   : 1;
588   uint8_t not_used1                    : 2;
589 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
590   uint8_t not_used1                    : 2;
591   uint8_t int_global                   : 1;
592   uint8_t not_used0                    : 4;
593   uint8_t drdy                         : 1;
594 #endif /* DRV_BYTE_ORDER */
595 } lis2duxs12_status_register_t;
596 
597 #define LIS2DUXS12_FIFO_STATUS1                         0x26U
598 typedef struct
599 {
600 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
601   uint8_t not_used0                    : 6;
602   uint8_t fifo_ovr_ia                  : 1;
603   uint8_t fifo_wtm_ia                  : 1;
604 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
605   uint8_t fifo_wtm_ia                  : 1;
606   uint8_t fifo_ovr_ia                  : 1;
607   uint8_t not_used0                    : 6;
608 #endif /* DRV_BYTE_ORDER */
609 } lis2duxs12_fifo_status1_t;
610 
611 #define LIS2DUXS12_FIFO_STATUS2                         0x27U
612 typedef struct
613 {
614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
615   uint8_t fss                          : 8;
616 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
617   uint8_t fss                          : 8;
618 #endif /* DRV_BYTE_ORDER */
619 } lis2duxs12_fifo_status2_t;
620 
621 #define LIS2DUXS12_OUT_X_L                              0x28U
622 typedef struct
623 {
624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
625   uint8_t outx                         : 8;
626 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
627   uint8_t outx                         : 8;
628 #endif /* DRV_BYTE_ORDER */
629 } lis2duxs12_out_x_l_t;
630 
631 #define LIS2DUXS12_OUT_X_H                              0x29U
632 typedef struct
633 {
634 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
635   uint8_t outx                         : 8;
636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
637   uint8_t outx                         : 8;
638 #endif /* DRV_BYTE_ORDER */
639 } lis2duxs12_out_x_h_t;
640 
641 #define LIS2DUXS12_OUT_Y_L                              0x2AU
642 typedef struct
643 {
644 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
645   uint8_t outy                         : 8;
646 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
647   uint8_t outy                         : 8;
648 #endif /* DRV_BYTE_ORDER */
649 } lis2duxs12_out_y_l_t;
650 
651 #define LIS2DUXS12_OUT_Y_H                              0x2BU
652 typedef struct
653 {
654 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
655   uint8_t outy                         : 8;
656 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
657   uint8_t outy                         : 8;
658 #endif /* DRV_BYTE_ORDER */
659 } lis2duxs12_out_y_h_t;
660 
661 #define LIS2DUXS12_OUT_Z_L                              0x2CU
662 typedef struct
663 {
664 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
665   uint8_t outz                         : 8;
666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
667   uint8_t outz                         : 8;
668 #endif /* DRV_BYTE_ORDER */
669 } lis2duxs12_out_z_l_t;
670 
671 #define LIS2DUXS12_OUT_Z_H                              0x2DU
672 typedef struct
673 {
674 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
675   uint8_t outz                         : 8;
676 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
677   uint8_t outz                         : 8;
678 #endif /* DRV_BYTE_ORDER */
679 } lis2duxs12_out_z_h_t;
680 
681 #define LIS2DUXS12_OUT_T_AH_QVAR_L                      0x2EU
682 typedef struct
683 {
684 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
685   uint8_t outt                         : 8;
686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
687   uint8_t outt                         : 8;
688 #endif /* DRV_BYTE_ORDER */
689 } lis2duxs12_out_t_ah_qvar_l_t;
690 
691 #define LIS2DUXS12_OUT_T_AH_QVAR_H                      0x2FU
692 typedef struct
693 {
694 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
695   uint8_t outt                         : 8;
696 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
697   uint8_t outt                         : 8;
698 #endif /* DRV_BYTE_ORDER */
699 } lis2duxs12_out_t_ah_qvar_h_t;
700 
701 #define LIS2DUXS12_AH_QVAR_CFG                          0x31U
702 typedef struct
703 {
704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
705   uint8_t not_used0                    : 1;
706   uint8_t ah_qvar_gain                 : 2;
707   uint8_t ah_qvar_c_zin                : 2;
708   uint8_t ah_qvar_notch_cutoff         : 1;
709   uint8_t ah_qvar_notch_en             : 1;
710   uint8_t ah_qvar_en                   : 1;
711 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
712   uint8_t ah_qvar_en                   : 1;
713   uint8_t ah_qvar_notch_en             : 1;
714   uint8_t ah_qvar_notch_cutoff         : 1;
715   uint8_t ah_qvar_c_zin                : 2;
716   uint8_t ah_qvar_gain                 : 2;
717   uint8_t not_used0                    : 1;
718 #endif /* DRV_BYTE_ORDER */
719 } lis2duxs12_ah_qvar_cfg_t;
720 
721 #define LIS2DUXS12_SELF_TEST                            0x32U
722 typedef struct
723 {
724 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
725   uint8_t not_used0                    : 4;
726   uint8_t st                           : 2;
727   uint8_t not_used1                    : 2;
728 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
729   uint8_t not_used1                    : 2;
730   uint8_t st                           : 2;
731   uint8_t not_used0                    : 4;
732 #endif /* DRV_BYTE_ORDER */
733 } lis2duxs12_self_test_t;
734 
735 #define LIS2DUXS12_I3C_IF_CTRL                          0x33U
736 typedef struct
737 {
738 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
739   uint8_t bus_act_sel                  : 2;
740   uint8_t not_used0                    : 3;
741   uint8_t asf_on                       : 1;
742   uint8_t dis_drstdaa                  : 1;
743   uint8_t not_used1                    : 1;
744 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
745   uint8_t not_used1                    : 1;
746   uint8_t dis_drstdaa                  : 1;
747   uint8_t asf_on                       : 1;
748   uint8_t not_used0                    : 3;
749   uint8_t bus_act_sel                  : 2;
750 #endif /* DRV_BYTE_ORDER */
751 } lis2duxs12_i3c_if_ctrl_t;
752 
753 #define LIS2DUXS12_EMB_FUNC_STATUS_MAINPAGE             0x34U
754 typedef struct
755 {
756 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
757   uint8_t not_used0                    : 3;
758   uint8_t is_step_det                  : 1;
759   uint8_t is_tilt                      : 1;
760   uint8_t is_sigmot                    : 1;
761   uint8_t not_used1                    : 1;
762   uint8_t is_fsm_lc                    : 1;
763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
764   uint8_t is_fsm_lc                    : 1;
765   uint8_t not_used1                    : 1;
766   uint8_t is_sigmot                    : 1;
767   uint8_t is_tilt                      : 1;
768   uint8_t is_step_det                  : 1;
769   uint8_t not_used0                    : 3;
770 #endif /* DRV_BYTE_ORDER */
771 } lis2duxs12_emb_func_status_mainpage_t;
772 
773 #define LIS2DUXS12_FSM_STATUS_MAINPAGE                  0x35U
774 typedef struct
775 {
776 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
777   uint8_t is_fsm1                      : 1;
778   uint8_t is_fsm2                      : 1;
779   uint8_t is_fsm3                      : 1;
780   uint8_t is_fsm4                      : 1;
781   uint8_t is_fsm5                      : 1;
782   uint8_t is_fsm6                      : 1;
783   uint8_t is_fsm7                      : 1;
784   uint8_t is_fsm8                      : 1;
785 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
786   uint8_t is_fsm8                      : 1;
787   uint8_t is_fsm7                      : 1;
788   uint8_t is_fsm6                      : 1;
789   uint8_t is_fsm5                      : 1;
790   uint8_t is_fsm4                      : 1;
791   uint8_t is_fsm3                      : 1;
792   uint8_t is_fsm2                      : 1;
793   uint8_t is_fsm1                      : 1;
794 #endif /* DRV_BYTE_ORDER */
795 } lis2duxs12_fsm_status_mainpage_t;
796 
797 #define LIS2DUXS12_MLC_STATUS_MAINPAGE                  0x36U
798 typedef struct
799 {
800 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
801   uint8_t is_mlc1                      : 1;
802   uint8_t is_mlc2                      : 1;
803   uint8_t is_mlc3                      : 1;
804   uint8_t is_mlc4                      : 1;
805   uint8_t not_used0                    : 4;
806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
807   uint8_t not_used0                    : 4;
808   uint8_t is_mlc4                      : 1;
809   uint8_t is_mlc3                      : 1;
810   uint8_t is_mlc2                      : 1;
811   uint8_t is_mlc1                      : 1;
812 #endif /* DRV_BYTE_ORDER */
813 } lis2duxs12_mlc_status_mainpage_t;
814 
815 #define LIS2DUXS12_SLEEP                                0x3DU
816 typedef struct
817 {
818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
819   uint8_t deep_pd                      : 1;
820   uint8_t not_used0                    : 7;
821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
822   uint8_t not_used0                    : 7;
823   uint8_t deep_pd                      : 1;
824 #endif /* DRV_BYTE_ORDER */
825 } lis2duxs12_sleep_t;
826 
827 #define LIS2DUXS12_IF_WAKE_UP                           0x3EU
828 typedef struct
829 {
830 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
831   uint8_t soft_pd                      : 1;
832   uint8_t not_used0                    : 7;
833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
834   uint8_t not_used0                    : 7;
835   uint8_t soft_pd                      : 1;
836 #endif /* DRV_BYTE_ORDER */
837 } lis2duxs12_if_wake_up_t;
838 
839 #define LIS2DUXS12_FUNC_CFG_ACCESS                      0x3FU
840 typedef struct
841 {
842 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
843   uint8_t fsm_wr_ctrl_en               : 1;
844   uint8_t not_used0                    : 6;
845   uint8_t emb_func_reg_access          : 1;
846 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
847   uint8_t emb_func_reg_access          : 1;
848   uint8_t not_used0                    : 6;
849   uint8_t fsm_wr_ctrl_en               : 1;
850 #endif /* DRV_BYTE_ORDER */
851 } lis2duxs12_func_cfg_access_t;
852 
853 #define LIS2DUXS12_FIFO_DATA_OUT_TAG                    0x40U
854 typedef struct
855 {
856 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
857   uint8_t not_used0                    : 3;
858   uint8_t tag_sensor                   : 5;
859 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
860   uint8_t tag_sensor                   : 5;
861   uint8_t not_used0                    : 3;
862 #endif /* DRV_BYTE_ORDER */
863 } lis2duxs12_fifo_data_out_tag_t;
864 
865 #define LIS2DUXS12_FIFO_DATA_OUT_X_L                    0x41U
866 typedef struct
867 {
868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
869   uint8_t fifo_data_out                : 8;
870 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
871   uint8_t fifo_data_out                : 8;
872 #endif /* DRV_BYTE_ORDER */
873 } lis2duxs12_fifo_data_out_x_l_t;
874 
875 #define LIS2DUXS12_FIFO_DATA_OUT_X_H                    0x42U
876 typedef struct
877 {
878 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
879   uint8_t fifo_data_out                : 8;
880 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
881   uint8_t fifo_data_out                : 8;
882 #endif /* DRV_BYTE_ORDER */
883 } lis2duxs12_fifo_data_out_x_h_t;
884 
885 #define LIS2DUXS12_FIFO_DATA_OUT_Y_L                    0x43U
886 typedef struct
887 {
888 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
889   uint8_t fifo_data_out                : 8;
890 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
891   uint8_t fifo_data_out                : 8;
892 #endif /* DRV_BYTE_ORDER */
893 } lis2duxs12_fifo_data_out_y_l_t;
894 
895 #define LIS2DUXS12_FIFO_DATA_OUT_Y_H                    0x44U
896 typedef struct
897 {
898 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
899   uint8_t fifo_data_out                : 8;
900 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
901   uint8_t fifo_data_out                : 8;
902 #endif /* DRV_BYTE_ORDER */
903 } lis2duxs12_fifo_data_out_y_h_t;
904 
905 #define LIS2DUXS12_FIFO_DATA_OUT_Z_L                    0x45U
906 typedef struct
907 {
908 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
909   uint8_t fifo_data_out                : 8;
910 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
911   uint8_t fifo_data_out                : 8;
912 #endif /* DRV_BYTE_ORDER */
913 } lis2duxs12_fifo_data_out_z_l_t;
914 
915 #define LIS2DUXS12_FIFO_DATA_OUT_Z_H                    0x46U
916 typedef struct
917 {
918 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
919   uint8_t fifo_data_out                : 8;
920 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
921   uint8_t fifo_data_out                : 8;
922 #endif /* DRV_BYTE_ORDER */
923 } lis2duxs12_fifo_data_out_z_h_t;
924 
925 #define LIS2DUXS12_FIFO_BATCH_DEC                       0x47U
926 typedef struct
927 {
928 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
929   uint8_t bdr_xl                       : 3;
930   uint8_t dec_ts_batch                 : 2;
931   uint8_t not_used0                    : 3;
932 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
933   uint8_t not_used0                    : 3;
934   uint8_t dec_ts_batch                 : 2;
935   uint8_t bdr_xl                       : 3;
936 #endif /* DRV_BYTE_ORDER */
937 } lis2duxs12_fifo_batch_dec_t;
938 
939 #define LIS2DUXS12_TAP_CFG0                             0x6FU
940 typedef struct
941 {
942 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
943   uint8_t not_used0                    : 1;
944   uint8_t invert_t                     : 5;
945   uint8_t axis                         : 2;
946 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
947   uint8_t axis                         : 2;
948   uint8_t invert_t                     : 5;
949   uint8_t not_used0                    : 1;
950 #endif /* DRV_BYTE_ORDER */
951 } lis2duxs12_tap_cfg0_t;
952 
953 #define LIS2DUXS12_TAP_CFG1                             0x70U
954 typedef struct
955 {
956 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
957   uint8_t post_still_t                 : 4;
958   uint8_t pre_still_ths                : 4;
959 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
960   uint8_t pre_still_ths                : 4;
961   uint8_t post_still_t                 : 4;
962 #endif /* DRV_BYTE_ORDER */
963 } lis2duxs12_tap_cfg1_t;
964 
965 #define LIS2DUXS12_TAP_CFG2                             0x71U
966 typedef struct
967 {
968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
969   uint8_t wait_t                       : 6;
970   uint8_t post_still_t                 : 2;
971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
972   uint8_t post_still_t                 : 2;
973   uint8_t wait_t                       : 6;
974 #endif /* DRV_BYTE_ORDER */
975 } lis2duxs12_tap_cfg2_t;
976 
977 #define LIS2DUXS12_TAP_CFG3                             0x72U
978 typedef struct
979 {
980 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
981   uint8_t latency_t                    : 4;
982   uint8_t post_still_ths               : 4;
983 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
984   uint8_t post_still_ths               : 4;
985   uint8_t latency_t                    : 4;
986 #endif /* DRV_BYTE_ORDER */
987 } lis2duxs12_tap_cfg3_t;
988 
989 #define LIS2DUXS12_TAP_CFG4                             0x73U
990 typedef struct
991 {
992 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
993   uint8_t peak_ths                     : 6;
994   uint8_t not_used0                    : 1;
995   uint8_t wait_end_latency             : 1;
996 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
997   uint8_t wait_end_latency             : 1;
998   uint8_t not_used0                    : 1;
999   uint8_t peak_ths                     : 6;
1000 #endif /* DRV_BYTE_ORDER */
1001 } lis2duxs12_tap_cfg4_t;
1002 
1003 #define LIS2DUXS12_TAP_CFG5                             0x74U
1004 typedef struct
1005 {
1006 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1007   uint8_t rebound_t                    : 5;
1008   uint8_t single_tap_en                : 1;
1009   uint8_t double_tap_en                : 1;
1010   uint8_t triple_tap_en                : 1;
1011 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1012   uint8_t triple_tap_en                : 1;
1013   uint8_t double_tap_en                : 1;
1014   uint8_t single_tap_en                : 1;
1015   uint8_t rebound_t                    : 5;
1016 #endif /* DRV_BYTE_ORDER */
1017 } lis2duxs12_tap_cfg5_t;
1018 
1019 #define LIS2DUXS12_TAP_CFG6                             0x75U
1020 typedef struct
1021 {
1022 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1023   uint8_t pre_still_n                  : 4;
1024   uint8_t pre_still_st                 : 4;
1025 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1026   uint8_t pre_still_st                 : 4;
1027   uint8_t pre_still_n                  : 4;
1028 #endif /* DRV_BYTE_ORDER */
1029 } lis2duxs12_tap_cfg6_t;
1030 
1031 #define LIS2DUXS12_TIMESTAMP0                           0x7AU
1032 typedef struct
1033 {
1034 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1035   uint8_t timestamp                    : 8;
1036 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1037   uint8_t timestamp                    : 8;
1038 #endif /* DRV_BYTE_ORDER */
1039 } lis2duxs12_timestamp0_t;
1040 
1041 #define LIS2DUXS12_TIMESTAMP1                           0x7BU
1042 typedef struct
1043 {
1044 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1045   uint8_t timestamp                    : 8;
1046 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1047   uint8_t timestamp                    : 8;
1048 #endif /* DRV_BYTE_ORDER */
1049 } lis2duxs12_timestamp1_t;
1050 
1051 #define LIS2DUXS12_TIMESTAMP2                           0x7CU
1052 typedef struct
1053 {
1054 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1055   uint8_t timestamp                    : 8;
1056 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1057   uint8_t timestamp                    : 8;
1058 #endif /* DRV_BYTE_ORDER */
1059 } lis2duxs12_timestamp2_t;
1060 
1061 #define LIS2DUXS12_TIMESTAMP3                           0x7DU
1062 typedef struct
1063 {
1064 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1065   uint8_t timestamp                    : 8;
1066 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1067   uint8_t timestamp                    : 8;
1068 #endif /* DRV_BYTE_ORDER */
1069 } lis2duxs12_timestamp3_t;
1070 
1071 /**
1072   * @}
1073   *
1074   */
1075 
1076 /** @defgroup bitfields page embedded
1077   * @{
1078   *
1079   */
1080 
1081 #define LIS2DUXS12_PAGE_SEL                             0x2U
1082 typedef struct
1083 {
1084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1085   uint8_t not_used0                    : 4;
1086   uint8_t page_sel                     : 4;
1087 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1088   uint8_t page_sel                     : 4;
1089   uint8_t not_used0                    : 4;
1090 #endif /* DRV_BYTE_ORDER */
1091 } lis2duxs12_page_sel_t;
1092 
1093 #define LIS2DUXS12_EMB_FUNC_EN_A                        0x4U
1094 typedef struct
1095 {
1096 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1097   uint8_t not_used0                    : 3;
1098   uint8_t pedo_en                      : 1;
1099   uint8_t tilt_en                      : 1;
1100   uint8_t sign_motion_en               : 1;
1101   uint8_t not_used1                    : 1;
1102   uint8_t mlc_before_fsm_en            : 1;
1103 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1104   uint8_t mlc_before_fsm_en            : 1;
1105   uint8_t not_used1                    : 1;
1106   uint8_t sign_motion_en               : 1;
1107   uint8_t tilt_en                      : 1;
1108   uint8_t pedo_en                      : 1;
1109   uint8_t not_used0                    : 3;
1110 #endif /* DRV_BYTE_ORDER */
1111 } lis2duxs12_emb_func_en_a_t;
1112 
1113 #define LIS2DUXS12_EMB_FUNC_EN_B                        0x5U
1114 typedef struct
1115 {
1116 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1117   uint8_t fsm_en                       : 1;
1118   uint8_t not_used0                    : 3;
1119   uint8_t mlc_en                       : 1;
1120   uint8_t not_used1                    : 3;
1121 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1122   uint8_t not_used1                    : 3;
1123   uint8_t mlc_en                       : 1;
1124   uint8_t not_used0                    : 3;
1125   uint8_t fsm_en                       : 1;
1126 #endif /* DRV_BYTE_ORDER */
1127 } lis2duxs12_emb_func_en_b_t;
1128 
1129 #define LIS2DUXS12_EMB_FUNC_EXEC_STATUS                 0x7U
1130 typedef struct
1131 {
1132 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1133   uint8_t emb_func_endop               : 1;
1134   uint8_t emb_func_exec_ovr            : 1;
1135   uint8_t not_used0                    : 6;
1136 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1137   uint8_t not_used0                    : 6;
1138   uint8_t emb_func_exec_ovr            : 1;
1139   uint8_t emb_func_endop               : 1;
1140 #endif /* DRV_BYTE_ORDER */
1141 } lis2duxs12_emb_func_exec_status_t;
1142 
1143 #define LIS2DUXS12_PAGE_ADDRESS                         0x8U
1144 typedef struct
1145 {
1146 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1147   uint8_t page_addr                    : 8;
1148 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1149   uint8_t page_addr                    : 8;
1150 #endif /* DRV_BYTE_ORDER */
1151 } lis2duxs12_page_address_t;
1152 
1153 #define LIS2DUXS12_PAGE_VALUE                           0x9U
1154 typedef struct
1155 {
1156 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1157   uint8_t page_value                   : 8;
1158 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1159   uint8_t page_value                   : 8;
1160 #endif /* DRV_BYTE_ORDER */
1161 } lis2duxs12_page_value_t;
1162 
1163 #define LIS2DUXS12_EMB_FUNC_INT1                        0x0AU
1164 typedef struct
1165 {
1166 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1167   uint8_t not_used0                    : 3;
1168   uint8_t int1_step_det                : 1;
1169   uint8_t int1_tilt                    : 1;
1170   uint8_t int1_sig_mot                 : 1;
1171   uint8_t not_used1                    : 1;
1172   uint8_t int1_fsm_lc                  : 1;
1173 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1174   uint8_t int1_fsm_lc                  : 1;
1175   uint8_t not_used1                    : 1;
1176   uint8_t int1_sig_mot                 : 1;
1177   uint8_t int1_tilt                    : 1;
1178   uint8_t int1_step_det                : 1;
1179   uint8_t not_used0                    : 3;
1180 #endif /* DRV_BYTE_ORDER */
1181 } lis2duxs12_emb_func_int1_t;
1182 
1183 #define LIS2DUXS12_FSM_INT1                             0x0BU
1184 typedef struct
1185 {
1186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1187   uint8_t int1_fsm1                    : 1;
1188   uint8_t int1_fsm2                    : 1;
1189   uint8_t int1_fsm3                    : 1;
1190   uint8_t int1_fsm4                    : 1;
1191   uint8_t int1_fsm5                    : 1;
1192   uint8_t int1_fsm6                    : 1;
1193   uint8_t int1_fsm7                    : 1;
1194   uint8_t int1_fsm8                    : 1;
1195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1196   uint8_t int1_fsm8                    : 1;
1197   uint8_t int1_fsm7                    : 1;
1198   uint8_t int1_fsm6                    : 1;
1199   uint8_t int1_fsm5                    : 1;
1200   uint8_t int1_fsm4                    : 1;
1201   uint8_t int1_fsm3                    : 1;
1202   uint8_t int1_fsm2                    : 1;
1203   uint8_t int1_fsm1                    : 1;
1204 #endif /* DRV_BYTE_ORDER */
1205 } lis2duxs12_fsm_int1_t;
1206 
1207 #define LIS2DUXS12_MLC_INT1                             0x0DU
1208 typedef struct
1209 {
1210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1211   uint8_t int1_mlc1                    : 1;
1212   uint8_t int1_mlc2                    : 1;
1213   uint8_t int1_mlc3                    : 1;
1214   uint8_t int1_mlc4                    : 1;
1215   uint8_t not_used0                    : 4;
1216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1217   uint8_t not_used0                    : 4;
1218   uint8_t int1_mlc4                    : 1;
1219   uint8_t int1_mlc3                    : 1;
1220   uint8_t int1_mlc2                    : 1;
1221   uint8_t int1_mlc1                    : 1;
1222 #endif /* DRV_BYTE_ORDER */
1223 } lis2duxs12_mlc_int1_t;
1224 
1225 #define LIS2DUXS12_EMB_FUNC_INT2                        0x0EU
1226 typedef struct
1227 {
1228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1229   uint8_t not_used0                    : 3;
1230   uint8_t int2_step_det                : 1;
1231   uint8_t int2_tilt                    : 1;
1232   uint8_t int2_sig_mot                 : 1;
1233   uint8_t not_used1                    : 1;
1234   uint8_t int2_fsm_lc                  : 1;
1235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1236   uint8_t int2_fsm_lc                  : 1;
1237   uint8_t not_used1                    : 1;
1238   uint8_t int2_sig_mot                 : 1;
1239   uint8_t int2_tilt                    : 1;
1240   uint8_t int2_step_det                : 1;
1241   uint8_t not_used0                    : 3;
1242 #endif /* DRV_BYTE_ORDER */
1243 } lis2duxs12_emb_func_int2_t;
1244 
1245 #define LIS2DUXS12_FSM_INT2                             0x0FU
1246 typedef struct
1247 {
1248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1249   uint8_t int2_fsm1                    : 1;
1250   uint8_t int2_fsm2                    : 1;
1251   uint8_t int2_fsm3                    : 1;
1252   uint8_t int2_fsm4                    : 1;
1253   uint8_t int2_fsm5                    : 1;
1254   uint8_t int2_fsm6                    : 1;
1255   uint8_t int2_fsm7                    : 1;
1256   uint8_t int2_fsm8                    : 1;
1257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1258   uint8_t int2_fsm8                    : 1;
1259   uint8_t int2_fsm7                    : 1;
1260   uint8_t int2_fsm6                    : 1;
1261   uint8_t int2_fsm5                    : 1;
1262   uint8_t int2_fsm4                    : 1;
1263   uint8_t int2_fsm3                    : 1;
1264   uint8_t int2_fsm2                    : 1;
1265   uint8_t int2_fsm1                    : 1;
1266 #endif /* DRV_BYTE_ORDER */
1267 } lis2duxs12_fsm_int2_t;
1268 
1269 #define LIS2DUXS12_MLC_INT2                             0x11U
1270 typedef struct
1271 {
1272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1273   uint8_t int2_mlc1                    : 1;
1274   uint8_t int2_mlc2                    : 1;
1275   uint8_t int2_mlc3                    : 1;
1276   uint8_t int2_mlc4                    : 1;
1277   uint8_t not_used0                    : 4;
1278 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1279   uint8_t not_used0                    : 4;
1280   uint8_t int2_mlc4                    : 1;
1281   uint8_t int2_mlc3                    : 1;
1282   uint8_t int2_mlc2                    : 1;
1283   uint8_t int2_mlc1                    : 1;
1284 #endif /* DRV_BYTE_ORDER */
1285 } lis2duxs12_mlc_int2_t;
1286 
1287 #define LIS2DUXS12_EMB_FUNC_STATUS                      0x12U
1288 typedef struct
1289 {
1290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1291   uint8_t not_used0                    : 3;
1292   uint8_t is_step_det                  : 1;
1293   uint8_t is_tilt                      : 1;
1294   uint8_t is_sigmot                    : 1;
1295   uint8_t not_used1                    : 1;
1296   uint8_t is_fsm_lc                    : 1;
1297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1298   uint8_t is_fsm_lc                    : 1;
1299   uint8_t not_used1                    : 1;
1300   uint8_t is_sigmot                    : 1;
1301   uint8_t is_tilt                      : 1;
1302   uint8_t is_step_det                  : 1;
1303   uint8_t not_used0                    : 3;
1304 #endif /* DRV_BYTE_ORDER */
1305 } lis2duxs12_emb_func_status_t;
1306 
1307 #define LIS2DUXS12_FSM_STATUS                           0x13U
1308 typedef struct
1309 {
1310 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1311   uint8_t is_fsm1                      : 1;
1312   uint8_t is_fsm2                      : 1;
1313   uint8_t is_fsm3                      : 1;
1314   uint8_t is_fsm4                      : 1;
1315   uint8_t is_fsm5                      : 1;
1316   uint8_t is_fsm6                      : 1;
1317   uint8_t is_fsm7                      : 1;
1318   uint8_t is_fsm8                      : 1;
1319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1320   uint8_t is_fsm8                      : 1;
1321   uint8_t is_fsm7                      : 1;
1322   uint8_t is_fsm6                      : 1;
1323   uint8_t is_fsm5                      : 1;
1324   uint8_t is_fsm4                      : 1;
1325   uint8_t is_fsm3                      : 1;
1326   uint8_t is_fsm2                      : 1;
1327   uint8_t is_fsm1                      : 1;
1328 #endif /* DRV_BYTE_ORDER */
1329 } lis2duxs12_fsm_status_t;
1330 
1331 #define LIS2DUXS12_MLC_STATUS                           0x15U
1332 typedef struct
1333 {
1334 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1335   uint8_t is_mlc1                      : 1;
1336   uint8_t is_mlc2                      : 1;
1337   uint8_t is_mlc3                      : 1;
1338   uint8_t is_mlc4                      : 1;
1339   uint8_t not_used0                    : 4;
1340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1341   uint8_t not_used0                    : 4;
1342   uint8_t is_mlc4                      : 1;
1343   uint8_t is_mlc3                      : 1;
1344   uint8_t is_mlc2                      : 1;
1345   uint8_t is_mlc1                      : 1;
1346 #endif /* DRV_BYTE_ORDER */
1347 } lis2duxs12_mlc_status_t;
1348 
1349 #define LIS2DUXS12_PAGE_RW                              0x17U
1350 typedef struct
1351 {
1352 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1353   uint8_t not_used0                    : 5;
1354   uint8_t page_read                    : 1;
1355   uint8_t page_write                   : 1;
1356   uint8_t emb_func_lir                 : 1;
1357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1358   uint8_t emb_func_lir                 : 1;
1359   uint8_t page_write                   : 1;
1360   uint8_t page_read                    : 1;
1361   uint8_t not_used0                    : 5;
1362 #endif /* DRV_BYTE_ORDER */
1363 } lis2duxs12_page_rw_t;
1364 
1365 #define LIS2DUXS12_EMB_FUNC_FIFO_EN                     0x18U
1366 typedef struct
1367 {
1368 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1369   uint8_t step_counter_fifo_en         : 1;
1370   uint8_t mlc_fifo_en                  : 1;
1371   uint8_t mlc_filter_feature_fifo_en   : 1;
1372   uint8_t fsm_fifo_en                  : 1;
1373   uint8_t not_used0                    : 4;
1374 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1375   uint8_t not_used0                    : 4;
1376   uint8_t fsm_fifo_en                  : 1;
1377   uint8_t mlc_filter_feature_fifo_en   : 1;
1378   uint8_t mlc_fifo_en                  : 1;
1379   uint8_t step_counter_fifo_en         : 1;
1380 #endif /* DRV_BYTE_ORDER */
1381 } lis2duxs12_emb_func_fifo_en_t;
1382 
1383 #define LIS2DUXS12_FSM_ENABLE                           0x1AU
1384 typedef struct
1385 {
1386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1387   uint8_t fsm1_en                      : 1;
1388   uint8_t fsm2_en                      : 1;
1389   uint8_t fsm3_en                      : 1;
1390   uint8_t fsm4_en                      : 1;
1391   uint8_t fsm5_en                      : 1;
1392   uint8_t fsm6_en                      : 1;
1393   uint8_t fsm7_en                      : 1;
1394   uint8_t fsm8_en                      : 1;
1395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1396   uint8_t fsm8_en                      : 1;
1397   uint8_t fsm7_en                      : 1;
1398   uint8_t fsm6_en                      : 1;
1399   uint8_t fsm5_en                      : 1;
1400   uint8_t fsm4_en                      : 1;
1401   uint8_t fsm3_en                      : 1;
1402   uint8_t fsm2_en                      : 1;
1403   uint8_t fsm1_en                      : 1;
1404 #endif /* DRV_BYTE_ORDER */
1405 } lis2duxs12_fsm_enable_t;
1406 
1407 #define LIS2DUXS12_FSM_LONG_COUNTER_L                   0x1CU
1408 typedef struct
1409 {
1410 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1411   uint8_t fsm_lc                       : 8;
1412 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1413   uint8_t fsm_lc                       : 8;
1414 #endif /* DRV_BYTE_ORDER */
1415 } lis2duxs12_fsm_long_counter_l_t;
1416 
1417 #define LIS2DUXS12_FSM_LONG_COUNTER_H                   0x1DU
1418 typedef struct
1419 {
1420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1421   uint8_t fsm_lc                       : 8;
1422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1423   uint8_t fsm_lc                       : 8;
1424 #endif /* DRV_BYTE_ORDER */
1425 } lis2duxs12_fsm_long_counter_h_t;
1426 
1427 #define LIS2DUXS12_INT_ACK_MASK                         0x1FU
1428 typedef struct
1429 {
1430 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1431   uint8_t iack_mask0                   : 1;
1432   uint8_t iack_mask1                   : 1;
1433   uint8_t iack_mask2                   : 1;
1434   uint8_t iack_mask3                   : 1;
1435   uint8_t iack_mask4                   : 1;
1436   uint8_t iack_mask5                   : 1;
1437   uint8_t iack_mask6                   : 1;
1438   uint8_t iack_mask7                   : 1;
1439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1440   uint8_t iack_mask7                   : 1;
1441   uint8_t iack_mask6                   : 1;
1442   uint8_t iack_mask5                   : 1;
1443   uint8_t iack_mask4                   : 1;
1444   uint8_t iack_mask3                   : 1;
1445   uint8_t iack_mask2                   : 1;
1446   uint8_t iack_mask1                   : 1;
1447   uint8_t iack_mask0                   : 1;
1448 #endif /* DRV_BYTE_ORDER */
1449 } lis2duxs12_int_ack_mask_t;
1450 
1451 #define LIS2DUXS12_FSM_OUTS1                            0x20U
1452 typedef struct
1453 {
1454 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1455   uint8_t n_v                          : 1;
1456   uint8_t p_v                          : 1;
1457   uint8_t n_z                          : 1;
1458   uint8_t p_z                          : 1;
1459   uint8_t n_y                          : 1;
1460   uint8_t p_y                          : 1;
1461   uint8_t n_x                          : 1;
1462   uint8_t p_x                          : 1;
1463 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1464   uint8_t p_x                          : 1;
1465   uint8_t n_x                          : 1;
1466   uint8_t p_y                          : 1;
1467   uint8_t n_y                          : 1;
1468   uint8_t p_z                          : 1;
1469   uint8_t n_z                          : 1;
1470   uint8_t p_v                          : 1;
1471   uint8_t n_v                          : 1;
1472 #endif /* DRV_BYTE_ORDER */
1473 } lis2duxs12_fsm_outs1_t;
1474 
1475 #define LIS2DUXS12_FSM_OUTS2                            0x21U
1476 typedef struct
1477 {
1478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1479   uint8_t n_v                          : 1;
1480   uint8_t p_v                          : 1;
1481   uint8_t n_z                          : 1;
1482   uint8_t p_z                          : 1;
1483   uint8_t n_y                          : 1;
1484   uint8_t p_y                          : 1;
1485   uint8_t n_x                          : 1;
1486   uint8_t p_x                          : 1;
1487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1488   uint8_t p_x                          : 1;
1489   uint8_t n_x                          : 1;
1490   uint8_t p_y                          : 1;
1491   uint8_t n_y                          : 1;
1492   uint8_t p_z                          : 1;
1493   uint8_t n_z                          : 1;
1494   uint8_t p_v                          : 1;
1495   uint8_t n_v                          : 1;
1496 #endif /* DRV_BYTE_ORDER */
1497 } lis2duxs12_fsm_outs2_t;
1498 
1499 #define LIS2DUXS12_FSM_OUTS3                            0x22U
1500 typedef struct
1501 {
1502 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1503   uint8_t n_v                          : 1;
1504   uint8_t p_v                          : 1;
1505   uint8_t n_z                          : 1;
1506   uint8_t p_z                          : 1;
1507   uint8_t n_y                          : 1;
1508   uint8_t p_y                          : 1;
1509   uint8_t n_x                          : 1;
1510   uint8_t p_x                          : 1;
1511 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1512   uint8_t p_x                          : 1;
1513   uint8_t n_x                          : 1;
1514   uint8_t p_y                          : 1;
1515   uint8_t n_y                          : 1;
1516   uint8_t p_z                          : 1;
1517   uint8_t n_z                          : 1;
1518   uint8_t p_v                          : 1;
1519   uint8_t n_v                          : 1;
1520 #endif /* DRV_BYTE_ORDER */
1521 } lis2duxs12_fsm_outs3_t;
1522 
1523 #define LIS2DUXS12_FSM_OUTS4                            0x23U
1524 typedef struct
1525 {
1526 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1527   uint8_t n_v                          : 1;
1528   uint8_t p_v                          : 1;
1529   uint8_t n_z                          : 1;
1530   uint8_t p_z                          : 1;
1531   uint8_t n_y                          : 1;
1532   uint8_t p_y                          : 1;
1533   uint8_t n_x                          : 1;
1534   uint8_t p_x                          : 1;
1535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1536   uint8_t p_x                          : 1;
1537   uint8_t n_x                          : 1;
1538   uint8_t p_y                          : 1;
1539   uint8_t n_y                          : 1;
1540   uint8_t p_z                          : 1;
1541   uint8_t n_z                          : 1;
1542   uint8_t p_v                          : 1;
1543   uint8_t n_v                          : 1;
1544 #endif /* DRV_BYTE_ORDER */
1545 } lis2duxs12_fsm_outs4_t;
1546 
1547 #define LIS2DUXS12_FSM_OUTS5                            0x24U
1548 typedef struct
1549 {
1550 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1551   uint8_t n_v                          : 1;
1552   uint8_t p_v                          : 1;
1553   uint8_t n_z                          : 1;
1554   uint8_t p_z                          : 1;
1555   uint8_t n_y                          : 1;
1556   uint8_t p_y                          : 1;
1557   uint8_t n_x                          : 1;
1558   uint8_t p_x                          : 1;
1559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1560   uint8_t p_x                          : 1;
1561   uint8_t n_x                          : 1;
1562   uint8_t p_y                          : 1;
1563   uint8_t n_y                          : 1;
1564   uint8_t p_z                          : 1;
1565   uint8_t n_z                          : 1;
1566   uint8_t p_v                          : 1;
1567   uint8_t n_v                          : 1;
1568 #endif /* DRV_BYTE_ORDER */
1569 } lis2duxs12_fsm_outs5_t;
1570 
1571 #define LIS2DUXS12_FSM_OUTS6                            0x25U
1572 typedef struct
1573 {
1574 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1575   uint8_t n_v                          : 1;
1576   uint8_t p_v                          : 1;
1577   uint8_t n_z                          : 1;
1578   uint8_t p_z                          : 1;
1579   uint8_t n_y                          : 1;
1580   uint8_t p_y                          : 1;
1581   uint8_t n_x                          : 1;
1582   uint8_t p_x                          : 1;
1583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1584   uint8_t p_x                          : 1;
1585   uint8_t n_x                          : 1;
1586   uint8_t p_y                          : 1;
1587   uint8_t n_y                          : 1;
1588   uint8_t p_z                          : 1;
1589   uint8_t n_z                          : 1;
1590   uint8_t p_v                          : 1;
1591   uint8_t n_v                          : 1;
1592 #endif /* DRV_BYTE_ORDER */
1593 } lis2duxs12_fsm_outs6_t;
1594 
1595 #define LIS2DUXS12_FSM_OUTS7                            0x26U
1596 typedef struct
1597 {
1598 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1599   uint8_t n_v                          : 1;
1600   uint8_t p_v                          : 1;
1601   uint8_t n_z                          : 1;
1602   uint8_t p_z                          : 1;
1603   uint8_t n_y                          : 1;
1604   uint8_t p_y                          : 1;
1605   uint8_t n_x                          : 1;
1606   uint8_t p_x                          : 1;
1607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1608   uint8_t p_x                          : 1;
1609   uint8_t n_x                          : 1;
1610   uint8_t p_y                          : 1;
1611   uint8_t n_y                          : 1;
1612   uint8_t p_z                          : 1;
1613   uint8_t n_z                          : 1;
1614   uint8_t p_v                          : 1;
1615   uint8_t n_v                          : 1;
1616 #endif /* DRV_BYTE_ORDER */
1617 } lis2duxs12_fsm_outs7_t;
1618 
1619 #define LIS2DUXS12_FSM_OUTS8                            0x27U
1620 typedef struct
1621 {
1622 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1623   uint8_t n_v                          : 1;
1624   uint8_t p_v                          : 1;
1625   uint8_t n_z                          : 1;
1626   uint8_t p_z                          : 1;
1627   uint8_t n_y                          : 1;
1628   uint8_t p_y                          : 1;
1629   uint8_t n_x                          : 1;
1630   uint8_t p_x                          : 1;
1631 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1632   uint8_t p_x                          : 1;
1633   uint8_t n_x                          : 1;
1634   uint8_t p_y                          : 1;
1635   uint8_t n_y                          : 1;
1636   uint8_t p_z                          : 1;
1637   uint8_t n_z                          : 1;
1638   uint8_t p_v                          : 1;
1639   uint8_t n_v                          : 1;
1640 #endif /* DRV_BYTE_ORDER */
1641 } lis2duxs12_fsm_outs8_t;
1642 
1643 #define LIS2DUXS12_STEP_COUNTER_L                       0x28U
1644 typedef struct
1645 {
1646 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1647   uint8_t step                         : 8;
1648 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1649   uint8_t step                         : 8;
1650 #endif /* DRV_BYTE_ORDER */
1651 } lis2duxs12_step_counter_l_t;
1652 
1653 #define LIS2DUXS12_STEP_COUNTER_H                       0x29U
1654 typedef struct
1655 {
1656 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1657   uint8_t step                         : 8;
1658 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1659   uint8_t step                         : 8;
1660 #endif /* DRV_BYTE_ORDER */
1661 } lis2duxs12_step_counter_h_t;
1662 
1663 #define LIS2DUXS12_EMB_FUNC_SRC                         0x2AU
1664 typedef struct
1665 {
1666 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1667   uint8_t not_used0                    : 2;
1668   uint8_t stepcounter_bit_set          : 1;
1669   uint8_t step_overflow                : 1;
1670   uint8_t step_count_delta_ia          : 1;
1671   uint8_t step_detected                : 1;
1672   uint8_t not_used1                    : 1;
1673   uint8_t pedo_rst_step                : 1;
1674 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1675   uint8_t pedo_rst_step                : 1;
1676   uint8_t not_used1                    : 1;
1677   uint8_t step_detected                : 1;
1678   uint8_t step_count_delta_ia          : 1;
1679   uint8_t step_overflow                : 1;
1680   uint8_t stepcounter_bit_set          : 1;
1681   uint8_t not_used0                    : 2;
1682 #endif /* DRV_BYTE_ORDER */
1683 } lis2duxs12_emb_func_src_t;
1684 
1685 #define LIS2DUXS12_EMB_FUNC_INIT_A                      0x2CU
1686 typedef struct
1687 {
1688 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1689   uint8_t not_used0                    : 3;
1690   uint8_t step_det_init                : 1;
1691   uint8_t tilt_init                    : 1;
1692   uint8_t sig_mot_init                 : 1;
1693   uint8_t not_used1                    : 1;
1694   uint8_t mlc_before_fsm_init          : 1;
1695 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1696   uint8_t mlc_before_fsm_init          : 1;
1697   uint8_t not_used1                    : 1;
1698   uint8_t sig_mot_init                 : 1;
1699   uint8_t tilt_init                    : 1;
1700   uint8_t step_det_init                : 1;
1701   uint8_t not_used0                    : 3;
1702 #endif /* DRV_BYTE_ORDER */
1703 } lis2duxs12_emb_func_init_a_t;
1704 
1705 #define LIS2DUXS12_EMB_FUNC_INIT_B                      0x2DU
1706 typedef struct
1707 {
1708 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1709   uint8_t fsm_init                     : 1;
1710   uint8_t not_used0                    : 3;
1711   uint8_t mlc_init                     : 1;
1712   uint8_t not_used1                    : 3;
1713 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1714   uint8_t not_used1                    : 3;
1715   uint8_t mlc_init                     : 1;
1716   uint8_t not_used0                    : 3;
1717   uint8_t fsm_init                     : 1;
1718 #endif /* DRV_BYTE_ORDER */
1719 } lis2duxs12_emb_func_init_b_t;
1720 
1721 #define LIS2DUXS12_MLC1_SRC                             0x34U
1722 typedef struct
1723 {
1724 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1725   uint8_t mlc1_src                     : 8;
1726 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1727   uint8_t mlc1_src                     : 8;
1728 #endif /* DRV_BYTE_ORDER */
1729 } lis2duxs12_mlc1_src_t;
1730 
1731 #define LIS2DUXS12_MLC2_SRC                             0x35U
1732 typedef struct
1733 {
1734 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1735   uint8_t mlc2_src                     : 8;
1736 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1737   uint8_t mlc2_src                     : 8;
1738 #endif /* DRV_BYTE_ORDER */
1739 } lis2duxs12_mlc2_src_t;
1740 
1741 #define LIS2DUXS12_MLC3_SRC                             0x36U
1742 typedef struct
1743 {
1744 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1745   uint8_t mlc3_src                     : 8;
1746 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1747   uint8_t mlc3_src                     : 8;
1748 #endif /* DRV_BYTE_ORDER */
1749 } lis2duxs12_mlc3_src_t;
1750 
1751 #define LIS2DUXS12_MLC4_SRC                             0x37U
1752 typedef struct
1753 {
1754 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1755   uint8_t mlc4_src                     : 8;
1756 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1757   uint8_t mlc4_src                     : 8;
1758 #endif /* DRV_BYTE_ORDER */
1759 } lis2duxs12_mlc4_src_t;
1760 
1761 #define LIS2DUXS12_FSM_ODR                              0x39U
1762 typedef struct
1763 {
1764 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1765   uint8_t not_used0                    : 3;
1766   uint8_t fsm_odr                      : 3;
1767   uint8_t not_used1                    : 2;
1768 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1769   uint8_t not_used1                    : 2;
1770   uint8_t fsm_odr                      : 3;
1771   uint8_t not_used0                    : 3;
1772 #endif /* DRV_BYTE_ORDER */
1773 } lis2duxs12_fsm_odr_t;
1774 
1775 #define LIS2DUXS12_MLC_ODR                              0x3AU
1776 typedef struct
1777 {
1778 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1779   uint8_t not_used0                    : 4;
1780   uint8_t mlc_odr                      : 3;
1781   uint8_t not_used1                    : 1;
1782 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1783   uint8_t not_used1                    : 1;
1784   uint8_t mlc_odr                      : 3;
1785   uint8_t not_used0                    : 4;
1786 #endif /* DRV_BYTE_ORDER */
1787 } lis2duxs12_mlc_odr_t;
1788 
1789 /**
1790   * @}
1791   *
1792   */
1793 
1794 /** @defgroup bitfields page pg0_emb_adv
1795   * @{
1796   *
1797   */
1798 #define LIS2DUXS12_EMB_ADV_PG_0                         0x000U
1799 
1800 #define LIS2DUXS12_FSM_LC_TIMEOUT_L                     0x54U
1801 typedef struct
1802 {
1803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1804   uint8_t fsm_lc_timeout               : 8;
1805 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1806   uint8_t fsm_lc_timeout               : 8;
1807 #endif /* DRV_BYTE_ORDER */
1808 } lis2duxs12_fsm_lc_timeout_l_t;
1809 
1810 #define LIS2DUXS12_FSM_LC_TIMEOUT_H                     0x55U
1811 typedef struct
1812 {
1813 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1814   uint8_t fsm_lc_timeout               : 8;
1815 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1816   uint8_t fsm_lc_timeout               : 8;
1817 #endif /* DRV_BYTE_ORDER */
1818 } lis2duxs12_fsm_lc_timeout_h_t;
1819 
1820 #define LIS2DUXS12_FSM_PROGRAMS                         0x56U
1821 typedef struct
1822 {
1823 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1824   uint8_t fsm_n_prog                   : 8;
1825 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1826   uint8_t fsm_n_prog                   : 8;
1827 #endif /* DRV_BYTE_ORDER */
1828 } lis2duxs12_fsm_programs_t;
1829 
1830 #define LIS2DUXS12_FSM_START_ADD_L                      0x58U
1831 typedef struct
1832 {
1833 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1834   uint8_t fsm_start                    : 8;
1835 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1836   uint8_t fsm_start                    : 8;
1837 #endif /* DRV_BYTE_ORDER */
1838 } lis2duxs12_fsm_start_add_l_t;
1839 
1840 #define LIS2DUXS12_FSM_START_ADD_H                      0x59U
1841 typedef struct
1842 {
1843 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1844   uint8_t fsm_start                    : 8;
1845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1846   uint8_t fsm_start                    : 8;
1847 #endif /* DRV_BYTE_ORDER */
1848 } lis2duxs12_fsm_start_add_h_t;
1849 
1850 #define LIS2DUXS12_PEDO_CMD_REG                         0x5DU
1851 typedef struct
1852 {
1853 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1854   uint8_t not_used0                    : 2;
1855   uint8_t fp_rejection_en              : 1;
1856   uint8_t carry_count_en               : 1;
1857   uint8_t not_used1                    : 4;
1858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1859   uint8_t not_used1                    : 4;
1860   uint8_t carry_count_en               : 1;
1861   uint8_t fp_rejection_en              : 1;
1862   uint8_t not_used0                    : 2;
1863 #endif /* DRV_BYTE_ORDER */
1864 } lis2duxs12_pedo_cmd_reg_t;
1865 
1866 #define LIS2DUXS12_PEDO_DEB_STEPS_CONF                  0x5EU
1867 typedef struct
1868 {
1869 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1870   uint8_t deb_step                     : 8;
1871 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1872   uint8_t deb_step                     : 8;
1873 #endif /* DRV_BYTE_ORDER */
1874 } lis2duxs12_pedo_deb_steps_conf_t;
1875 
1876 #define LIS2DUXS12_PEDO_SC_DELTAT_L                     0xAAU
1877 typedef struct
1878 {
1879 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1880   uint8_t pd_sc                        : 8;
1881 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1882   uint8_t pd_sc                        : 8;
1883 #endif /* DRV_BYTE_ORDER */
1884 } lis2duxs12_pedo_sc_deltat_l_t;
1885 
1886 #define LIS2DUXS12_PEDO_SC_DELTAT_H                     0xABU
1887 typedef struct
1888 {
1889 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1890   uint8_t pd_sc                        : 8;
1891 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1892   uint8_t pd_sc                        : 8;
1893 #endif /* DRV_BYTE_ORDER */
1894 } lis2duxs12_pedo_sc_deltat_h_t;
1895 
1896 #define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_L              0xB6U
1897 typedef struct
1898 {
1899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1900   uint8_t t_ah_qvar_s                  : 8;
1901 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1902   uint8_t t_ah_qvar_s                  : 8;
1903 #endif /* DRV_BYTE_ORDER */
1904 } lis2duxs12_t_ah_qvar_sensitivity_l_t;
1905 
1906 #define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_H              0xB7U
1907 typedef struct
1908 {
1909 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1910   uint8_t t_ah_qvar_s                  : 8;
1911 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1912   uint8_t t_ah_qvar_s                  : 8;
1913 #endif /* DRV_BYTE_ORDER */
1914 } lis2duxs12_t_ah_qvar_sensitivity_h_t;
1915 
1916 /**
1917   * @}
1918   *
1919   */
1920 
1921 typedef union
1922 {
1923   lis2duxs12_pin_ctrl_t    pin_ctrl;
1924   lis2duxs12_wake_up_dur_ext_t    wake_up_dur_ext;
1925   lis2duxs12_who_am_i_t    who_am_i;
1926   lis2duxs12_ctrl1_t    ctrl1;
1927   lis2duxs12_ctrl2_t    ctrl2;
1928   lis2duxs12_ctrl3_t    ctrl3;
1929   lis2duxs12_ctrl4_t    ctrl4;
1930   lis2duxs12_ctrl5_t    ctrl5;
1931   lis2duxs12_fifo_ctrl_t    fifo_ctrl;
1932   lis2duxs12_fifo_wtm_t    fifo_wtm;
1933   lis2duxs12_interrupt_cfg_t    interrupt_cfg;
1934   lis2duxs12_sixd_t    sixd;
1935   lis2duxs12_wake_up_ths_t    wake_up_ths;
1936   lis2duxs12_wake_up_dur_t    wake_up_dur;
1937   lis2duxs12_free_fall_t    free_fall;
1938   lis2duxs12_md1_cfg_t    md1_cfg;
1939   lis2duxs12_md2_cfg_t    md2_cfg;
1940   lis2duxs12_wake_up_src_t    wake_up_src;
1941   lis2duxs12_tap_src_t    tap_src;
1942   lis2duxs12_sixd_src_t    sixd_src;
1943   lis2duxs12_all_int_src_t    all_int_src;
1944   lis2duxs12_status_register_t    status;
1945   lis2duxs12_fifo_status1_t    fifo_status1;
1946   lis2duxs12_fifo_status2_t    fifo_status2;
1947   lis2duxs12_out_x_l_t    out_x_l;
1948   lis2duxs12_out_x_h_t    out_x_h;
1949   lis2duxs12_out_y_l_t    out_y_l;
1950   lis2duxs12_out_y_h_t    out_y_h;
1951   lis2duxs12_out_z_l_t    out_z_l;
1952   lis2duxs12_out_z_h_t    out_z_h;
1953   lis2duxs12_out_t_ah_qvar_l_t    out_t_ah_qvar_l;
1954   lis2duxs12_out_t_ah_qvar_h_t    out_t_ah_qvar_h;
1955   lis2duxs12_ah_qvar_cfg_t    ah_qvar_cfg;
1956   lis2duxs12_self_test_t    self_test;
1957   lis2duxs12_i3c_if_ctrl_t    i3c_if_ctrl;
1958   lis2duxs12_emb_func_status_mainpage_t    emb_func_status_mainpage;
1959   lis2duxs12_fsm_status_mainpage_t    fsm_status_mainpage;
1960   lis2duxs12_mlc_status_mainpage_t    mlc_status_mainpage;
1961   lis2duxs12_sleep_t    sleep;
1962   lis2duxs12_if_wake_up_t    if_wake_up;
1963   lis2duxs12_func_cfg_access_t    func_cfg_access;
1964   lis2duxs12_fifo_data_out_tag_t    fifo_data_out_tag;
1965   lis2duxs12_fifo_data_out_x_l_t    fifo_data_out_x_l;
1966   lis2duxs12_fifo_data_out_x_h_t    fifo_data_out_x_h;
1967   lis2duxs12_fifo_data_out_y_l_t    fifo_data_out_y_l;
1968   lis2duxs12_fifo_data_out_y_h_t    fifo_data_out_y_h;
1969   lis2duxs12_fifo_data_out_z_l_t    fifo_data_out_z_l;
1970   lis2duxs12_fifo_data_out_z_h_t    fifo_data_out_z_h;
1971   lis2duxs12_fifo_batch_dec_t    fifo_batch_dec;
1972   lis2duxs12_tap_cfg0_t    tap_cfg0;
1973   lis2duxs12_tap_cfg1_t    tap_cfg1;
1974   lis2duxs12_tap_cfg2_t    tap_cfg2;
1975   lis2duxs12_tap_cfg3_t    tap_cfg3;
1976   lis2duxs12_tap_cfg4_t    tap_cfg4;
1977   lis2duxs12_tap_cfg5_t    tap_cfg5;
1978   lis2duxs12_tap_cfg6_t    tap_cfg6;
1979   lis2duxs12_timestamp0_t    timestamp0;
1980   lis2duxs12_timestamp1_t    timestamp1;
1981   lis2duxs12_timestamp2_t    timestamp2;
1982   lis2duxs12_timestamp3_t    timestamp3;
1983   lis2duxs12_page_sel_t    page_sel;
1984   lis2duxs12_emb_func_en_a_t    emb_func_en_a;
1985   lis2duxs12_emb_func_en_b_t    emb_func_en_b;
1986   lis2duxs12_emb_func_exec_status_t    emb_func_exec_status;
1987   lis2duxs12_page_address_t    page_address;
1988   lis2duxs12_page_value_t    page_value;
1989   lis2duxs12_emb_func_int1_t    emb_func_int1;
1990   lis2duxs12_fsm_int1_t    fsm_int1;
1991   lis2duxs12_mlc_int1_t    mlc_int1;
1992   lis2duxs12_emb_func_int2_t    emb_func_int2;
1993   lis2duxs12_fsm_int2_t    fsm_int2;
1994   lis2duxs12_mlc_int2_t    mlc_int2;
1995   lis2duxs12_emb_func_status_t    emb_func_status;
1996   lis2duxs12_fsm_status_t    fsm_status;
1997   lis2duxs12_mlc_status_t    mlc_status;
1998   lis2duxs12_page_rw_t    page_rw;
1999   lis2duxs12_emb_func_fifo_en_t    emb_func_fifo_en;
2000   lis2duxs12_fsm_enable_t    fsm_enable;
2001   lis2duxs12_fsm_long_counter_l_t    fsm_long_counter_l;
2002   lis2duxs12_fsm_long_counter_h_t    fsm_long_counter_h;
2003   lis2duxs12_int_ack_mask_t    int_ack_mask;
2004   lis2duxs12_fsm_outs1_t    fsm_outs1;
2005   lis2duxs12_fsm_outs2_t    fsm_outs2;
2006   lis2duxs12_fsm_outs3_t    fsm_outs3;
2007   lis2duxs12_fsm_outs4_t    fsm_outs4;
2008   lis2duxs12_fsm_outs5_t    fsm_outs5;
2009   lis2duxs12_fsm_outs6_t    fsm_outs6;
2010   lis2duxs12_fsm_outs7_t    fsm_outs7;
2011   lis2duxs12_fsm_outs8_t    fsm_outs8;
2012   lis2duxs12_step_counter_l_t    step_counter_l;
2013   lis2duxs12_step_counter_h_t    step_counter_h;
2014   lis2duxs12_emb_func_src_t    emb_func_src;
2015   lis2duxs12_emb_func_init_a_t    emb_func_init_a;
2016   lis2duxs12_emb_func_init_b_t    emb_func_init_b;
2017   lis2duxs12_mlc1_src_t    mlc1_src;
2018   lis2duxs12_mlc2_src_t    mlc2_src;
2019   lis2duxs12_mlc3_src_t    mlc3_src;
2020   lis2duxs12_mlc4_src_t    mlc4_src;
2021   lis2duxs12_fsm_odr_t    fsm_odr;
2022   lis2duxs12_mlc_odr_t    mlc_odr;
2023   lis2duxs12_fsm_lc_timeout_l_t    fsm_lc_timeout_l;
2024   lis2duxs12_fsm_lc_timeout_h_t    fsm_lc_timeout_h;
2025   lis2duxs12_fsm_programs_t    fsm_programs;
2026   lis2duxs12_fsm_start_add_l_t    fsm_start_add_l;
2027   lis2duxs12_fsm_start_add_h_t    fsm_start_add_h;
2028   lis2duxs12_pedo_cmd_reg_t    pedo_cmd_reg;
2029   lis2duxs12_pedo_deb_steps_conf_t    pedo_deb_steps_conf;
2030   lis2duxs12_pedo_sc_deltat_l_t    pedo_sc_deltat_l;
2031   lis2duxs12_pedo_sc_deltat_h_t    pedo_sc_deltat_h;
2032   lis2duxs12_t_ah_qvar_sensitivity_l_t    t_ah_qvar_sensitivity_l;
2033   lis2duxs12_t_ah_qvar_sensitivity_h_t    t_ah_qvar_sensitivity_h;
2034   bitwise_t    bitwise;
2035   uint8_t    byte;
2036 } lis2duxs12_reg_t;
2037 
2038 /**
2039   * @}
2040   *
2041   */
2042 
2043 #ifndef __weak
2044 #define __weak __attribute__((weak))
2045 #endif /* __weak */
2046 
2047 /*
2048  * These are the basic platform dependent I/O routines to read
2049  * and write device registers connected on a standard bus.
2050  * The driver keeps offering a default implementation based on function
2051  * pointers to read/write routines for backward compatibility.
2052  * The __weak directive allows the final application to overwrite
2053  * them with a custom implementation.
2054  */
2055 
2056 int32_t lis2duxs12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
2057                           uint8_t *data,
2058                           uint16_t len);
2059 int32_t lis2duxs12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
2060                            uint8_t *data,
2061                            uint16_t len);
2062 
2063 float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb);
2064 float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb);
2065 float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb);
2066 float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb);
2067 float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb);
2068 
2069 int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val);
2070 
2071 typedef enum {
2072   LIS2DUXS12_SENSOR_ONLY_ON     = 0x00, /* Initialize the driver for sensor usage */
2073   LIS2DUXS12_BOOT               = 0x01, /* Restore calib. param. (it takes 10ms) */
2074   LIS2DUXS12_RESET              = 0x02, /* Reset configuration registers */
2075   LIS2DUXS12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or
2076                                            embedded functions usage (it takes 10ms) */
2077 } lis2duxs12_init_t;
2078 int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val);
2079 
2080 typedef struct {
2081   uint8_t sw_reset                     : 1; /* Restoring configuration registers */
2082   uint8_t boot                         : 1; /* Restoring calibration parameters */
2083   uint8_t drdy                         : 1; /* Accelerometer data ready */
2084   uint8_t power_down                   : 1; /* Monitors power-down. */
2085 } lis2duxs12_status_t;
2086 int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val);
2087 
2088 typedef struct {
2089   uint8_t is_step_det                  : 1; /* Step detected */
2090   uint8_t is_tilt                      : 1; /* Tilt detected */
2091   uint8_t is_sigmot                    : 1; /* Significant motion detected */
2092 } lis2duxs12_embedded_status_t;
2093 int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val);
2094 
2095 typedef enum
2096 {
2097   LIS2DUXS12_DRDY_LATCHED = 0x0,
2098   LIS2DUXS12_DRDY_PULSED  = 0x1,
2099 } lis2duxs12_data_ready_mode_t;
2100 int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val);
2101 int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val);
2102 
2103 typedef struct {
2104   enum {
2105     LIS2DUXS12_OFF               = 0x00, /* in power down */
2106     LIS2DUXS12_1Hz5_ULP          = 0x01, /* @1Hz6 (low power) */
2107     LIS2DUXS12_3Hz_ULP           = 0x02, /* @3Hz (ultra low) */
2108     LIS2DUXS12_25Hz_ULP          = 0x03, /* @25Hz (ultra low) */
2109     LIS2DUXS12_6Hz               = 0x04, /* @6Hz (low power) */
2110     LIS2DUXS12_12Hz5             = 0x05, /* @12Hz5 (low power) */
2111     LIS2DUXS12_25Hz              = 0x06, /* @25Hz  (low power ) */
2112     LIS2DUXS12_50Hz              = 0x07, /* @50Hz  (low power) */
2113     LIS2DUXS12_100Hz             = 0x08, /* @100Hz (low power) */
2114     LIS2DUXS12_200Hz             = 0x09, /* @200Hz (low power) */
2115     LIS2DUXS12_400Hz             = 0x0A, /* @400Hz (low power) */
2116     LIS2DUXS12_800Hz             = 0x0B, /* @800Hz (low power) */
2117     LIS2DUXS12_TRIG_PIN          = 0x0E, /* Single-shot high latency by INT2 */
2118     LIS2DUXS12_TRIG_SW           = 0x0F, /* Single-shot high latency by IF */
2119     LIS2DUXS12_6Hz_HP            = 0x14, /* @6Hz (high performance) */
2120     LIS2DUXS12_12Hz5_HP          = 0x15, /* @12Hz5 (high performance) */
2121     LIS2DUXS12_25Hz_HP           = 0x16, /* @25Hz  (high performance ) */
2122     LIS2DUXS12_50Hz_HP           = 0x17, /* @50Hz  (high performance) */
2123     LIS2DUXS12_100Hz_HP          = 0x18, /* @100Hz (high performance) */
2124     LIS2DUXS12_200Hz_HP          = 0x19, /* @200Hz (high performance) */
2125     LIS2DUXS12_400Hz_HP          = 0x1A, /* @400Hz (high performance) */
2126     LIS2DUXS12_800Hz_HP          = 0x1B, /* @800Hz (high performance) */
2127   } odr;
2128   enum {
2129     LIS2DUXS12_2g   = 0,
2130     LIS2DUXS12_4g   = 1,
2131     LIS2DUXS12_8g   = 2,
2132     LIS2DUXS12_16g  = 3,
2133   } fs;
2134   enum {
2135     LIS2DUXS12_ODR_div_2   = 0,
2136     LIS2DUXS12_ODR_div_4   = 1,
2137     LIS2DUXS12_ODR_div_8   = 2,
2138     LIS2DUXS12_ODR_div_16  = 3,
2139   } bw;
2140 } lis2duxs12_md_t;
2141 int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val);
2142 int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val);
2143 
2144 int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md);
2145 
2146 typedef struct
2147 {
2148   uint8_t drdy                         : 1;
2149   uint8_t timestamp                    : 1;
2150   uint8_t free_fall                    : 1;
2151   uint8_t wake_up                      : 1;
2152   uint8_t wake_up_z                    : 1;
2153   uint8_t wake_up_y                    : 1;
2154   uint8_t wake_up_x                    : 1;
2155   uint8_t single_tap                   : 1;
2156   uint8_t double_tap                   : 1;
2157   uint8_t triple_tap                   : 1;
2158   uint8_t six_d                        : 1;
2159   uint8_t six_d_xl                     : 1;
2160   uint8_t six_d_xh                     : 1;
2161   uint8_t six_d_yl                     : 1;
2162   uint8_t six_d_yh                     : 1;
2163   uint8_t six_d_zl                     : 1;
2164   uint8_t six_d_zh                     : 1;
2165   uint8_t sleep_change                 : 1;
2166   uint8_t sleep_state                  : 1;
2167   uint8_t tilt                         : 1;
2168   uint8_t fifo_bdr                     : 1;
2169   uint8_t fifo_full                    : 1;
2170   uint8_t fifo_ovr                     : 1;
2171   uint8_t fifo_th                      : 1;
2172 } lis2duxs12_all_sources_t;
2173 int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val);
2174 
2175 typedef struct {
2176   float_t mg[3];
2177   int16_t raw[3];
2178 } lis2duxs12_xl_data_t;
2179 int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
2180                                lis2duxs12_xl_data_t *data);
2181 
2182 typedef struct {
2183   struct {
2184     float_t deg_c;
2185     int16_t raw;
2186   }heat;
2187 } lis2duxs12_outt_data_t;
2188 int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
2189                                lis2duxs12_outt_data_t *data);
2190 
2191 typedef struct {
2192   int16_t ah_qvar;
2193 } lis2duxs12_ah_qvar_data_t;
2194 int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
2195                                lis2duxs12_ah_qvar_data_t *data);
2196 
2197 typedef enum
2198 {
2199   LIS2DUXS12_XL_ST_DISABLE  = 0x0,
2200   LIS2DUXS12_XL_ST_POSITIVE = 0x1,
2201   LIS2DUXS12_XL_ST_NEGATIVE = 0x2,
2202 } lis2duxs12_xl_self_test_t;
2203 int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val);
2204 int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val);
2205 int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx);
2206 
2207 int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val);
2208 int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx);
2209 
2210 typedef struct {
2211   enum {
2212     LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US = 0x0,
2213     LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US = 0x1,
2214     LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS  = 0x2,
2215     LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS = 0x3,
2216   } bus_act_sel;
2217   uint8_t asf_on                       : 1;
2218   uint8_t drstdaa_en                   : 1;
2219 } lis2duxs12_i3c_cfg_t;
2220 int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val);
2221 int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val);
2222 
2223 typedef enum
2224 {
2225   LIS2DUXS12_MAIN_MEM_BANK       = 0x0,
2226   LIS2DUXS12_EMBED_FUNC_MEM_BANK = 0x1,
2227 } lis2duxs12_mem_bank_t;
2228 int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val);
2229 int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val);
2230 
2231 int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len);
2232 int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len);
2233 
2234 typedef struct {
2235   uint8_t sdo_pull_up                  : 1; /* 1 = pull up enable */
2236   uint8_t sda_pull_up                  : 1; /* 1 = pull up enable */
2237   uint8_t cs_pull_up                   : 1; /* 1 = pull up enable */
2238   uint8_t int1_int2_push_pull          : 1; /* 1 = push-pull / 0 = open-drain*/
2239   uint8_t int1_pull_down               : 1; /* 1 = pull-down always disabled (0=auto) */
2240   uint8_t int2_pull_down               : 1; /* 1 = pull-down always disabled (0=auto) */
2241 } lis2duxs12_pin_conf_t;
2242 int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val);
2243 int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val);
2244 
2245 typedef enum
2246 {
2247   LIS2DUXS12_ACTIVE_HIGH = 0x0,
2248   LIS2DUXS12_ACTIVE_LOW  = 0x1,
2249 } lis2duxs12_int_pin_polarity_t;
2250 int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val);
2251 int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val);
2252 
2253 typedef enum
2254 {
2255   LIS2DUXS12_SPI_4_WIRE  = 0x0, /* SPI 4 wires */
2256   LIS2DUXS12_SPI_3_WIRE  = 0x1, /* SPI 3 wires */
2257 } lis2duxs12_spi_mode;
2258 int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val);
2259 int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val);
2260 
2261 typedef struct {
2262   uint8_t int_on_res                   : 1; /* Interrupt on RES pin */
2263   uint8_t drdy                         : 1; /* Accelerometer data ready */
2264   uint8_t boot                         : 1; /* Restoring calibration parameters */
2265   uint8_t fifo_th                      : 1; /* FIFO threshold reached */
2266   uint8_t fifo_ovr                     : 1; /* FIFO overrun */
2267   uint8_t fifo_full                    : 1; /* FIFO full */
2268   uint8_t free_fall                    : 1; /* free fall event */
2269   uint8_t six_d                        : 1; /* orientation change (6D/4D detection) */
2270   uint8_t tap                          : 1; /* all tap event */
2271   uint8_t wake_up                      : 1; /* wake up event */
2272   uint8_t sleep_change                 : 1; /* Act/Inact (or Vice-versa) status changed */
2273   uint8_t emb_function                 : 1; /* Embedded Function */
2274   uint8_t timestamp                    : 1; /* Timestamp */
2275 } lis2duxs12_pin_int_route_t;
2276 int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx,
2277                                       lis2duxs12_pin_int_route_t *val);
2278 int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx,
2279                                       lis2duxs12_pin_int_route_t *val);
2280 int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx,
2281                                       lis2duxs12_pin_int_route_t *val);
2282 int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx,
2283                                       lis2duxs12_pin_int_route_t *val);
2284 
2285 typedef struct {
2286   uint8_t step_det                     : 1; /* route step detection event on INT pad */
2287   uint8_t tilt                         : 1; /* route tilt event on INT pad */
2288   uint8_t sig_mot                      : 1; /* route significant motion event on INT pad */
2289   uint8_t fsm_lc                       : 1; /* route FSM long counter event on INT pad */
2290 } lis2duxs12_emb_pin_int_route_t;
2291 int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx,
2292                                           lis2duxs12_emb_pin_int_route_t *val);
2293 int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx,
2294                                           lis2duxs12_emb_pin_int_route_t *val);
2295 int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx,
2296                                           lis2duxs12_emb_pin_int_route_t *val);
2297 int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx,
2298                                           lis2duxs12_emb_pin_int_route_t *val);
2299 
2300 typedef struct {
2301   enum int_cfg
2302   {
2303     LIS2DUXS12_INT_DISABLED             = 0x0,
2304     LIS2DUXS12_INT_LEVEL                = 0x1,
2305     LIS2DUXS12_INT_LATCHED              = 0x2,
2306   } int_cfg;
2307   uint8_t sleep_status_on_int          : 1;  /* route sleep_status on interrupt */
2308   uint8_t dis_rst_lir_all_int          : 1;  /* disable LIR reset when reading ALL_INT_SRC */
2309 } lis2duxs12_int_config_t;
2310 int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val);
2311 int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val);
2312 
2313 typedef enum
2314 {
2315   LIS2DUXS12_EMBEDDED_INT_LEVEL         = 0x0,
2316   LIS2DUXS12_EMBEDDED_INT_LATCHED       = 0x1,
2317 } lis2duxs12_embedded_int_config_t;
2318 int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val);
2319 int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val);
2320 
2321 typedef struct {
2322   enum operation
2323   {
2324     LIS2DUXS12_BYPASS_MODE              = 0x0,
2325     LIS2DUXS12_FIFO_MODE                = 0x1,
2326     LIS2DUXS12_STREAM_TO_FIFO_MODE      = 0x3,
2327     LIS2DUXS12_BYPASS_TO_STREAM_MODE    = 0x4,
2328     LIS2DUXS12_STREAM_MODE              = 0x6,
2329     LIS2DUXS12_BYPASS_TO_FIFO_MODE      = 0x7,
2330     LIS2DUXS12_FIFO_OFF                 = 0x8,
2331   } operation;
2332   enum store {
2333     LIS2DUXS12_FIFO_1X                  = 0,
2334     LIS2DUXS12_FIFO_2X                  = 1,
2335   } store;
2336   uint8_t xl_only                      : 1; /* when set to 1, only XL samples (16-bit) are stored in FIFO */
2337   uint8_t watermark                    : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/
2338   uint8_t cfg_change_in_fifo           : 1;
2339   struct {
2340     enum dec_ts
2341     {
2342       LIS2DUXS12_DEC_TS_OFF             = 0x0,
2343       LIS2DUXS12_DEC_TS_1               = 0x1,
2344       LIS2DUXS12_DEC_TS_8               = 0x2,
2345       LIS2DUXS12_DEC_TS_32              = 0x3,
2346     } dec_ts; /* decimation for timestamp batching*/
2347     enum bdr_xl
2348     {
2349       LIS2DUXS12_BDR_XL_ODR             = 0x0,
2350       LIS2DUXS12_BDR_XL_ODR_DIV_2       = 0x1,
2351       LIS2DUXS12_BDR_XL_ODR_DIV_4       = 0x2,
2352       LIS2DUXS12_BDR_XL_ODR_DIV_8       = 0x3,
2353       LIS2DUXS12_BDR_XL_ODR_DIV_16      = 0x4,
2354       LIS2DUXS12_BDR_XL_ODR_DIV_32      = 0x5,
2355       LIS2DUXS12_BDR_XL_ODR_DIV_64      = 0x6,
2356       LIS2DUXS12_BDR_XL_ODR_OFF         = 0x7,
2357     } bdr_xl; /* accelerometer batch data rate*/
2358   } batch;
2359 } lis2duxs12_fifo_mode_t;
2360 int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val);
2361 int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val);
2362 
2363 int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
2364 int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
2365 
2366 typedef enum
2367 {
2368   LIS2DUXS12_FIFO_EMPTY                 = 0x0,
2369   LIS2DUXS12_XL_TEMP_TAG                = 0x2,
2370   LIS2DUXS12_XL_ONLY_2X_TAG             = 0x3,
2371   LIS2DUXS12_TIMESTAMP_TAG              = 0x4,
2372   LIS2DUXS12_STEP_COUNTER_TAG           = 0x12,
2373   LIS2DUXS12_MLC_RESULT_TAG             = 0x1A,
2374   LIS2DUXS12_MLC_FILTER_TAG             = 0x1B,
2375   LIS2DUXS12_MLC_FEATURE                = 0x1C,
2376   LIS2DUXS12_FSM_RESULT_TAG             = 0x1D,
2377   LIS2DUXS12_XL_ONLY_2X_TAG_2ND         = 0x1E,
2378   LIS2DUXS12_XL_AND_QVAR                = 0x1F,
2379 } lis2duxs12_fifo_sensor_tag_t;
2380 int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
2381                                        lis2duxs12_fifo_sensor_tag_t *val);
2382 
2383 int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
2384 
2385 typedef struct {
2386   uint8_t tag;
2387   struct {
2388     float_t mg[3];
2389     int16_t raw[3];
2390   }xl[2];
2391   int16_t ah_qvar;
2392   struct {
2393     float_t deg_c;
2394     int16_t raw;
2395   }heat;
2396   struct pedo {
2397     uint32_t steps;
2398     uint32_t timestamp;
2399   } pedo;
2400   struct cfg_chg {
2401     uint8_t cfg_change                 : 1; /* 1 if ODR/BDR configuration is changed */
2402     uint8_t odr                        : 4; /* ODR */
2403     uint8_t bw                         : 2; /* BW */
2404     uint8_t lp_hp                      : 1; /* Power (LP == 0/HP == 1) */
2405     uint8_t qvar_en                    : 1; /* QVAR is enabled */
2406     uint8_t fs                         : 2; /* FS */
2407     uint8_t dec_ts                     : 2; /* Timestamp decimator value */
2408     uint8_t odr_xl_batch               : 1; /* Accelerometer ODR is batched */
2409     uint32_t timestamp;
2410   } cfg_chg;
2411 } lis2duxs12_fifo_data_t;
2412 int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md,
2413                                  lis2duxs12_fifo_mode_t *fmd,
2414                                  lis2duxs12_fifo_data_t *data);
2415 
2416 typedef struct
2417 {
2418   uint8_t ah_qvar_en                   : 1;
2419   uint8_t ah_qvar_notch_en             : 1;
2420   enum {
2421     LIS2DUXS12_NOTCH_50HZ       = 0x0,
2422     LIS2DUXS12_NOTCH_60HZ       = 0x1,
2423   } ah_qvar_notch;
2424   enum {
2425     LIS2DUXS12_520MOhm          = 0x0,
2426     LIS2DUXS12_175MOhm          = 0x1,
2427     LIS2DUXS12_310MOhm          = 0x2,
2428     LIS2DUXS12_75MOhm           = 0x3,
2429   } ah_qvar_zin;
2430   enum {
2431     LIS2DUXS12_GAIN_0_5         = 0x0,
2432     LIS2DUXS12_GAIN_1           = 0x1,
2433     LIS2DUXS12_GAIN_2           = 0x2,
2434     LIS2DUXS12_GAIN_4           = 0x3,
2435   } ah_qvar_gain;
2436 } lis2duxs12_ah_qvar_mode_t;
2437 int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx,
2438                                     lis2duxs12_ah_qvar_mode_t val);
2439 int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx,
2440                                     lis2duxs12_ah_qvar_mode_t *val);
2441 
2442 typedef struct
2443 {
2444   uint8_t false_step_rej               : 1;
2445   uint8_t step_counter_enable          : 1;
2446   uint8_t step_counter_in_fifo         : 1;
2447 } lis2duxs12_stpcnt_mode_t;
2448 int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val);
2449 int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val);
2450 
2451 int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
2452 
2453 int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx);
2454 
2455 int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val);
2456 int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val);
2457 
2458 int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val);
2459 int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val);
2460 
2461 int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val);
2462 int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
2463 int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val);
2464 int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
2465 
2466 
2467 int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val);
2468 int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
2469 
2470 typedef enum
2471 {
2472   LIS2DUXS12_156_mg = 0x0,
2473   LIS2DUXS12_219_mg = 0x1,
2474   LIS2DUXS12_250_mg = 0x2,
2475   LIS2DUXS12_312_mg = 0x3,
2476   LIS2DUXS12_344_mg = 0x4,
2477   LIS2DUXS12_406_mg = 0x5,
2478   LIS2DUXS12_469_mg = 0x6,
2479   LIS2DUXS12_500_mg = 0x7,
2480 } lis2duxs12_ff_thresholds_t;
2481 int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val);
2482 int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val);
2483 
2484 typedef struct {
2485   enum threshold
2486   {
2487     LIS2DUXS12_DEG_80 = 0x0,
2488     LIS2DUXS12_DEG_70 = 0x1,
2489     LIS2DUXS12_DEG_60 = 0x2,
2490     LIS2DUXS12_DEG_50 = 0x3,
2491   } threshold;
2492   enum mode
2493   {
2494     LIS2DUXS12_6D = 0x0,
2495     LIS2DUXS12_4D = 0x1,
2496   } mode;
2497 } lis2duxs12_sixd_config_t;
2498 
2499 int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val);
2500 int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val);
2501 
2502 typedef struct {
2503   enum wake_dur
2504   {
2505     LIS2DUXS12_0_ODR  = 0x000, /* 0 ODR time */
2506     LIS2DUXS12_1_ODR  = 0x001, /* 1 ODR time */
2507     LIS2DUXS12_2_ODR  = 0x002, /* 2 ODR time */
2508     LIS2DUXS12_3_ODR  = 0x100, /* 3 ODR time */
2509     LIS2DUXS12_7_ODR  = 0x101, /* 7 ODR time */
2510     LIS2DUXS12_11_ODR = 0x102, /* 11 ODR time */
2511     LIS2DUXS12_15_ODR = 0x103, /* 15 ODR time */
2512   } wake_dur;
2513   uint8_t sleep_dur                    : 4;       /* 1 LSB == 512 ODR time */
2514   uint8_t wake_ths                     : 7;       /* wakeup threshold */
2515   uint8_t wake_ths_weight              : 1;       /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */
2516   enum wake_enable
2517   {
2518     LIS2DUXS12_SLEEP_OFF = 0,
2519     LIS2DUXS12_SLEEP_ON  = 1,
2520   } wake_enable;
2521   enum inact_odr
2522   {
2523     LIS2DUXS12_ODR_NO_CHANGE       = 0,  /* no odr change during inactivity state */
2524     LIS2DUXS12_ODR_1_6_HZ          = 1,  /* set odr to 1.6Hz during inactivity state */
2525     LIS2DUXS12_ODR_3_HZ            = 1,  /* set odr to 3Hz during inactivity state */
2526     LIS2DUXS12_ODR_25_HZ           = 1,  /* set odr to 25Hz during inactivity state */
2527   } inact_odr;
2528 } lis2duxs12_wakeup_config_t;
2529 
2530 int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val);
2531 int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val);
2532 
2533 typedef struct {
2534   enum axis
2535   {
2536     LIS2DUXS12_TAP_NONE  = 0x0, /* No axis */
2537     LIS2DUXS12_TAP_ON_X  = 0x1, /* Detect tap on X axis */
2538     LIS2DUXS12_TAP_ON_Y  = 0x2, /* Detect tap on Y axis */
2539     LIS2DUXS12_TAP_ON_Z  = 0x3, /* Detect tap on Z axis */
2540   } axis;
2541   uint8_t inverted_peak_time           : 5; /* 1 LSB == 1 sample */
2542   uint8_t pre_still_ths                : 4; /* 1 LSB == 62.5 mg */
2543   uint8_t post_still_ths               : 4; /* 1 LSB == 62.5 mg */
2544   uint8_t post_still_time              : 6; /* samples num during stationary condition */
2545   uint8_t shock_wait_time              : 6; /* samples num during shock condition */
2546   uint8_t latency                      : 4; /* samples max num between taps */
2547   uint8_t wait_end_latency             : 1; /* wait end of latency time to generate tap events */
2548   uint8_t peak_ths                     : 6; /* 1 LSB == 62.5 mg */
2549   uint8_t rebound                      : 5; /* samples num during rebound condition */
2550   uint8_t pre_still_start              : 4; /* pre still start */
2551   uint8_t pre_still_n                  : 4; /* pre still n */
2552   uint8_t single_tap_on                : 1; /* enable single tap */
2553   uint8_t double_tap_on                : 1; /* enable double tap */
2554   uint8_t triple_tap_on                : 1; /* enable triple tap */
2555 } lis2duxs12_tap_config_t;
2556 
2557 int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val);
2558 int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val);
2559 
2560 int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
2561 int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
2562 
2563 int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
2564 
2565 int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
2566                                                 uint8_t *val);
2567 
2568 int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
2569 int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
2570 
2571 typedef struct
2572 {
2573   lis2duxs12_fsm_enable_t          fsm_enable;
2574 } lis2duxs12_emb_fsm_enable_t;
2575 int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx,
2576                                   lis2duxs12_emb_fsm_enable_t *val);
2577 int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx,
2578                                   lis2duxs12_emb_fsm_enable_t *val);
2579 
2580 int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
2581 int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
2582 
2583 int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx,
2584                                   lis2duxs12_fsm_status_mainpage_t *val);
2585 int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val);
2586 
2587 typedef enum
2588 {
2589   LIS2DUXS12_ODR_FSM_12Hz5 = 0,
2590   LIS2DUXS12_ODR_FSM_25Hz  = 1,
2591   LIS2DUXS12_ODR_FSM_50Hz  = 2,
2592   LIS2DUXS12_ODR_FSM_100Hz = 3,
2593   LIS2DUXS12_ODR_FSM_200Hz = 4,
2594   LIS2DUXS12_ODR_FSM_400Hz = 5,
2595   LIS2DUXS12_ODR_FSM_800Hz = 6,
2596 } lis2duxs12_fsm_val_odr_t;
2597 int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx,
2598                                      lis2duxs12_fsm_val_odr_t val);
2599 int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx,
2600                                      lis2duxs12_fsm_val_odr_t *val);
2601 
2602 int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
2603 int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
2604 
2605 int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx,
2606                                           uint16_t val);
2607 int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx,
2608                                           uint16_t *val);
2609 
2610 int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
2611                                               uint8_t *buff);
2612 int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
2613                                               uint8_t *buff);
2614 
2615 int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx,
2616                                          uint16_t val);
2617 int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx,
2618                                          uint16_t *val);
2619 
2620 typedef enum
2621 {
2622   LIS2DUXS12_MLC_OFF                    = 0,
2623   LIS2DUXS12_MLC_ON                     = 1,
2624   LIS2DUXS12_MLC_ON_BEFORE_FSM          = 2,
2625 } lis2duxs12_mlc_mode_t;
2626 int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val);
2627 int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val);
2628 
2629 int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx,
2630                                   lis2duxs12_mlc_status_mainpage_t *val);
2631 
2632 int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
2633 
2634 typedef enum
2635 {
2636   LIS2DUXS12_ODR_PRGS_12Hz5 = 0,
2637   LIS2DUXS12_ODR_PRGS_25Hz  = 1,
2638   LIS2DUXS12_ODR_PRGS_50Hz  = 2,
2639   LIS2DUXS12_ODR_PRGS_100Hz = 3,
2640   LIS2DUXS12_ODR_PRGS_200Hz = 4,
2641 } lis2duxs12_mlc_odr_val_t;
2642 int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx,
2643                                      lis2duxs12_mlc_odr_val_t val);
2644 int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx,
2645                                      lis2duxs12_mlc_odr_val_t *val);
2646 
2647 #ifdef __cplusplus
2648 }
2649 #endif
2650 
2651 #endif /* LIS2DUXS12_REGS_H */
2652 
2653 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2654