1 /* 2 ****************************************************************************** 3 * @file lis2duxs12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2duxs12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DUXS12_REGS_H 23 #define LIS2DUXS12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DUXS12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, const uint8_t *data, uint16_t len); 113 typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DUXS12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ 172 #define LIS2DUXS12_I2C_ADD_L 0x31U 173 #define LIS2DUXS12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DUXS12_ID 0x47U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DUXS12_EXT_CLK_CFG 0x08U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used0 : 7; 188 uint8_t ext_clk_en : 1; 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t ext_clk_en : 1; 191 uint8_t not_used0 : 7; 192 #endif /* DRV_BYTE_ORDER */ 193 } lis2duxs12_ext_clk_cfg_t; 194 195 #define LIS2DUXS12_PIN_CTRL 0x0CU 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t sim : 1; 200 uint8_t pp_od : 1; 201 uint8_t cs_pu_dis : 1; 202 uint8_t h_lactive : 1; 203 uint8_t pd_dis_int1 : 1; 204 uint8_t pd_dis_int2 : 1; 205 uint8_t sda_pu_en : 1; 206 uint8_t sdo_pu_en : 1; 207 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 208 uint8_t sdo_pu_en : 1; 209 uint8_t sda_pu_en : 1; 210 uint8_t pd_dis_int2 : 1; 211 uint8_t pd_dis_int1 : 1; 212 uint8_t h_lactive : 1; 213 uint8_t cs_pu_dis : 1; 214 uint8_t pp_od : 1; 215 uint8_t sim : 1; 216 #endif /* DRV_BYTE_ORDER */ 217 } lis2duxs12_pin_ctrl_t; 218 219 #define LIS2DUXS12_WAKE_UP_DUR_EXT 0x0EU 220 typedef struct 221 { 222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 223 uint8_t not_used0 : 4; 224 uint8_t wu_dur_extended : 1; 225 uint8_t not_used1 : 3; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t not_used1 : 3; 228 uint8_t wu_dur_extended : 1; 229 uint8_t not_used0 : 4; 230 #endif /* DRV_BYTE_ORDER */ 231 } lis2duxs12_wake_up_dur_ext_t; 232 233 #define LIS2DUXS12_WHO_AM_I 0x0FU 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t id : 8; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t id : 8; 240 #endif /* DRV_BYTE_ORDER */ 241 } lis2duxs12_who_am_i_t; 242 243 #define LIS2DUXS12_CTRL1 0x10U 244 typedef struct 245 { 246 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 247 uint8_t wu_z_en : 1; 248 uint8_t wu_y_en : 1; 249 uint8_t wu_x_en : 1; 250 uint8_t drdy_pulsed : 1; 251 uint8_t if_add_inc : 1; 252 uint8_t sw_reset : 1; 253 uint8_t int1_on_res : 1; 254 uint8_t smart_power_en : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t smart_power_en : 1; 257 uint8_t int1_on_res : 1; 258 uint8_t sw_reset : 1; 259 uint8_t if_add_inc : 1; 260 uint8_t drdy_pulsed : 1; 261 uint8_t wu_x_en : 1; 262 uint8_t wu_y_en : 1; 263 uint8_t wu_z_en : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } lis2duxs12_ctrl1_t; 266 267 #define LIS2DUXS12_CTRL2 0x11U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t not_used0 : 3; 272 uint8_t int1_drdy : 1; 273 uint8_t int1_fifo_ovr : 1; 274 uint8_t int1_fifo_th : 1; 275 uint8_t int1_fifo_full : 1; 276 uint8_t int1_boot : 1; 277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 278 uint8_t int1_boot : 1; 279 uint8_t int1_fifo_full : 1; 280 uint8_t int1_fifo_th : 1; 281 uint8_t int1_fifo_ovr : 1; 282 uint8_t int1_drdy : 1; 283 uint8_t not_used0 : 3; 284 #endif /* DRV_BYTE_ORDER */ 285 } lis2duxs12_ctrl2_t; 286 287 #define LIS2DUXS12_CTRL3 0x12U 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t st_sign_x : 1; 292 uint8_t st_sign_y : 1; 293 uint8_t hp_en : 1; 294 uint8_t int2_drdy : 1; 295 uint8_t int2_fifo_ovr : 1; 296 uint8_t int2_fifo_th : 1; 297 uint8_t int2_fifo_full : 1; 298 uint8_t int2_boot : 1; 299 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 300 uint8_t int2_boot : 1; 301 uint8_t int2_fifo_full : 1; 302 uint8_t int2_fifo_th : 1; 303 uint8_t int2_fifo_ovr : 1; 304 uint8_t int2_drdy : 1; 305 uint8_t hp_en : 1; 306 uint8_t st_sign_y : 1; 307 uint8_t st_sign_x : 1; 308 #endif /* DRV_BYTE_ORDER */ 309 } lis2duxs12_ctrl3_t; 310 311 #define LIS2DUXS12_CTRL4 0x13U 312 typedef struct 313 { 314 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 315 uint8_t boot : 1; 316 uint8_t soc : 1; 317 uint8_t not_used0 : 1; 318 uint8_t fifo_en : 1; 319 uint8_t emb_func_en : 1; 320 uint8_t bdu : 1; 321 uint8_t inact_odr : 2; 322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 323 uint8_t inact_odr : 2; 324 uint8_t bdu : 1; 325 uint8_t emb_func_en : 1; 326 uint8_t fifo_en : 1; 327 uint8_t not_used0 : 1; 328 uint8_t soc : 1; 329 uint8_t boot : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } lis2duxs12_ctrl4_t; 332 333 #define LIS2DUXS12_CTRL5 0x14U 334 typedef struct 335 { 336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 337 uint8_t fs : 2; 338 uint8_t bw : 2; 339 uint8_t odr : 4; 340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 uint8_t odr : 4; 342 uint8_t bw : 2; 343 uint8_t fs : 2; 344 #endif /* DRV_BYTE_ORDER */ 345 } lis2duxs12_ctrl5_t; 346 347 #define LIS2DUXS12_FIFO_CTRL 0x15U 348 typedef struct 349 { 350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 351 uint8_t fifo_mode : 3; 352 uint8_t stop_on_fth : 1; 353 uint8_t not_used0 : 2; 354 uint8_t fifo_depth : 1; 355 uint8_t cfg_chg_en : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t cfg_chg_en : 1; 358 uint8_t fifo_depth : 1; 359 uint8_t not_used0 : 2; 360 uint8_t stop_on_fth : 1; 361 uint8_t fifo_mode : 3; 362 #endif /* DRV_BYTE_ORDER */ 363 } lis2duxs12_fifo_ctrl_t; 364 365 #define LIS2DUXS12_FIFO_WTM 0x16U 366 typedef struct 367 { 368 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 369 uint8_t fth : 7; 370 uint8_t xl_only_fifo : 1; 371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 372 uint8_t xl_only_fifo : 1; 373 uint8_t fth : 7; 374 #endif /* DRV_BYTE_ORDER */ 375 } lis2duxs12_fifo_wtm_t; 376 377 #define LIS2DUXS12_INTERRUPT_CFG 0x17U 378 typedef struct 379 { 380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 381 uint8_t interrupts_enable : 1; 382 uint8_t lir : 1; 383 uint8_t dis_rst_lir_all_int : 1; 384 uint8_t sleep_status_on_int : 1; 385 uint8_t not_used0 : 1; 386 uint8_t wake_ths_w : 1; 387 uint8_t not_used1 : 1; 388 uint8_t timestamp_en : 1; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t timestamp_en : 1; 391 uint8_t not_used1 : 1; 392 uint8_t wake_ths_w : 1; 393 uint8_t not_used0 : 1; 394 uint8_t sleep_status_on_int : 1; 395 uint8_t dis_rst_lir_all_int : 1; 396 uint8_t lir : 1; 397 uint8_t interrupts_enable : 1; 398 #endif /* DRV_BYTE_ORDER */ 399 } lis2duxs12_interrupt_cfg_t; 400 401 #define LIS2DUXS12_SIXD 0x18U 402 typedef struct 403 { 404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 405 uint8_t not_used0 : 5; 406 uint8_t d6d_ths : 2; 407 uint8_t d4d_en : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t d4d_en : 1; 410 uint8_t d6d_ths : 2; 411 uint8_t not_used0 : 5; 412 #endif /* DRV_BYTE_ORDER */ 413 } lis2duxs12_sixd_t; 414 415 #define LIS2DUXS12_WAKE_UP_THS 0x1CU 416 typedef struct 417 { 418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 419 uint8_t wk_ths : 6; 420 uint8_t sleep_on : 1; 421 uint8_t not_used0 : 1; 422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 423 uint8_t not_used0 : 1; 424 uint8_t sleep_on : 1; 425 uint8_t wk_ths : 6; 426 #endif /* DRV_BYTE_ORDER */ 427 } lis2duxs12_wake_up_ths_t; 428 429 #define LIS2DUXS12_WAKE_UP_DUR 0x1DU 430 typedef struct 431 { 432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 433 uint8_t sleep_dur : 4; 434 uint8_t st_sign_z : 1; 435 uint8_t wake_dur : 2; 436 uint8_t ff_dur : 1; 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t ff_dur : 1; 439 uint8_t wake_dur : 2; 440 uint8_t st_sign_z : 1; 441 uint8_t sleep_dur : 4; 442 #endif /* DRV_BYTE_ORDER */ 443 } lis2duxs12_wake_up_dur_t; 444 445 #define LIS2DUXS12_FREE_FALL 0x1EU 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t ff_ths : 3; 450 uint8_t ff_dur : 5; 451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 452 uint8_t ff_dur : 5; 453 uint8_t ff_ths : 3; 454 #endif /* DRV_BYTE_ORDER */ 455 } lis2duxs12_free_fall_t; 456 457 #define LIS2DUXS12_MD1_CFG 0x1FU 458 typedef struct 459 { 460 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 461 uint8_t int1_emb_func : 1; 462 uint8_t int1_timestamp : 1; 463 uint8_t int1_6d : 1; 464 uint8_t int1_tap : 1; 465 uint8_t int1_ff : 1; 466 uint8_t int1_wu : 1; 467 uint8_t not_used0 : 1; 468 uint8_t int1_sleep_change : 1; 469 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 470 uint8_t int1_sleep_change : 1; 471 uint8_t not_used0 : 1; 472 uint8_t int1_wu : 1; 473 uint8_t int1_ff : 1; 474 uint8_t int1_tap : 1; 475 uint8_t int1_6d : 1; 476 uint8_t int1_timestamp : 1; 477 uint8_t int1_emb_func : 1; 478 #endif /* DRV_BYTE_ORDER */ 479 } lis2duxs12_md1_cfg_t; 480 481 #define LIS2DUXS12_MD2_CFG 0x20U 482 typedef struct 483 { 484 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 485 uint8_t int2_emb_func : 1; 486 uint8_t int2_timestamp : 1; 487 uint8_t int2_6d : 1; 488 uint8_t int2_tap : 1; 489 uint8_t int2_ff : 1; 490 uint8_t int2_wu : 1; 491 uint8_t not_used0 : 1; 492 uint8_t int2_sleep_change : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t int2_sleep_change : 1; 495 uint8_t not_used0 : 1; 496 uint8_t int2_wu : 1; 497 uint8_t int2_ff : 1; 498 uint8_t int2_tap : 1; 499 uint8_t int2_6d : 1; 500 uint8_t int2_timestamp : 1; 501 uint8_t int2_emb_func : 1; 502 #endif /* DRV_BYTE_ORDER */ 503 } lis2duxs12_md2_cfg_t; 504 505 #define LIS2DUXS12_WAKE_UP_SRC 0x21U 506 typedef struct 507 { 508 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 509 uint8_t z_wu : 1; 510 uint8_t y_wu : 1; 511 uint8_t x_wu : 1; 512 uint8_t wu_ia : 1; 513 uint8_t sleep_state : 1; 514 uint8_t ff_ia : 1; 515 uint8_t sleep_change_ia : 1; 516 uint8_t not_used0 : 1; 517 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 518 uint8_t not_used0 : 1; 519 uint8_t sleep_change_ia : 1; 520 uint8_t ff_ia : 1; 521 uint8_t sleep_state : 1; 522 uint8_t wu_ia : 1; 523 uint8_t x_wu : 1; 524 uint8_t y_wu : 1; 525 uint8_t z_wu : 1; 526 #endif /* DRV_BYTE_ORDER */ 527 } lis2duxs12_wake_up_src_t; 528 529 #define LIS2DUXS12_TAP_SRC 0x22U 530 typedef struct 531 { 532 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 533 uint8_t not_used0 : 4; 534 uint8_t triple_tap_ia : 1; 535 uint8_t double_tap_ia : 1; 536 uint8_t single_tap_ia : 1; 537 uint8_t tap_ia : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t tap_ia : 1; 540 uint8_t single_tap_ia : 1; 541 uint8_t double_tap_ia : 1; 542 uint8_t triple_tap_ia : 1; 543 uint8_t not_used0 : 4; 544 #endif /* DRV_BYTE_ORDER */ 545 } lis2duxs12_tap_src_t; 546 547 #define LIS2DUXS12_SIXD_SRC 0x23U 548 typedef struct 549 { 550 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 551 uint8_t xl : 1; 552 uint8_t xh : 1; 553 uint8_t yl : 1; 554 uint8_t yh : 1; 555 uint8_t zl : 1; 556 uint8_t zh : 1; 557 uint8_t d6d_ia : 1; 558 uint8_t not_used0 : 1; 559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 560 uint8_t not_used0 : 1; 561 uint8_t d6d_ia : 1; 562 uint8_t zh : 1; 563 uint8_t zl : 1; 564 uint8_t yh : 1; 565 uint8_t yl : 1; 566 uint8_t xh : 1; 567 uint8_t xl : 1; 568 #endif /* DRV_BYTE_ORDER */ 569 } lis2duxs12_sixd_src_t; 570 571 #define LIS2DUXS12_ALL_INT_SRC 0x24U 572 typedef struct 573 { 574 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 575 uint8_t ff_ia_all : 1; 576 uint8_t wu_ia_all : 1; 577 uint8_t single_tap_all : 1; 578 uint8_t double_tap_all : 1; 579 uint8_t triple_tap_all : 1; 580 uint8_t d6d_ia_all : 1; 581 uint8_t sleep_change_ia_all : 1; 582 uint8_t not_used0 : 1; 583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 584 uint8_t not_used0 : 1; 585 uint8_t sleep_change_ia_all : 1; 586 uint8_t d6d_ia_all : 1; 587 uint8_t triple_tap_all : 1; 588 uint8_t double_tap_all : 1; 589 uint8_t single_tap_all : 1; 590 uint8_t wu_ia_all : 1; 591 uint8_t ff_ia_all : 1; 592 #endif /* DRV_BYTE_ORDER */ 593 } lis2duxs12_all_int_src_t; 594 595 #define LIS2DUXS12_STATUS 0x25U 596 typedef struct 597 { 598 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 599 uint8_t drdy : 1; 600 uint8_t not_used0 : 4; 601 uint8_t int_global : 1; 602 uint8_t not_used1 : 2; 603 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 604 uint8_t not_used1 : 2; 605 uint8_t int_global : 1; 606 uint8_t not_used0 : 4; 607 uint8_t drdy : 1; 608 #endif /* DRV_BYTE_ORDER */ 609 } lis2duxs12_status_register_t; 610 611 #define LIS2DUXS12_FIFO_STATUS1 0x26U 612 typedef struct 613 { 614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 615 uint8_t not_used0 : 6; 616 uint8_t fifo_ovr_ia : 1; 617 uint8_t fifo_wtm_ia : 1; 618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 619 uint8_t fifo_wtm_ia : 1; 620 uint8_t fifo_ovr_ia : 1; 621 uint8_t not_used0 : 6; 622 #endif /* DRV_BYTE_ORDER */ 623 } lis2duxs12_fifo_status1_t; 624 625 #define LIS2DUXS12_FIFO_STATUS2 0x27U 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t fss : 8; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t fss : 8; 632 #endif /* DRV_BYTE_ORDER */ 633 } lis2duxs12_fifo_status2_t; 634 635 #define LIS2DUXS12_OUT_X_L 0x28U 636 typedef struct 637 { 638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 639 uint8_t outx : 8; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t outx : 8; 642 #endif /* DRV_BYTE_ORDER */ 643 } lis2duxs12_out_x_l_t; 644 645 #define LIS2DUXS12_OUT_X_H 0x29U 646 typedef struct 647 { 648 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 649 uint8_t outx : 8; 650 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 651 uint8_t outx : 8; 652 #endif /* DRV_BYTE_ORDER */ 653 } lis2duxs12_out_x_h_t; 654 655 #define LIS2DUXS12_OUT_Y_L 0x2AU 656 typedef struct 657 { 658 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 659 uint8_t outy : 8; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t outy : 8; 662 #endif /* DRV_BYTE_ORDER */ 663 } lis2duxs12_out_y_l_t; 664 665 #define LIS2DUXS12_OUT_Y_H 0x2BU 666 typedef struct 667 { 668 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 669 uint8_t outy : 8; 670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 671 uint8_t outy : 8; 672 #endif /* DRV_BYTE_ORDER */ 673 } lis2duxs12_out_y_h_t; 674 675 #define LIS2DUXS12_OUT_Z_L 0x2CU 676 typedef struct 677 { 678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 679 uint8_t outz : 8; 680 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 681 uint8_t outz : 8; 682 #endif /* DRV_BYTE_ORDER */ 683 } lis2duxs12_out_z_l_t; 684 685 #define LIS2DUXS12_OUT_Z_H 0x2DU 686 typedef struct 687 { 688 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 689 uint8_t outz : 8; 690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 691 uint8_t outz : 8; 692 #endif /* DRV_BYTE_ORDER */ 693 } lis2duxs12_out_z_h_t; 694 695 #define LIS2DUXS12_OUT_T_AH_QVAR_L 0x2EU 696 typedef struct 697 { 698 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 699 uint8_t outt : 8; 700 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 701 uint8_t outt : 8; 702 #endif /* DRV_BYTE_ORDER */ 703 } lis2duxs12_out_t_ah_qvar_l_t; 704 705 #define LIS2DUXS12_OUT_T_AH_QVAR_H 0x2FU 706 typedef struct 707 { 708 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 709 uint8_t outt : 8; 710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 711 uint8_t outt : 8; 712 #endif /* DRV_BYTE_ORDER */ 713 } lis2duxs12_out_t_ah_qvar_h_t; 714 715 #define LIS2DUXS12_AH_QVAR_CFG 0x31U 716 typedef struct 717 { 718 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 719 uint8_t not_used0 : 1; 720 uint8_t ah_qvar_gain : 2; 721 uint8_t ah_qvar_c_zin : 2; 722 uint8_t ah_qvar_notch_cutoff : 1; 723 uint8_t ah_qvar_notch_en : 1; 724 uint8_t ah_qvar_en : 1; 725 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 726 uint8_t ah_qvar_en : 1; 727 uint8_t ah_qvar_notch_en : 1; 728 uint8_t ah_qvar_notch_cutoff : 1; 729 uint8_t ah_qvar_c_zin : 2; 730 uint8_t ah_qvar_gain : 2; 731 uint8_t not_used0 : 1; 732 #endif /* DRV_BYTE_ORDER */ 733 } lis2duxs12_ah_qvar_cfg_t; 734 735 #define LIS2DUXS12_SELF_TEST 0x32U 736 typedef struct 737 { 738 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 739 uint8_t t_ah_qvar_dis : 1; 740 uint8_t not_used0 : 3; 741 uint8_t st : 2; 742 uint8_t not_used1 : 2; 743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 744 uint8_t not_used1 : 2; 745 uint8_t st : 2; 746 uint8_t not_used0 : 3; 747 uint8_t t_ah_qvar_dis : 1; 748 #endif /* DRV_BYTE_ORDER */ 749 } lis2duxs12_self_test_t; 750 751 #define LIS2DUXS12_I3C_IF_CTRL 0x33U 752 typedef struct 753 { 754 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 755 uint8_t bus_act_sel : 2; 756 uint8_t not_used0 : 3; 757 uint8_t asf_on : 1; 758 uint8_t dis_drstdaa : 1; 759 uint8_t not_used1 : 1; 760 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 761 uint8_t not_used1 : 1; 762 uint8_t dis_drstdaa : 1; 763 uint8_t asf_on : 1; 764 uint8_t not_used0 : 3; 765 uint8_t bus_act_sel : 2; 766 #endif /* DRV_BYTE_ORDER */ 767 } lis2duxs12_i3c_if_ctrl_t; 768 769 #define LIS2DUXS12_EMB_FUNC_STATUS_MAINPAGE 0x34U 770 typedef struct 771 { 772 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 773 uint8_t not_used0 : 3; 774 uint8_t is_step_det : 1; 775 uint8_t is_tilt : 1; 776 uint8_t is_sigmot : 1; 777 uint8_t not_used1 : 1; 778 uint8_t is_fsm_lc : 1; 779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 780 uint8_t is_fsm_lc : 1; 781 uint8_t not_used1 : 1; 782 uint8_t is_sigmot : 1; 783 uint8_t is_tilt : 1; 784 uint8_t is_step_det : 1; 785 uint8_t not_used0 : 3; 786 #endif /* DRV_BYTE_ORDER */ 787 } lis2duxs12_emb_func_status_mainpage_t; 788 789 #define LIS2DUXS12_FSM_STATUS_MAINPAGE 0x35U 790 typedef struct 791 { 792 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 793 uint8_t is_fsm1 : 1; 794 uint8_t is_fsm2 : 1; 795 uint8_t is_fsm3 : 1; 796 uint8_t is_fsm4 : 1; 797 uint8_t is_fsm5 : 1; 798 uint8_t is_fsm6 : 1; 799 uint8_t is_fsm7 : 1; 800 uint8_t is_fsm8 : 1; 801 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 802 uint8_t is_fsm8 : 1; 803 uint8_t is_fsm7 : 1; 804 uint8_t is_fsm6 : 1; 805 uint8_t is_fsm5 : 1; 806 uint8_t is_fsm4 : 1; 807 uint8_t is_fsm3 : 1; 808 uint8_t is_fsm2 : 1; 809 uint8_t is_fsm1 : 1; 810 #endif /* DRV_BYTE_ORDER */ 811 } lis2duxs12_fsm_status_mainpage_t; 812 813 #define LIS2DUXS12_MLC_STATUS_MAINPAGE 0x36U 814 typedef struct 815 { 816 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 817 uint8_t is_mlc1 : 1; 818 uint8_t is_mlc2 : 1; 819 uint8_t is_mlc3 : 1; 820 uint8_t is_mlc4 : 1; 821 uint8_t not_used0 : 4; 822 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 823 uint8_t not_used0 : 4; 824 uint8_t is_mlc4 : 1; 825 uint8_t is_mlc3 : 1; 826 uint8_t is_mlc2 : 1; 827 uint8_t is_mlc1 : 1; 828 #endif /* DRV_BYTE_ORDER */ 829 } lis2duxs12_mlc_status_mainpage_t; 830 831 #define LIS2DUXS12_SLEEP 0x3DU 832 typedef struct 833 { 834 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 835 uint8_t deep_pd : 1; 836 uint8_t not_used0 : 7; 837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 838 uint8_t not_used0 : 7; 839 uint8_t deep_pd : 1; 840 #endif /* DRV_BYTE_ORDER */ 841 } lis2duxs12_sleep_t; 842 843 #define LIS2DUXS12_EN_DEVICE_CONFIG 0x3EU 844 typedef struct 845 { 846 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 847 uint8_t soft_pd : 1; 848 uint8_t not_used0 : 7; 849 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 850 uint8_t not_used0 : 7; 851 uint8_t soft_pd : 1; 852 #endif /* DRV_BYTE_ORDER */ 853 } lis2duxs12_en_device_config_t; 854 855 #define LIS2DUXS12_FUNC_CFG_ACCESS 0x3FU 856 typedef struct 857 { 858 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 859 uint8_t fsm_wr_ctrl_en : 1; 860 uint8_t not_used0 : 6; 861 uint8_t emb_func_reg_access : 1; 862 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 863 uint8_t emb_func_reg_access : 1; 864 uint8_t not_used0 : 6; 865 uint8_t fsm_wr_ctrl_en : 1; 866 #endif /* DRV_BYTE_ORDER */ 867 } lis2duxs12_func_cfg_access_t; 868 869 #define LIS2DUXS12_FIFO_DATA_OUT_TAG 0x40U 870 typedef struct 871 { 872 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 873 uint8_t not_used0 : 3; 874 uint8_t tag_sensor : 5; 875 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 876 uint8_t tag_sensor : 5; 877 uint8_t not_used0 : 3; 878 #endif /* DRV_BYTE_ORDER */ 879 } lis2duxs12_fifo_data_out_tag_t; 880 881 #define LIS2DUXS12_FIFO_DATA_OUT_X_L 0x41U 882 typedef struct 883 { 884 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 885 uint8_t fifo_data_out : 8; 886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 887 uint8_t fifo_data_out : 8; 888 #endif /* DRV_BYTE_ORDER */ 889 } lis2duxs12_fifo_data_out_x_l_t; 890 891 #define LIS2DUXS12_FIFO_DATA_OUT_X_H 0x42U 892 typedef struct 893 { 894 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 895 uint8_t fifo_data_out : 8; 896 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 897 uint8_t fifo_data_out : 8; 898 #endif /* DRV_BYTE_ORDER */ 899 } lis2duxs12_fifo_data_out_x_h_t; 900 901 #define LIS2DUXS12_FIFO_DATA_OUT_Y_L 0x43U 902 typedef struct 903 { 904 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 905 uint8_t fifo_data_out : 8; 906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 907 uint8_t fifo_data_out : 8; 908 #endif /* DRV_BYTE_ORDER */ 909 } lis2duxs12_fifo_data_out_y_l_t; 910 911 #define LIS2DUXS12_FIFO_DATA_OUT_Y_H 0x44U 912 typedef struct 913 { 914 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 915 uint8_t fifo_data_out : 8; 916 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 917 uint8_t fifo_data_out : 8; 918 #endif /* DRV_BYTE_ORDER */ 919 } lis2duxs12_fifo_data_out_y_h_t; 920 921 #define LIS2DUXS12_FIFO_DATA_OUT_Z_L 0x45U 922 typedef struct 923 { 924 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 925 uint8_t fifo_data_out : 8; 926 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 927 uint8_t fifo_data_out : 8; 928 #endif /* DRV_BYTE_ORDER */ 929 } lis2duxs12_fifo_data_out_z_l_t; 930 931 #define LIS2DUXS12_FIFO_DATA_OUT_Z_H 0x46U 932 typedef struct 933 { 934 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 935 uint8_t fifo_data_out : 8; 936 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 937 uint8_t fifo_data_out : 8; 938 #endif /* DRV_BYTE_ORDER */ 939 } lis2duxs12_fifo_data_out_z_h_t; 940 941 #define LIS2DUXS12_FIFO_BATCH_DEC 0x47U 942 typedef struct 943 { 944 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 945 uint8_t bdr_xl : 3; 946 uint8_t dec_ts_batch : 2; 947 uint8_t not_used0 : 3; 948 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 949 uint8_t not_used0 : 3; 950 uint8_t dec_ts_batch : 2; 951 uint8_t bdr_xl : 3; 952 #endif /* DRV_BYTE_ORDER */ 953 } lis2duxs12_fifo_batch_dec_t; 954 955 #define LIS2DUXS12_TAP_CFG0 0x6FU 956 typedef struct 957 { 958 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 959 uint8_t not_used0 : 1; 960 uint8_t invert_t : 5; 961 uint8_t axis : 2; 962 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 963 uint8_t axis : 2; 964 uint8_t invert_t : 5; 965 uint8_t not_used0 : 1; 966 #endif /* DRV_BYTE_ORDER */ 967 } lis2duxs12_tap_cfg0_t; 968 969 #define LIS2DUXS12_TAP_CFG1 0x70U 970 typedef struct 971 { 972 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 973 uint8_t post_still_t : 4; 974 uint8_t pre_still_ths : 4; 975 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 976 uint8_t pre_still_ths : 4; 977 uint8_t post_still_t : 4; 978 #endif /* DRV_BYTE_ORDER */ 979 } lis2duxs12_tap_cfg1_t; 980 981 #define LIS2DUXS12_TAP_CFG2 0x71U 982 typedef struct 983 { 984 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 985 uint8_t wait_t : 6; 986 uint8_t post_still_t : 2; 987 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 988 uint8_t post_still_t : 2; 989 uint8_t wait_t : 6; 990 #endif /* DRV_BYTE_ORDER */ 991 } lis2duxs12_tap_cfg2_t; 992 993 #define LIS2DUXS12_TAP_CFG3 0x72U 994 typedef struct 995 { 996 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 997 uint8_t latency_t : 4; 998 uint8_t post_still_ths : 4; 999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1000 uint8_t post_still_ths : 4; 1001 uint8_t latency_t : 4; 1002 #endif /* DRV_BYTE_ORDER */ 1003 } lis2duxs12_tap_cfg3_t; 1004 1005 #define LIS2DUXS12_TAP_CFG4 0x73U 1006 typedef struct 1007 { 1008 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1009 uint8_t peak_ths : 6; 1010 uint8_t not_used0 : 1; 1011 uint8_t wait_end_latency : 1; 1012 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1013 uint8_t wait_end_latency : 1; 1014 uint8_t not_used0 : 1; 1015 uint8_t peak_ths : 6; 1016 #endif /* DRV_BYTE_ORDER */ 1017 } lis2duxs12_tap_cfg4_t; 1018 1019 #define LIS2DUXS12_TAP_CFG5 0x74U 1020 typedef struct 1021 { 1022 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1023 uint8_t rebound_t : 5; 1024 uint8_t single_tap_en : 1; 1025 uint8_t double_tap_en : 1; 1026 uint8_t triple_tap_en : 1; 1027 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1028 uint8_t triple_tap_en : 1; 1029 uint8_t double_tap_en : 1; 1030 uint8_t single_tap_en : 1; 1031 uint8_t rebound_t : 5; 1032 #endif /* DRV_BYTE_ORDER */ 1033 } lis2duxs12_tap_cfg5_t; 1034 1035 #define LIS2DUXS12_TAP_CFG6 0x75U 1036 typedef struct 1037 { 1038 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1039 uint8_t pre_still_n : 4; 1040 uint8_t pre_still_st : 4; 1041 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1042 uint8_t pre_still_st : 4; 1043 uint8_t pre_still_n : 4; 1044 #endif /* DRV_BYTE_ORDER */ 1045 } lis2duxs12_tap_cfg6_t; 1046 1047 #define LIS2DUXS12_TIMESTAMP0 0x7AU 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t timestamp : 8; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t timestamp : 8; 1054 #endif /* DRV_BYTE_ORDER */ 1055 } lis2duxs12_timestamp0_t; 1056 1057 #define LIS2DUXS12_TIMESTAMP1 0x7BU 1058 typedef struct 1059 { 1060 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1061 uint8_t timestamp : 8; 1062 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1063 uint8_t timestamp : 8; 1064 #endif /* DRV_BYTE_ORDER */ 1065 } lis2duxs12_timestamp1_t; 1066 1067 #define LIS2DUXS12_TIMESTAMP2 0x7CU 1068 typedef struct 1069 { 1070 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1071 uint8_t timestamp : 8; 1072 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1073 uint8_t timestamp : 8; 1074 #endif /* DRV_BYTE_ORDER */ 1075 } lis2duxs12_timestamp2_t; 1076 1077 #define LIS2DUXS12_TIMESTAMP3 0x7DU 1078 typedef struct 1079 { 1080 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1081 uint8_t timestamp : 8; 1082 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1083 uint8_t timestamp : 8; 1084 #endif /* DRV_BYTE_ORDER */ 1085 } lis2duxs12_timestamp3_t; 1086 1087 /** 1088 * @} 1089 * 1090 */ 1091 1092 /** @defgroup bitfields page embedded 1093 * @{ 1094 * 1095 */ 1096 1097 #define LIS2DUXS12_PAGE_SEL 0x2U 1098 typedef struct 1099 { 1100 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1101 uint8_t not_used0 : 4; 1102 uint8_t page_sel : 4; 1103 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1104 uint8_t page_sel : 4; 1105 uint8_t not_used0 : 4; 1106 #endif /* DRV_BYTE_ORDER */ 1107 } lis2duxs12_page_sel_t; 1108 1109 #define LIS2DUXS12_EMB_FUNC_EN_A 0x4U 1110 typedef struct 1111 { 1112 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1113 uint8_t not_used0 : 3; 1114 uint8_t pedo_en : 1; 1115 uint8_t tilt_en : 1; 1116 uint8_t sign_motion_en : 1; 1117 uint8_t not_used1 : 1; 1118 uint8_t mlc_before_fsm_en : 1; 1119 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1120 uint8_t mlc_before_fsm_en : 1; 1121 uint8_t not_used1 : 1; 1122 uint8_t sign_motion_en : 1; 1123 uint8_t tilt_en : 1; 1124 uint8_t pedo_en : 1; 1125 uint8_t not_used0 : 3; 1126 #endif /* DRV_BYTE_ORDER */ 1127 } lis2duxs12_emb_func_en_a_t; 1128 1129 #define LIS2DUXS12_EMB_FUNC_EN_B 0x5U 1130 typedef struct 1131 { 1132 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1133 uint8_t fsm_en : 1; 1134 uint8_t not_used0 : 3; 1135 uint8_t mlc_en : 1; 1136 uint8_t not_used1 : 3; 1137 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1138 uint8_t not_used1 : 3; 1139 uint8_t mlc_en : 1; 1140 uint8_t not_used0 : 3; 1141 uint8_t fsm_en : 1; 1142 #endif /* DRV_BYTE_ORDER */ 1143 } lis2duxs12_emb_func_en_b_t; 1144 1145 #define LIS2DUXS12_EMB_FUNC_EXEC_STATUS 0x7U 1146 typedef struct 1147 { 1148 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1149 uint8_t emb_func_endop : 1; 1150 uint8_t emb_func_exec_ovr : 1; 1151 uint8_t not_used0 : 6; 1152 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1153 uint8_t not_used0 : 6; 1154 uint8_t emb_func_exec_ovr : 1; 1155 uint8_t emb_func_endop : 1; 1156 #endif /* DRV_BYTE_ORDER */ 1157 } lis2duxs12_emb_func_exec_status_t; 1158 1159 #define LIS2DUXS12_PAGE_ADDRESS 0x8U 1160 typedef struct 1161 { 1162 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1163 uint8_t page_addr : 8; 1164 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1165 uint8_t page_addr : 8; 1166 #endif /* DRV_BYTE_ORDER */ 1167 } lis2duxs12_page_address_t; 1168 1169 #define LIS2DUXS12_PAGE_VALUE 0x9U 1170 typedef struct 1171 { 1172 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1173 uint8_t page_value : 8; 1174 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1175 uint8_t page_value : 8; 1176 #endif /* DRV_BYTE_ORDER */ 1177 } lis2duxs12_page_value_t; 1178 1179 #define LIS2DUXS12_EMB_FUNC_INT1 0x0AU 1180 typedef struct 1181 { 1182 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1183 uint8_t not_used0 : 3; 1184 uint8_t int1_step_det : 1; 1185 uint8_t int1_tilt : 1; 1186 uint8_t int1_sig_mot : 1; 1187 uint8_t not_used1 : 1; 1188 uint8_t int1_fsm_lc : 1; 1189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1190 uint8_t int1_fsm_lc : 1; 1191 uint8_t not_used1 : 1; 1192 uint8_t int1_sig_mot : 1; 1193 uint8_t int1_tilt : 1; 1194 uint8_t int1_step_det : 1; 1195 uint8_t not_used0 : 3; 1196 #endif /* DRV_BYTE_ORDER */ 1197 } lis2duxs12_emb_func_int1_t; 1198 1199 #define LIS2DUXS12_FSM_INT1 0x0BU 1200 typedef struct 1201 { 1202 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1203 uint8_t int1_fsm1 : 1; 1204 uint8_t int1_fsm2 : 1; 1205 uint8_t int1_fsm3 : 1; 1206 uint8_t int1_fsm4 : 1; 1207 uint8_t int1_fsm5 : 1; 1208 uint8_t int1_fsm6 : 1; 1209 uint8_t int1_fsm7 : 1; 1210 uint8_t int1_fsm8 : 1; 1211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1212 uint8_t int1_fsm8 : 1; 1213 uint8_t int1_fsm7 : 1; 1214 uint8_t int1_fsm6 : 1; 1215 uint8_t int1_fsm5 : 1; 1216 uint8_t int1_fsm4 : 1; 1217 uint8_t int1_fsm3 : 1; 1218 uint8_t int1_fsm2 : 1; 1219 uint8_t int1_fsm1 : 1; 1220 #endif /* DRV_BYTE_ORDER */ 1221 } lis2duxs12_fsm_int1_t; 1222 1223 #define LIS2DUXS12_MLC_INT1 0x0DU 1224 typedef struct 1225 { 1226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1227 uint8_t int1_mlc1 : 1; 1228 uint8_t int1_mlc2 : 1; 1229 uint8_t int1_mlc3 : 1; 1230 uint8_t int1_mlc4 : 1; 1231 uint8_t not_used0 : 4; 1232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1233 uint8_t not_used0 : 4; 1234 uint8_t int1_mlc4 : 1; 1235 uint8_t int1_mlc3 : 1; 1236 uint8_t int1_mlc2 : 1; 1237 uint8_t int1_mlc1 : 1; 1238 #endif /* DRV_BYTE_ORDER */ 1239 } lis2duxs12_mlc_int1_t; 1240 1241 #define LIS2DUXS12_EMB_FUNC_INT2 0x0EU 1242 typedef struct 1243 { 1244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1245 uint8_t not_used0 : 3; 1246 uint8_t int2_step_det : 1; 1247 uint8_t int2_tilt : 1; 1248 uint8_t int2_sig_mot : 1; 1249 uint8_t not_used1 : 1; 1250 uint8_t int2_fsm_lc : 1; 1251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1252 uint8_t int2_fsm_lc : 1; 1253 uint8_t not_used1 : 1; 1254 uint8_t int2_sig_mot : 1; 1255 uint8_t int2_tilt : 1; 1256 uint8_t int2_step_det : 1; 1257 uint8_t not_used0 : 3; 1258 #endif /* DRV_BYTE_ORDER */ 1259 } lis2duxs12_emb_func_int2_t; 1260 1261 #define LIS2DUXS12_FSM_INT2 0x0FU 1262 typedef struct 1263 { 1264 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1265 uint8_t int2_fsm1 : 1; 1266 uint8_t int2_fsm2 : 1; 1267 uint8_t int2_fsm3 : 1; 1268 uint8_t int2_fsm4 : 1; 1269 uint8_t int2_fsm5 : 1; 1270 uint8_t int2_fsm6 : 1; 1271 uint8_t int2_fsm7 : 1; 1272 uint8_t int2_fsm8 : 1; 1273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1274 uint8_t int2_fsm8 : 1; 1275 uint8_t int2_fsm7 : 1; 1276 uint8_t int2_fsm6 : 1; 1277 uint8_t int2_fsm5 : 1; 1278 uint8_t int2_fsm4 : 1; 1279 uint8_t int2_fsm3 : 1; 1280 uint8_t int2_fsm2 : 1; 1281 uint8_t int2_fsm1 : 1; 1282 #endif /* DRV_BYTE_ORDER */ 1283 } lis2duxs12_fsm_int2_t; 1284 1285 #define LIS2DUXS12_MLC_INT2 0x11U 1286 typedef struct 1287 { 1288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1289 uint8_t int2_mlc1 : 1; 1290 uint8_t int2_mlc2 : 1; 1291 uint8_t int2_mlc3 : 1; 1292 uint8_t int2_mlc4 : 1; 1293 uint8_t not_used0 : 4; 1294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1295 uint8_t not_used0 : 4; 1296 uint8_t int2_mlc4 : 1; 1297 uint8_t int2_mlc3 : 1; 1298 uint8_t int2_mlc2 : 1; 1299 uint8_t int2_mlc1 : 1; 1300 #endif /* DRV_BYTE_ORDER */ 1301 } lis2duxs12_mlc_int2_t; 1302 1303 #define LIS2DUXS12_EMB_FUNC_STATUS 0x12U 1304 typedef struct 1305 { 1306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1307 uint8_t not_used0 : 3; 1308 uint8_t is_step_det : 1; 1309 uint8_t is_tilt : 1; 1310 uint8_t is_sigmot : 1; 1311 uint8_t not_used1 : 1; 1312 uint8_t is_fsm_lc : 1; 1313 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1314 uint8_t is_fsm_lc : 1; 1315 uint8_t not_used1 : 1; 1316 uint8_t is_sigmot : 1; 1317 uint8_t is_tilt : 1; 1318 uint8_t is_step_det : 1; 1319 uint8_t not_used0 : 3; 1320 #endif /* DRV_BYTE_ORDER */ 1321 } lis2duxs12_emb_func_status_t; 1322 1323 #define LIS2DUXS12_FSM_STATUS 0x13U 1324 typedef struct 1325 { 1326 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1327 uint8_t is_fsm1 : 1; 1328 uint8_t is_fsm2 : 1; 1329 uint8_t is_fsm3 : 1; 1330 uint8_t is_fsm4 : 1; 1331 uint8_t is_fsm5 : 1; 1332 uint8_t is_fsm6 : 1; 1333 uint8_t is_fsm7 : 1; 1334 uint8_t is_fsm8 : 1; 1335 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1336 uint8_t is_fsm8 : 1; 1337 uint8_t is_fsm7 : 1; 1338 uint8_t is_fsm6 : 1; 1339 uint8_t is_fsm5 : 1; 1340 uint8_t is_fsm4 : 1; 1341 uint8_t is_fsm3 : 1; 1342 uint8_t is_fsm2 : 1; 1343 uint8_t is_fsm1 : 1; 1344 #endif /* DRV_BYTE_ORDER */ 1345 } lis2duxs12_fsm_status_t; 1346 1347 #define LIS2DUXS12_MLC_STATUS 0x15U 1348 typedef struct 1349 { 1350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1351 uint8_t is_mlc1 : 1; 1352 uint8_t is_mlc2 : 1; 1353 uint8_t is_mlc3 : 1; 1354 uint8_t is_mlc4 : 1; 1355 uint8_t not_used0 : 4; 1356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1357 uint8_t not_used0 : 4; 1358 uint8_t is_mlc4 : 1; 1359 uint8_t is_mlc3 : 1; 1360 uint8_t is_mlc2 : 1; 1361 uint8_t is_mlc1 : 1; 1362 #endif /* DRV_BYTE_ORDER */ 1363 } lis2duxs12_mlc_status_t; 1364 1365 #define LIS2DUXS12_PAGE_RW 0x17U 1366 typedef struct 1367 { 1368 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1369 uint8_t not_used0 : 5; 1370 uint8_t page_read : 1; 1371 uint8_t page_write : 1; 1372 uint8_t emb_func_lir : 1; 1373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1374 uint8_t emb_func_lir : 1; 1375 uint8_t page_write : 1; 1376 uint8_t page_read : 1; 1377 uint8_t not_used0 : 5; 1378 #endif /* DRV_BYTE_ORDER */ 1379 } lis2duxs12_page_rw_t; 1380 1381 #define LIS2DUXS12_EMB_FUNC_FIFO_EN 0x18U 1382 typedef struct 1383 { 1384 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1385 uint8_t step_counter_fifo_en : 1; 1386 uint8_t mlc_fifo_en : 1; 1387 uint8_t mlc_filter_feature_fifo_en : 1; 1388 uint8_t fsm_fifo_en : 1; 1389 uint8_t not_used0 : 4; 1390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1391 uint8_t not_used0 : 4; 1392 uint8_t fsm_fifo_en : 1; 1393 uint8_t mlc_filter_feature_fifo_en : 1; 1394 uint8_t mlc_fifo_en : 1; 1395 uint8_t step_counter_fifo_en : 1; 1396 #endif /* DRV_BYTE_ORDER */ 1397 } lis2duxs12_emb_func_fifo_en_t; 1398 1399 #define LIS2DUXS12_FSM_ENABLE 0x1AU 1400 typedef struct 1401 { 1402 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1403 uint8_t fsm1_en : 1; 1404 uint8_t fsm2_en : 1; 1405 uint8_t fsm3_en : 1; 1406 uint8_t fsm4_en : 1; 1407 uint8_t fsm5_en : 1; 1408 uint8_t fsm6_en : 1; 1409 uint8_t fsm7_en : 1; 1410 uint8_t fsm8_en : 1; 1411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1412 uint8_t fsm8_en : 1; 1413 uint8_t fsm7_en : 1; 1414 uint8_t fsm6_en : 1; 1415 uint8_t fsm5_en : 1; 1416 uint8_t fsm4_en : 1; 1417 uint8_t fsm3_en : 1; 1418 uint8_t fsm2_en : 1; 1419 uint8_t fsm1_en : 1; 1420 #endif /* DRV_BYTE_ORDER */ 1421 } lis2duxs12_fsm_enable_t; 1422 1423 #define LIS2DUXS12_FSM_LONG_COUNTER_L 0x1CU 1424 typedef struct 1425 { 1426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1427 uint8_t fsm_lc : 8; 1428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1429 uint8_t fsm_lc : 8; 1430 #endif /* DRV_BYTE_ORDER */ 1431 } lis2duxs12_fsm_long_counter_l_t; 1432 1433 #define LIS2DUXS12_FSM_LONG_COUNTER_H 0x1DU 1434 typedef struct 1435 { 1436 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1437 uint8_t fsm_lc : 8; 1438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1439 uint8_t fsm_lc : 8; 1440 #endif /* DRV_BYTE_ORDER */ 1441 } lis2duxs12_fsm_long_counter_h_t; 1442 1443 #define LIS2DUXS12_INT_ACK_MASK 0x1FU 1444 typedef struct 1445 { 1446 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1447 uint8_t iack_mask0 : 1; 1448 uint8_t iack_mask1 : 1; 1449 uint8_t iack_mask2 : 1; 1450 uint8_t iack_mask3 : 1; 1451 uint8_t iack_mask4 : 1; 1452 uint8_t iack_mask5 : 1; 1453 uint8_t iack_mask6 : 1; 1454 uint8_t iack_mask7 : 1; 1455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1456 uint8_t iack_mask7 : 1; 1457 uint8_t iack_mask6 : 1; 1458 uint8_t iack_mask5 : 1; 1459 uint8_t iack_mask4 : 1; 1460 uint8_t iack_mask3 : 1; 1461 uint8_t iack_mask2 : 1; 1462 uint8_t iack_mask1 : 1; 1463 uint8_t iack_mask0 : 1; 1464 #endif /* DRV_BYTE_ORDER */ 1465 } lis2duxs12_int_ack_mask_t; 1466 1467 #define LIS2DUXS12_FSM_OUTS1 0x20U 1468 typedef struct 1469 { 1470 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1471 uint8_t n_v : 1; 1472 uint8_t p_v : 1; 1473 uint8_t n_z : 1; 1474 uint8_t p_z : 1; 1475 uint8_t n_y : 1; 1476 uint8_t p_y : 1; 1477 uint8_t n_x : 1; 1478 uint8_t p_x : 1; 1479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1480 uint8_t p_x : 1; 1481 uint8_t n_x : 1; 1482 uint8_t p_y : 1; 1483 uint8_t n_y : 1; 1484 uint8_t p_z : 1; 1485 uint8_t n_z : 1; 1486 uint8_t p_v : 1; 1487 uint8_t n_v : 1; 1488 #endif /* DRV_BYTE_ORDER */ 1489 } lis2duxs12_fsm_outs1_t; 1490 1491 #define LIS2DUXS12_FSM_OUTS2 0x21U 1492 typedef struct 1493 { 1494 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1495 uint8_t n_v : 1; 1496 uint8_t p_v : 1; 1497 uint8_t n_z : 1; 1498 uint8_t p_z : 1; 1499 uint8_t n_y : 1; 1500 uint8_t p_y : 1; 1501 uint8_t n_x : 1; 1502 uint8_t p_x : 1; 1503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1504 uint8_t p_x : 1; 1505 uint8_t n_x : 1; 1506 uint8_t p_y : 1; 1507 uint8_t n_y : 1; 1508 uint8_t p_z : 1; 1509 uint8_t n_z : 1; 1510 uint8_t p_v : 1; 1511 uint8_t n_v : 1; 1512 #endif /* DRV_BYTE_ORDER */ 1513 } lis2duxs12_fsm_outs2_t; 1514 1515 #define LIS2DUXS12_FSM_OUTS3 0x22U 1516 typedef struct 1517 { 1518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1519 uint8_t n_v : 1; 1520 uint8_t p_v : 1; 1521 uint8_t n_z : 1; 1522 uint8_t p_z : 1; 1523 uint8_t n_y : 1; 1524 uint8_t p_y : 1; 1525 uint8_t n_x : 1; 1526 uint8_t p_x : 1; 1527 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1528 uint8_t p_x : 1; 1529 uint8_t n_x : 1; 1530 uint8_t p_y : 1; 1531 uint8_t n_y : 1; 1532 uint8_t p_z : 1; 1533 uint8_t n_z : 1; 1534 uint8_t p_v : 1; 1535 uint8_t n_v : 1; 1536 #endif /* DRV_BYTE_ORDER */ 1537 } lis2duxs12_fsm_outs3_t; 1538 1539 #define LIS2DUXS12_FSM_OUTS4 0x23U 1540 typedef struct 1541 { 1542 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1543 uint8_t n_v : 1; 1544 uint8_t p_v : 1; 1545 uint8_t n_z : 1; 1546 uint8_t p_z : 1; 1547 uint8_t n_y : 1; 1548 uint8_t p_y : 1; 1549 uint8_t n_x : 1; 1550 uint8_t p_x : 1; 1551 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1552 uint8_t p_x : 1; 1553 uint8_t n_x : 1; 1554 uint8_t p_y : 1; 1555 uint8_t n_y : 1; 1556 uint8_t p_z : 1; 1557 uint8_t n_z : 1; 1558 uint8_t p_v : 1; 1559 uint8_t n_v : 1; 1560 #endif /* DRV_BYTE_ORDER */ 1561 } lis2duxs12_fsm_outs4_t; 1562 1563 #define LIS2DUXS12_FSM_OUTS5 0x24U 1564 typedef struct 1565 { 1566 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1567 uint8_t n_v : 1; 1568 uint8_t p_v : 1; 1569 uint8_t n_z : 1; 1570 uint8_t p_z : 1; 1571 uint8_t n_y : 1; 1572 uint8_t p_y : 1; 1573 uint8_t n_x : 1; 1574 uint8_t p_x : 1; 1575 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1576 uint8_t p_x : 1; 1577 uint8_t n_x : 1; 1578 uint8_t p_y : 1; 1579 uint8_t n_y : 1; 1580 uint8_t p_z : 1; 1581 uint8_t n_z : 1; 1582 uint8_t p_v : 1; 1583 uint8_t n_v : 1; 1584 #endif /* DRV_BYTE_ORDER */ 1585 } lis2duxs12_fsm_outs5_t; 1586 1587 #define LIS2DUXS12_FSM_OUTS6 0x25U 1588 typedef struct 1589 { 1590 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1591 uint8_t n_v : 1; 1592 uint8_t p_v : 1; 1593 uint8_t n_z : 1; 1594 uint8_t p_z : 1; 1595 uint8_t n_y : 1; 1596 uint8_t p_y : 1; 1597 uint8_t n_x : 1; 1598 uint8_t p_x : 1; 1599 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1600 uint8_t p_x : 1; 1601 uint8_t n_x : 1; 1602 uint8_t p_y : 1; 1603 uint8_t n_y : 1; 1604 uint8_t p_z : 1; 1605 uint8_t n_z : 1; 1606 uint8_t p_v : 1; 1607 uint8_t n_v : 1; 1608 #endif /* DRV_BYTE_ORDER */ 1609 } lis2duxs12_fsm_outs6_t; 1610 1611 #define LIS2DUXS12_FSM_OUTS7 0x26U 1612 typedef struct 1613 { 1614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1615 uint8_t n_v : 1; 1616 uint8_t p_v : 1; 1617 uint8_t n_z : 1; 1618 uint8_t p_z : 1; 1619 uint8_t n_y : 1; 1620 uint8_t p_y : 1; 1621 uint8_t n_x : 1; 1622 uint8_t p_x : 1; 1623 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1624 uint8_t p_x : 1; 1625 uint8_t n_x : 1; 1626 uint8_t p_y : 1; 1627 uint8_t n_y : 1; 1628 uint8_t p_z : 1; 1629 uint8_t n_z : 1; 1630 uint8_t p_v : 1; 1631 uint8_t n_v : 1; 1632 #endif /* DRV_BYTE_ORDER */ 1633 } lis2duxs12_fsm_outs7_t; 1634 1635 #define LIS2DUXS12_FSM_OUTS8 0x27U 1636 typedef struct 1637 { 1638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1639 uint8_t n_v : 1; 1640 uint8_t p_v : 1; 1641 uint8_t n_z : 1; 1642 uint8_t p_z : 1; 1643 uint8_t n_y : 1; 1644 uint8_t p_y : 1; 1645 uint8_t n_x : 1; 1646 uint8_t p_x : 1; 1647 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1648 uint8_t p_x : 1; 1649 uint8_t n_x : 1; 1650 uint8_t p_y : 1; 1651 uint8_t n_y : 1; 1652 uint8_t p_z : 1; 1653 uint8_t n_z : 1; 1654 uint8_t p_v : 1; 1655 uint8_t n_v : 1; 1656 #endif /* DRV_BYTE_ORDER */ 1657 } lis2duxs12_fsm_outs8_t; 1658 1659 #define LIS2DUXS12_STEP_COUNTER_L 0x28U 1660 typedef struct 1661 { 1662 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1663 uint8_t step : 8; 1664 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1665 uint8_t step : 8; 1666 #endif /* DRV_BYTE_ORDER */ 1667 } lis2duxs12_step_counter_l_t; 1668 1669 #define LIS2DUXS12_STEP_COUNTER_H 0x29U 1670 typedef struct 1671 { 1672 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1673 uint8_t step : 8; 1674 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1675 uint8_t step : 8; 1676 #endif /* DRV_BYTE_ORDER */ 1677 } lis2duxs12_step_counter_h_t; 1678 1679 #define LIS2DUXS12_EMB_FUNC_SRC 0x2AU 1680 typedef struct 1681 { 1682 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1683 uint8_t not_used0 : 2; 1684 uint8_t stepcounter_bit_set : 1; 1685 uint8_t step_overflow : 1; 1686 uint8_t step_count_delta_ia : 1; 1687 uint8_t step_detected : 1; 1688 uint8_t not_used1 : 1; 1689 uint8_t pedo_rst_step : 1; 1690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1691 uint8_t pedo_rst_step : 1; 1692 uint8_t not_used1 : 1; 1693 uint8_t step_detected : 1; 1694 uint8_t step_count_delta_ia : 1; 1695 uint8_t step_overflow : 1; 1696 uint8_t stepcounter_bit_set : 1; 1697 uint8_t not_used0 : 2; 1698 #endif /* DRV_BYTE_ORDER */ 1699 } lis2duxs12_emb_func_src_t; 1700 1701 #define LIS2DUXS12_EMB_FUNC_INIT_A 0x2CU 1702 typedef struct 1703 { 1704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1705 uint8_t not_used0 : 3; 1706 uint8_t step_det_init : 1; 1707 uint8_t tilt_init : 1; 1708 uint8_t sig_mot_init : 1; 1709 uint8_t not_used1 : 1; 1710 uint8_t mlc_before_fsm_init : 1; 1711 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1712 uint8_t mlc_before_fsm_init : 1; 1713 uint8_t not_used1 : 1; 1714 uint8_t sig_mot_init : 1; 1715 uint8_t tilt_init : 1; 1716 uint8_t step_det_init : 1; 1717 uint8_t not_used0 : 3; 1718 #endif /* DRV_BYTE_ORDER */ 1719 } lis2duxs12_emb_func_init_a_t; 1720 1721 #define LIS2DUXS12_EMB_FUNC_INIT_B 0x2DU 1722 typedef struct 1723 { 1724 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1725 uint8_t fsm_init : 1; 1726 uint8_t not_used0 : 3; 1727 uint8_t mlc_init : 1; 1728 uint8_t not_used1 : 3; 1729 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1730 uint8_t not_used1 : 3; 1731 uint8_t mlc_init : 1; 1732 uint8_t not_used0 : 3; 1733 uint8_t fsm_init : 1; 1734 #endif /* DRV_BYTE_ORDER */ 1735 } lis2duxs12_emb_func_init_b_t; 1736 1737 #define LIS2DUXS12_MLC1_SRC 0x34U 1738 typedef struct 1739 { 1740 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1741 uint8_t mlc1_src : 8; 1742 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1743 uint8_t mlc1_src : 8; 1744 #endif /* DRV_BYTE_ORDER */ 1745 } lis2duxs12_mlc1_src_t; 1746 1747 #define LIS2DUXS12_MLC2_SRC 0x35U 1748 typedef struct 1749 { 1750 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1751 uint8_t mlc2_src : 8; 1752 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1753 uint8_t mlc2_src : 8; 1754 #endif /* DRV_BYTE_ORDER */ 1755 } lis2duxs12_mlc2_src_t; 1756 1757 #define LIS2DUXS12_MLC3_SRC 0x36U 1758 typedef struct 1759 { 1760 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1761 uint8_t mlc3_src : 8; 1762 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1763 uint8_t mlc3_src : 8; 1764 #endif /* DRV_BYTE_ORDER */ 1765 } lis2duxs12_mlc3_src_t; 1766 1767 #define LIS2DUXS12_MLC4_SRC 0x37U 1768 typedef struct 1769 { 1770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1771 uint8_t mlc4_src : 8; 1772 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1773 uint8_t mlc4_src : 8; 1774 #endif /* DRV_BYTE_ORDER */ 1775 } lis2duxs12_mlc4_src_t; 1776 1777 #define LIS2DUXS12_FSM_ODR 0x39U 1778 typedef struct 1779 { 1780 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1781 uint8_t not_used0 : 3; 1782 uint8_t fsm_odr : 3; 1783 uint8_t not_used1 : 2; 1784 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1785 uint8_t not_used1 : 2; 1786 uint8_t fsm_odr : 3; 1787 uint8_t not_used0 : 3; 1788 #endif /* DRV_BYTE_ORDER */ 1789 } lis2duxs12_fsm_odr_t; 1790 1791 #define LIS2DUXS12_MLC_ODR 0x3AU 1792 typedef struct 1793 { 1794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1795 uint8_t not_used0 : 4; 1796 uint8_t mlc_odr : 3; 1797 uint8_t not_used1 : 1; 1798 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1799 uint8_t not_used1 : 1; 1800 uint8_t mlc_odr : 3; 1801 uint8_t not_used0 : 4; 1802 #endif /* DRV_BYTE_ORDER */ 1803 } lis2duxs12_mlc_odr_t; 1804 1805 /** 1806 * @} 1807 * 1808 */ 1809 1810 /** @defgroup bitfields page pg0_emb_adv 1811 * @{ 1812 * 1813 */ 1814 #define LIS2DUXS12_EMB_ADV_PG_0 0x000U 1815 1816 #define LIS2DUXS12_FSM_LC_TIMEOUT_L 0x54U 1817 typedef struct 1818 { 1819 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1820 uint8_t fsm_lc_timeout : 8; 1821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1822 uint8_t fsm_lc_timeout : 8; 1823 #endif /* DRV_BYTE_ORDER */ 1824 } lis2duxs12_fsm_lc_timeout_l_t; 1825 1826 #define LIS2DUXS12_FSM_LC_TIMEOUT_H 0x55U 1827 typedef struct 1828 { 1829 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1830 uint8_t fsm_lc_timeout : 8; 1831 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1832 uint8_t fsm_lc_timeout : 8; 1833 #endif /* DRV_BYTE_ORDER */ 1834 } lis2duxs12_fsm_lc_timeout_h_t; 1835 1836 #define LIS2DUXS12_FSM_PROGRAMS 0x56U 1837 typedef struct 1838 { 1839 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1840 uint8_t fsm_n_prog : 8; 1841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1842 uint8_t fsm_n_prog : 8; 1843 #endif /* DRV_BYTE_ORDER */ 1844 } lis2duxs12_fsm_programs_t; 1845 1846 #define LIS2DUXS12_FSM_START_ADD_L 0x58U 1847 typedef struct 1848 { 1849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1850 uint8_t fsm_start : 8; 1851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1852 uint8_t fsm_start : 8; 1853 #endif /* DRV_BYTE_ORDER */ 1854 } lis2duxs12_fsm_start_add_l_t; 1855 1856 #define LIS2DUXS12_FSM_START_ADD_H 0x59U 1857 typedef struct 1858 { 1859 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1860 uint8_t fsm_start : 8; 1861 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1862 uint8_t fsm_start : 8; 1863 #endif /* DRV_BYTE_ORDER */ 1864 } lis2duxs12_fsm_start_add_h_t; 1865 1866 #define LIS2DUXS12_PEDO_CMD_REG 0x5DU 1867 typedef struct 1868 { 1869 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1870 uint8_t not_used0 : 2; 1871 uint8_t fp_rejection_en : 1; 1872 uint8_t carry_count_en : 1; 1873 uint8_t not_used1 : 4; 1874 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1875 uint8_t not_used1 : 4; 1876 uint8_t carry_count_en : 1; 1877 uint8_t fp_rejection_en : 1; 1878 uint8_t not_used0 : 2; 1879 #endif /* DRV_BYTE_ORDER */ 1880 } lis2duxs12_pedo_cmd_reg_t; 1881 1882 #define LIS2DUXS12_PEDO_DEB_STEPS_CONF 0x5EU 1883 typedef struct 1884 { 1885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1886 uint8_t deb_step : 8; 1887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1888 uint8_t deb_step : 8; 1889 #endif /* DRV_BYTE_ORDER */ 1890 } lis2duxs12_pedo_deb_steps_conf_t; 1891 1892 #define LIS2DUXS12_PEDO_SC_DELTAT_L 0xAAU 1893 typedef struct 1894 { 1895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1896 uint8_t pd_sc : 8; 1897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1898 uint8_t pd_sc : 8; 1899 #endif /* DRV_BYTE_ORDER */ 1900 } lis2duxs12_pedo_sc_deltat_l_t; 1901 1902 #define LIS2DUXS12_PEDO_SC_DELTAT_H 0xABU 1903 typedef struct 1904 { 1905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1906 uint8_t pd_sc : 8; 1907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1908 uint8_t pd_sc : 8; 1909 #endif /* DRV_BYTE_ORDER */ 1910 } lis2duxs12_pedo_sc_deltat_h_t; 1911 1912 #define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_L 0xB6U 1913 typedef struct 1914 { 1915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1916 uint8_t t_ah_qvar_s : 8; 1917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1918 uint8_t t_ah_qvar_s : 8; 1919 #endif /* DRV_BYTE_ORDER */ 1920 } lis2duxs12_t_ah_qvar_sensitivity_l_t; 1921 1922 #define LIS2DUXS12_T_AH_QVAR_SENSITIVITY_H 0xB7U 1923 typedef struct 1924 { 1925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1926 uint8_t t_ah_qvar_s : 8; 1927 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1928 uint8_t t_ah_qvar_s : 8; 1929 #endif /* DRV_BYTE_ORDER */ 1930 } lis2duxs12_t_ah_qvar_sensitivity_h_t; 1931 1932 #define LIS2DUXS12_SMART_POWER_CTRL 0xD2U 1933 typedef struct 1934 { 1935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1936 uint8_t smart_power_ctrl_win : 4; 1937 uint8_t smart_power_ctrl_dur : 4; 1938 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1939 uint8_t smart_power_ctrl_dur : 4; 1940 uint8_t smart_power_ctrl_win : 4; 1941 #endif /* DRV_BYTE_ORDER */ 1942 } lis2duxs12_smart_power_ctrl_t; 1943 1944 /** 1945 * @} 1946 * 1947 */ 1948 1949 typedef union 1950 { 1951 lis2duxs12_pin_ctrl_t pin_ctrl; 1952 lis2duxs12_wake_up_dur_ext_t wake_up_dur_ext; 1953 lis2duxs12_who_am_i_t who_am_i; 1954 lis2duxs12_ctrl1_t ctrl1; 1955 lis2duxs12_ctrl2_t ctrl2; 1956 lis2duxs12_ctrl3_t ctrl3; 1957 lis2duxs12_ctrl4_t ctrl4; 1958 lis2duxs12_ctrl5_t ctrl5; 1959 lis2duxs12_fifo_ctrl_t fifo_ctrl; 1960 lis2duxs12_fifo_wtm_t fifo_wtm; 1961 lis2duxs12_interrupt_cfg_t interrupt_cfg; 1962 lis2duxs12_sixd_t sixd; 1963 lis2duxs12_wake_up_ths_t wake_up_ths; 1964 lis2duxs12_wake_up_dur_t wake_up_dur; 1965 lis2duxs12_free_fall_t free_fall; 1966 lis2duxs12_md1_cfg_t md1_cfg; 1967 lis2duxs12_md2_cfg_t md2_cfg; 1968 lis2duxs12_wake_up_src_t wake_up_src; 1969 lis2duxs12_tap_src_t tap_src; 1970 lis2duxs12_sixd_src_t sixd_src; 1971 lis2duxs12_all_int_src_t all_int_src; 1972 lis2duxs12_status_register_t status; 1973 lis2duxs12_fifo_status1_t fifo_status1; 1974 lis2duxs12_fifo_status2_t fifo_status2; 1975 lis2duxs12_out_x_l_t out_x_l; 1976 lis2duxs12_out_x_h_t out_x_h; 1977 lis2duxs12_out_y_l_t out_y_l; 1978 lis2duxs12_out_y_h_t out_y_h; 1979 lis2duxs12_out_z_l_t out_z_l; 1980 lis2duxs12_out_z_h_t out_z_h; 1981 lis2duxs12_out_t_ah_qvar_l_t out_t_ah_qvar_l; 1982 lis2duxs12_out_t_ah_qvar_h_t out_t_ah_qvar_h; 1983 lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; 1984 lis2duxs12_self_test_t self_test; 1985 lis2duxs12_i3c_if_ctrl_t i3c_if_ctrl; 1986 lis2duxs12_emb_func_status_mainpage_t emb_func_status_mainpage; 1987 lis2duxs12_fsm_status_mainpage_t fsm_status_mainpage; 1988 lis2duxs12_mlc_status_mainpage_t mlc_status_mainpage; 1989 lis2duxs12_sleep_t sleep; 1990 lis2duxs12_en_device_config_t en_device_config; 1991 lis2duxs12_func_cfg_access_t func_cfg_access; 1992 lis2duxs12_fifo_data_out_tag_t fifo_data_out_tag; 1993 lis2duxs12_fifo_data_out_x_l_t fifo_data_out_x_l; 1994 lis2duxs12_fifo_data_out_x_h_t fifo_data_out_x_h; 1995 lis2duxs12_fifo_data_out_y_l_t fifo_data_out_y_l; 1996 lis2duxs12_fifo_data_out_y_h_t fifo_data_out_y_h; 1997 lis2duxs12_fifo_data_out_z_l_t fifo_data_out_z_l; 1998 lis2duxs12_fifo_data_out_z_h_t fifo_data_out_z_h; 1999 lis2duxs12_fifo_batch_dec_t fifo_batch_dec; 2000 lis2duxs12_tap_cfg0_t tap_cfg0; 2001 lis2duxs12_tap_cfg1_t tap_cfg1; 2002 lis2duxs12_tap_cfg2_t tap_cfg2; 2003 lis2duxs12_tap_cfg3_t tap_cfg3; 2004 lis2duxs12_tap_cfg4_t tap_cfg4; 2005 lis2duxs12_tap_cfg5_t tap_cfg5; 2006 lis2duxs12_tap_cfg6_t tap_cfg6; 2007 lis2duxs12_timestamp0_t timestamp0; 2008 lis2duxs12_timestamp1_t timestamp1; 2009 lis2duxs12_timestamp2_t timestamp2; 2010 lis2duxs12_timestamp3_t timestamp3; 2011 lis2duxs12_page_sel_t page_sel; 2012 lis2duxs12_emb_func_en_a_t emb_func_en_a; 2013 lis2duxs12_emb_func_en_b_t emb_func_en_b; 2014 lis2duxs12_emb_func_exec_status_t emb_func_exec_status; 2015 lis2duxs12_page_address_t page_address; 2016 lis2duxs12_page_value_t page_value; 2017 lis2duxs12_emb_func_int1_t emb_func_int1; 2018 lis2duxs12_fsm_int1_t fsm_int1; 2019 lis2duxs12_mlc_int1_t mlc_int1; 2020 lis2duxs12_emb_func_int2_t emb_func_int2; 2021 lis2duxs12_fsm_int2_t fsm_int2; 2022 lis2duxs12_mlc_int2_t mlc_int2; 2023 lis2duxs12_emb_func_status_t emb_func_status; 2024 lis2duxs12_fsm_status_t fsm_status; 2025 lis2duxs12_mlc_status_t mlc_status; 2026 lis2duxs12_page_rw_t page_rw; 2027 lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en; 2028 lis2duxs12_fsm_enable_t fsm_enable; 2029 lis2duxs12_fsm_long_counter_l_t fsm_long_counter_l; 2030 lis2duxs12_fsm_long_counter_h_t fsm_long_counter_h; 2031 lis2duxs12_int_ack_mask_t int_ack_mask; 2032 lis2duxs12_fsm_outs1_t fsm_outs1; 2033 lis2duxs12_fsm_outs2_t fsm_outs2; 2034 lis2duxs12_fsm_outs3_t fsm_outs3; 2035 lis2duxs12_fsm_outs4_t fsm_outs4; 2036 lis2duxs12_fsm_outs5_t fsm_outs5; 2037 lis2duxs12_fsm_outs6_t fsm_outs6; 2038 lis2duxs12_fsm_outs7_t fsm_outs7; 2039 lis2duxs12_fsm_outs8_t fsm_outs8; 2040 lis2duxs12_step_counter_l_t step_counter_l; 2041 lis2duxs12_step_counter_h_t step_counter_h; 2042 lis2duxs12_emb_func_src_t emb_func_src; 2043 lis2duxs12_emb_func_init_a_t emb_func_init_a; 2044 lis2duxs12_emb_func_init_b_t emb_func_init_b; 2045 lis2duxs12_mlc1_src_t mlc1_src; 2046 lis2duxs12_mlc2_src_t mlc2_src; 2047 lis2duxs12_mlc3_src_t mlc3_src; 2048 lis2duxs12_mlc4_src_t mlc4_src; 2049 lis2duxs12_fsm_odr_t fsm_odr; 2050 lis2duxs12_mlc_odr_t mlc_odr; 2051 lis2duxs12_fsm_lc_timeout_l_t fsm_lc_timeout_l; 2052 lis2duxs12_fsm_lc_timeout_h_t fsm_lc_timeout_h; 2053 lis2duxs12_fsm_programs_t fsm_programs; 2054 lis2duxs12_fsm_start_add_l_t fsm_start_add_l; 2055 lis2duxs12_fsm_start_add_h_t fsm_start_add_h; 2056 lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; 2057 lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; 2058 lis2duxs12_pedo_sc_deltat_l_t pedo_sc_deltat_l; 2059 lis2duxs12_pedo_sc_deltat_h_t pedo_sc_deltat_h; 2060 lis2duxs12_t_ah_qvar_sensitivity_l_t t_ah_qvar_sensitivity_l; 2061 lis2duxs12_t_ah_qvar_sensitivity_h_t t_ah_qvar_sensitivity_h; 2062 lis2duxs12_smart_power_ctrl_t smart_power_ctrl; 2063 bitwise_t bitwise; 2064 uint8_t byte; 2065 } lis2duxs12_reg_t; 2066 2067 /** 2068 * @} 2069 * 2070 */ 2071 2072 #ifndef __weak 2073 #define __weak __attribute__((weak)) 2074 #endif /* __weak */ 2075 2076 /* 2077 * These are the basic platform dependent I/O routines to read 2078 * and write device registers connected on a standard bus. 2079 * The driver keeps offering a default implementation based on function 2080 * pointers to read/write routines for backward compatibility. 2081 * The __weak directive allows the final application to overwrite 2082 * them with a custom implementation. 2083 */ 2084 2085 int32_t lis2duxs12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2086 uint8_t *data, 2087 uint16_t len); 2088 int32_t lis2duxs12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2089 uint8_t *data, 2090 uint16_t len); 2091 2092 float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb); 2093 float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb); 2094 float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb); 2095 float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb); 2096 float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb); 2097 float_t lis2duxs12_from_lsb_to_mv(int16_t lsb); 2098 2099 int32_t lis2duxs12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 2100 2101 typedef enum 2102 { 2103 LIS2DUXS12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ 2104 LIS2DUXS12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ 2105 LIS2DUXS12_RESET = 0x02, /* Reset configuration registers */ 2106 LIS2DUXS12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or 2107 embedded functions usage (it takes 10ms) */ 2108 } lis2duxs12_init_t; 2109 int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val); 2110 2111 typedef struct 2112 { 2113 uint8_t sw_reset : 1; /* Restoring configuration registers */ 2114 uint8_t boot : 1; /* Restoring calibration parameters */ 2115 uint8_t drdy : 1; /* Accelerometer data ready */ 2116 uint8_t power_down : 1; /* Monitors power-down. */ 2117 } lis2duxs12_status_t; 2118 int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val); 2119 2120 typedef struct 2121 { 2122 uint8_t is_step_det : 1; /* Step detected */ 2123 uint8_t is_tilt : 1; /* Tilt detected */ 2124 uint8_t is_sigmot : 1; /* Significant motion detected */ 2125 } lis2duxs12_embedded_status_t; 2126 int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val); 2127 2128 typedef enum 2129 { 2130 LIS2DUXS12_DRDY_LATCHED = 0x0, 2131 LIS2DUXS12_DRDY_PULSED = 0x1, 2132 } lis2duxs12_data_ready_mode_t; 2133 int32_t lis2duxs12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val); 2134 int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val); 2135 2136 typedef enum 2137 { 2138 LIS2DUXS12_OFF = 0x00, /* in power down */ 2139 LIS2DUXS12_1Hz6_ULP = 0x01, /* @1Hz6 (ultra low power) */ 2140 LIS2DUXS12_3Hz_ULP = 0x02, /* @3Hz (ultra low power) */ 2141 LIS2DUXS12_25Hz_ULP = 0x03, /* @25Hz (ultra low power) */ 2142 LIS2DUXS12_6Hz_LP = 0x04, /* @6Hz (low power) */ 2143 LIS2DUXS12_12Hz5_LP = 0x05, /* @12Hz5 (low power) */ 2144 LIS2DUXS12_25Hz_LP = 0x06, /* @25Hz (low power ) */ 2145 LIS2DUXS12_50Hz_LP = 0x07, /* @50Hz (low power) */ 2146 LIS2DUXS12_100Hz_LP = 0x08, /* @100Hz (low power) */ 2147 LIS2DUXS12_200Hz_LP = 0x09, /* @200Hz (low power) */ 2148 LIS2DUXS12_400Hz_LP = 0x0A, /* @400Hz (low power) */ 2149 LIS2DUXS12_800Hz_LP = 0x0B, /* @800Hz (low power) */ 2150 LIS2DUXS12_6Hz_HP = 0x14, /* @6Hz (high performance) */ 2151 LIS2DUXS12_12Hz5_HP = 0x15, /* @12Hz5 (high performance) */ 2152 LIS2DUXS12_25Hz_HP = 0x16, /* @25Hz (high performance ) */ 2153 LIS2DUXS12_50Hz_HP = 0x17, /* @50Hz (high performance) */ 2154 LIS2DUXS12_100Hz_HP = 0x18, /* @100Hz (high performance) */ 2155 LIS2DUXS12_200Hz_HP = 0x19, /* @200Hz (high performance) */ 2156 LIS2DUXS12_400Hz_HP = 0x1A, /* @400Hz (high performance) */ 2157 LIS2DUXS12_800Hz_HP = 0x1B, /* @800Hz (high performance) */ 2158 LIS2DUXS12_TRIG_PIN = 0x2E, /* Single-shot high latency by INT2 */ 2159 LIS2DUXS12_TRIG_SW = 0x2F, /* Single-shot high latency by IF */ 2160 } lis2duxs12_odr_t; 2161 2162 typedef enum 2163 { 2164 LIS2DUXS12_2g = 0, 2165 LIS2DUXS12_4g = 1, 2166 LIS2DUXS12_8g = 2, 2167 LIS2DUXS12_16g = 3, 2168 } lis2duxs12_fs_t; 2169 2170 typedef enum 2171 { 2172 LIS2DUXS12_ODR_div_2 = 0, 2173 LIS2DUXS12_ODR_div_4 = 1, 2174 LIS2DUXS12_ODR_div_8 = 2, 2175 LIS2DUXS12_ODR_div_16 = 3, 2176 } lis2duxs12_bw_t; 2177 2178 typedef struct 2179 { 2180 lis2duxs12_odr_t odr; 2181 lis2duxs12_fs_t fs; 2182 lis2duxs12_bw_t bw; 2183 } lis2duxs12_md_t; 2184 int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val); 2185 int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val); 2186 2187 int32_t lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t *ctx, uint8_t val); 2188 int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); 2189 2190 int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md); 2191 2192 typedef struct 2193 { 2194 uint8_t drdy : 1; 2195 uint8_t timestamp : 1; 2196 uint8_t free_fall : 1; 2197 uint8_t wake_up : 1; 2198 uint8_t wake_up_z : 1; 2199 uint8_t wake_up_y : 1; 2200 uint8_t wake_up_x : 1; 2201 uint8_t single_tap : 1; 2202 uint8_t double_tap : 1; 2203 uint8_t triple_tap : 1; 2204 uint8_t six_d : 1; 2205 uint8_t six_d_xl : 1; 2206 uint8_t six_d_xh : 1; 2207 uint8_t six_d_yl : 1; 2208 uint8_t six_d_yh : 1; 2209 uint8_t six_d_zl : 1; 2210 uint8_t six_d_zh : 1; 2211 uint8_t sleep_change : 1; 2212 uint8_t sleep_state : 1; 2213 uint8_t tilt : 1; 2214 uint8_t fifo_bdr : 1; 2215 uint8_t fifo_full : 1; 2216 uint8_t fifo_ovr : 1; 2217 uint8_t fifo_th : 1; 2218 } lis2duxs12_all_sources_t; 2219 int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val); 2220 2221 typedef struct 2222 { 2223 float_t mg[3]; 2224 int16_t raw[3]; 2225 } lis2duxs12_xl_data_t; 2226 int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, 2227 lis2duxs12_xl_data_t *data); 2228 2229 typedef struct 2230 { 2231 struct 2232 { 2233 float_t deg_c; 2234 int16_t raw; 2235 } heat; 2236 } lis2duxs12_outt_data_t; 2237 int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx, 2238 lis2duxs12_outt_data_t *data); 2239 2240 typedef struct 2241 { 2242 float_t mv; 2243 int16_t raw; 2244 } lis2duxs12_ah_qvar_data_t; 2245 int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx, 2246 lis2duxs12_ah_qvar_data_t *data); 2247 2248 typedef enum 2249 { 2250 LIS2DUXS12_XL_ST_DISABLE = 0x0, 2251 LIS2DUXS12_XL_ST_POSITIVE = 0x1, 2252 LIS2DUXS12_XL_ST_NEGATIVE = 0x2, 2253 } lis2duxs12_xl_self_test_t; 2254 int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val); 2255 int32_t lis2duxs12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); 2256 int32_t lis2duxs12_self_test_stop(const stmdev_ctx_t *ctx); 2257 2258 int32_t lis2duxs12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); 2259 int32_t lis2duxs12_exit_deep_power_down(const stmdev_ctx_t *ctx); 2260 2261 typedef enum 2262 { 2263 LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US = 0x0, 2264 LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US = 0x1, 2265 LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS = 0x2, 2266 LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS = 0x3, 2267 } lis2duxs12_bus_act_sel_t; 2268 2269 typedef struct 2270 { 2271 lis2duxs12_bus_act_sel_t bus_act_sel; 2272 uint8_t asf_on : 1; 2273 uint8_t drstdaa_en : 1; 2274 } lis2duxs12_i3c_cfg_t; 2275 int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i3c_cfg_t *val); 2276 int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); 2277 2278 typedef enum 2279 { 2280 LIS2DUXS12_MAIN_MEM_BANK = 0x0, 2281 LIS2DUXS12_EMBED_FUNC_MEM_BANK = 0x1, 2282 } lis2duxs12_mem_bank_t; 2283 int32_t lis2duxs12_mem_bank_set(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val); 2284 int32_t lis2duxs12_mem_bank_get(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val); 2285 2286 int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, 2287 uint8_t len); 2288 int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); 2289 2290 int32_t lis2duxs12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2291 int32_t lis2duxs12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2292 2293 typedef struct 2294 { 2295 uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ 2296 uint8_t sda_pull_up : 1; /* 1 = pull up enable */ 2297 uint8_t cs_pull_up : 1; /* 1 = pull up enable */ 2298 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 2299 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 2300 uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 2301 } lis2duxs12_pin_conf_t; 2302 int32_t lis2duxs12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2duxs12_pin_conf_t *val); 2303 int32_t lis2duxs12_pin_conf_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); 2304 2305 typedef enum 2306 { 2307 LIS2DUXS12_ACTIVE_HIGH = 0x0, 2308 LIS2DUXS12_ACTIVE_LOW = 0x1, 2309 } lis2duxs12_int_pin_polarity_t; 2310 int32_t lis2duxs12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val); 2311 int32_t lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t *ctx, 2312 lis2duxs12_int_pin_polarity_t *val); 2313 2314 typedef enum 2315 { 2316 LIS2DUXS12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ 2317 LIS2DUXS12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ 2318 } lis2duxs12_spi_mode; 2319 int32_t lis2duxs12_spi_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode val); 2320 int32_t lis2duxs12_spi_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val); 2321 2322 typedef struct 2323 { 2324 uint8_t int_on_res : 1; /* Interrupt on RES pin */ 2325 uint8_t drdy : 1; /* Accelerometer data ready */ 2326 uint8_t boot : 1; /* Restoring calibration parameters */ 2327 uint8_t fifo_th : 1; /* FIFO threshold reached */ 2328 uint8_t fifo_ovr : 1; /* FIFO overrun */ 2329 uint8_t fifo_full : 1; /* FIFO full */ 2330 uint8_t free_fall : 1; /* free fall event */ 2331 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 2332 uint8_t tap : 1; /* all tap event */ 2333 uint8_t wake_up : 1; /* wake up event */ 2334 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 2335 uint8_t emb_function : 1; /* Embedded Function */ 2336 uint8_t timestamp : 1; /* Timestamp */ 2337 } lis2duxs12_pin_int_route_t; 2338 int32_t lis2duxs12_pin_int1_route_set(const stmdev_ctx_t *ctx, 2339 const lis2duxs12_pin_int_route_t *val); 2340 int32_t lis2duxs12_pin_int1_route_get(const stmdev_ctx_t *ctx, 2341 lis2duxs12_pin_int_route_t *val); 2342 int32_t lis2duxs12_pin_int2_route_set(const stmdev_ctx_t *ctx, 2343 const lis2duxs12_pin_int_route_t *val); 2344 int32_t lis2duxs12_pin_int2_route_get(const stmdev_ctx_t *ctx, 2345 lis2duxs12_pin_int_route_t *val); 2346 2347 typedef struct 2348 { 2349 uint8_t step_det : 1; /* route step detection event on INT pad */ 2350 uint8_t tilt : 1; /* route tilt event on INT pad */ 2351 uint8_t sig_mot : 1; /* route significant motion event on INT pad */ 2352 uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ 2353 } lis2duxs12_emb_pin_int_route_t; 2354 int32_t lis2duxs12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, 2355 const lis2duxs12_emb_pin_int_route_t *val); 2356 int32_t lis2duxs12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, 2357 lis2duxs12_emb_pin_int_route_t *val); 2358 int32_t lis2duxs12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, 2359 const lis2duxs12_emb_pin_int_route_t *val); 2360 int32_t lis2duxs12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, 2361 lis2duxs12_emb_pin_int_route_t *val); 2362 2363 typedef enum 2364 { 2365 LIS2DUXS12_INT_DISABLED = 0x0, 2366 LIS2DUXS12_INT_LEVEL = 0x1, 2367 LIS2DUXS12_INT_LATCHED = 0x2, 2368 } lis2duxs12_int_cfg_t; 2369 2370 typedef struct 2371 { 2372 lis2duxs12_int_cfg_t int_cfg; 2373 uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ 2374 uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ 2375 } lis2duxs12_int_config_t; 2376 int32_t lis2duxs12_int_config_set(const stmdev_ctx_t *ctx, const lis2duxs12_int_config_t *val); 2377 int32_t lis2duxs12_int_config_get(const stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); 2378 2379 typedef enum 2380 { 2381 LIS2DUXS12_EMBEDDED_INT_LEVEL = 0x0, 2382 LIS2DUXS12_EMBEDDED_INT_LATCHED = 0x1, 2383 } lis2duxs12_embedded_int_config_t; 2384 int32_t lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, 2385 lis2duxs12_embedded_int_config_t val); 2386 int32_t lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, 2387 lis2duxs12_embedded_int_config_t *val); 2388 2389 typedef enum 2390 { 2391 LIS2DUXS12_BYPASS_MODE = 0x0, 2392 LIS2DUXS12_FIFO_MODE = 0x1, 2393 LIS2DUXS12_STREAM_TO_FIFO_MODE = 0x3, 2394 LIS2DUXS12_BYPASS_TO_STREAM_MODE = 0x4, 2395 LIS2DUXS12_STREAM_MODE = 0x6, 2396 LIS2DUXS12_BYPASS_TO_FIFO_MODE = 0x7, 2397 LIS2DUXS12_FIFO_OFF = 0x8, 2398 } lis2duxs12_operation_t; 2399 2400 typedef enum 2401 { 2402 LIS2DUXS12_FIFO_1X = 0, 2403 LIS2DUXS12_FIFO_2X = 1, 2404 } lis2duxs12_store_t; 2405 2406 typedef enum 2407 { 2408 LIS2DUXS12_DEC_TS_OFF = 0x0, 2409 LIS2DUXS12_DEC_TS_1 = 0x1, 2410 LIS2DUXS12_DEC_TS_8 = 0x2, 2411 LIS2DUXS12_DEC_TS_32 = 0x3, 2412 } lis2duxs12_dec_ts_t; 2413 2414 typedef enum 2415 { 2416 LIS2DUXS12_BDR_XL_ODR = 0x0, 2417 LIS2DUXS12_BDR_XL_ODR_DIV_2 = 0x1, 2418 LIS2DUXS12_BDR_XL_ODR_DIV_4 = 0x2, 2419 LIS2DUXS12_BDR_XL_ODR_DIV_8 = 0x3, 2420 LIS2DUXS12_BDR_XL_ODR_DIV_16 = 0x4, 2421 LIS2DUXS12_BDR_XL_ODR_DIV_32 = 0x5, 2422 LIS2DUXS12_BDR_XL_ODR_DIV_64 = 0x6, 2423 LIS2DUXS12_BDR_XL_ODR_OFF = 0x7, 2424 } lis2duxs12_bdr_xl_t; 2425 2426 typedef struct 2427 { 2428 lis2duxs12_operation_t operation; 2429 lis2duxs12_store_t store; 2430 uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ 2431 uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ 2432 uint8_t cfg_change_in_fifo : 1; 2433 struct 2434 { 2435 lis2duxs12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ 2436 lis2duxs12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ 2437 } batch; 2438 } lis2duxs12_fifo_mode_t; 2439 int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val); 2440 int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val); 2441 2442 int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 2443 int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2444 2445 typedef enum 2446 { 2447 LIS2DUXS12_FIFO_EMPTY = 0x0, 2448 LIS2DUXS12_XL_TEMP_TAG = 0x2, 2449 LIS2DUXS12_XL_ONLY_2X_TAG = 0x3, 2450 LIS2DUXS12_TIMESTAMP_TAG = 0x4, 2451 LIS2DUXS12_STEP_COUNTER_TAG = 0x12, 2452 LIS2DUXS12_MLC_RESULT_TAG = 0x1A, 2453 LIS2DUXS12_MLC_FILTER_TAG = 0x1B, 2454 LIS2DUXS12_MLC_FEATURE = 0x1C, 2455 LIS2DUXS12_FSM_RESULT_TAG = 0x1D, 2456 LIS2DUXS12_XL_ONLY_2X_TAG_2ND = 0x1E, 2457 LIS2DUXS12_XL_AND_QVAR = 0x1F, 2458 } lis2duxs12_fifo_sensor_tag_t; 2459 int32_t lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 2460 lis2duxs12_fifo_sensor_tag_t *val); 2461 2462 int32_t lis2duxs12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2463 2464 typedef struct 2465 { 2466 uint8_t tag; 2467 struct 2468 { 2469 float_t mg[3]; 2470 int16_t raw[3]; 2471 } xl[2]; 2472 struct 2473 { 2474 float_t mv; 2475 int16_t raw; 2476 } ah_qvar; 2477 struct 2478 { 2479 float_t deg_c; 2480 int16_t raw; 2481 } heat; 2482 struct 2483 { 2484 uint32_t steps; 2485 uint32_t timestamp; 2486 } pedo; 2487 struct 2488 { 2489 uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ 2490 uint8_t odr : 4; /* ODR */ 2491 uint8_t bw : 2; /* BW */ 2492 uint8_t lp_hp : 1; /* Power: 0 for LP, 1 for HP */ 2493 uint8_t qvar_en : 1; /* QVAR is enabled */ 2494 uint8_t fs : 2; /* FS */ 2495 uint8_t dec_ts : 2; /* Timestamp decimator value */ 2496 uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ 2497 uint32_t timestamp; 2498 } cfg_chg; 2499 } lis2duxs12_fifo_data_t; 2500 int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, 2501 const lis2duxs12_fifo_mode_t *fmd, 2502 lis2duxs12_fifo_data_t *data); 2503 2504 typedef enum 2505 { 2506 LIS2DUXS12_NOTCH_50HZ = 0x0, 2507 LIS2DUXS12_NOTCH_60HZ = 0x1, 2508 } lis2duxs12_ah_qvar_notch_t; 2509 2510 typedef enum 2511 { 2512 LIS2DUXS12_520MOhm = 0x0, 2513 LIS2DUXS12_175MOhm = 0x1, 2514 LIS2DUXS12_310MOhm = 0x2, 2515 LIS2DUXS12_75MOhm = 0x3, 2516 } lis2duxs12_ah_qvar_zin_t; 2517 2518 typedef enum 2519 { 2520 LIS2DUXS12_GAIN_0_5 = 0x0, 2521 LIS2DUXS12_GAIN_1 = 0x1, 2522 LIS2DUXS12_GAIN_2 = 0x2, 2523 LIS2DUXS12_GAIN_4 = 0x3, 2524 } lis2duxs12_ah_qvar_gain_t; 2525 2526 typedef struct 2527 { 2528 uint8_t ah_qvar_en : 1; 2529 uint8_t ah_qvar_notch_en : 1; 2530 lis2duxs12_ah_qvar_notch_t ah_qvar_notch; 2531 lis2duxs12_ah_qvar_zin_t ah_qvar_zin; 2532 lis2duxs12_ah_qvar_gain_t ah_qvar_gain; 2533 } lis2duxs12_ah_qvar_mode_t; 2534 int32_t lis2duxs12_ah_qvar_mode_set(const stmdev_ctx_t *ctx, 2535 lis2duxs12_ah_qvar_mode_t val); 2536 int32_t lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t *ctx, 2537 lis2duxs12_ah_qvar_mode_t *val); 2538 2539 typedef struct 2540 { 2541 uint8_t false_step_rej : 1; 2542 uint8_t step_counter_enable : 1; 2543 uint8_t step_counter_in_fifo : 1; 2544 } lis2duxs12_stpcnt_mode_t; 2545 int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val); 2546 int32_t lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val); 2547 2548 int32_t lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 2549 2550 int32_t lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); 2551 2552 int32_t lis2duxs12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 2553 int32_t lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 2554 2555 int32_t lis2duxs12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 2556 int32_t lis2duxs12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 2557 2558 typedef struct 2559 { 2560 uint8_t enable : 1; 2561 uint8_t window : 1; 2562 uint8_t duration : 1; 2563 } lis2duxs12_smart_power_cfg_t; 2564 int32_t lis2duxs12_smart_power_set(const stmdev_ctx_t *ctx, lis2duxs12_smart_power_cfg_t val); 2565 int32_t lis2duxs12_smart_power_get(const stmdev_ctx_t *ctx, lis2duxs12_smart_power_cfg_t *val); 2566 2567 int32_t lis2duxs12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2568 int32_t lis2duxs12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2569 int32_t lis2duxs12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2570 int32_t lis2duxs12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2571 2572 2573 int32_t lis2duxs12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 2574 int32_t lis2duxs12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 2575 2576 typedef enum 2577 { 2578 LIS2DUXS12_156_mg = 0x0, 2579 LIS2DUXS12_219_mg = 0x1, 2580 LIS2DUXS12_250_mg = 0x2, 2581 LIS2DUXS12_312_mg = 0x3, 2582 LIS2DUXS12_344_mg = 0x4, 2583 LIS2DUXS12_406_mg = 0x5, 2584 LIS2DUXS12_469_mg = 0x6, 2585 LIS2DUXS12_500_mg = 0x7, 2586 } lis2duxs12_ff_thresholds_t; 2587 int32_t lis2duxs12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val); 2588 int32_t lis2duxs12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val); 2589 2590 typedef enum 2591 { 2592 LIS2DUXS12_DEG_80 = 0x0, 2593 LIS2DUXS12_DEG_70 = 0x1, 2594 LIS2DUXS12_DEG_60 = 0x2, 2595 LIS2DUXS12_DEG_50 = 0x3, 2596 } lis2duxs12_threshold_t; 2597 2598 typedef enum 2599 { 2600 LIS2DUXS12_6D = 0x0, 2601 LIS2DUXS12_4D = 0x1, 2602 } lis2duxs12_mode_t; 2603 2604 typedef struct 2605 { 2606 lis2duxs12_threshold_t threshold; 2607 lis2duxs12_mode_t mode; 2608 } lis2duxs12_sixd_config_t; 2609 2610 int32_t lis2duxs12_sixd_config_set(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val); 2611 int32_t lis2duxs12_sixd_config_get(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val); 2612 2613 typedef enum 2614 { 2615 LIS2DUXS12_0_ODR = 0x000, /* 0 ODR time */ 2616 LIS2DUXS12_1_ODR = 0x001, /* 1 ODR time */ 2617 LIS2DUXS12_2_ODR = 0x002, /* 2 ODR time */ 2618 LIS2DUXS12_3_ODR = 0x100, /* 3 ODR time */ 2619 LIS2DUXS12_7_ODR = 0x101, /* 7 ODR time */ 2620 LIS2DUXS12_11_ODR = 0x102, /* 11 ODR time */ 2621 LIS2DUXS12_15_ODR = 0x103, /* 15 ODR time */ 2622 } lis2duxs12_wake_dur_t; 2623 2624 typedef enum 2625 { 2626 LIS2DUXS12_SLEEP_OFF = 0, 2627 LIS2DUXS12_SLEEP_ON = 1, 2628 } lis2duxs12_wake_enable_t; 2629 2630 typedef enum 2631 { 2632 LIS2DUXS12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ 2633 LIS2DUXS12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ 2634 LIS2DUXS12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ 2635 LIS2DUXS12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ 2636 } lis2duxs12_inact_odr_t; 2637 2638 typedef struct 2639 { 2640 lis2duxs12_wake_dur_t wake_dur; 2641 uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ 2642 uint8_t wake_ths : 7; /* wakeup threshold */ 2643 uint8_t wake_ths_weight : 1; /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */ 2644 lis2duxs12_wake_enable_t wake_enable; 2645 lis2duxs12_inact_odr_t inact_odr; 2646 } lis2duxs12_wakeup_config_t; 2647 2648 int32_t lis2duxs12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val); 2649 int32_t lis2duxs12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val); 2650 2651 typedef enum 2652 { 2653 LIS2DUXS12_TAP_NONE = 0x0, /* No axis */ 2654 LIS2DUXS12_TAP_ON_X = 0x1, /* Detect tap on X axis */ 2655 LIS2DUXS12_TAP_ON_Y = 0x2, /* Detect tap on Y axis */ 2656 LIS2DUXS12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ 2657 } lis2duxs12_axis_t; 2658 2659 typedef struct 2660 { 2661 lis2duxs12_axis_t axis; 2662 uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ 2663 uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ 2664 uint8_t post_still_ths : 4; /* 1 LSB == 62.5 mg */ 2665 uint8_t post_still_time : 6; /* samples num during stationary condition */ 2666 uint8_t shock_wait_time : 6; /* samples num during shock condition */ 2667 uint8_t latency : 4; /* samples max num between taps */ 2668 uint8_t wait_end_latency : 1; /* wait end of latency time to generate tap events */ 2669 uint8_t peak_ths : 6; /* 1 LSB == 62.5 mg */ 2670 uint8_t rebound : 5; /* samples num during rebound condition */ 2671 uint8_t pre_still_start : 4; /* pre still start */ 2672 uint8_t pre_still_n : 4; /* pre still n */ 2673 uint8_t single_tap_on : 1; /* enable single tap */ 2674 uint8_t double_tap_on : 1; /* enable double tap */ 2675 uint8_t triple_tap_on : 1; /* enable triple tap */ 2676 } lis2duxs12_tap_config_t; 2677 2678 int32_t lis2duxs12_tap_config_set(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val); 2679 int32_t lis2duxs12_tap_config_get(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val); 2680 2681 int32_t lis2duxs12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2682 int32_t lis2duxs12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2683 2684 int32_t lis2duxs12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2685 2686 int32_t lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 2687 uint8_t *val); 2688 2689 int32_t lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2690 int32_t lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2691 2692 typedef struct 2693 { 2694 lis2duxs12_fsm_enable_t fsm_enable; 2695 } lis2duxs12_emb_fsm_enable_t; 2696 int32_t lis2duxs12_fsm_enable_set(const stmdev_ctx_t *ctx, 2697 lis2duxs12_emb_fsm_enable_t *val); 2698 int32_t lis2duxs12_fsm_enable_get(const stmdev_ctx_t *ctx, 2699 lis2duxs12_emb_fsm_enable_t *val); 2700 2701 int32_t lis2duxs12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 2702 int32_t lis2duxs12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 2703 2704 int32_t lis2duxs12_fsm_status_get(const stmdev_ctx_t *ctx, 2705 lis2duxs12_fsm_status_mainpage_t *val); 2706 int32_t lis2duxs12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 2707 2708 typedef enum 2709 { 2710 LIS2DUXS12_ODR_FSM_12Hz5 = 0, 2711 LIS2DUXS12_ODR_FSM_25Hz = 1, 2712 LIS2DUXS12_ODR_FSM_50Hz = 2, 2713 LIS2DUXS12_ODR_FSM_100Hz = 3, 2714 LIS2DUXS12_ODR_FSM_200Hz = 4, 2715 LIS2DUXS12_ODR_FSM_400Hz = 5, 2716 LIS2DUXS12_ODR_FSM_800Hz = 6, 2717 } lis2duxs12_fsm_val_odr_t; 2718 int32_t lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t *ctx, 2719 lis2duxs12_fsm_val_odr_t val); 2720 int32_t lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t *ctx, 2721 lis2duxs12_fsm_val_odr_t *val); 2722 2723 int32_t lis2duxs12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 2724 int32_t lis2duxs12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 2725 2726 int32_t lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2727 int32_t lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2728 2729 int32_t lis2duxs12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 2730 uint16_t val); 2731 int32_t lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 2732 uint16_t *val); 2733 2734 int32_t lis2duxs12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); 2735 int32_t lis2duxs12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); 2736 2737 int32_t lis2duxs12_fsm_start_address_set(const stmdev_ctx_t *ctx, 2738 uint16_t val); 2739 int32_t lis2duxs12_fsm_start_address_get(const stmdev_ctx_t *ctx, 2740 uint16_t *val); 2741 2742 typedef enum 2743 { 2744 LIS2DUXS12_MLC_OFF = 0, 2745 LIS2DUXS12_MLC_ON = 1, 2746 LIS2DUXS12_MLC_ON_BEFORE_FSM = 2, 2747 } lis2duxs12_mlc_mode_t; 2748 int32_t lis2duxs12_mlc_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val); 2749 int32_t lis2duxs12_mlc_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val); 2750 2751 int32_t lis2duxs12_mlc_status_get(const stmdev_ctx_t *ctx, 2752 lis2duxs12_mlc_status_mainpage_t *val); 2753 2754 int32_t lis2duxs12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2755 2756 typedef enum 2757 { 2758 LIS2DUXS12_ODR_PRGS_12Hz5 = 0, 2759 LIS2DUXS12_ODR_PRGS_25Hz = 1, 2760 LIS2DUXS12_ODR_PRGS_50Hz = 2, 2761 LIS2DUXS12_ODR_PRGS_100Hz = 3, 2762 LIS2DUXS12_ODR_PRGS_200Hz = 4, 2763 } lis2duxs12_mlc_odr_val_t; 2764 int32_t lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t *ctx, 2765 lis2duxs12_mlc_odr_val_t val); 2766 int32_t lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t *ctx, 2767 lis2duxs12_mlc_odr_val_t *val); 2768 2769 int32_t lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2770 int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2771 2772 #ifdef __cplusplus 2773 } 2774 #endif 2775 2776 #endif /* LIS2DUXS12_REGS_H */ 2777 2778 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2779
