1 /*
2 ******************************************************************************
3 * @file lis2duxs12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DUXS12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2duxs12_reg.h"
21
22 /**
23 * @defgroup LIS2DUXS12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2duxs12 sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DUXS12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2duxs12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2duxs12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 if (ctx == NULL)
53 {
54 return -1;
55 }
56
57 return ctx->read_reg(ctx->handle, reg, data, len);
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2duxs12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2duxs12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
71 uint16_t len)
72 {
73 if (ctx == NULL)
74 {
75 return -1;
76 }
77
78 return ctx->write_reg(ctx->handle, reg, data, len);
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2DUXS12_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis2duxs12_from_fs2g_to_mg(int16_t lsb)93 float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb)
94 {
95 return (float_t)lsb * 0.061f;
96 }
97
lis2duxs12_from_fs4g_to_mg(int16_t lsb)98 float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb)
99 {
100 return (float_t)lsb * 0.122f;
101 }
102
lis2duxs12_from_fs8g_to_mg(int16_t lsb)103 float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb)
104 {
105 return (float_t)lsb * 0.244f;
106 }
107
lis2duxs12_from_fs16g_to_mg(int16_t lsb)108 float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb)
109 {
110 return (float_t)lsb * 0.488f;
111 }
112
lis2duxs12_from_lsb_to_celsius(int16_t lsb)113 float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb)
114 {
115 return ((float_t)lsb / 355.5f) + 25.0f;
116 }
117
lis2duxs12_from_lsb_to_mv(int16_t lsb)118 float_t lis2duxs12_from_lsb_to_mv(int16_t lsb)
119 {
120 return ((float_t)lsb) / 74.4f;
121 }
122
123 /**
124 * @}
125 *
126 */
127
128 /**
129 * @defgroup Common
130 * @brief Common
131 * @{/
132 *
133 */
134 /**
135 * @brief Device ID.[get]
136 *
137 * @param ctx read / write interface definitions
138 * @param val Device ID.
139 * @retval interface status (MANDATORY: return 0 -> no Error)
140 *
141 */
lis2duxs12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)142 int32_t lis2duxs12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
143 {
144 int32_t ret;
145
146 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WHO_AM_I, val, 1);
147
148 return ret;
149 }
150
151 /**
152 * @brief Configures the bus operating mode.[get]
153 *
154 * @param ctx communication interface handler.(ptr)
155 * @param val configures the bus operating mode.(ptr)
156 * @retval interface status (MANDATORY: return 0 -> no Error)
157 *
158 */
lis2duxs12_init_set(const stmdev_ctx_t * ctx,lis2duxs12_init_t val)159 int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val)
160 {
161 lis2duxs12_ctrl1_t ctrl1;
162 lis2duxs12_ctrl4_t ctrl4;
163 lis2duxs12_status_t status;
164 uint8_t cnt = 0;
165 int32_t ret = 0;
166
167 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
168 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
169 switch (val)
170 {
171 case LIS2DUXS12_BOOT:
172 ctrl4.boot = PROPERTY_ENABLE;
173 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
174 if (ret != 0)
175 {
176 break;
177 }
178
179 do
180 {
181 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
182 if (ret != 0)
183 {
184 break;
185 }
186
187 /* boot procedure ended correctly */
188 if (ctrl4.boot == 0U)
189 {
190 break;
191 }
192
193 if (ctx->mdelay != NULL)
194 {
195 ctx->mdelay(25); /* 25 ms of boot time */
196 }
197 } while (cnt++ < 5U);
198
199 if (cnt >= 5U)
200 {
201 ret = -1; /* boot procedure failed */
202 }
203 break;
204 case LIS2DUXS12_RESET:
205 ctrl1.sw_reset = PROPERTY_ENABLE;
206 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
207 if (ret != 0)
208 {
209 break;
210 }
211
212 do
213 {
214 ret = lis2duxs12_status_get(ctx, &status);
215 if (ret != 0)
216 {
217 break;
218 }
219
220 /* sw-reset procedure ended correctly */
221 if (status.sw_reset == 0U)
222 {
223 break;
224 }
225
226 if (ctx->mdelay != NULL)
227 {
228 ctx->mdelay(1); /* should be 50 us */
229 }
230 } while (cnt++ < 5U);
231
232 if (cnt >= 5U)
233 {
234 ret = -1; /* sw-reset procedure failed */
235 }
236 break;
237 case LIS2DUXS12_SENSOR_ONLY_ON:
238 /* no embedded funcs are used */
239 ctrl4.emb_func_en = PROPERTY_DISABLE;
240 ctrl4.bdu = PROPERTY_ENABLE;
241 ctrl1.if_add_inc = PROPERTY_ENABLE;
242 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
243 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
244 break;
245 case LIS2DUXS12_SENSOR_EMB_FUNC_ON:
246 /* complete configuration is used */
247 ctrl4.emb_func_en = PROPERTY_ENABLE;
248 ctrl4.bdu = PROPERTY_ENABLE;
249 ctrl1.if_add_inc = PROPERTY_ENABLE;
250 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
251 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
252 break;
253 default:
254 ctrl1.sw_reset = PROPERTY_ENABLE;
255 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
256 break;
257 }
258 return ret;
259 }
260
261 /**
262 * @brief Get the status of the device.[get]
263 *
264 * @param ctx communication interface handler.(ptr)
265 * @param val the status of the device.(ptr)
266 * @retval interface status (MANDATORY: return 0 -> no Error)
267 *
268 */
lis2duxs12_status_get(const stmdev_ctx_t * ctx,lis2duxs12_status_t * val)269 int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val)
270 {
271 lis2duxs12_status_register_t status_register;
272 lis2duxs12_ctrl1_t ctrl1;
273 lis2duxs12_ctrl4_t ctrl4;
274 int32_t ret;
275
276 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS,
277 (uint8_t *)&status_register, 1);
278 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
279 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
280
281 val->sw_reset = ctrl1.sw_reset;
282 val->boot = ctrl4.boot;
283 val->drdy = status_register.drdy;
284
285 return ret;
286 }
287
288 /**
289 * @brief Get the status of the embedded funcs.[get]
290 *
291 * @param ctx communication interface handler.(ptr)
292 * @param val the status of the embedded funcs.(ptr)
293 * @retval interface status (MANDATORY: return 0 -> no Error)
294 *
295 */
lis2duxs12_embedded_status_get(const stmdev_ctx_t * ctx,lis2duxs12_embedded_status_t * val)296 int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val)
297 {
298 lis2duxs12_emb_func_status_t status;
299 int32_t ret;
300
301 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
302 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t *)&status, 1);
303 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
304
305 val->is_step_det = status.is_step_det;
306 val->is_tilt = status.is_tilt;
307 val->is_sigmot = status.is_sigmot;
308
309 return ret;
310 }
311
312 /**
313 * @brief Enables pulsed data-ready mode (~75 us).[set]
314 *
315 * @param ctx read / write interface definitions
316 * @param val DRDY_LATCHED, DRDY_PULSED,
317 * @retval interface status (MANDATORY: return 0 -> no Error)
318 *
319 */
lis2duxs12_data_ready_mode_set(const stmdev_ctx_t * ctx,lis2duxs12_data_ready_mode_t val)320 int32_t lis2duxs12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val)
321 {
322 lis2duxs12_ctrl1_t ctrl1;
323 int32_t ret;
324
325 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
326
327 if (ret == 0)
328 {
329 ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U);
330 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
331 }
332
333 return ret;
334 }
335
336 /**
337 * @brief Enables pulsed data-ready mode (~75 us).[get]
338 *
339 * @param ctx read / write interface definitions
340 * @param val DRDY_LATCHED, DRDY_PULSED,
341 * @retval interface status (MANDATORY: return 0 -> no Error)
342 *
343 */
lis2duxs12_data_ready_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_data_ready_mode_t * val)344 int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val)
345 {
346 lis2duxs12_ctrl1_t ctrl1;
347 int32_t ret;
348
349 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
350
351 switch ((ctrl1.drdy_pulsed))
352 {
353 case 0x0:
354 *val = LIS2DUXS12_DRDY_LATCHED;
355 break;
356
357 case 0x1:
358 *val = LIS2DUXS12_DRDY_PULSED;
359 break;
360
361 default:
362 *val = LIS2DUXS12_DRDY_LATCHED;
363 break;
364 }
365 return ret;
366 }
367
368 /**
369 * @brief Sensor mode.[set]
370 *
371 * @param ctx communication interface handler.(ptr)
372 * @param val set the sensor FS and ODR.(ptr)
373 * @retval interface status (MANDATORY: return 0 -> no Error)
374 *
375 */
lis2duxs12_mode_set(const stmdev_ctx_t * ctx,const lis2duxs12_md_t * val)376 int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val)
377 {
378 lis2duxs12_ctrl3_t ctrl3;
379 lis2duxs12_ctrl5_t ctrl5;
380 int32_t ret;
381
382 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
383
384 ctrl5.odr = (uint8_t)val->odr & 0xFU;
385 ctrl5.fs = (uint8_t)val->fs;
386
387 /* set the bandwidth */
388 switch (val->odr)
389 {
390 /* no anti-aliasing filter present */
391 case LIS2DUXS12_OFF:
392 case LIS2DUXS12_1Hz6_ULP:
393 case LIS2DUXS12_3Hz_ULP:
394 case LIS2DUXS12_25Hz_ULP:
395 ctrl5.bw = 0x0;
396 break;
397
398 /* low-power mode with ODR < 50 Hz */
399 case LIS2DUXS12_6Hz_LP:
400 switch (val->bw)
401 {
402 default:
403 case LIS2DUXS12_ODR_div_2:
404 case LIS2DUXS12_ODR_div_4:
405 case LIS2DUXS12_ODR_div_8:
406 /* value not allowed */
407 ret = -1;
408 break;
409 case LIS2DUXS12_ODR_div_16:
410 ctrl5.bw = 0x3;
411 break;
412 }
413 break;
414 case LIS2DUXS12_12Hz5_LP:
415 switch (val->bw)
416 {
417 default:
418 case LIS2DUXS12_ODR_div_2:
419 case LIS2DUXS12_ODR_div_4:
420 /* value not allowed */
421 ret = -1;
422 break;
423 case LIS2DUXS12_ODR_div_8:
424 ctrl5.bw = 0x2;
425 break;
426 case LIS2DUXS12_ODR_div_16:
427 ctrl5.bw = 0x3;
428 break;
429 }
430 break;
431 case LIS2DUXS12_25Hz_LP:
432 switch (val->bw)
433 {
434 default:
435 case LIS2DUXS12_ODR_div_2:
436 /* value not allowed */
437 ret = -1;
438 break;
439 case LIS2DUXS12_ODR_div_4:
440 ctrl5.bw = 0x1;
441 break;
442 case LIS2DUXS12_ODR_div_8:
443 ctrl5.bw = 0x2;
444 break;
445 case LIS2DUXS12_ODR_div_16:
446 ctrl5.bw = 0x3;
447 break;
448 }
449 break;
450
451 /* standard cases */
452 case LIS2DUXS12_50Hz_LP:
453 case LIS2DUXS12_100Hz_LP:
454 case LIS2DUXS12_200Hz_LP:
455 case LIS2DUXS12_400Hz_LP:
456 case LIS2DUXS12_800Hz_LP:
457 case LIS2DUXS12_TRIG_PIN:
458 case LIS2DUXS12_TRIG_SW:
459 case LIS2DUXS12_6Hz_HP:
460 case LIS2DUXS12_12Hz5_HP:
461 case LIS2DUXS12_25Hz_HP:
462 case LIS2DUXS12_50Hz_HP:
463 case LIS2DUXS12_100Hz_HP:
464 case LIS2DUXS12_200Hz_HP:
465 case LIS2DUXS12_400Hz_HP:
466 case LIS2DUXS12_800Hz_HP:
467 default:
468 ctrl5.bw = (uint8_t)val->bw;
469 break;
470 }
471
472 if (ret != 0)
473 {
474 return ret;
475 }
476
477 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
478
479 ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U;
480
481 if (ret == 0)
482 {
483 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
484 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
485 }
486
487 return ret;
488 }
489
490 /**
491 * @brief Sensor mode.[get]
492 *
493 * @param ctx communication interface handler.(ptr)
494 * @param val get the sensor FS and ODR.(ptr)
495 * @retval interface status (MANDATORY: return 0 -> no Error)
496 *
497 */
lis2duxs12_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_md_t * val)498 int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val)
499 {
500 lis2duxs12_ctrl3_t ctrl3;
501 lis2duxs12_ctrl5_t ctrl5;
502 int32_t ret;
503
504 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
505 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
506
507 switch (ctrl5.odr)
508 {
509 case 0x00:
510 val->odr = LIS2DUXS12_OFF;
511 break;
512 case 0x01:
513 val->odr = LIS2DUXS12_1Hz6_ULP;
514 break;
515 case 0x02:
516 val->odr = LIS2DUXS12_3Hz_ULP;
517 break;
518 case 0x03:
519 val->odr = LIS2DUXS12_25Hz_ULP;
520 break;
521 case 0x04:
522 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_6Hz_HP : LIS2DUXS12_6Hz_LP;
523 break;
524 case 0x05:
525 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_12Hz5_HP : LIS2DUXS12_12Hz5_LP;
526 break;
527 case 0x06:
528 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_25Hz_HP : LIS2DUXS12_25Hz_LP;
529 break;
530 case 0x07:
531 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_50Hz_HP : LIS2DUXS12_50Hz_LP;
532 break;
533 case 0x08:
534 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_100Hz_HP : LIS2DUXS12_100Hz_LP;
535 break;
536 case 0x09:
537 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_200Hz_HP : LIS2DUXS12_200Hz_LP;
538 break;
539 case 0x0A:
540 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_400Hz_HP : LIS2DUXS12_400Hz_LP;
541 break;
542 case 0x0B:
543 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_800Hz_HP : LIS2DUXS12_800Hz_LP;
544 break;
545 case 0xe:
546 val->odr = LIS2DUXS12_TRIG_PIN;
547 break;
548 case 0xf:
549 val->odr = LIS2DUXS12_TRIG_SW;
550 break;
551 default:
552 val->odr = LIS2DUXS12_OFF;
553 break;
554 }
555
556 switch (ctrl5.fs)
557 {
558 case 0:
559 val->fs = LIS2DUXS12_2g;
560 break;
561 case 1:
562 val->fs = LIS2DUXS12_4g;
563 break;
564 case 2:
565 val->fs = LIS2DUXS12_8g;
566 break;
567 case 3:
568 val->fs = LIS2DUXS12_16g;
569 break;
570 default:
571 val->fs = LIS2DUXS12_2g;
572 break;
573 }
574
575 switch (ctrl5.bw)
576 {
577 case 0:
578 val->bw = LIS2DUXS12_ODR_div_2;
579 break;
580 case 1:
581 val->bw = LIS2DUXS12_ODR_div_4;
582 break;
583 case 2:
584 val->bw = LIS2DUXS12_ODR_div_8;
585 break;
586 case 3:
587 val->bw = LIS2DUXS12_ODR_div_16;
588 break;
589 default:
590 val->bw = LIS2DUXS12_ODR_div_2;
591 break;
592 }
593
594 return ret;
595 }
596
597 /**
598 * @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[set]
599 *
600 * @param ctx read / write interface definitions
601 * @param val 1: disable temp acquisition - 0: enable temp acquisition
602 * @retval interface status (MANDATORY: return 0 -> no Error)
603 *
604 */
lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t * ctx,uint8_t val)605 int32_t lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t *ctx, uint8_t val)
606 {
607 lis2duxs12_self_test_t temp;
608 int32_t ret;
609
610 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
611
612 if (ret == 0)
613 {
614 temp.t_ah_qvar_dis = val;
615 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
616 }
617
618 return ret;
619 }
620
621 /**
622 * @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[get]
623 *
624 * @param ctx read / write interface definitions
625 * @param val 1: disable temp acquisition - 0: enable temp acquisition
626 * @retval interface status (MANDATORY: return 0 -> no Error)
627 *
628 */
lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t * ctx,uint8_t * val)629 int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val)
630 {
631 lis2duxs12_self_test_t temp;
632 int32_t ret;
633
634 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
635 *val = temp.t_ah_qvar_dis;
636
637 return ret;
638 }
639
640 /**
641 * @brief Enter deep power down[set]
642 *
643 * @param ctx read / write interface definitions
644 * @param val Enter deep power down
645 * @retval interface status (MANDATORY: return 0 -> no Error)
646 *
647 */
lis2duxs12_enter_deep_power_down(const stmdev_ctx_t * ctx,uint8_t val)648 int32_t lis2duxs12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val)
649 {
650 lis2duxs12_sleep_t sleep;
651 int32_t ret;
652
653 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
654
655 if (ret == 0)
656 {
657 sleep.deep_pd = val;
658 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
659 }
660
661 return ret;
662 }
663
664 /**
665 * @brief Enter soft power down in SPI case[set]
666 *
667 * @param ctx read / write interface definitions
668 * @param val Enter soft power down in SPI case
669 * @retval interface status (MANDATORY: return 0 -> no Error)
670 *
671 */
lis2duxs12_exit_deep_power_down(const stmdev_ctx_t * ctx)672 int32_t lis2duxs12_exit_deep_power_down(const stmdev_ctx_t *ctx)
673 {
674 lis2duxs12_en_device_config_t en_device_config = {0};
675 int32_t ret;
676
677 en_device_config.soft_pd = PROPERTY_ENABLE;
678 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EN_DEVICE_CONFIG, (uint8_t *)&en_device_config, 1);
679
680 if (ctx->mdelay != NULL)
681 {
682 ctx->mdelay(25); /* See AN5812 - paragraphs 3.1.1.1 and 3.1.1.2 */
683 }
684
685 return ret;
686 }
687
688 /**
689 * @brief Software trigger for One-Shot.[get]
690 *
691 * @param ctx communication interface handler.(ptr)
692 * @param md the sensor conversion parameters.(ptr)
693 * @retval interface status (MANDATORY: return 0 -> no Error)
694 *
695 */
lis2duxs12_trigger_sw(const stmdev_ctx_t * ctx,const lis2duxs12_md_t * md)696 int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md)
697 {
698 lis2duxs12_ctrl4_t ctrl4;
699 int32_t ret = 0;
700
701 if (md->odr == LIS2DUXS12_TRIG_SW)
702 {
703 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
704 ctrl4.soc = PROPERTY_ENABLE;
705 if (ret == 0)
706 {
707 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
708 }
709 }
710 return ret;
711 }
712
lis2duxs12_all_sources_get(const stmdev_ctx_t * ctx,lis2duxs12_all_sources_t * val)713 int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val)
714 {
715 lis2duxs12_status_register_t status;
716 int32_t ret;
717
718 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t *)&status, 1);
719 val->drdy = status.drdy;
720
721 if (ret == 0 && status.int_global == 0x1U)
722 {
723 lis2duxs12_wake_up_src_t wu_src;
724 lis2duxs12_tap_src_t tap_src;
725 lis2duxs12_sixd_src_t sixd_src;
726
727 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t *)&sixd_src, 1);
728 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1);
729 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t *)&tap_src, 1);
730
731 val->six_d = sixd_src.d6d_ia;
732 val->six_d_xl = sixd_src.xl;
733 val->six_d_xh = sixd_src.xh;
734 val->six_d_yl = sixd_src.yl;
735 val->six_d_yh = sixd_src.yh;
736 val->six_d_zl = sixd_src.zl;
737 val->six_d_zh = sixd_src.zh;
738
739 val->wake_up = wu_src.wu_ia;
740 val->wake_up_z = wu_src.z_wu;
741 val->wake_up_y = wu_src.y_wu;
742 val->wake_up_x = wu_src.x_wu;
743 val->free_fall = wu_src.ff_ia;
744 val->sleep_change = wu_src.sleep_change_ia;
745 val->sleep_state = wu_src.sleep_state;
746
747 val->single_tap = tap_src.single_tap_ia;
748 val->double_tap = tap_src.double_tap_ia;
749 val->triple_tap = tap_src.triple_tap_ia;
750 }
751
752 return ret;
753 }
754
755 /**
756 * @brief Accelerometer data.[get]
757 *
758 * @param ctx communication interface handler.(ptr)
759 * @param md the sensor conversion parameters.(ptr)
760 * @param data data retrived from the sensor.(ptr)
761 * @retval interface status (MANDATORY: return 0 -> no Error)
762 *
763 */
lis2duxs12_xl_data_get(const stmdev_ctx_t * ctx,const lis2duxs12_md_t * md,lis2duxs12_xl_data_t * data)764 int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md,
765 lis2duxs12_xl_data_t *data)
766 {
767 uint8_t buff[6];
768 int32_t ret;
769 uint8_t i;
770 uint8_t j;
771
772 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_X_L, buff, 6);
773
774 /* acceleration conversion */
775 j = 0U;
776 for (i = 0U; i < 3U; i++)
777 {
778 data->raw[i] = (int16_t)buff[j + 1U];
779 data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j];
780 j += 2U;
781 switch (md->fs)
782 {
783 case LIS2DUXS12_2g:
784 data->mg[i] = lis2duxs12_from_fs2g_to_mg(data->raw[i]);
785 break;
786 case LIS2DUXS12_4g:
787 data->mg[i] = lis2duxs12_from_fs4g_to_mg(data->raw[i]);
788 break;
789 case LIS2DUXS12_8g:
790 data->mg[i] = lis2duxs12_from_fs8g_to_mg(data->raw[i]);
791 break;
792 case LIS2DUXS12_16g:
793 data->mg[i] = lis2duxs12_from_fs16g_to_mg(data->raw[i]);
794 break;
795 default:
796 data->mg[i] = 0.0f;
797 break;
798 }
799 }
800
801 return ret;
802 }
803
804 /**
805 * @brief OUTT data.[get]
806 *
807 * @param ctx communication interface handler.(ptr)
808 * @param md the sensor conversion parameters.(ptr)
809 * @param data data retrived from the sensor.(ptr)
810 * @retval interface status (MANDATORY: return 0 -> no Error)
811 *
812 */
lis2duxs12_outt_data_get(const stmdev_ctx_t * ctx,lis2duxs12_outt_data_t * data)813 int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx,
814 lis2duxs12_outt_data_t *data)
815 {
816 uint8_t buff[2];
817 int32_t ret;
818
819 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
820
821 data->heat.raw = (int16_t)buff[1U];
822 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0];
823 /* temperature conversion */
824 data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw);
825
826 return ret;
827 }
828
829 /**
830 * @brief AH_QVAR data.[get]
831 *
832 * @param ctx communication interface handler.(ptr)
833 * @param md the sensor conversion parameters.(ptr)
834 * @param data data retrived from the sensor.(ptr)
835 * @retval interface status (MANDATORY: return 0 -> no Error)
836 *
837 */
lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t * ctx,lis2duxs12_ah_qvar_data_t * data)838 int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx,
839 lis2duxs12_ah_qvar_data_t *data)
840 {
841 uint8_t buff[2];
842 int32_t ret;
843
844 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
845
846 data->raw = (int16_t)buff[1U];
847 data->raw = (data->raw * 256) + (int16_t) buff[0];
848
849 data->mv = lis2duxs12_from_lsb_to_mv(data->raw);
850 return ret;
851 }
852
853 /**
854 * @brief Configures the self test.[set]
855 *
856 * @param ctx communication interface handler.(ptr)
857 * @param val self test mode.(ptr)
858 * @retval interface status (MANDATORY: return 0 -> no Error)
859 *
860 */
lis2duxs12_self_test_sign_set(const stmdev_ctx_t * ctx,lis2duxs12_xl_self_test_t val)861 int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val)
862 {
863 lis2duxs12_ctrl3_t ctrl3;
864 lis2duxs12_wake_up_dur_t wkup_dur;
865 int32_t ret;
866
867 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
868 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
869
870 switch (val)
871 {
872 case LIS2DUXS12_XL_ST_POSITIVE:
873 ctrl3.st_sign_x = 1;
874 ctrl3.st_sign_y = 1;
875 wkup_dur.st_sign_z = 0;
876 break;
877
878 case LIS2DUXS12_XL_ST_NEGATIVE:
879 ctrl3.st_sign_x = 0;
880 ctrl3.st_sign_y = 0;
881 wkup_dur.st_sign_z = 1;
882 break;
883
884 case LIS2DUXS12_XL_ST_DISABLE:
885 default:
886 ret = -1;
887 break;
888 }
889
890
891 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
892 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
893
894 return ret;
895 }
896
897 /**
898 * @brief Configures the self test.[start]
899 *
900 * @param ctx communication interface handler.(ptr)
901 * @param val valid values 2 (1st step) or 1 (2nd step)
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
lis2duxs12_self_test_start(const stmdev_ctx_t * ctx,uint8_t val)905 int32_t lis2duxs12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val)
906 {
907 lis2duxs12_self_test_t self_test;
908 int32_t ret;
909
910 if (val != 1U && val != 2U)
911 {
912 return -1;
913 }
914
915 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
916 if (ret == 0)
917 {
918 self_test.st = (uint8_t) val;
919 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
920 }
921 return ret;
922 }
923
924 /**
925 * @brief Configures the self test.[stop]
926 *
927 * @param ctx communication interface handler.(ptr)
928 * @retval interface status (MANDATORY: return 0 -> no Error)
929 *
930 */
lis2duxs12_self_test_stop(const stmdev_ctx_t * ctx)931 int32_t lis2duxs12_self_test_stop(const stmdev_ctx_t *ctx)
932 {
933 lis2duxs12_self_test_t self_test;
934 int32_t ret;
935
936 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
937 if (ret == 0)
938 {
939 self_test.st = 0;
940 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
941 }
942 return ret;
943 }
944
945 /**
946 * @brief Configures I3C bus.[set]
947 *
948 * @param ctx communication interface handler.(ptr)
949 * @param val configuration params
950 * @retval interface status (MANDATORY: return 0 -> no Error)
951 *
952 */
lis2duxs12_i3c_configure_set(const stmdev_ctx_t * ctx,const lis2duxs12_i3c_cfg_t * val)953 int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i3c_cfg_t *val)
954 {
955 lis2duxs12_i3c_if_ctrl_t i3c_cfg;
956 int32_t ret;
957
958 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
959
960 if (ret == 0)
961 {
962 i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel;
963 i3c_cfg.dis_drstdaa = val->drstdaa_en;
964 i3c_cfg.asf_on = val->asf_on;
965 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
966 }
967
968 return ret;
969 }
970
971 /**
972 * @brief Configures I3C bus.[get]
973 *
974 * @param ctx communication interface handler.(ptr)
975 * @param val configuration params
976 * @retval interface status (MANDATORY: return 0 -> no Error)
977 *
lis2duxs12_i3c_configure_get(const stmdev_ctx_t * ctx,lis2duxs12_i3c_cfg_t * val)978 */int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val)
979 {
980 lis2duxs12_i3c_if_ctrl_t i3c_cfg;
981 int32_t ret;
982
983 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
984
985 val->drstdaa_en = i3c_cfg.dis_drstdaa;
986 val->asf_on = i3c_cfg.asf_on;
987
988 switch (val->bus_act_sel)
989 {
990 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US:
991 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US;
992 break;
993
994 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US:
995 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US;
996 break;
997
998 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS:
999 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS;
1000 break;
1001
1002 case LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS:
1003 default:
1004 val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS;
1005 break;
1006 }
1007
1008 return ret;
1009 }
1010
1011 /**
1012 * @brief Change memory bank.[set]
1013 *
1014 * @param ctx read / write interface definitions
1015 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
1016 * @retval interface status (MANDATORY: return 0 -> no Error)
1017 *
1018 */
lis2duxs12_mem_bank_set(const stmdev_ctx_t * ctx,lis2duxs12_mem_bank_t val)1019 int32_t lis2duxs12_mem_bank_set(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val)
1020 {
1021 lis2duxs12_func_cfg_access_t func_cfg_access;
1022 int32_t ret;
1023
1024 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
1025
1026 if (ret == 0)
1027 {
1028 func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U);
1029 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
1030 }
1031
1032 return ret;
1033 }
1034
1035 /**
1036 * @brief Change memory bank.[get]
1037 *
1038 * @param ctx read / write interface definitions
1039 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
1040 * @retval interface status (MANDATORY: return 0 -> no Error)
1041 *
1042 */
lis2duxs12_mem_bank_get(const stmdev_ctx_t * ctx,lis2duxs12_mem_bank_t * val)1043 int32_t lis2duxs12_mem_bank_get(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val)
1044 {
1045 lis2duxs12_func_cfg_access_t func_cfg_access;
1046 int32_t ret;
1047
1048 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
1049
1050 switch ((func_cfg_access.emb_func_reg_access))
1051 {
1052 case 0x0:
1053 *val = LIS2DUXS12_MAIN_MEM_BANK;
1054 break;
1055
1056 case 0x1:
1057 *val = LIS2DUXS12_EMBED_FUNC_MEM_BANK;
1058 break;
1059
1060 default:
1061 *val = LIS2DUXS12_MAIN_MEM_BANK;
1062 break;
1063 }
1064 return ret;
1065 }
1066
1067 /**
1068 * @brief Write buffer in a page.
1069 *
1070 * @param ctx read / write interface definitions
1071 * @param address Address of page register to be written (page number in 8-bit
1072 * msb, register address in 8-bit lsb).
1073 * @param buf Pointer to data buffer.
1074 * @param len Buffer len.
1075 * @retval interface status (MANDATORY: return 0 -> no Error)
1076 *
1077 */
lis2duxs12_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1078 int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
1079 {
1080 lis2duxs12_page_address_t page_address;
1081 lis2duxs12_page_sel_t page_sel;
1082 lis2duxs12_page_rw_t page_rw;
1083 uint8_t msb;
1084 uint8_t lsb;
1085 int32_t ret;
1086 uint8_t i ;
1087
1088 msb = ((uint8_t)(address >> 8) & 0x0FU);
1089 lsb = (uint8_t)address & 0xFFU;
1090
1091 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1092 if (ret != 0)
1093 {
1094 goto exit;
1095 }
1096
1097 /* page write */
1098 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1099 page_rw.page_read = PROPERTY_DISABLE;
1100 page_rw.page_write = PROPERTY_ENABLE;
1101 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1102
1103 /* set page num */
1104 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1105 page_sel.page_sel = msb;
1106 page_sel.not_used0 = 1; // Default value
1107 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1108
1109 /* set page addr */
1110 page_address.page_addr = lsb;
1111 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
1112
1113 for (i = 0; i < len; i++)
1114 {
1115 /* read value */
1116 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1);
1117 lsb++;
1118
1119 /* Check if page wrap */
1120 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1121 {
1122 msb++;
1123 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1124 page_sel.page_sel = msb;
1125 page_sel.not_used0 = 1; // Default value
1126 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1127 }
1128
1129 if (ret != 0)
1130 {
1131 break;
1132 }
1133 }
1134
1135 page_sel.page_sel = 0;
1136 page_sel.not_used0 = 1;// Default value
1137 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1138
1139 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1140 page_rw.page_read = PROPERTY_DISABLE;
1141 page_rw.page_write = PROPERTY_DISABLE;
1142 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1143
1144 exit:
1145 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1146
1147 return ret;
1148 }
1149
1150 /**
1151 * @brief Read buffer in a page.
1152 *
1153 * @param ctx read / write interface definitions
1154 * @param address Address of page register to be read (page number in 8-bit
1155 * msb, register address in 8-bit lsb).
1156 * @param buf Pointer to data buffer.
1157 * @param len Buffer len.
1158 * @retval interface status (MANDATORY: return 0 -> no Error)
1159 *
1160 */
lis2duxs12_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1161 int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
1162 {
1163 lis2duxs12_page_address_t page_address;
1164 lis2duxs12_page_sel_t page_sel;
1165 lis2duxs12_page_rw_t page_rw;
1166 uint8_t msb;
1167 uint8_t lsb;
1168 int32_t ret;
1169 uint8_t i ;
1170
1171 msb = ((uint8_t)(address >> 8) & 0x0FU);
1172 lsb = (uint8_t)address & 0xFFU;
1173
1174 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1175 if (ret != 0)
1176 {
1177 goto exit;
1178 }
1179
1180 /* page read */
1181 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1182 page_rw.page_read = PROPERTY_ENABLE;
1183 page_rw.page_write = PROPERTY_DISABLE;
1184 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1185 if (ret != 0)
1186 {
1187 goto exit;
1188 }
1189
1190 /* set page num */
1191 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1192 page_sel.page_sel = msb;
1193 page_sel.not_used0 = 1; // Default value
1194 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1195 if (ret != 0)
1196 {
1197 goto exit;
1198 }
1199
1200 for (i = 0; i < len; i++)
1201 {
1202 /* Sequential readings are not allowed. Set page address every loop */
1203 page_address.page_addr = lsb++;
1204 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
1205
1206 /* read value */
1207 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1);
1208
1209 /* Check if page wrap */
1210 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1211 {
1212 msb++;
1213 lsb = 0;
1214
1215 /* set page */
1216 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1217 page_sel.page_sel = msb;
1218 page_sel.not_used0 = 1; // Default value
1219 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1220 }
1221
1222 if (ret != 0)
1223 {
1224 goto exit;
1225 }
1226 }
1227
1228 page_sel.page_sel = 0;
1229 page_sel.not_used0 = 1;// Default value
1230 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1231
1232 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1233 page_rw.page_read = PROPERTY_DISABLE;
1234 page_rw.page_write = PROPERTY_DISABLE;
1235 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1236
1237 exit:
1238 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1239
1240 return ret;
1241 }
1242
1243 /**
1244 * @}
1245 *
1246 */
1247
1248 /**
1249 * @defgroup Interrupt PINs
1250 * @brief Interrupt PINs
1251 * @{/
1252 *
1253 */
1254
1255 /**
1256 * @brief External Clock Enable/Disable on INT pin.[set]
1257 *
1258 * @param ctx read / write interface definitions
1259 * @param val 0: disable ext_clk - 1: enable ext_clk
1260 * @retval interface status (MANDATORY: return 0 -> no Error)
1261 *
1262 */
lis2duxs12_ext_clk_en_set(const stmdev_ctx_t * ctx,uint8_t val)1263 int32_t lis2duxs12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val)
1264 {
1265 lis2duxs12_ext_clk_cfg_t clk;
1266 int32_t ret;
1267
1268 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1269 clk.ext_clk_en = val;
1270 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1271
1272 return ret;
1273 }
1274
1275 /**
1276 * @brief External Clock Enable/Disable on INT pin.[get]
1277 *
1278 * @param ctx read / write interface definitions
1279 * @param val 0: disable ext_clk - 1: enable ext_clk
1280 * @retval interface status (MANDATORY: return 0 -> no Error)
1281 *
1282 */
lis2duxs12_ext_clk_en_get(const stmdev_ctx_t * ctx,uint8_t * val)1283 int32_t lis2duxs12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
1284 {
1285 lis2duxs12_ext_clk_cfg_t clk;
1286 int32_t ret;
1287
1288 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1289 *val = clk.ext_clk_en;
1290
1291 return ret;
1292 }
1293
1294 /**
1295 * @brief Electrical pin configuration.[set]
1296 *
1297 * @param ctx read / write interface definitions
1298 * @param val the electrical settings for the configurable pins.(ptr)
1299 * @retval interface status (MANDATORY: return 0 -> no Error)
1300 *
1301 */
lis2duxs12_pin_conf_set(const stmdev_ctx_t * ctx,const lis2duxs12_pin_conf_t * val)1302 int32_t lis2duxs12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2duxs12_pin_conf_t *val)
1303 {
1304 lis2duxs12_pin_ctrl_t pin_ctrl;
1305 int32_t ret;
1306
1307 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1308
1309 if (ret == 0)
1310 {
1311 pin_ctrl.cs_pu_dis = ~val->cs_pull_up;
1312 pin_ctrl.pd_dis_int1 = ~val->int1_pull_down;
1313 pin_ctrl.pd_dis_int2 = ~val->int2_pull_down;
1314 pin_ctrl.sda_pu_en = val->sda_pull_up;
1315 pin_ctrl.sdo_pu_en = val->sdo_pull_up;
1316 pin_ctrl.pp_od = ~val->int1_int2_push_pull;
1317
1318 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1319 }
1320
1321 return ret;
1322 }
1323
1324 /**
1325 * @brief Electrical pin configuration.[get]
1326 *
1327 * @param ctx read / write interface definitions
1328 * @param val the electrical settings for the configurable pins.(ptr)
1329 * @retval interface status (MANDATORY: return 0 -> no Error)
1330 *
1331 */
lis2duxs12_pin_conf_get(const stmdev_ctx_t * ctx,lis2duxs12_pin_conf_t * val)1332 int32_t lis2duxs12_pin_conf_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val)
1333 {
1334 lis2duxs12_pin_ctrl_t pin_ctrl;
1335 int32_t ret;
1336
1337 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1338
1339 val->cs_pull_up = ~pin_ctrl.cs_pu_dis;
1340 val->int1_pull_down = ~pin_ctrl.pd_dis_int1;
1341 val->int2_pull_down = ~pin_ctrl.pd_dis_int2;
1342 val->sda_pull_up = pin_ctrl.sda_pu_en;
1343 val->sdo_pull_up = pin_ctrl.sdo_pu_en;
1344 val->int1_int2_push_pull = ~pin_ctrl.pp_od;
1345
1346 return ret;
1347 }
1348
1349 /**
1350 * @brief Interrupt activation level.[set]
1351 *
1352 * @param ctx read / write interface definitions
1353 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1354 * @retval interface status (MANDATORY: return 0 -> no Error)
1355 *
1356 */
lis2duxs12_int_pin_polarity_set(const stmdev_ctx_t * ctx,lis2duxs12_int_pin_polarity_t val)1357 int32_t lis2duxs12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val)
1358 {
1359 lis2duxs12_pin_ctrl_t pin_ctrl;
1360 int32_t ret;
1361
1362 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1363
1364 if (ret == 0)
1365 {
1366 pin_ctrl.h_lactive = (uint8_t)val;
1367 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1368 }
1369
1370 return ret;
1371 }
1372
1373 /**
1374 * @brief Interrupt activation level.[get]
1375 *
1376 * @param ctx read / write interface definitions
1377 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1378 * @retval interface status (MANDATORY: return 0 -> no Error)
1379 *
1380 */
lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t * ctx,lis2duxs12_int_pin_polarity_t * val)1381 int32_t lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val)
1382 {
1383 lis2duxs12_pin_ctrl_t pin_ctrl;
1384 int32_t ret;
1385
1386 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1387
1388 switch ((pin_ctrl.h_lactive))
1389 {
1390 case 0x0:
1391 *val = LIS2DUXS12_ACTIVE_HIGH;
1392 break;
1393
1394 case 0x1:
1395 *val = LIS2DUXS12_ACTIVE_LOW;
1396 break;
1397
1398 default:
1399 *val = LIS2DUXS12_ACTIVE_HIGH;
1400 break;
1401 }
1402 return ret;
1403 }
1404
1405 /**
1406 * @brief SPI mode.[set]
1407 *
1408 * @param ctx read / write interface definitions
1409 * @param val SPI_4_WIRE, SPI_3_WIRE,
1410 * @retval interface status (MANDATORY: return 0 -> no Error)
1411 *
1412 */
lis2duxs12_spi_mode_set(const stmdev_ctx_t * ctx,lis2duxs12_spi_mode val)1413 int32_t lis2duxs12_spi_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode val)
1414 {
1415 lis2duxs12_pin_ctrl_t pin_ctrl;
1416 int32_t ret;
1417
1418 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1419
1420 if (ret == 0)
1421 {
1422 pin_ctrl.sim = (uint8_t)val;
1423 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1424 }
1425
1426 return ret;
1427 }
1428
1429 /**
1430 * @brief SPI mode.[get]
1431 *
1432 * @param ctx read / write interface definitions
1433 * @param val SPI_4_WIRE, SPI_3_WIRE,
1434 * @retval interface status (MANDATORY: return 0 -> no Error)
1435 *
1436 */
lis2duxs12_spi_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_spi_mode * val)1437 int32_t lis2duxs12_spi_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val)
1438 {
1439 lis2duxs12_pin_ctrl_t pin_ctrl;
1440 int32_t ret;
1441
1442 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1443
1444 switch ((pin_ctrl.sim))
1445 {
1446 case 0x0:
1447 *val = LIS2DUXS12_SPI_4_WIRE;
1448 break;
1449
1450 case 0x1:
1451 *val = LIS2DUXS12_SPI_3_WIRE;
1452 break;
1453
1454 default:
1455 *val = LIS2DUXS12_SPI_4_WIRE;
1456 break;
1457 }
1458 return ret;
1459 }
1460
1461 /**
1462 * @brief routes interrupt signals on INT 1 pin.[set]
1463 *
1464 * @param ctx read / write interface definitions
1465 * @param val routes interrupt signals on INT 1 pin.
1466 * @retval interface status (MANDATORY: return 0 -> no Error)
1467 *
1468 */
lis2duxs12_pin_int1_route_set(const stmdev_ctx_t * ctx,const lis2duxs12_pin_int_route_t * val)1469 int32_t lis2duxs12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1470 const lis2duxs12_pin_int_route_t *val)
1471 {
1472 lis2duxs12_ctrl1_t ctrl1;
1473 lis2duxs12_ctrl2_t ctrl2;
1474 lis2duxs12_md1_cfg_t md1_cfg;
1475 int32_t ret;
1476
1477 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1478
1479 if (ret == 0)
1480 {
1481 ctrl1.int1_on_res = val->int_on_res;
1482
1483 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1484 }
1485
1486 if (ret == 0)
1487 {
1488 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1489
1490 if (ret == 0)
1491 {
1492 ctrl2.int1_drdy = val->drdy;
1493 ctrl2.int1_fifo_ovr = val->fifo_ovr;
1494 ctrl2.int1_fifo_th = val->fifo_th;
1495 ctrl2.int1_fifo_full = val->fifo_full;
1496 ctrl2.int1_boot = val->boot;
1497
1498 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1499 }
1500 }
1501
1502 if (ret == 0)
1503 {
1504 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1505
1506 if (ret == 0)
1507 {
1508 md1_cfg.int1_ff = val->free_fall;
1509 md1_cfg.int1_6d = val->six_d;
1510 md1_cfg.int1_tap = val->tap;
1511 md1_cfg.int1_wu = val->wake_up;
1512 md1_cfg.int1_sleep_change = val->sleep_change;
1513 md1_cfg.int1_emb_func = val->emb_function;
1514 md1_cfg.int1_timestamp = val->timestamp;
1515
1516 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1517 }
1518 }
1519
1520 return ret;
1521 }
1522
1523 /**
1524 * @brief routes interrupt signals on INT 1 pin.[get]
1525 *
1526 * @param ctx read / write interface definitions
1527 * @param val Get interrupt signals routing on INT 1 pin.
1528 * @retval interface status (MANDATORY: return 0 -> no Error)
1529 *
1530 */
lis2duxs12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1531 int32_t lis2duxs12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1532 {
1533 lis2duxs12_ctrl1_t ctrl1;
1534 lis2duxs12_ctrl2_t ctrl2;
1535 lis2duxs12_md1_cfg_t md1_cfg;
1536 int32_t ret;
1537
1538 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
1539 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl2, 1);
1540 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1541
1542 if (ret == 0)
1543 {
1544 val->int_on_res = ctrl1.int1_on_res;
1545 val->drdy = ctrl2.int1_drdy;
1546 val->fifo_ovr = ctrl2.int1_fifo_ovr;
1547 val->fifo_th = ctrl2.int1_fifo_th;
1548 val->fifo_full = ctrl2.int1_fifo_full;
1549 val->boot = ctrl2.int1_boot;
1550 val->free_fall = md1_cfg.int1_ff;
1551 val->six_d = md1_cfg.int1_6d;
1552 val->tap = md1_cfg.int1_tap;
1553 val->wake_up = md1_cfg.int1_wu;
1554 val->sleep_change = md1_cfg.int1_sleep_change;
1555 val->emb_function = md1_cfg.int1_emb_func;
1556 val->timestamp = md1_cfg.int1_timestamp;
1557 }
1558
1559 return ret;
1560 }
1561
1562 /**
1563 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
1564 *
1565 * @param ctx read / write interface definitions
1566 * @param val routes embedded func interrupt signals on INT 1 pin.
1567 * @retval interface status (MANDATORY: return 0 -> no Error)
1568 *
1569 */
lis2duxs12_emb_pin_int1_route_set(const stmdev_ctx_t * ctx,const lis2duxs12_emb_pin_int_route_t * val)1570 int32_t lis2duxs12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx,
1571 const lis2duxs12_emb_pin_int_route_t *val)
1572 {
1573 lis2duxs12_emb_func_int1_t emb_func_int1;
1574 lis2duxs12_md1_cfg_t md1_cfg;
1575 int32_t ret;
1576
1577 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1578 if (ret == 0)
1579 {
1580 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1581 }
1582
1583 if (ret == 0)
1584 {
1585 emb_func_int1.int1_tilt = val->tilt;
1586 emb_func_int1.int1_sig_mot = val->sig_mot;
1587 emb_func_int1.int1_step_det = val->step_det;
1588 emb_func_int1.int1_fsm_lc = val->fsm_lc;
1589
1590 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1591 }
1592 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1593
1594 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1595 if (ret == 0)
1596 {
1597 md1_cfg.int1_emb_func = 1;
1598 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1599 }
1600
1601 return ret;
1602 }
1603
1604 /**
1605 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
1606 *
1607 * @param ctx read / write interface definitions
1608 * @param val routes embedded func interrupt signals on INT 1 pin.
1609 * @retval interface status (MANDATORY: return 0 -> no Error)
1610 *
1611 */
lis2duxs12_emb_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1612 int32_t lis2duxs12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx,
1613 lis2duxs12_emb_pin_int_route_t *val)
1614 {
1615 lis2duxs12_emb_func_int1_t emb_func_int1;
1616 int32_t ret;
1617
1618 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1619 if (ret == 0)
1620 {
1621 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1622 }
1623
1624 if (ret == 0)
1625 {
1626 val->tilt = emb_func_int1.int1_tilt;
1627 val->sig_mot = emb_func_int1.int1_sig_mot;
1628 val->step_det = emb_func_int1.int1_step_det;
1629 val->fsm_lc = emb_func_int1.int1_fsm_lc;
1630 }
1631 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1632
1633 return ret;
1634 }
1635
1636 /**
1637 * @brief routes interrupt signals on INT 2 pin.[set]
1638 *
1639 * @param ctx read / write interface definitions
1640 * @param val routes interrupt signals on INT 2 pin.
1641 * @retval interface status (MANDATORY: return 0 -> no Error)
1642 *
1643 */
lis2duxs12_pin_int2_route_set(const stmdev_ctx_t * ctx,const lis2duxs12_pin_int_route_t * val)1644 int32_t lis2duxs12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1645 const lis2duxs12_pin_int_route_t *val)
1646 {
1647 lis2duxs12_ctrl3_t ctrl3;
1648 lis2duxs12_md2_cfg_t md2_cfg;
1649 int32_t ret;
1650
1651 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
1652
1653 if (ret == 0)
1654 {
1655 ctrl3.int2_drdy = val->drdy;
1656 ctrl3.int2_fifo_ovr = val->fifo_ovr;
1657 ctrl3.int2_fifo_th = val->fifo_th;
1658 ctrl3.int2_fifo_full = val->fifo_full;
1659 ctrl3.int2_boot = val->boot;
1660
1661 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
1662 }
1663
1664 if (ret == 0)
1665 {
1666 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1667
1668 if (ret == 0)
1669 {
1670 md2_cfg.int2_ff = val->free_fall;
1671 md2_cfg.int2_6d = val->six_d;
1672 md2_cfg.int2_tap = val->tap;
1673 md2_cfg.int2_wu = val->wake_up;
1674 md2_cfg.int2_sleep_change = val->sleep_change;
1675 md2_cfg.int2_emb_func = val->emb_function;
1676 md2_cfg.int2_timestamp = val->timestamp;
1677
1678 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1679 }
1680 }
1681
1682 return ret;
1683 }
1684
1685 /**
1686 * @brief routes interrupt signals on INT 2 pin.[get]
1687 *
1688 * @param ctx read / write interface definitions
1689 * @param val Get interrupt signals routing on INT 2 pin.
1690 * @retval interface status (MANDATORY: return 0 -> no Error)
1691 *
1692 */
lis2duxs12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2duxs12_pin_int_route_t * val)1693 int32_t lis2duxs12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val)
1694 {
1695 lis2duxs12_ctrl3_t ctrl3;
1696 lis2duxs12_md2_cfg_t md2_cfg;
1697 int32_t ret;
1698
1699 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1);
1700 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md2_cfg, 1);
1701
1702 if (ret == 0)
1703 {
1704 val->drdy = ctrl3.int2_drdy;
1705 val->fifo_ovr = ctrl3.int2_fifo_ovr;
1706 val->fifo_th = ctrl3.int2_fifo_th;
1707 val->fifo_full = ctrl3.int2_fifo_full;
1708 val->boot = ctrl3.int2_boot;
1709 val->free_fall = md2_cfg.int2_ff;
1710 val->six_d = md2_cfg.int2_6d;
1711 val->tap = md2_cfg.int2_tap;
1712 val->wake_up = md2_cfg.int2_wu;
1713 val->sleep_change = md2_cfg.int2_sleep_change;
1714 val->emb_function = md2_cfg.int2_emb_func;
1715 val->timestamp = md2_cfg.int2_timestamp;
1716 }
1717
1718 return ret;
1719 }
1720
1721 /**
1722 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
1723 *
1724 * @param ctx read / write interface definitions
1725 * @param val routes embedded func interrupt signals on INT 2 pin.
1726 * @retval interface status (MANDATORY: return 0 -> no Error)
1727 *
1728 */
lis2duxs12_emb_pin_int2_route_set(const stmdev_ctx_t * ctx,const lis2duxs12_emb_pin_int_route_t * val)1729 int32_t lis2duxs12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx,
1730 const lis2duxs12_emb_pin_int_route_t *val)
1731 {
1732 lis2duxs12_emb_func_int2_t emb_func_int2;
1733 lis2duxs12_md2_cfg_t md2_cfg;
1734 int32_t ret;
1735
1736 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1737 if (ret == 0)
1738 {
1739 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1740 }
1741
1742 if (ret == 0)
1743 {
1744 emb_func_int2.int2_tilt = val->tilt;
1745 emb_func_int2.int2_sig_mot = val->sig_mot;
1746 emb_func_int2.int2_step_det = val->step_det;
1747 emb_func_int2.int2_fsm_lc = val->fsm_lc;
1748
1749 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1750 }
1751 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1752
1753 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1754 if (ret == 0)
1755 {
1756 md2_cfg.int2_emb_func = 1;
1757 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1758 }
1759
1760 return ret;
1761 }
1762
1763 /**
1764 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
1765 *
1766 * @param ctx read / write interface definitions
1767 * @param val routes embedded func interrupt signals on INT 2 pin.
1768 * @retval interface status (MANDATORY: return 0 -> no Error)
1769 *
1770 */
lis2duxs12_emb_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2duxs12_emb_pin_int_route_t * val)1771 int32_t lis2duxs12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx,
1772 lis2duxs12_emb_pin_int_route_t *val)
1773 {
1774 lis2duxs12_emb_func_int2_t emb_func_int2;
1775 int32_t ret;
1776
1777 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1778 if (ret == 0)
1779 {
1780 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1781 }
1782
1783 if (ret == 0)
1784 {
1785 val->tilt = emb_func_int2.int2_tilt;
1786 val->sig_mot = emb_func_int2.int2_sig_mot;
1787 val->step_det = emb_func_int2.int2_step_det;
1788 val->fsm_lc = emb_func_int2.int2_fsm_lc;
1789 }
1790 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1791
1792 return ret;
1793 }
1794
1795 /**
1796 * @brief Interrupt configuration mode.[set]
1797 *
1798 * @param ctx read / write interface definitions
1799 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1800 * @retval interface status (MANDATORY: return 0 -> no Error)
1801 *
1802 */
lis2duxs12_int_config_set(const stmdev_ctx_t * ctx,const lis2duxs12_int_config_t * val)1803 int32_t lis2duxs12_int_config_set(const stmdev_ctx_t *ctx, const lis2duxs12_int_config_t *val)
1804 {
1805 lis2duxs12_interrupt_cfg_t interrupt_cfg;
1806 int32_t ret;
1807
1808 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1809
1810 if (ret == 0)
1811 {
1812 switch (val->int_cfg)
1813 {
1814 case LIS2DUXS12_INT_DISABLED:
1815 interrupt_cfg.interrupts_enable = 0;
1816 break;
1817
1818 case LIS2DUXS12_INT_LEVEL:
1819 interrupt_cfg.interrupts_enable = 1;
1820 interrupt_cfg.lir = 0;
1821 break;
1822
1823 case LIS2DUXS12_INT_LATCHED:
1824 default:
1825 interrupt_cfg.interrupts_enable = 1;
1826 interrupt_cfg.lir = 1;
1827 break;
1828 }
1829
1830 interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int;
1831 interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int;
1832
1833 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1834 }
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief Interrupt configuration mode.[get]
1841 *
1842 * @param ctx read / write interface definitions
1843 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1844 * @retval interface status (MANDATORY: return 0 -> no Error)
1845 *
1846 */
lis2duxs12_int_config_get(const stmdev_ctx_t * ctx,lis2duxs12_int_config_t * val)1847 int32_t lis2duxs12_int_config_get(const stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val)
1848 {
1849 lis2duxs12_interrupt_cfg_t interrupt_cfg;
1850 int32_t ret;
1851
1852 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1853
1854 if (ret == 0)
1855 {
1856 val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int;
1857 val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int;
1858
1859 if (interrupt_cfg.interrupts_enable == 0U)
1860 {
1861 val->int_cfg = LIS2DUXS12_INT_DISABLED;
1862 }
1863 else if (interrupt_cfg.lir == 0U)
1864 {
1865 val->int_cfg = LIS2DUXS12_INT_LEVEL;
1866 }
1867 else
1868 {
1869 val->int_cfg = LIS2DUXS12_INT_LATCHED;
1870 }
1871 }
1872
1873 return ret;
1874 }
1875
1876 /**
1877 * @brief Embedded Interrupt configuration mode.[set]
1878 *
1879 * @param ctx read / write interface definitions
1880 * @param val INT_PULSED, INT_LATCHED
1881 * @retval interface status (MANDATORY: return 0 -> no Error)
1882 *
1883 */
lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t * ctx,lis2duxs12_embedded_int_config_t val)1884 int32_t lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t *ctx,
1885 lis2duxs12_embedded_int_config_t val)
1886 {
1887 lis2duxs12_page_rw_t page_rw;
1888 int32_t ret;
1889
1890 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1891 if (ret == 0)
1892 {
1893 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1894
1895 switch (val)
1896 {
1897 case LIS2DUXS12_EMBEDDED_INT_LEVEL:
1898 page_rw.emb_func_lir = 0;
1899 break;
1900
1901 case LIS2DUXS12_EMBEDDED_INT_LATCHED:
1902 default:
1903 page_rw.emb_func_lir = 1;
1904 break;
1905 }
1906
1907 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1908 }
1909
1910 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1911
1912 return ret;
1913 }
1914
1915 /**
1916 * @brief Interrupt configuration mode.[get]
1917 *
1918 * @param ctx read / write interface definitions
1919 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
1920 * @retval interface status (MANDATORY: return 0 -> no Error)
1921 *
1922 */
lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t * ctx,lis2duxs12_embedded_int_config_t * val)1923 int32_t lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
1924 lis2duxs12_embedded_int_config_t *val)
1925 {
1926 lis2duxs12_page_rw_t page_rw;
1927 int32_t ret;
1928
1929 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
1930 if (ret == 0)
1931 {
1932 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1);
1933
1934 if (page_rw.emb_func_lir == 0U)
1935 {
1936 *val = LIS2DUXS12_EMBEDDED_INT_LEVEL;
1937 }
1938 else
1939 {
1940 *val = LIS2DUXS12_EMBEDDED_INT_LATCHED;
1941 }
1942 }
1943
1944 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
1945
1946 return ret;
1947 }
1948
1949 /**
1950 * @}
1951 *
1952 */
1953
1954 /**
1955 * @defgroup FIFO
1956 * @brief FIFO
1957 * @{/
1958 *
1959 */
1960
1961 /**
1962 * @brief FIFO mode selection.[set]
1963 *
1964 * @param ctx read / write interface definitions
1965 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1966 * @retval interface status (MANDATORY: return 0 -> no Error)
1967 *
1968 */
lis2duxs12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2duxs12_fifo_mode_t val)1969 int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val)
1970 {
1971 lis2duxs12_ctrl4_t ctrl4;
1972 lis2duxs12_fifo_ctrl_t fifo_ctrl;
1973 lis2duxs12_fifo_wtm_t fifo_wtm;
1974 lis2duxs12_fifo_batch_dec_t fifo_batch;
1975 int32_t ret;
1976
1977 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
1978 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1979 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1980 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1981
1982 if (ret == 0)
1983 {
1984 /* set FIFO mode */
1985 if (val.operation != LIS2DUXS12_FIFO_OFF)
1986 {
1987 ctrl4.fifo_en = 1;
1988 fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U);
1989 }
1990 else
1991 {
1992 ctrl4.fifo_en = 0;
1993 }
1994
1995 /* set fifo depth (1X/2X) */
1996 fifo_ctrl.fifo_depth = (uint8_t)val.store;
1997
1998 /* Set xl_only_fifo */
1999 fifo_wtm.xl_only_fifo = val.xl_only;
2000
2001 /* set batching info */
2002 if (val.batch.dec_ts != LIS2DUXS12_DEC_TS_OFF)
2003 {
2004 fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts;
2005 fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl;
2006 }
2007
2008 fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo;
2009
2010 /* set watermark */
2011 if (val.watermark > 0U)
2012 {
2013 fifo_ctrl.stop_on_fth = 1;
2014 fifo_wtm.fth = val.watermark;
2015 }
2016
2017 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
2018 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
2019 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2020 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
2021 }
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @brief FIFO mode selection.[get]
2028 *
2029 * @param ctx read / write interface definitions
2030 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
2031 * @retval interface status (MANDATORY: return 0 -> no Error)
2032 *
2033 */
lis2duxs12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_fifo_mode_t * val)2034 int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val)
2035 {
2036 lis2duxs12_ctrl4_t ctrl4;
2037 lis2duxs12_fifo_ctrl_t fifo_ctrl;
2038 lis2duxs12_fifo_wtm_t fifo_wtm;
2039 lis2duxs12_fifo_batch_dec_t fifo_batch;
2040 int32_t ret;
2041
2042 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
2043 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2044 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
2045 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
2046
2047 if (ret == 0)
2048 {
2049 /* get FIFO mode */
2050 if (ctrl4.fifo_en == 0U)
2051 {
2052 val->operation = LIS2DUXS12_FIFO_OFF;
2053 }
2054 else
2055 {
2056 val->operation = (lis2duxs12_operation_t)fifo_ctrl.fifo_mode;
2057 }
2058 val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en;
2059
2060 /* get fifo depth (1X/2X) */
2061 val->store = (lis2duxs12_store_t)fifo_ctrl.fifo_depth;
2062
2063 /* Get xl_only_fifo */
2064 val->xl_only = fifo_wtm.xl_only_fifo;
2065
2066 /* get batching info */
2067 val->batch.dec_ts = (lis2duxs12_dec_ts_t)fifo_batch.dec_ts_batch;
2068 val->batch.bdr_xl = (lis2duxs12_bdr_xl_t)fifo_batch.bdr_xl;
2069
2070 /* get watermark */
2071 val->watermark = fifo_wtm.fth;
2072 }
2073
2074 return ret;
2075 }
2076
2077 /**
2078 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
2079 *
2080 * @param ctx read / write interface definitions
2081 * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO.
2082 * @retval interface status (MANDATORY: return 0 -> no Error)
2083 *
2084 */
lis2duxs12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)2085 int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
2086 {
2087 uint8_t buff;
2088 int32_t ret;
2089
2090 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS2, &buff, 1);
2091
2092 *val = buff;
2093
2094 return ret;
2095 }
2096
lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2097 int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2098 {
2099 lis2duxs12_fifo_status1_t fifo_status1;
2100 int32_t ret;
2101
2102 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1);
2103
2104 *val = fifo_status1.fifo_wtm_ia;
2105
2106 return ret;
2107 }
2108
lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lis2duxs12_fifo_sensor_tag_t * val)2109 int32_t lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val)
2110 {
2111 lis2duxs12_fifo_data_out_tag_t fifo_tag;
2112 int32_t ret;
2113
2114 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
2115
2116 *val = (lis2duxs12_fifo_sensor_tag_t) fifo_tag.tag_sensor;
2117
2118 return ret;
2119 }
2120
lis2duxs12_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)2121 int32_t lis2duxs12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2122 {
2123 int32_t ret;
2124
2125 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_X_L, buff, 6);
2126
2127 return ret;
2128 }
2129
lis2duxs12_fifo_data_get(const stmdev_ctx_t * ctx,const lis2duxs12_md_t * md,const lis2duxs12_fifo_mode_t * fmd,lis2duxs12_fifo_data_t * data)2130 int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md,
2131 const lis2duxs12_fifo_mode_t *fmd,
2132 lis2duxs12_fifo_data_t *data)
2133 {
2134 lis2duxs12_fifo_data_out_tag_t fifo_tag;
2135 uint8_t fifo_raw[6];
2136 int32_t ret, i;
2137
2138 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
2139 data->tag = fifo_tag.tag_sensor;
2140
2141 switch (fifo_tag.tag_sensor)
2142 {
2143 case 0x3:
2144 case 0x1E:
2145 /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */
2146 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
2147 for (i = 0; i < 3; i++)
2148 {
2149 data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256;
2150 data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256;
2151 }
2152 break;
2153 case 0x1F:
2154 case 0x2:
2155 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
2156 if (fmd->xl_only == 0x0U)
2157 {
2158 /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/
2159 data->xl[0].raw[0] = (int16_t)fifo_raw[0];
2160 data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16;
2161 data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16;
2162 data->xl[0].raw[1] = (data->xl[0].raw[1] + ((int16_t)fifo_raw[2] * 16)) * 16;
2163 data->xl[0].raw[2] = (int16_t)fifo_raw[3];
2164 data->xl[0].raw[2] = (data->xl[0].raw[2] + (int16_t)fifo_raw[4] * 256) * 16;
2165 data->heat.raw = (int16_t)fifo_raw[4] / 16;
2166 data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16;
2167 if (fifo_tag.tag_sensor == (uint8_t)LIS2DUXS12_XL_TEMP_TAG)
2168 {
2169 data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw);
2170 }
2171 else
2172 {
2173 data->ah_qvar.raw = data->heat.raw;
2174 data->ah_qvar.mv = lis2duxs12_from_lsb_to_mv(data->ah_qvar.raw);
2175 }
2176 }
2177 else
2178 {
2179 /* A FIFO sample consists of 16-bits 3-axis XL at ODR */
2180 data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256;
2181 data->xl[0].raw[1] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[3] * 256;
2182 data->xl[0].raw[2] = (int16_t)fifo_raw[4] + (int16_t)fifo_raw[5] * 256;
2183 }
2184 break;
2185 case 0x4:
2186 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
2187
2188 data->cfg_chg.cfg_change = fifo_raw[0] >> 7;
2189 data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU;
2190 data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U;
2191 data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U;
2192 data->cfg_chg.qvar_en = fifo_raw[1] >> 7;
2193 data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U;
2194 data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U;
2195 data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U;
2196
2197 data->cfg_chg.timestamp = fifo_raw[5];
2198 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4];
2199 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3];
2200 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2];
2201 break;
2202
2203 case 0x12:
2204 ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw);
2205
2206 data->pedo.steps = fifo_raw[1];
2207 data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0];
2208
2209 data->pedo.timestamp = fifo_raw[5];
2210 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4];
2211 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3];
2212 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2];
2213
2214 break;
2215
2216 case 0x0:
2217 default:
2218 /* do nothing */
2219 break;
2220 }
2221
2222 for (i = 0; i < 3; i++)
2223 {
2224 switch (md->fs)
2225 {
2226 case LIS2DUXS12_2g:
2227 data->xl[0].mg[i] = lis2duxs12_from_fs2g_to_mg(data->xl[0].raw[i]);
2228 data->xl[1].mg[i] = lis2duxs12_from_fs2g_to_mg(data->xl[1].raw[i]);
2229 break;
2230 case LIS2DUXS12_4g:
2231 data->xl[0].mg[i] = lis2duxs12_from_fs4g_to_mg(data->xl[0].raw[i]);
2232 data->xl[1].mg[i] = lis2duxs12_from_fs4g_to_mg(data->xl[1].raw[i]);
2233 break;
2234 case LIS2DUXS12_8g:
2235 data->xl[0].mg[i] = lis2duxs12_from_fs8g_to_mg(data->xl[0].raw[i]);
2236 data->xl[1].mg[i] = lis2duxs12_from_fs8g_to_mg(data->xl[1].raw[i]);
2237 break;
2238 case LIS2DUXS12_16g:
2239 data->xl[0].mg[i] = lis2duxs12_from_fs16g_to_mg(data->xl[0].raw[i]);
2240 data->xl[1].mg[i] = lis2duxs12_from_fs16g_to_mg(data->xl[1].raw[i]);
2241 break;
2242 default:
2243 data->xl[0].mg[i] = 0.0f;
2244 data->xl[1].mg[i] = 0.0f;
2245 break;
2246 }
2247 }
2248
2249 return ret;
2250 }
2251
2252 /**
2253 * @brief Enables AH_QVAR chain.[set]
2254 *
2255 * @param ctx read / write interface definitions
2256 * @param val Enables and configures AH_QVAR chain.
2257 * @retval interface status (MANDATORY: return 0 -> no Error)
2258 *
2259 */
lis2duxs12_ah_qvar_mode_set(const stmdev_ctx_t * ctx,lis2duxs12_ah_qvar_mode_t val)2260 int32_t lis2duxs12_ah_qvar_mode_set(const stmdev_ctx_t *ctx,
2261 lis2duxs12_ah_qvar_mode_t val)
2262 {
2263 lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg;
2264 int32_t ret;
2265
2266 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
2267 if (ret == 0)
2268 {
2269 ah_qvar_cfg.ah_qvar_gain = (uint8_t)val.ah_qvar_gain;
2270 ah_qvar_cfg.ah_qvar_c_zin = (uint8_t)val.ah_qvar_zin;
2271 ah_qvar_cfg.ah_qvar_notch_cutoff = (uint8_t)val.ah_qvar_notch;
2272 ah_qvar_cfg.ah_qvar_notch_en = val.ah_qvar_notch_en;
2273 ah_qvar_cfg.ah_qvar_en = val.ah_qvar_en;
2274 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
2275 }
2276
2277 return ret;
2278 }
2279
2280 /**
2281 * @brief Enables AH_QVAR chain.[get]
2282 *
2283 * @param ctx read / write interface definitions
2284 * @param val Enables and configures AH_QVAR chain.
2285 * @retval interface status (MANDATORY: return 0 -> no Error)
2286 *
2287 */
lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_ah_qvar_mode_t * val)2288 int32_t lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t *ctx,
2289 lis2duxs12_ah_qvar_mode_t *val)
2290 {
2291 lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg;
2292 int32_t ret;
2293
2294 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1);
2295
2296 switch (ah_qvar_cfg.ah_qvar_gain)
2297 {
2298 case 0x0:
2299 val->ah_qvar_gain = LIS2DUXS12_GAIN_0_5;
2300 break;
2301
2302 case 0x1:
2303 val->ah_qvar_gain = LIS2DUXS12_GAIN_1;
2304 break;
2305
2306 case 0x2:
2307 val->ah_qvar_gain = LIS2DUXS12_GAIN_2;
2308 break;
2309
2310 case 0x3:
2311 default:
2312 val->ah_qvar_gain = LIS2DUXS12_GAIN_4;
2313 break;
2314 }
2315
2316 switch (ah_qvar_cfg.ah_qvar_c_zin)
2317 {
2318 case 0x0:
2319 val->ah_qvar_zin = LIS2DUXS12_520MOhm;
2320 break;
2321
2322 case 0x1:
2323 val->ah_qvar_zin = LIS2DUXS12_175MOhm;
2324 break;
2325
2326 case 0x2:
2327 val->ah_qvar_zin = LIS2DUXS12_310MOhm;
2328 break;
2329
2330 case 0x3:
2331 default:
2332 val->ah_qvar_zin = LIS2DUXS12_75MOhm;
2333 break;
2334 }
2335
2336 switch (ah_qvar_cfg.ah_qvar_notch_cutoff)
2337 {
2338 case 0x0:
2339 val->ah_qvar_notch = LIS2DUXS12_NOTCH_50HZ;
2340 break;
2341
2342 case 0x1:
2343 default:
2344 val->ah_qvar_notch = LIS2DUXS12_NOTCH_60HZ;
2345 break;
2346 }
2347
2348 val->ah_qvar_notch_en = ah_qvar_cfg.ah_qvar_notch_en;
2349 val->ah_qvar_en = ah_qvar_cfg.ah_qvar_en;
2350
2351 return ret;
2352 }
2353
2354 /**
2355 * @defgroup Step Counter (Pedometer)
2356 * @brief Step Counter (Pedometer)
2357 * @{/
2358 *
2359 */
2360 /**
2361 * @brief Step counter mode[set]
2362 *
2363 * @param ctx read / write interface definitions
2364 * @param val Step counter mode
2365 * @retval interface status (MANDATORY: return 0 -> no Error)
2366 *
2367 */
lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t * ctx,lis2duxs12_stpcnt_mode_t val)2368 int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val)
2369 {
2370 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2371 lis2duxs12_emb_func_en_b_t emb_func_en_b;
2372 lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en;
2373 lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg;
2374 int32_t ret;
2375
2376 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2377 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2378 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
2379 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2380
2381 if ((val.false_step_rej == PROPERTY_ENABLE)
2382 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE))
2383 {
2384 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
2385 }
2386
2387 emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo;
2388 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2389
2390 emb_func_en_a.pedo_en = val.step_counter_enable;
2391 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2392
2393 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2394 ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG,
2395 (uint8_t *)&pedo_cmd_reg, 1);
2396
2397 if (ret == 0)
2398 {
2399 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
2400 ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG,
2401 (uint8_t *)&pedo_cmd_reg, 1);
2402 }
2403
2404 return ret;
2405 }
2406
2407 /**
2408 * @brief Step counter mode[get]
2409 *
2410 * @param ctx read / write interface definitions
2411 * @param val Step counter mode
2412 * @retval interface status (MANDATORY: return 0 -> no Error)
2413 *
2414 */
lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t * ctx,lis2duxs12_stpcnt_mode_t * val)2415 int32_t lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val)
2416 {
2417 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2418 lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg;
2419 int32_t ret;
2420
2421 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2422 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2423 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2424
2425 ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG,
2426 (uint8_t *)&pedo_cmd_reg, 1);
2427 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
2428 val->step_counter_enable = emb_func_en_a.pedo_en;
2429
2430 return ret;
2431 }
2432
2433 /**
2434 * @brief Step counter output, number of detected steps.[get]
2435 *
2436 * @param ctx read / write interface definitions
2437 * @param val Step counter output, number of detected steps.
2438 * @retval interface status (MANDATORY: return 0 -> no Error)
2439 *
2440 */
lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)2441 int32_t lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
2442 {
2443 uint8_t buff[2];
2444 int32_t ret;
2445
2446 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2447 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_STEP_COUNTER_L, &buff[0], 2);
2448 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2449
2450 *val = buff[1];
2451 *val = (*val * 256U) + buff[0];
2452
2453 return ret;
2454 }
2455
2456 /**
2457 * @brief Reset step counter.[set]
2458 *
2459 * @param ctx read / write interface definitions
2460 * @param val Reset step counter.
2461 * @retval interface status (MANDATORY: return 0 -> no Error)
2462 *
2463 */
lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t * ctx)2464 int32_t lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx)
2465 {
2466 lis2duxs12_emb_func_src_t emb_func_src;
2467 int32_t ret;
2468
2469 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2470 if (ret == 0)
2471 {
2472 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2473 emb_func_src.pedo_rst_step = 1;
2474 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2475 }
2476
2477 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2478
2479 return ret;
2480 }
2481
2482 /**
2483 * @brief Pedometer debounce configuration.[set]
2484 *
2485 * @param ctx read / write interface definitions
2486 * @param val Pedometer debounce configuration.
2487 * @retval interface status (MANDATORY: return 0 -> no Error)
2488 *
2489 */
lis2duxs12_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)2490 int32_t lis2duxs12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
2491 {
2492 lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2493 int32_t ret;
2494
2495 pedo_deb_steps_conf.deb_step = val;
2496 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF,
2497 (uint8_t *)&pedo_deb_steps_conf, 1);
2498
2499 return ret;
2500 }
2501
2502 /**
2503 * @brief Pedometer debounce configuration.[get]
2504 *
2505 * @param ctx read / write interface definitions
2506 * @param val Pedometer debounce configuration.
2507 * @retval interface status (MANDATORY: return 0 -> no Error)
2508 *
2509 */
lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)2510 int32_t lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
2511 {
2512 lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2513 int32_t ret;
2514
2515 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF,
2516 (uint8_t *)&pedo_deb_steps_conf, 1);
2517 *val = pedo_deb_steps_conf.deb_step;
2518
2519 return ret;
2520 }
2521
2522 /**
2523 * @brief Time period register for step detection on delta time.[set]
2524 *
2525 * @param ctx read / write interface definitions
2526 * @param val Time period register for step detection on delta time.
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
lis2duxs12_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)2530 int32_t lis2duxs12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
2531 {
2532 uint8_t buff[2];
2533 int32_t ret;
2534
2535 buff[1] = (uint8_t)(val / 256U);
2536 buff[0] = (uint8_t)(val - (buff[1] * 256U));
2537
2538 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L,
2539 (uint8_t *)buff, 2);
2540
2541 return ret;
2542 }
2543
2544 /**
2545 * @brief Time period register for step detection on delta time.[get]
2546 *
2547 * @param ctx read / write interface definitions
2548 * @param val Time period register for step detection on delta time.
2549 * @retval interface status (MANDATORY: return 0 -> no Error)
2550 *
2551 */
lis2duxs12_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)2552 int32_t lis2duxs12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
2553 {
2554 uint8_t buff[2];
2555 int32_t ret;
2556
2557 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L,
2558 (uint8_t *)buff, 2);
2559 *val = buff[1];
2560 *val = (*val * 256U) + buff[0];
2561
2562 return ret;
2563 }
2564
2565 /**
2566 * @brief smart_power functionality configuration.[set]
2567 *
2568 * @param ctx read / write interface definitions
2569 * @param val lis2duxs12_smart_power_cfg_t structure.
2570 * @retval interface status (MANDATORY: return 0 -> no Error)
2571 */
lis2duxs12_smart_power_set(const stmdev_ctx_t * ctx,lis2duxs12_smart_power_cfg_t val)2572 int32_t lis2duxs12_smart_power_set(const stmdev_ctx_t *ctx, lis2duxs12_smart_power_cfg_t val)
2573 {
2574 lis2duxs12_ctrl1_t ctrl1;
2575 lis2duxs12_smart_power_ctrl_t smart_power_ctrl;
2576 int32_t ret;
2577
2578 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
2579 ctrl1.smart_power_en = val.enable;
2580 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
2581
2582 if (val.enable == 0)
2583 {
2584 /* if disabling smart_power no need to set win/dur fields */
2585 return ret;
2586 }
2587
2588 smart_power_ctrl.smart_power_ctrl_win = val.window;
2589 smart_power_ctrl.smart_power_ctrl_dur = val.duration;
2590 ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_SMART_POWER_CTRL,
2591 (uint8_t *)&smart_power_ctrl, 1);
2592
2593 return ret;
2594 }
2595
2596 /**
2597 * @brief smart_power functionality configuration.[get]
2598 *
2599 * @param ctx read / write interface definitions
2600 * @param val lis2duxs12_smart_power_cfg_t structure.
2601 * @retval interface status (MANDATORY: return 0 -> no Error)
2602 */
lis2duxs12_smart_power_get(const stmdev_ctx_t * ctx,lis2duxs12_smart_power_cfg_t * val)2603 int32_t lis2duxs12_smart_power_get(const stmdev_ctx_t *ctx, lis2duxs12_smart_power_cfg_t *val)
2604 {
2605 lis2duxs12_ctrl1_t ctrl1;
2606 lis2duxs12_smart_power_ctrl_t smart_power_ctrl;
2607 int32_t ret;
2608
2609 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
2610 val->enable = ctrl1.smart_power_en;
2611
2612 ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_SMART_POWER_CTRL,
2613 (uint8_t *)&smart_power_ctrl, 1);
2614 val->window = smart_power_ctrl.smart_power_ctrl_win;
2615 val->duration = smart_power_ctrl.smart_power_ctrl_dur;
2616
2617 return ret;
2618 }
2619
2620 /**
2621 * @}
2622 *
2623 */
2624
2625 /**
2626 * @defgroup Tilt
2627 * @brief Tilt
2628 * @{/
2629 *
2630 */
2631 /**
2632 * @brief Tilt calculation.[set]
2633 *
2634 * @param ctx read / write interface definitions
2635 * @param val Tilt calculation.
2636 * @retval interface status (MANDATORY: return 0 -> no Error)
2637 *
2638 */
lis2duxs12_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2639 int32_t lis2duxs12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2640 {
2641 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2642 int32_t ret;
2643
2644 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2645 if (ret == 0)
2646 {
2647 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2648 emb_func_en_a.tilt_en = val;
2649 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2650 }
2651
2652 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2653
2654 return ret;
2655 }
2656
2657 /**
2658 * @brief Tilt calculation.[get]
2659 *
2660 * @param ctx read / write interface definitions
2661 * @param val Tilt calculation.
2662 * @retval interface status (MANDATORY: return 0 -> no Error)
2663 *
2664 */
lis2duxs12_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2665 int32_t lis2duxs12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2666 {
2667 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2668 int32_t ret;
2669
2670 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2671 if (ret == 0)
2672 {
2673 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2674 *val = emb_func_en_a.tilt_en;
2675 }
2676
2677 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2678
2679 return ret;
2680 }
2681
2682 /**
2683 * @}
2684 *
2685 */
2686
2687 /**
2688 * @defgroup Significant motion detection
2689 * @brief Significant motion detection
2690 * @{/
2691 *
2692 */
2693 /**
2694 * @brief Enables significant motion detection function.[set]
2695 *
2696 * @param ctx read / write interface definitions
2697 * @param val Enables significant motion detection function.
2698 * @retval interface status (MANDATORY: return 0 -> no Error)
2699 *
2700 */
lis2duxs12_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2701 int32_t lis2duxs12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2702 {
2703 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2704 int32_t ret;
2705
2706 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2707 if (ret == 0)
2708 {
2709 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2710 emb_func_en_a.sign_motion_en = val;
2711 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2712 }
2713
2714 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2715
2716 return ret;
2717 }
2718
2719 /**
2720 * @brief Enables significant motion detection function.[get]
2721 *
2722 * @param ctx read / write interface definitions
2723 * @param val Enables significant motion detection function.
2724 * @retval interface status (MANDATORY: return 0 -> no Error)
2725 *
2726 */
lis2duxs12_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2727 int32_t lis2duxs12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2728 {
2729 lis2duxs12_emb_func_en_a_t emb_func_en_a;
2730 int32_t ret;
2731
2732 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
2733 if (ret == 0)
2734 {
2735 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2736 *val = emb_func_en_a.sign_motion_en;
2737 }
2738
2739 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
2740
2741 return ret;
2742 }
2743
2744 /**
2745 * @}
2746 *
2747 */
2748
2749
2750 /**
2751 * @defgroup Free Fall
2752 * @brief Free Fall
2753 * @{/
2754 *
2755 */
2756 /**
2757 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
2758 *
2759 * @param ctx read / write interface definitions
2760 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2761 * @retval interface status (MANDATORY: return 0 -> no Error)
2762 *
2763 */
lis2duxs12_ff_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2764 int32_t lis2duxs12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
2765 {
2766 lis2duxs12_wake_up_dur_t wake_up_dur;
2767 lis2duxs12_free_fall_t free_fall;
2768 int32_t ret;
2769
2770 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2771
2772 if (ret == 0)
2773 {
2774 wake_up_dur.ff_dur = (val >> 5) & 0x1U;
2775 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2776 }
2777
2778 if (ret == 0)
2779 {
2780 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2781 free_fall.ff_dur = val & 0x1FU;
2782 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2783 }
2784
2785 return ret;
2786 }
2787
2788 /**
2789 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
2790 *
2791 * @param ctx read / write interface definitions
2792 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2793 * @retval interface status (MANDATORY: return 0 -> no Error)
2794 *
2795 */
lis2duxs12_ff_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2796 int32_t lis2duxs12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
2797 {
2798 lis2duxs12_wake_up_dur_t wake_up_dur;
2799 lis2duxs12_free_fall_t free_fall;
2800 int32_t ret;
2801
2802 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2803 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2804
2805 *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur;
2806
2807 return ret;
2808 }
2809
2810 /**
2811 * @brief Free fall threshold setting.[set]
2812 *
2813 * @param ctx read / write interface definitions
2814 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2815 * @retval interface status (MANDATORY: return 0 -> no Error)
2816 *
2817 */
lis2duxs12_ff_thresholds_set(const stmdev_ctx_t * ctx,lis2duxs12_ff_thresholds_t val)2818 int32_t lis2duxs12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val)
2819 {
2820 lis2duxs12_free_fall_t free_fall;
2821 int32_t ret;
2822
2823 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2824 free_fall.ff_ths = ((uint8_t)val & 0x7U);
2825 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2826
2827 return ret;
2828 }
2829
2830 /**
2831 * @brief Free fall threshold setting.[get]
2832 *
2833 * @param ctx read / write interface definitions
2834 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2835 * @retval interface status (MANDATORY: return 0 -> no Error)
2836 *
2837 */
lis2duxs12_ff_thresholds_get(const stmdev_ctx_t * ctx,lis2duxs12_ff_thresholds_t * val)2838 int32_t lis2duxs12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val)
2839 {
2840 lis2duxs12_free_fall_t free_fall;
2841 int32_t ret;
2842
2843 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1);
2844
2845 switch (free_fall.ff_ths)
2846 {
2847 case 0x0:
2848 *val = LIS2DUXS12_156_mg;
2849 break;
2850
2851 case 0x1:
2852 *val = LIS2DUXS12_219_mg;
2853 break;
2854
2855 case 0x2:
2856 *val = LIS2DUXS12_250_mg;
2857 break;
2858
2859 case 0x3:
2860 *val = LIS2DUXS12_312_mg;
2861 break;
2862
2863 case 0x4:
2864 *val = LIS2DUXS12_344_mg;
2865 break;
2866
2867 case 0x5:
2868 *val = LIS2DUXS12_406_mg;
2869 break;
2870
2871 case 0x6:
2872 *val = LIS2DUXS12_469_mg;
2873 break;
2874
2875 case 0x7:
2876 *val = LIS2DUXS12_500_mg;
2877 break;
2878
2879 default:
2880 *val = LIS2DUXS12_156_mg;
2881 break;
2882 }
2883 return ret;
2884 }
2885
2886 /**
2887 * @}
2888 *
2889 */
2890
2891
2892 /**
2893 * @defgroup Orientation 6D (and 4D)
2894 * @brief Orientation 6D (and 4D)
2895 * @{/
2896 *
2897 */
2898 /**
2899 * @brief configuration for 4D/6D function.[set]
2900 *
2901 * @param ctx read / write interface definitions
2902 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2903 * @retval interface status (MANDATORY: return 0 -> no Error)
2904 *
2905 */
lis2duxs12_sixd_config_set(const stmdev_ctx_t * ctx,lis2duxs12_sixd_config_t val)2906 int32_t lis2duxs12_sixd_config_set(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val)
2907 {
2908 lis2duxs12_sixd_t sixd;
2909 int32_t ret;
2910
2911 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2912
2913 if (ret == 0)
2914 {
2915 sixd.d4d_en = ((uint8_t)val.mode);
2916 sixd.d6d_ths = ((uint8_t)val.threshold);
2917 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2918 }
2919
2920 return ret;
2921 }
2922
2923 /**
2924 * @brief configuration for 4D/6D function.[get]
2925 *
2926 * @param ctx read / write interface definitions
2927 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2928 * @retval interface status (MANDATORY: return 0 -> no Error)
2929 *
2930 */
lis2duxs12_sixd_config_get(const stmdev_ctx_t * ctx,lis2duxs12_sixd_config_t * val)2931 int32_t lis2duxs12_sixd_config_get(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val)
2932 {
2933 lis2duxs12_sixd_t sixd;
2934 int32_t ret;
2935
2936 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1);
2937
2938 val->mode = (lis2duxs12_mode_t)sixd.d4d_en;
2939
2940 switch ((sixd.d6d_ths))
2941 {
2942 case 0x0:
2943 val->threshold = LIS2DUXS12_DEG_80;
2944 break;
2945
2946 case 0x1:
2947 val->threshold = LIS2DUXS12_DEG_70;
2948 break;
2949
2950 case 0x2:
2951 val->threshold = LIS2DUXS12_DEG_60;
2952 break;
2953
2954 case 0x3:
2955 val->threshold = LIS2DUXS12_DEG_50;
2956 break;
2957
2958 default:
2959 val->threshold = LIS2DUXS12_DEG_80;
2960 break;
2961 }
2962
2963 return ret;
2964 }
2965
2966 /**
2967 * @}
2968 *
2969 */
2970
2971 /**
2972 * @defgroup wakeup configuration
2973 * @brief wakeup configuration
2974 * @{/
2975 *
2976 */
2977
2978 /**
2979 * @brief configuration for wakeup function.[set]
2980 *
2981 * @param ctx read / write interface definitions
2982 * @param val threshold, duration, ...
2983 * @retval interface status (MANDATORY: return 0 -> no Error)
2984 *
2985 */
lis2duxs12_wakeup_config_set(const stmdev_ctx_t * ctx,lis2duxs12_wakeup_config_t val)2986 int32_t lis2duxs12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val)
2987 {
2988 lis2duxs12_wake_up_ths_t wup_ths;
2989 lis2duxs12_wake_up_dur_t wup_dur;
2990 lis2duxs12_wake_up_dur_ext_t wup_dur_ext;
2991 lis2duxs12_interrupt_cfg_t int_cfg;
2992 lis2duxs12_ctrl1_t ctrl1;
2993 lis2duxs12_ctrl4_t ctrl4;
2994 int32_t ret;
2995
2996 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2997 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2998 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2999 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3000 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
3001 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
3002
3003 if (ret == 0)
3004 {
3005 wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U;
3006 wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2;
3007 wup_dur.sleep_dur = val.sleep_dur;
3008
3009 int_cfg.wake_ths_w = val.wake_ths_weight;
3010 wup_ths.wk_ths = val.wake_ths;
3011 wup_ths.sleep_on = (uint8_t)val.wake_enable;
3012 ctrl4.inact_odr = (uint8_t)val.inact_odr;
3013
3014 if (val.wake_enable == LIS2DUXS12_SLEEP_ON)
3015 {
3016 ctrl1.wu_x_en = 1;
3017 ctrl1.wu_y_en = 1;
3018 ctrl1.wu_z_en = 1;
3019 }
3020 else
3021 {
3022 ctrl1.wu_x_en = 0;
3023 ctrl1.wu_y_en = 0;
3024 ctrl1.wu_z_en = 0;
3025 }
3026
3027 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
3028 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
3029 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
3030 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3031 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
3032 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
3033 }
3034
3035 return ret;
3036 }
3037
3038 /**
3039 * @brief configuration for wakeup function.[get]
3040 *
3041 * @param ctx read / write interface definitions
3042 * @param val threshold, duration, ...
3043 * @retval interface status (MANDATORY: return 0 -> no Error)
3044 *
3045 */
lis2duxs12_wakeup_config_get(const stmdev_ctx_t * ctx,lis2duxs12_wakeup_config_t * val)3046 int32_t lis2duxs12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val)
3047 {
3048 lis2duxs12_wake_up_ths_t wup_ths;
3049 lis2duxs12_wake_up_dur_t wup_dur;
3050 lis2duxs12_wake_up_dur_ext_t wup_dur_ext;
3051 lis2duxs12_interrupt_cfg_t int_cfg;
3052 lis2duxs12_ctrl4_t ctrl4;
3053 int32_t ret;
3054
3055 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
3056 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
3057 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
3058 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3059 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
3060
3061 if (ret == 0)
3062 {
3063 switch (wup_dur.wake_dur)
3064 {
3065 case 0x0:
3066 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3067 LIS2DUXS12_3_ODR : LIS2DUXS12_0_ODR;
3068 break;
3069
3070 case 0x1:
3071 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3072 LIS2DUXS12_7_ODR : LIS2DUXS12_1_ODR;
3073 break;
3074
3075 case 0x2:
3076 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3077 LIS2DUXS12_11_ODR : LIS2DUXS12_2_ODR;
3078 break;
3079
3080 case 0x3:
3081 default:
3082 val->wake_dur = LIS2DUXS12_15_ODR;
3083 break;
3084 }
3085
3086 val->sleep_dur = wup_dur.sleep_dur;
3087
3088 val->wake_ths_weight = int_cfg.wake_ths_w;
3089 val->wake_ths = wup_ths.wk_ths;
3090 val->wake_enable = (lis2duxs12_wake_enable_t)wup_ths.sleep_on;
3091 val->inact_odr = (lis2duxs12_inact_odr_t)ctrl4.inact_odr;
3092 }
3093
3094 return ret;
3095 }
3096
3097 /**
3098 * @}
3099 *
3100 */
3101
lis2duxs12_tap_config_set(const stmdev_ctx_t * ctx,lis2duxs12_tap_config_t val)3102 int32_t lis2duxs12_tap_config_set(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val)
3103 {
3104 lis2duxs12_tap_cfg0_t tap_cfg0;
3105 lis2duxs12_tap_cfg1_t tap_cfg1;
3106 lis2duxs12_tap_cfg2_t tap_cfg2;
3107 lis2duxs12_tap_cfg3_t tap_cfg3;
3108 lis2duxs12_tap_cfg4_t tap_cfg4;
3109 lis2duxs12_tap_cfg5_t tap_cfg5;
3110 lis2duxs12_tap_cfg6_t tap_cfg6;
3111 int32_t ret;
3112
3113 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3114 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3115 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3116 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3117 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3118 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3119 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3120
3121 if (ret == 0)
3122 {
3123 tap_cfg0.axis = (uint8_t)val.axis;
3124 tap_cfg0.invert_t = val.inverted_peak_time;
3125 tap_cfg1.pre_still_ths = val.pre_still_ths;
3126 tap_cfg3.post_still_ths = val.post_still_ths;
3127 tap_cfg1.post_still_t = val.post_still_time & 0xFU;
3128 tap_cfg2.post_still_t = val.post_still_time >> 4;
3129 tap_cfg2.wait_t = val.shock_wait_time;
3130 tap_cfg3.latency_t = val.latency;
3131 tap_cfg4.wait_end_latency = val.wait_end_latency;
3132 tap_cfg4.peak_ths = val.peak_ths;
3133 tap_cfg5.rebound_t = val.rebound;
3134 tap_cfg5.single_tap_en = val.single_tap_on;
3135 tap_cfg5.double_tap_en = val.double_tap_on;
3136 tap_cfg5.triple_tap_en = val.triple_tap_on;
3137 tap_cfg6.pre_still_st = val.pre_still_start;
3138 tap_cfg6.pre_still_n = val.pre_still_n;
3139
3140 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3141 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3142 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3143 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3144 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3145 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3146 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3147 }
3148
3149 return ret;
3150 }
3151
lis2duxs12_tap_config_get(const stmdev_ctx_t * ctx,lis2duxs12_tap_config_t * val)3152 int32_t lis2duxs12_tap_config_get(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val)
3153 {
3154 lis2duxs12_tap_cfg0_t tap_cfg0;
3155 lis2duxs12_tap_cfg1_t tap_cfg1;
3156 lis2duxs12_tap_cfg2_t tap_cfg2;
3157 lis2duxs12_tap_cfg3_t tap_cfg3;
3158 lis2duxs12_tap_cfg4_t tap_cfg4;
3159 lis2duxs12_tap_cfg5_t tap_cfg5;
3160 lis2duxs12_tap_cfg6_t tap_cfg6;
3161 int32_t ret;
3162
3163 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3164 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3165 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3166 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3167 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3168 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3169 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3170
3171 if (ret == 0)
3172 {
3173 val->axis = (lis2duxs12_axis_t)tap_cfg0.axis;
3174 val->inverted_peak_time = tap_cfg0.invert_t;
3175 val->pre_still_ths = tap_cfg1.pre_still_ths;
3176 val->post_still_ths = tap_cfg3.post_still_ths;
3177 val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t;
3178 val->shock_wait_time = tap_cfg2.wait_t;
3179 val->latency = tap_cfg3.latency_t;
3180 val->wait_end_latency = tap_cfg4.wait_end_latency;
3181 val->peak_ths = tap_cfg4.peak_ths;
3182 val->rebound = tap_cfg5.rebound_t;
3183 val->single_tap_on = tap_cfg5.single_tap_en;
3184 val->double_tap_on = tap_cfg5.double_tap_en;
3185 val->triple_tap_on = tap_cfg5.triple_tap_en;
3186 val->pre_still_start = tap_cfg6.pre_still_st;
3187 val->pre_still_n = tap_cfg6.pre_still_n;
3188 }
3189
3190 return ret;
3191 }
3192
3193 /**
3194 * @}
3195 *
3196 */
3197
3198 /**
3199 * @defgroup lis2duxs12_Timestamp
3200 * @brief This section groups all the functions that manage the
3201 * timestamp generation.
3202 * @{
3203 *
3204 */
3205
3206 /**
3207 * @brief Enables timestamp counter.[set]
3208 *
3209 * @param ctx Read / write interface definitions.(ptr)
3210 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3211 * @retval Interface status (MANDATORY: return 0 -> no Error).
3212 *
3213 */
lis2duxs12_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)3214 int32_t lis2duxs12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
3215 {
3216 lis2duxs12_interrupt_cfg_t int_cfg;
3217 int32_t ret;
3218
3219 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3220
3221 if (ret == 0)
3222 {
3223 int_cfg.timestamp_en = (uint8_t)val;
3224 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3225 }
3226
3227 return ret;
3228 }
3229
3230 /**
3231 * @brief Enables timestamp counter.[get]
3232 *
3233 * @param ctx Read / write interface definitions.(ptr)
3234 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3235 * @retval Interface status (MANDATORY: return 0 -> no Error).
3236 *
3237 */
lis2duxs12_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)3238 int32_t lis2duxs12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
3239 {
3240 lis2duxs12_interrupt_cfg_t int_cfg;
3241 int32_t ret;
3242
3243 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3244 *val = int_cfg.timestamp_en;
3245
3246 return ret;
3247 }
3248
3249 /**
3250 * @brief Timestamp first data output register (r).
3251 * The value is expressed as a 32-bit word and the bit resolution
3252 * is 10 us.[get]
3253 *
3254 * @param ctx Read / write interface definitions.(ptr)
3255 * @param buff Buffer that stores data read
3256 * @retval Interface status (MANDATORY: return 0 -> no Error).
3257 *
3258 */
lis2duxs12_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)3259 int32_t lis2duxs12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
3260 {
3261 uint8_t buff[4];
3262 int32_t ret;
3263
3264 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TIMESTAMP0, buff, 4);
3265 *val = buff[3];
3266 *val = (*val * 256U) + buff[2];
3267 *val = (*val * 256U) + buff[1];
3268 *val = (*val * 256U) + buff[0];
3269
3270 return ret;
3271 }
3272
3273 /**
3274 * @}
3275 *
3276 */
3277
3278 /**
3279 * @defgroup LIS2DUXS12_finite_state_machine
3280 * @brief This section groups all the functions that manage the
3281 * state_machine.
3282 * @{
3283 *
3284 */
3285
3286 /**
3287 * @brief Interrupt status bit for FSM long counter timeout interrupt
3288 * event.[get]
3289 *
3290 * @param ctx Read / write interface definitions.(ptr)
3291 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
3292 * @retval Interface status (MANDATORY: return 0 -> no Error).
3293 *
3294 */
lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3295 int32_t lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
3296 uint8_t *val)
3297 {
3298 lis2duxs12_emb_func_status_t emb_func_status;
3299 int32_t ret;
3300
3301 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3302
3303 if (ret == 0)
3304 {
3305 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS,
3306 (uint8_t *)&emb_func_status, 1);
3307
3308 *val = emb_func_status.is_fsm_lc;
3309 }
3310
3311 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3312
3313 return ret;
3314 }
3315
3316 /**
3317 * @brief Embedded final state machine functions mode.[set]
3318 *
3319 * @param ctx Read / write interface definitions.(ptr)
3320 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
3321 * @retval Interface status (MANDATORY: return 0 -> no Error).
3322 *
3323 */
lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)3324 int32_t lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3325 {
3326 int32_t ret;
3327
3328 lis2duxs12_emb_func_en_b_t emb_func_en_b;
3329 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3330
3331 if (ret == 0)
3332 {
3333 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3334 (uint8_t *)&emb_func_en_b, 1);
3335
3336 emb_func_en_b.fsm_en = (uint8_t)val;
3337
3338 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3339 (uint8_t *)&emb_func_en_b, 1);
3340 }
3341
3342 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3343
3344 return ret;
3345 }
3346
3347 /**
3348 * @brief Embedded final state machine functions mode.[get]
3349 *
3350 * @param ctx Read / write interface definitions.(ptr)
3351 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
3352 * @retval Interface status (MANDATORY: return 0 -> no Error).
3353 *
3354 */
lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3355 int32_t lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3356 {
3357 int32_t ret;
3358
3359 lis2duxs12_emb_func_en_b_t emb_func_en_b;
3360 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3361
3362 if (ret == 0)
3363 {
3364 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3365 (uint8_t *)&emb_func_en_b, 1);
3366
3367 *val = emb_func_en_b.fsm_en;
3368
3369 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3370 (uint8_t *)&emb_func_en_b, 1);
3371 }
3372
3373 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3374
3375 return ret;
3376 }
3377
3378 /**
3379 * @brief Embedded final state machine functions mode.[set]
3380 *
3381 * @param ctx Read / write interface definitions.(ptr)
3382 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3383 * @retval Interface status (MANDATORY: return 0 -> no Error).
3384 *
3385 */
lis2duxs12_fsm_enable_set(const stmdev_ctx_t * ctx,lis2duxs12_emb_fsm_enable_t * val)3386 int32_t lis2duxs12_fsm_enable_set(const stmdev_ctx_t *ctx,
3387 lis2duxs12_emb_fsm_enable_t *val)
3388 {
3389 lis2duxs12_emb_func_en_b_t emb_func_en_b;
3390 int32_t ret;
3391
3392 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3393
3394 if (ret == 0)
3395 {
3396 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ENABLE,
3397 (uint8_t *)&val->fsm_enable, 1);
3398 }
3399
3400 if (ret == 0)
3401 {
3402 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3403 (uint8_t *)&emb_func_en_b, 1);
3404
3405 if ((val->fsm_enable.fsm1_en |
3406 val->fsm_enable.fsm2_en |
3407 val->fsm_enable.fsm3_en |
3408 val->fsm_enable.fsm4_en |
3409 val->fsm_enable.fsm5_en |
3410 val->fsm_enable.fsm6_en |
3411 val->fsm_enable.fsm7_en |
3412 val->fsm_enable.fsm8_en) != PROPERTY_DISABLE)
3413 {
3414 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
3415 }
3416 else
3417 {
3418 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
3419 }
3420
3421 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B,
3422 (uint8_t *)&emb_func_en_b, 1);
3423 }
3424
3425 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3426
3427 return ret;
3428 }
3429
3430 /**
3431 * @brief Embedded final state machine functions mode.[get]
3432 *
3433 * @param ctx Read / write interface definitions.(ptr)
3434 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3435 * @retval Interface status (MANDATORY: return 0 -> no Error).
3436 *
3437 */
lis2duxs12_fsm_enable_get(const stmdev_ctx_t * ctx,lis2duxs12_emb_fsm_enable_t * val)3438 int32_t lis2duxs12_fsm_enable_get(const stmdev_ctx_t *ctx,
3439 lis2duxs12_emb_fsm_enable_t *val)
3440 {
3441 int32_t ret;
3442
3443 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3444
3445 if (ret == 0)
3446 {
3447 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ENABLE,
3448 (uint8_t *)&val->fsm_enable, 1);
3449 }
3450
3451 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3452
3453 return ret;
3454 }
3455
3456 /**
3457 * @brief FSM long counter status register. Long counter value is an
3458 * unsigned integer value (16-bit format).[set]
3459 *
3460 * @param ctx Read / write interface definitions.(ptr)
3461 * @param buff Buffer that contains data to write
3462 * @retval Interface status (MANDATORY: return 0 -> no Error).
3463 *
3464 */
lis2duxs12_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)3465 int32_t lis2duxs12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
3466 {
3467 uint8_t buff[2];
3468 int32_t ret;
3469
3470 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3471
3472 if (ret == 0)
3473 {
3474 buff[1] = (uint8_t)(val / 256U);
3475 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3476 ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2);
3477 }
3478
3479 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3480
3481 return ret;
3482 }
3483
3484 /**
3485 * @brief FSM long counter status register. Long counter value is an
3486 * unsigned integer value (16-bit format).[get]
3487 *
3488 * @param ctx Read / write interface definitions.(ptr)
3489 * @param buff Buffer that stores data read
3490 * @retval Interface status (MANDATORY: return 0 -> no Error).
3491 *
3492 */
lis2duxs12_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)3493 int32_t lis2duxs12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
3494 {
3495 uint8_t buff[2];
3496 int32_t ret;
3497
3498 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3499
3500 if (ret == 0)
3501 {
3502 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_LONG_COUNTER_L, buff, 2);
3503 *val = buff[1];
3504 *val = (*val * 256U) + buff[0];
3505 }
3506
3507 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3508
3509 return ret;
3510 }
3511
3512 /**
3513 * @brief FSM status.[get]
3514 *
3515 * @param ctx read / write interface definitions
3516 * @param val register FSM_STATUS_MAINPAGE
3517 *
3518 */
lis2duxs12_fsm_status_get(const stmdev_ctx_t * ctx,lis2duxs12_fsm_status_mainpage_t * val)3519 int32_t lis2duxs12_fsm_status_get(const stmdev_ctx_t *ctx,
3520 lis2duxs12_fsm_status_mainpage_t *val)
3521 {
3522 return lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_STATUS_MAINPAGE,
3523 (uint8_t *) val, 1);
3524 }
3525
3526 /**
3527 * @brief FSM output registers.[get]
3528 *
3529 * @param ctx Read / write interface definitions.(ptr)
3530 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
3531 * @retval Interface status (MANDATORY: return 0 -> no Error).
3532 *
3533 */
lis2duxs12_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * val)3534 int32_t lis2duxs12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
3535 {
3536 int32_t ret;
3537
3538 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3539
3540 if (ret == 0)
3541 {
3542 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_OUTS1, val, 8);
3543 }
3544
3545 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3546
3547 return ret;
3548 }
3549
3550 /**
3551 * @brief Finite State Machine ODR configuration.[set]
3552 *
3553 * @param ctx Read / write interface definitions.(ptr)
3554 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3555 * @retval Interface status (MANDATORY: return 0 -> no Error).
3556 *
3557 */
lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t * ctx,lis2duxs12_fsm_val_odr_t val)3558 int32_t lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t *ctx,
3559 lis2duxs12_fsm_val_odr_t val)
3560 {
3561 lis2duxs12_fsm_odr_t fsm_odr_reg;
3562 int32_t ret;
3563
3564 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3565
3566 if (ret == 0)
3567 {
3568 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR,
3569 (uint8_t *)&fsm_odr_reg, 1);
3570
3571 fsm_odr_reg.fsm_odr = (uint8_t)val;
3572 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ODR,
3573 (uint8_t *)&fsm_odr_reg, 1);
3574 }
3575
3576 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3577
3578 return ret;
3579 }
3580
3581 /**
3582 * @brief Finite State Machine ODR configuration.[get]
3583 *
3584 * @param ctx Read / write interface definitions.(ptr)
3585 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3586 * @retval Interface status (MANDATORY: return 0 -> no Error).
3587 *
3588 */
lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t * ctx,lis2duxs12_fsm_val_odr_t * val)3589 int32_t lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t *ctx,
3590 lis2duxs12_fsm_val_odr_t *val)
3591 {
3592 lis2duxs12_fsm_odr_t fsm_odr_reg;
3593 int32_t ret;
3594
3595 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3596 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1);
3597 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3598
3599 switch (fsm_odr_reg.fsm_odr)
3600 {
3601 case 0:
3602 *val = LIS2DUXS12_ODR_FSM_12Hz5;
3603 break;
3604
3605 case 1:
3606 *val = LIS2DUXS12_ODR_FSM_25Hz;
3607 break;
3608
3609 case 2:
3610 *val = LIS2DUXS12_ODR_FSM_50Hz;
3611 break;
3612
3613 case 3:
3614 *val = LIS2DUXS12_ODR_FSM_100Hz;
3615 break;
3616
3617 case 4:
3618 *val = LIS2DUXS12_ODR_FSM_200Hz;
3619 break;
3620
3621 case 5:
3622 *val = LIS2DUXS12_ODR_FSM_400Hz;
3623 break;
3624
3625 case 6:
3626 *val = LIS2DUXS12_ODR_FSM_800Hz;
3627 break;
3628
3629 default:
3630 *val = LIS2DUXS12_ODR_FSM_12Hz5;
3631 break;
3632 }
3633
3634 return ret;
3635 }
3636
3637 /**
3638 * @brief FSM initialization request.[set]
3639 *
3640 * @param ctx Read / write interface definitions.(ptr)
3641 * @param val Change the values of fsm_init in reg FSM_INIT
3642 * @retval Interface status (MANDATORY: return 0 -> no Error).
3643 *
3644 */
lis2duxs12_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)3645 int32_t lis2duxs12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
3646 {
3647 lis2duxs12_emb_func_init_b_t emb_func_init_b;
3648 int32_t ret;
3649
3650 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3651
3652 if (ret == 0)
3653 {
3654 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3655 (uint8_t *)&emb_func_init_b, 1);
3656
3657 emb_func_init_b.fsm_init = (uint8_t)val;
3658
3659 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3660 (uint8_t *)&emb_func_init_b, 1);
3661 }
3662
3663 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3664
3665 return ret;
3666 }
3667
3668 /**
3669 * @brief FSM initialization request.[get]
3670 *
3671 * @param ctx Read / write interface definitions.(ptr)
3672 * @param val Change the values of fsm_init in reg FSM_INIT
3673 * @retval Interface status (MANDATORY: return 0 -> no Error).
3674 *
3675 */
lis2duxs12_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)3676 int32_t lis2duxs12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
3677 {
3678 lis2duxs12_emb_func_init_b_t emb_func_init_b;
3679 int32_t ret;
3680
3681 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3682
3683 if (ret == 0)
3684 {
3685 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B,
3686 (uint8_t *)&emb_func_init_b, 1);
3687
3688 *val = emb_func_init_b.fsm_init;
3689 }
3690
3691 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3692
3693 return ret;
3694 }
3695
3696 /**
3697 * @brief FSM FIFO en bit.[set]
3698 *
3699 * @param ctx Read / write interface definitions.(ptr)
3700 * @param val Change the value of fsm_fifo_en in reg LIS2DUXS12_EMB_FUNC_FIFO_EN
3701 * @retval Interface status (MANDATORY: return 0 -> no Error).
3702 *
3703 */
lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)3704 int32_t lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3705 {
3706 lis2duxs12_emb_func_fifo_en_t fifo_reg;
3707 int32_t ret;
3708
3709 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3710
3711 if (ret == 0)
3712 {
3713 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3714 fifo_reg.fsm_fifo_en = val;
3715 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3716 }
3717
3718 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3719
3720 return ret;
3721 }
3722
3723 /**
3724 * @brief FSM FIFO en bit.[get]
3725 *
3726 * @param ctx Read / write interface definitions.(ptr)
3727 * @param val Get the value of fsm_fifo_en in reg LIS2DUXS12_EMB_FUNC_FIFO_EN
3728 * @retval Interface status (MANDATORY: return 0 -> no Error).
3729 *
3730 */
lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3731 int32_t lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3732 {
3733 lis2duxs12_emb_func_fifo_en_t fifo_reg;
3734 int32_t ret;
3735
3736 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3737
3738 if (ret == 0)
3739 {
3740 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3741 *val = fifo_reg.fsm_fifo_en;
3742 }
3743
3744 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3745
3746 return ret;
3747 }
3748
3749 /**
3750 * @brief FSM long counter timeout register (r/w). The long counter
3751 * timeout value is an unsigned integer value (16-bit format).
3752 * When the long counter value reached this value, the FSM
3753 * generates an interrupt.[set]
3754 *
3755 * @param ctx Read / write interface definitions.(ptr)
3756 * @param buff Buffer that contains data to write
3757 * @retval Interface status (MANDATORY: return 0 -> no Error).
3758 *
3759 */
lis2duxs12_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)3760 int32_t lis2duxs12_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
3761 uint16_t val)
3762 {
3763 uint8_t buff[2];
3764 int32_t ret;
3765
3766 buff[1] = (uint8_t)(val / 256U);
3767 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3768 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2);
3769
3770 return ret;
3771 }
3772
3773 /**
3774 * @brief FSM long counter timeout register (r/w). The long counter
3775 * timeout value is an unsigned integer value (16-bit format).
3776 * When the long counter value reached this value, the FSM generates
3777 * an interrupt.[get]
3778 *
3779 * @param ctx Read / write interface definitions.(ptr)
3780 * @param buff Buffer that stores data read
3781 * @retval Interface status (MANDATORY: return 0 -> no Error).
3782 *
3783 */
lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)3784 int32_t lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
3785 uint16_t *val)
3786 {
3787 uint8_t buff[2];
3788 int32_t ret;
3789
3790 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2);
3791 *val = buff[1];
3792 *val = (*val * 256U) + buff[0];
3793
3794 return ret;
3795 }
3796
3797 /**
3798 * @brief FSM number of programs register.[set]
3799 *
3800 * @param ctx Read / write interface definitions.(ptr)
3801 * @param val Buffer that contains data to write
3802 * @retval Interface status (MANDATORY: return 0 -> no Error).
3803 *
3804 */
lis2duxs12_fsm_programs_num_set(const stmdev_ctx_t * ctx,uint8_t val)3805 int32_t lis2duxs12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val)
3806 {
3807 int32_t ret;
3808
3809 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_PROGRAMS, &val, 1);
3810
3811 return ret;
3812 }
3813
3814 /**
3815 * @brief FSM number of programs register.[get]
3816 *
3817 * @param ctx Read / write interface definitions.(ptr)
3818 * @param val Buffer that stores data read
3819 * @retval Interface status (MANDATORY: return 0 -> no Error).
3820 *
3821 */
lis2duxs12_fsm_programs_num_get(const stmdev_ctx_t * ctx,uint8_t * val)3822 int32_t lis2duxs12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val)
3823 {
3824 int32_t ret;
3825
3826 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_PROGRAMS, val, 1);
3827
3828 return ret;
3829 }
3830
3831 /**
3832 * @brief FSM start address register (r/w). First available address is
3833 * 0x033C.[set]
3834 *
3835 * @param ctx Read / write interface definitions.(ptr)
3836 * @param buff Buffer that contains data to write
3837 * @retval Interface status (MANDATORY: return 0 -> no Error).
3838 *
3839 */
lis2duxs12_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)3840 int32_t lis2duxs12_fsm_start_address_set(const stmdev_ctx_t *ctx,
3841 uint16_t val)
3842 {
3843 uint8_t buff[2];
3844 int32_t ret;
3845
3846 buff[1] = (uint8_t)(val / 256U);
3847 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3848 ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2);
3849
3850 return ret;
3851 }
3852
3853 /**
3854 * @brief FSM start address register (r/w). First available address
3855 * is 0x033C.[get]
3856 *
3857 * @param ctx Read / write interface definitions.(ptr)
3858 * @param buff Buffer that stores data read
3859 * @retval Interface status (MANDATORY: return 0 -> no Error).
3860 *
3861 */
lis2duxs12_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)3862 int32_t lis2duxs12_fsm_start_address_get(const stmdev_ctx_t *ctx,
3863 uint16_t *val)
3864 {
3865 uint8_t buff[2];
3866 int32_t ret;
3867
3868 ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2);
3869 *val = buff[1];
3870 *val = (*val * 256U) + buff[0];
3871
3872 return ret;
3873 }
3874
3875 /**
3876 * @}
3877 *
3878 */
3879
3880 /**
3881 * @addtogroup Machine Learning Core
3882 * @brief This section group all the functions concerning the
3883 * usage of Machine Learning Core
3884 * @{
3885 *
3886 */
3887
3888 /**
3889 * @brief Enable Machine Learning Core.[set]
3890 *
3891 * @param ctx read / write interface definitions
3892 * @param val change the values of mlc_en in
3893 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3894 * in EMB_FUNC_INIT_A
3895 *
3896 */
lis2duxs12_mlc_set(const stmdev_ctx_t * ctx,lis2duxs12_mlc_mode_t val)3897 int32_t lis2duxs12_mlc_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val)
3898 {
3899 lis2duxs12_emb_func_en_a_t emb_en_a;
3900 lis2duxs12_emb_func_en_b_t emb_en_b;
3901 int32_t ret;
3902
3903 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3904
3905 if (ret == 0)
3906 {
3907 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3908 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3909
3910 switch (val)
3911 {
3912 case LIS2DUXS12_MLC_OFF:
3913 emb_en_a.mlc_before_fsm_en = 0;
3914 emb_en_b.mlc_en = 0;
3915 break;
3916 case LIS2DUXS12_MLC_ON:
3917 emb_en_a.mlc_before_fsm_en = 0;
3918 emb_en_b.mlc_en = 1;
3919 break;
3920 case LIS2DUXS12_MLC_ON_BEFORE_FSM:
3921 emb_en_a.mlc_before_fsm_en = 1;
3922 emb_en_b.mlc_en = 0;
3923 break;
3924 default:
3925 /* do nothing */
3926 break;
3927 }
3928
3929 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3930 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3931 }
3932
3933 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3934
3935 return ret;
3936 }
3937
3938 /**
3939 * @brief Enable Machine Learning Core.[get]
3940 *
3941 * @param ctx read / write interface definitions
3942 * @param val get the values of mlc_en in
3943 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3944 * in EMB_FUNC_INIT_A
3945 *
3946 */
lis2duxs12_mlc_get(const stmdev_ctx_t * ctx,lis2duxs12_mlc_mode_t * val)3947 int32_t lis2duxs12_mlc_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val)
3948 {
3949 lis2duxs12_emb_func_en_a_t emb_en_a;
3950 lis2duxs12_emb_func_en_b_t emb_en_b;
3951 int32_t ret;
3952
3953 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
3954
3955 if (ret == 0)
3956 {
3957 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3958 ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3959
3960 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
3961 {
3962 *val = LIS2DUXS12_MLC_OFF;
3963 }
3964 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
3965 {
3966 *val = LIS2DUXS12_MLC_ON;
3967 }
3968 else if (emb_en_a.mlc_before_fsm_en == 1U)
3969 {
3970 *val = LIS2DUXS12_MLC_ON_BEFORE_FSM;
3971 }
3972 else
3973 {
3974 /* Do nothing */
3975 }
3976 }
3977
3978 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
3979
3980 return ret;
3981 }
3982
3983 /**
3984 * @brief Machine Learning Core status register[get]
3985 *
3986 * @param ctx read / write interface definitions
3987 * @param val register MLC_STATUS_MAINPAGE
3988 *
3989 */
lis2duxs12_mlc_status_get(const stmdev_ctx_t * ctx,lis2duxs12_mlc_status_mainpage_t * val)3990 int32_t lis2duxs12_mlc_status_get(const stmdev_ctx_t *ctx,
3991 lis2duxs12_mlc_status_mainpage_t *val)
3992 {
3993 return lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_STATUS_MAINPAGE,
3994 (uint8_t *) val, 1);
3995 }
3996
3997 /**
3998 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
3999 *
4000 * @param ctx_t *ctx: read / write interface definitions
4001 * @param uint8_t * : buffer that stores data read
4002 *
4003 */
lis2duxs12_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)4004 int32_t lis2duxs12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
4005 {
4006 int32_t ret;
4007
4008 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
4009
4010 if (ret == 0)
4011 {
4012 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC1_SRC, buff, 4);
4013 }
4014
4015 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
4016
4017 return ret;
4018 }
4019
4020 /**
4021 * @brief Machine Learning Core data rate selection.[set]
4022 *
4023 * @param ctx read / write interface definitions
4024 * @param val get the values of mlc_odr in
4025 * reg EMB_FUNC_ODR_CFG_C
4026 *
4027 */
lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t * ctx,lis2duxs12_mlc_odr_val_t val)4028 int32_t lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t *ctx,
4029 lis2duxs12_mlc_odr_val_t val)
4030 {
4031 lis2duxs12_mlc_odr_t reg;
4032 int32_t ret;
4033
4034 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
4035
4036 if (ret == 0)
4037 {
4038 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
4039 reg.mlc_odr = (uint8_t)val;
4040 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
4041 }
4042
4043 if (ret == 0)
4044 {
4045 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
4046 }
4047
4048 return ret;
4049 }
4050
4051 /**
4052 * @brief Machine Learning Core data rate selection.[get]
4053 *
4054 * @param ctx read / write interface definitions
4055 * @param val change the values of mlc_odr in
4056 * reg EMB_FUNC_ODR_CFG_C
4057 *
4058 */
lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t * ctx,lis2duxs12_mlc_odr_val_t * val)4059 int32_t lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t *ctx,
4060 lis2duxs12_mlc_odr_val_t *val)
4061 {
4062 lis2duxs12_mlc_odr_t reg;
4063 int32_t ret;
4064
4065 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
4066
4067 if (ret == 0)
4068 {
4069 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1);
4070
4071 switch (reg.mlc_odr)
4072 {
4073 case 0:
4074 *val = LIS2DUXS12_ODR_PRGS_12Hz5;
4075 break;
4076
4077 case 1:
4078 *val = LIS2DUXS12_ODR_PRGS_25Hz;
4079 break;
4080
4081 case 2:
4082 *val = LIS2DUXS12_ODR_PRGS_50Hz;
4083 break;
4084
4085 case 3:
4086 *val = LIS2DUXS12_ODR_PRGS_100Hz;
4087 break;
4088
4089 case 4:
4090 *val = LIS2DUXS12_ODR_PRGS_200Hz;
4091 break;
4092
4093 default:
4094 *val = LIS2DUXS12_ODR_PRGS_12Hz5;
4095 break;
4096 }
4097 }
4098
4099 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
4100
4101 return ret;
4102 }
4103
4104 /**
4105 * @brief MLC FIFO en bit.[set]
4106 *
4107 * @param ctx Read / write interface definitions.(ptr)
4108 * @param val Change the value of mlc_fifo_en in reg LIS2DUXS12_EMB_FUNC_FIFO_EN
4109 * @retval Interface status (MANDATORY: return 0 -> no Error).
4110 *
4111 */
lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)4112 int32_t lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
4113 {
4114 lis2duxs12_emb_func_fifo_en_t fifo_reg;
4115 int32_t ret;
4116
4117 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
4118
4119 if (ret == 0)
4120 {
4121 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
4122 fifo_reg.mlc_fifo_en = val;
4123 ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
4124 }
4125
4126 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
4127
4128 return ret;
4129 }
4130
4131 /**
4132 * @brief MLC FIFO en bit.[get]
4133 *
4134 * @param ctx Read / write interface definitions.(ptr)
4135 * @param val Get the value of mlc_fifo_en in reg LIS2DUXS12_EMB_FUNC_FIFO_EN
4136 * @retval Interface status (MANDATORY: return 0 -> no Error).
4137 *
4138 */
lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)4139 int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
4140 {
4141 lis2duxs12_emb_func_fifo_en_t fifo_reg;
4142 int32_t ret;
4143
4144 ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
4145
4146 if (ret == 0)
4147 {
4148 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
4149 *val = fifo_reg.mlc_fifo_en;
4150 }
4151
4152 ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
4153
4154 return ret;
4155 }
4156
4157 /**
4158 * @}
4159 *
4160 */
4161
4162 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4163
