1 /**
2 ******************************************************************************
3 * @file lis2dtw12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DTW12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2dtw12_reg.h"
21
22 /**
23 * @defgroup LIS2DTW12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2dtw12 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DTW12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2dtw12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2dtw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis2dtw12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis2dtw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS2DTW12_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lis2dtw12_from_fs2_to_mg(int16_t lsb)103 float_t lis2dtw12_from_fs2_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb) * 0.061f;
106 }
107
lis2dtw12_from_fs4_to_mg(int16_t lsb)108 float_t lis2dtw12_from_fs4_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb) * 0.122f;
111 }
112
lis2dtw12_from_fs8_to_mg(int16_t lsb)113 float_t lis2dtw12_from_fs8_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb) * 0.244f;
116 }
117
lis2dtw12_from_fs16_to_mg(int16_t lsb)118 float_t lis2dtw12_from_fs16_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb) * 0.488f;
121 }
122
lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb)123 float_t lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb)
124 {
125 return ((float_t)lsb) * 0.061f;
126 }
127
lis2dtw12_from_fs4_lp1_to_mg(int16_t lsb)128 float_t lis2dtw12_from_fs4_lp1_to_mg(int16_t lsb)
129 {
130 return ((float_t)lsb) * 0.122f;
131 }
132
lis2dtw12_from_fs8_lp1_to_mg(int16_t lsb)133 float_t lis2dtw12_from_fs8_lp1_to_mg(int16_t lsb)
134 {
135 return ((float_t)lsb) * 0.244f;
136 }
137
lis2dtw12_from_fs16_lp1_to_mg(int16_t lsb)138 float_t lis2dtw12_from_fs16_lp1_to_mg(int16_t lsb)
139 {
140 return ((float_t)lsb) * 0.488f;
141 }
142
lis2dtw12_from_lsb_to_celsius(int16_t lsb)143 float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb)
144 {
145 return (((float_t)lsb / 256.0f) + 25.0f);
146 }
147
148 /**
149 * @}
150 *
151 */
152
153 /**
154 * @defgroup LIS2DTW12_Data_Generation
155 * @brief This section groups all the functions concerning
156 * data generation
157 * @{
158 *
159 */
160
161 /**
162 * @brief Select accelerometer operating modes.[set]
163 *
164 * @param ctx read / write interface definitions
165 * @param val change the values of mode / lp_mode in reg CTRL1
166 * and low_noise in reg CTRL6
167 * @retval interface status (MANDATORY: return 0 -> no Error)
168 *
169 */
lis2dtw12_power_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_mode_t val)170 int32_t lis2dtw12_power_mode_set(const stmdev_ctx_t *ctx,
171 lis2dtw12_mode_t val)
172 {
173 lis2dtw12_ctrl1_t ctrl1;
174 lis2dtw12_ctrl6_t ctrl6;
175 int32_t ret;
176
177 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
178
179 if (ret == 0)
180 {
181 ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
182 ctrl1.lp_mode = (uint8_t) val & 0x03U ;
183 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
184 }
185
186 if (ret == 0)
187 {
188 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
189 }
190
191 if (ret == 0)
192 {
193 ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
194 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
195 }
196
197 return ret;
198 }
199
200 /**
201 * @brief Select accelerometer operating modes.[get]
202 *
203 * @param ctx read / write interface definitions
204 * @param val change the values of mode / lp_mode in reg CTRL1
205 * and low_noise in reg CTRL6
206 * @retval interface status (MANDATORY: return 0 -> no Error)
207 *
208 */
lis2dtw12_power_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_mode_t * val)209 int32_t lis2dtw12_power_mode_get(const stmdev_ctx_t *ctx,
210 lis2dtw12_mode_t *val)
211 {
212 lis2dtw12_ctrl1_t ctrl1;
213 lis2dtw12_ctrl6_t ctrl6;
214 int32_t ret;
215
216 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
217
218 if (ret == 0)
219 {
220 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
221
222 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
223 ctrl1.lp_mode))
224 {
225 case LIS2DTW12_HIGH_PERFORMANCE:
226 *val = LIS2DTW12_HIGH_PERFORMANCE;
227 break;
228
229 case LIS2DTW12_CONT_LOW_PWR_4:
230 *val = LIS2DTW12_CONT_LOW_PWR_4;
231 break;
232
233 case LIS2DTW12_CONT_LOW_PWR_3:
234 *val = LIS2DTW12_CONT_LOW_PWR_3;
235 break;
236
237 case LIS2DTW12_CONT_LOW_PWR_2:
238 *val = LIS2DTW12_CONT_LOW_PWR_2;
239 break;
240
241 case LIS2DTW12_CONT_LOW_PWR_12bit:
242 *val = LIS2DTW12_CONT_LOW_PWR_12bit;
243 break;
244
245 case LIS2DTW12_SINGLE_LOW_PWR_4:
246 *val = LIS2DTW12_SINGLE_LOW_PWR_4;
247 break;
248
249 case LIS2DTW12_SINGLE_LOW_PWR_3:
250 *val = LIS2DTW12_SINGLE_LOW_PWR_3;
251 break;
252
253 case LIS2DTW12_SINGLE_LOW_PWR_2:
254 *val = LIS2DTW12_SINGLE_LOW_PWR_2;
255 break;
256
257 case LIS2DTW12_SINGLE_LOW_PWR_12bit:
258 *val = LIS2DTW12_SINGLE_LOW_PWR_12bit;
259 break;
260
261 case LIS2DTW12_HIGH_PERFORMANCE_LOW_NOISE:
262 *val = LIS2DTW12_HIGH_PERFORMANCE_LOW_NOISE;
263 break;
264
265 case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_4:
266 *val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_4;
267 break;
268
269 case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_3:
270 *val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_3;
271 break;
272
273 case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_2:
274 *val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_2;
275 break;
276
277 case LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_12bit:
278 *val = LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_12bit;
279 break;
280
281 case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_4:
282 *val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_4;
283 break;
284
285 case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_3:
286 *val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_3;
287 break;
288
289 case LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2:
290 *val = LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2;
291 break;
292
293 case LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
294 *val = LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
295 break;
296
297 default:
298 *val = LIS2DTW12_HIGH_PERFORMANCE;
299 break;
300 }
301 }
302
303 return ret;
304 }
305
306 /**
307 * @brief Accelerometer data rate selection.[set]
308 *
309 * @param ctx read / write interface definitions
310 * @param val change the values of odr in reg CTRL1
311 * @retval interface status (MANDATORY: return 0 -> no Error)
312 *
313 */
lis2dtw12_data_rate_set(const stmdev_ctx_t * ctx,lis2dtw12_odr_t val)314 int32_t lis2dtw12_data_rate_set(const stmdev_ctx_t *ctx,
315 lis2dtw12_odr_t val)
316 {
317 lis2dtw12_ctrl1_t ctrl1;
318 lis2dtw12_ctrl3_t ctrl3;
319 int32_t ret;
320
321 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
322
323 if (ret == 0)
324 {
325 ctrl1.odr = (uint8_t) val;
326 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
327 }
328
329 if (ret == 0)
330 {
331 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
332 }
333
334 if (ret == 0)
335 {
336 ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
337 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
338 }
339
340 return ret;
341 }
342
343 /**
344 * @brief Accelerometer data rate selection.[get]
345 *
346 * @param ctx read / write interface definitions
347 * @param val Get the values of odr in reg CTRL1
348 * @retval interface status (MANDATORY: return 0 -> no Error)
349 *
350 */
lis2dtw12_data_rate_get(const stmdev_ctx_t * ctx,lis2dtw12_odr_t * val)351 int32_t lis2dtw12_data_rate_get(const stmdev_ctx_t *ctx,
352 lis2dtw12_odr_t *val)
353 {
354 lis2dtw12_ctrl1_t ctrl1;
355 lis2dtw12_ctrl3_t ctrl3;
356 int32_t ret;
357
358 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1);
359
360 if (ret == 0)
361 {
362 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1);
363
364 switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
365 {
366 case LIS2DTW12_XL_ODR_OFF:
367 *val = LIS2DTW12_XL_ODR_OFF;
368 break;
369
370 case LIS2DTW12_XL_ODR_1Hz6_LP_ONLY:
371 *val = LIS2DTW12_XL_ODR_1Hz6_LP_ONLY;
372 break;
373
374 case LIS2DTW12_XL_ODR_12Hz5:
375 *val = LIS2DTW12_XL_ODR_12Hz5;
376 break;
377
378 case LIS2DTW12_XL_ODR_25Hz:
379 *val = LIS2DTW12_XL_ODR_25Hz;
380 break;
381
382 case LIS2DTW12_XL_ODR_50Hz:
383 *val = LIS2DTW12_XL_ODR_50Hz;
384 break;
385
386 case LIS2DTW12_XL_ODR_100Hz:
387 *val = LIS2DTW12_XL_ODR_100Hz;
388 break;
389
390 case LIS2DTW12_XL_ODR_200Hz:
391 *val = LIS2DTW12_XL_ODR_200Hz;
392 break;
393
394 case LIS2DTW12_XL_ODR_400Hz:
395 *val = LIS2DTW12_XL_ODR_400Hz;
396 break;
397
398 case LIS2DTW12_XL_ODR_800Hz:
399 *val = LIS2DTW12_XL_ODR_800Hz;
400 break;
401
402 case LIS2DTW12_XL_ODR_1k6Hz:
403 *val = LIS2DTW12_XL_ODR_1k6Hz;
404 break;
405
406 case LIS2DTW12_XL_SET_SW_TRIG:
407 *val = LIS2DTW12_XL_SET_SW_TRIG;
408 break;
409
410 case LIS2DTW12_XL_SET_PIN_TRIG:
411 *val = LIS2DTW12_XL_SET_PIN_TRIG;
412 break;
413
414 default:
415 *val = LIS2DTW12_XL_ODR_OFF;
416 break;
417 }
418 }
419
420 return ret;
421 }
422
423 /**
424 * @brief Block data update.[set]
425 *
426 * @param ctx read / write interface definitions
427 * @param val change the values of bdu in reg CTRL2
428 * @retval interface status (MANDATORY: return 0 -> no Error)
429 *
430 */
lis2dtw12_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)431 int32_t lis2dtw12_block_data_update_set(const stmdev_ctx_t *ctx,
432 uint8_t val)
433 {
434 lis2dtw12_ctrl2_t reg;
435 int32_t ret;
436
437 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
438
439 if (ret == 0)
440 {
441 reg.bdu = val;
442 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
443 }
444
445 return ret;
446 }
447
448 /**
449 * @brief Block data update.[get]
450 *
451 * @param ctx read / write interface definitions
452 * @param val change the values of bdu in reg CTRL2
453 * @retval interface status (MANDATORY: return 0 -> no Error)
454 *
455 */
lis2dtw12_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)456 int32_t lis2dtw12_block_data_update_get(const stmdev_ctx_t *ctx,
457 uint8_t *val)
458 {
459 lis2dtw12_ctrl2_t reg;
460 int32_t ret;
461
462 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
463 *val = reg.bdu;
464
465 return ret;
466 }
467
468 /**
469 * @brief Accelerometer full-scale selection.[set]
470 *
471 * @param ctx read / write interface definitions
472 * @param val change the values of fs in reg CTRL6
473 * @retval interface status (MANDATORY: return 0 -> no Error)
474 *
475 */
lis2dtw12_full_scale_set(const stmdev_ctx_t * ctx,lis2dtw12_fs_t val)476 int32_t lis2dtw12_full_scale_set(const stmdev_ctx_t *ctx,
477 lis2dtw12_fs_t val)
478 {
479 lis2dtw12_ctrl6_t reg;
480 int32_t ret;
481
482 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
483
484 if (ret == 0)
485 {
486 reg.fs = (uint8_t) val;
487 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
488 }
489
490 return ret;
491 }
492
493 /**
494 * @brief Accelerometer full-scale selection.[get]
495 *
496 * @param ctx read / write interface definitions
497 * @param val Get the values of fs in reg CTRL6
498 * @retval interface status (MANDATORY: return 0 -> no Error)
499 *
500 */
lis2dtw12_full_scale_get(const stmdev_ctx_t * ctx,lis2dtw12_fs_t * val)501 int32_t lis2dtw12_full_scale_get(const stmdev_ctx_t *ctx,
502 lis2dtw12_fs_t *val)
503 {
504 lis2dtw12_ctrl6_t reg;
505 int32_t ret;
506
507 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
508
509 switch (reg.fs)
510 {
511 case LIS2DTW12_2g:
512 *val = LIS2DTW12_2g;
513 break;
514
515 case LIS2DTW12_4g:
516 *val = LIS2DTW12_4g;
517 break;
518
519 case LIS2DTW12_8g:
520 *val = LIS2DTW12_8g;
521 break;
522
523 case LIS2DTW12_16g:
524 *val = LIS2DTW12_16g;
525 break;
526
527 default:
528 *val = LIS2DTW12_2g;
529 break;
530 }
531
532 return ret;
533 }
534
535 /**
536 * @brief The STATUS_REG register of the device.[get]
537 *
538 * @param ctx read / write interface definitions
539 * @param val union of registers from STATUS to
540 * @retval interface status (MANDATORY: return 0 -> no Error)
541 *
542 */
lis2dtw12_status_reg_get(const stmdev_ctx_t * ctx,lis2dtw12_status_t * val)543 int32_t lis2dtw12_status_reg_get(const stmdev_ctx_t *ctx,
544 lis2dtw12_status_t *val)
545 {
546 int32_t ret;
547
548 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t *) val, 1);
549
550 return ret;
551 }
552
553 /**
554 * @brief Accelerometer new data available.[get]
555 *
556 * @param ctx read / write interface definitions
557 * @param val change the values of drdy in reg STATUS
558 * @retval interface status (MANDATORY: return 0 -> no Error)
559 *
560 */
lis2dtw12_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)561 int32_t lis2dtw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
562 {
563 lis2dtw12_status_t reg;
564 int32_t ret;
565
566 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t *) ®, 1);
567 *val = reg.drdy;
568
569 return ret;
570 }
571 /**
572 * @brief Read all the interrupt/status flag of the device.[get]
573 *
574 * @param ctx read / write interface definitions
575 * @param val registers STATUS_DUP, WAKE_UP_SRC,
576 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
577 * @retval interface status (MANDATORY: return 0 -> no Error)
578 *
579 */
lis2dtw12_all_sources_get(const stmdev_ctx_t * ctx,lis2dtw12_all_sources_t * val)580 int32_t lis2dtw12_all_sources_get(const stmdev_ctx_t *ctx,
581 lis2dtw12_all_sources_t *val)
582 {
583 int32_t ret;
584
585 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS_DUP, (uint8_t *) val,
586 5);
587
588 return ret;
589 }
590
591 /**
592 * @brief Accelerometer X-axis user offset correction expressed in two’s
593 * complement, weight depends on bit USR_OFF_W. The value must be
594 * in the range [-127 127].[set]
595 *
596 * @param ctx read / write interface definitions
597 * @param buff buffer that contains data to write
598 * @retval interface status (MANDATORY: return 0 -> no Error)
599 *
600 */
lis2dtw12_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)601 int32_t lis2dtw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
602 {
603 int32_t ret;
604
605 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_X_OFS_USR, buff, 1);
606
607 return ret;
608 }
609
610 /**
611 * @brief Accelerometer X-axis user offset correction expressed in two’s
612 * complement, weight depends on bit USR_OFF_W. The value must be
613 * in the range [-127 127].[get]
614 *
615 * @param ctx read / write interface definitions
616 * @param buff buffer that stores data read
617 * @retval interface status (MANDATORY: return 0 -> no Error)
618 *
619 */
lis2dtw12_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)620 int32_t lis2dtw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
621 {
622 int32_t ret;
623
624 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_X_OFS_USR, buff, 1);
625
626 return ret;
627 }
628
629 /**
630 * @brief Accelerometer Y-axis user offset correction expressed in two’s
631 * complement, weight depends on bit USR_OFF_W. The value must be
632 * in the range [-127 127].[set]
633 *
634 * @param ctx read / write interface definitions
635 * @param buff buffer that contains data to write
636 * @retval interface status (MANDATORY: return 0 -> no Error)
637 *
638 */
lis2dtw12_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)639 int32_t lis2dtw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
640 {
641 int32_t ret;
642
643 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_Y_OFS_USR, buff, 1);
644
645 return ret;
646 }
647
648 /**
649 * @brief Accelerometer Y-axis user offset correction expressed in two’s
650 * complement, weight depends on bit USR_OFF_W. The value must be
651 * in the range [-127 127].[get]
652 *
653 * @param ctx read / write interface definitions
654 * @param buff buffer that stores data read
655 * @retval interface status (MANDATORY: return 0 -> no Error)
656 *
657 */
lis2dtw12_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)658 int32_t lis2dtw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
659 {
660 int32_t ret;
661
662 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_Y_OFS_USR, buff, 1);
663
664 return ret;
665 }
666
667 /**
668 * @brief Accelerometer Z-axis user offset correction expressed in two’s
669 * complement, weight depends on bit USR_OFF_W. The value must be
670 * in the range [-127 127].[set]
671 *
672 * @param ctx read / write interface definitions
673 * @param buff buffer that contains data to write
674 * @retval interface status (MANDATORY: return 0 -> no Error)
675 *
676 */
lis2dtw12_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)677 int32_t lis2dtw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
678 {
679 int32_t ret;
680
681 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_Z_OFS_USR, buff, 1);
682
683 return ret;
684 }
685
686 /**
687 * @brief Accelerometer Z-axis user offset correction expressed in two’s
688 * complement, weight depends on bit USR_OFF_W. The value must be
689 * in the range [-127 127].[get]
690 *
691 * @param ctx read / write interface definitions
692 * @param buff buffer that stores data read
693 * @retval interface status (MANDATORY: return 0 -> no Error)
694 *
695 */
lis2dtw12_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)696 int32_t lis2dtw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
697 {
698 int32_t ret;
699
700 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_Z_OFS_USR, buff, 1);
701
702 return ret;
703 }
704
705 /**
706 * @brief Weight of XL user offset bits of registers X_OFS_USR,
707 * Y_OFS_USR, Z_OFS_USR.[set]
708 *
709 * @param ctx read / write interface definitions
710 * @param val change the values of usr_off_w in
711 * reg CTRL_REG7
712 * @retval interface status (MANDATORY: return 0 -> no Error)
713 *
714 */
lis2dtw12_offset_weight_set(const stmdev_ctx_t * ctx,lis2dtw12_usr_off_w_t val)715 int32_t lis2dtw12_offset_weight_set(const stmdev_ctx_t *ctx,
716 lis2dtw12_usr_off_w_t val)
717 {
718 lis2dtw12_ctrl_reg7_t reg;
719 int32_t ret;
720
721 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
722
723 if (ret == 0)
724 {
725 reg.usr_off_w = (uint8_t) val;
726 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
727 }
728
729 return ret;
730 }
731
732 /**
733 * @brief Weight of XL user offset bits of registers X_OFS_USR,
734 * Y_OFS_USR, Z_OFS_USR.[get]
735 *
736 * @param ctx read / write interface definitions
737 * @param val Get the values of usr_off_w in reg CTRL_REG7
738 * @retval interface status (MANDATORY: return 0 -> no Error)
739 *
740 */
lis2dtw12_offset_weight_get(const stmdev_ctx_t * ctx,lis2dtw12_usr_off_w_t * val)741 int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx,
742 lis2dtw12_usr_off_w_t *val)
743 {
744 lis2dtw12_ctrl_reg7_t reg;
745 int32_t ret;
746
747 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
748
749 switch (reg.usr_off_w)
750 {
751 case LIS2DTW12_LSb_977ug:
752 *val = LIS2DTW12_LSb_977ug;
753 break;
754
755 case LIS2DTW12_LSb_15mg6:
756 *val = LIS2DTW12_LSb_15mg6;
757 break;
758
759 default:
760 *val = LIS2DTW12_LSb_977ug;
761 break;
762 }
763
764 return ret;
765 }
766
767 /**
768 * @}
769 *
770 */
771
772 /**
773 * @defgroup LIS2DTW12_Data_Output
774 * @brief This section groups all the data output functions.
775 * @{
776 *
777 */
778
779 /**
780 * @brief Temperature data output register (r). L and H registers
781 * together express a 16-bit word in two’s complement.[get]
782 *
783 * @param ctx read / write interface definitions
784 * @param buff buffer that stores data read
785 * @retval interface status (MANDATORY: return 0 -> no Error)
786 *
787 */
lis2dtw12_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)788 int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
789 {
790 uint8_t buff[2];
791 int32_t ret;
792
793 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_T_L, buff, 2);
794 *val = (int16_t)buff[1];
795 *val = (*val * 256) + (int16_t)buff[0];
796
797 return ret;
798 }
799
800 /**
801 * @brief Linear acceleration output register. The value is expressed as
802 * a 16-bit word in two’s complement.[get]
803 *
804 * @param ctx read / write interface definitions
805 * @param buff buffer that stores data read
806 * @retval interface status (MANDATORY: return 0 -> no Error)
807 *
808 */
lis2dtw12_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)809 int32_t lis2dtw12_acceleration_raw_get(const stmdev_ctx_t *ctx,
810 int16_t *val)
811 {
812 uint8_t buff[6];
813 int32_t ret;
814
815 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_X_L, buff, 6);
816 val[0] = (int16_t)buff[1];
817 val[0] = (val[0] * 256) + (int16_t)buff[0];
818 val[1] = (int16_t)buff[3];
819 val[1] = (val[1] * 256) + (int16_t)buff[2];
820 val[2] = (int16_t)buff[5];
821 val[2] = (val[2] * 256) + (int16_t)buff[4];
822
823 return ret;
824 }
825
826 /**
827 * @}
828 *
829 */
830
831 /**
832 * @defgroup LIS2DTW12_Common
833 * @brief This section groups common useful functions.
834 * @{
835 *
836 */
837
838 /**
839 * @brief Device Who am I.[get]
840 *
841 * @param ctx read / write interface definitions
842 * @param buff buffer that stores data read
843 * @retval interface status (MANDATORY: return 0 -> no Error)
844 *
845 */
lis2dtw12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)846 int32_t lis2dtw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
847 {
848 int32_t ret;
849
850 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WHO_AM_I, buff, 1);
851
852 return ret;
853 }
854
855 /**
856 * @brief Register address automatically incremented during multiple byte
857 * access with a serial interface.[set]
858 *
859 * @param ctx read / write interface definitions
860 * @param val change the values of if_add_inc in reg CTRL2
861 * @retval interface status (MANDATORY: return 0 -> no Error)
862 *
863 */
lis2dtw12_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)864 int32_t lis2dtw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
865 {
866 lis2dtw12_ctrl2_t reg;
867 int32_t ret;
868
869 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
870
871 if (ret == 0)
872 {
873 reg.if_add_inc = val;
874 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
875 }
876
877 return ret;
878 }
879
880 /**
881 * @brief Register address automatically incremented during multiple
882 * byte access with a serial interface.[get]
883 *
884 * @param ctx read / write interface definitions
885 * @param val change the values of if_add_inc in reg CTRL2
886 * @retval interface status (MANDATORY: return 0 -> no Error)
887 *
888 */
lis2dtw12_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)889 int32_t lis2dtw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
890 {
891 lis2dtw12_ctrl2_t reg;
892 int32_t ret;
893
894 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
895 *val = reg.if_add_inc;
896
897 return ret;
898 }
899
900 /**
901 * @brief Software reset. Restore the default values in user registers.[set]
902 *
903 * @param ctx read / write interface definitions
904 * @param val change the values of soft_reset in reg CTRL2
905 * @retval interface status (MANDATORY: return 0 -> no Error)
906 *
907 */
lis2dtw12_reset_set(const stmdev_ctx_t * ctx,uint8_t val)908 int32_t lis2dtw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
909 {
910 lis2dtw12_ctrl2_t reg;
911 int32_t ret;
912
913 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
914
915 if (ret == 0)
916 {
917 reg.soft_reset = val;
918 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
919 }
920
921 return ret;
922 }
923
924 /**
925 * @brief Software reset. Restore the default values in user registers.[get]
926 *
927 * @param ctx read / write interface definitions
928 * @param val change the values of soft_reset in reg CTRL2
929 * @retval interface status (MANDATORY: return 0 -> no Error)
930 *
931 */
lis2dtw12_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)932 int32_t lis2dtw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
933 {
934 lis2dtw12_ctrl2_t reg;
935 int32_t ret;
936
937 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
938 *val = reg.soft_reset;
939
940 return ret;
941 }
942
943 /**
944 * @brief Reboot memory content. Reload the calibration parameters.[set]
945 *
946 * @param ctx read / write interface definitions
947 * @param val change the values of boot in reg CTRL2
948 * @retval interface status (MANDATORY: return 0 -> no Error)
949 *
950 */
lis2dtw12_boot_set(const stmdev_ctx_t * ctx,uint8_t val)951 int32_t lis2dtw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
952 {
953 lis2dtw12_ctrl2_t reg;
954 int32_t ret;
955
956 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
957
958 if (ret == 0)
959 {
960 reg.boot = val;
961 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
962 }
963
964 return ret;
965 }
966
967 /**
968 * @brief Reboot memory content. Reload the calibration parameters.[get]
969 *
970 * @param ctx read / write interface definitions
971 * @param val change the values of boot in reg CTRL2
972 * @retval interface status (MANDATORY: return 0 -> no Error)
973 *
974 */
lis2dtw12_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)975 int32_t lis2dtw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
976 {
977 lis2dtw12_ctrl2_t reg;
978 int32_t ret;
979
980 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
981 *val = reg.boot;
982
983 return ret;
984 }
985
986 /**
987 * @brief Sensor self-test enable.[set]
988 *
989 * @param ctx read / write interface definitions
990 * @param val change the values of st in reg CTRL3
991 * @retval interface status (MANDATORY: return 0 -> no Error)
992 *
993 */
lis2dtw12_self_test_set(const stmdev_ctx_t * ctx,lis2dtw12_st_t val)994 int32_t lis2dtw12_self_test_set(const stmdev_ctx_t *ctx, lis2dtw12_st_t val)
995 {
996 lis2dtw12_ctrl3_t reg;
997 int32_t ret;
998
999 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1000
1001 if (ret == 0)
1002 {
1003 reg.st = (uint8_t) val;
1004 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1005 }
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Sensor self-test enable.[get]
1012 *
1013 * @param ctx read / write interface definitions
1014 * @param val Get the values of st in reg CTRL3
1015 * @retval interface status (MANDATORY: return 0 -> no Error)
1016 *
1017 */
lis2dtw12_self_test_get(const stmdev_ctx_t * ctx,lis2dtw12_st_t * val)1018 int32_t lis2dtw12_self_test_get(const stmdev_ctx_t *ctx,
1019 lis2dtw12_st_t *val)
1020 {
1021 lis2dtw12_ctrl3_t reg;
1022 int32_t ret;
1023
1024 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1025
1026 switch (reg.st)
1027 {
1028 case LIS2DTW12_XL_ST_DISABLE:
1029 *val = LIS2DTW12_XL_ST_DISABLE;
1030 break;
1031
1032 case LIS2DTW12_XL_ST_POSITIVE:
1033 *val = LIS2DTW12_XL_ST_POSITIVE;
1034 break;
1035
1036 case LIS2DTW12_XL_ST_NEGATIVE:
1037 *val = LIS2DTW12_XL_ST_NEGATIVE;
1038 break;
1039
1040 default:
1041 *val = LIS2DTW12_XL_ST_DISABLE;
1042 break;
1043 }
1044
1045 return ret;
1046 }
1047
1048 /**
1049 * @brief Data-ready pulsed / letched mode.[set]
1050 *
1051 * @param ctx read / write interface definitions
1052 * @param val change the values of drdy_pulsed in reg CTRL_REG7
1053 * @retval interface status (MANDATORY: return 0 -> no Error)
1054 *
1055 */
lis2dtw12_data_ready_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_drdy_pulsed_t val)1056 int32_t lis2dtw12_data_ready_mode_set(const stmdev_ctx_t *ctx,
1057 lis2dtw12_drdy_pulsed_t val)
1058 {
1059 lis2dtw12_ctrl_reg7_t reg;
1060 int32_t ret;
1061
1062 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1063
1064 if (ret == 0)
1065 {
1066 reg.drdy_pulsed = (uint8_t) val;
1067 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1068 }
1069
1070 return ret;
1071 }
1072
1073 /**
1074 * @brief Data-ready pulsed / letched mode.[get]
1075 *
1076 * @param ctx read / write interface definitions
1077 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
1078 * @retval interface status (MANDATORY: return 0 -> no Error)
1079 *
1080 */
lis2dtw12_data_ready_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_drdy_pulsed_t * val)1081 int32_t lis2dtw12_data_ready_mode_get(const stmdev_ctx_t *ctx,
1082 lis2dtw12_drdy_pulsed_t *val)
1083 {
1084 lis2dtw12_ctrl_reg7_t reg;
1085 int32_t ret;
1086
1087 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1088
1089 switch (reg.drdy_pulsed)
1090 {
1091 case LIS2DTW12_DRDY_LATCHED:
1092 *val = LIS2DTW12_DRDY_LATCHED;
1093 break;
1094
1095 case LIS2DTW12_DRDY_PULSED:
1096 *val = LIS2DTW12_DRDY_PULSED;
1097 break;
1098
1099 default:
1100 *val = LIS2DTW12_DRDY_LATCHED;
1101 break;
1102 }
1103
1104 return ret;
1105 }
1106
1107 /**
1108 * @}
1109 *
1110 */
1111
1112 /**
1113 * @defgroup LIS2DTW12_Filters
1114 * @brief This section group all the functions concerning the filters
1115 * configuration.
1116 * @{
1117 *
1118 */
1119
1120 /**
1121 * @brief Accelerometer filtering path for outputs.[set]
1122 *
1123 * @param ctx read / write interface definitions
1124 * @param val change the values of fds in reg CTRL6
1125 * @retval interface status (MANDATORY: return 0 -> no Error)
1126 *
1127 */
lis2dtw12_filter_path_set(const stmdev_ctx_t * ctx,lis2dtw12_fds_t val)1128 int32_t lis2dtw12_filter_path_set(const stmdev_ctx_t *ctx,
1129 lis2dtw12_fds_t val)
1130 {
1131 lis2dtw12_ctrl6_t ctrl6;
1132 lis2dtw12_ctrl_reg7_t ctrl_reg7;
1133 int32_t ret;
1134
1135 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
1136
1137 if (ret == 0)
1138 {
1139 ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
1140 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
1141 }
1142
1143 if (ret == 0)
1144 {
1145 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,
1146 (uint8_t *) &ctrl_reg7, 1);
1147 }
1148
1149 if (ret == 0)
1150 {
1151 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
1152 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7,
1153 (uint8_t *) &ctrl_reg7, 1);
1154 }
1155
1156 return ret;
1157 }
1158
1159 /**
1160 * @brief Accelerometer filtering path for outputs.[get]
1161 *
1162 * @param ctx read / write interface definitions
1163 * @param val Get the values of fds in reg CTRL6
1164 * @retval interface status (MANDATORY: return 0 -> no Error)
1165 *
1166 */
lis2dtw12_filter_path_get(const stmdev_ctx_t * ctx,lis2dtw12_fds_t * val)1167 int32_t lis2dtw12_filter_path_get(const stmdev_ctx_t *ctx,
1168 lis2dtw12_fds_t *val)
1169 {
1170 lis2dtw12_ctrl6_t ctrl6;
1171 lis2dtw12_ctrl_reg7_t ctrl_reg7;
1172 int32_t ret;
1173
1174 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1);
1175
1176 if (ret == 0)
1177 {
1178 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7,
1179 (uint8_t *) &ctrl_reg7, 1);
1180
1181 switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
1182 {
1183 case LIS2DTW12_LPF_ON_OUT:
1184 *val = LIS2DTW12_LPF_ON_OUT;
1185 break;
1186
1187 case LIS2DTW12_USER_OFFSET_ON_OUT:
1188 *val = LIS2DTW12_USER_OFFSET_ON_OUT;
1189 break;
1190
1191 case LIS2DTW12_HIGH_PASS_ON_OUT:
1192 *val = LIS2DTW12_HIGH_PASS_ON_OUT;
1193 break;
1194
1195 default:
1196 *val = LIS2DTW12_LPF_ON_OUT;
1197 break;
1198 }
1199 }
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Accelerometer cutoff filter frequency. Valid for low and high
1206 * pass filter.[set]
1207 *
1208 * @param ctx read / write interface definitions
1209 * @param val change the values of bw_filt in reg CTRL6
1210 * @retval interface status (MANDATORY: return 0 -> no Error)
1211 *
1212 */
lis2dtw12_filter_bandwidth_set(const stmdev_ctx_t * ctx,lis2dtw12_bw_filt_t val)1213 int32_t lis2dtw12_filter_bandwidth_set(const stmdev_ctx_t *ctx,
1214 lis2dtw12_bw_filt_t val)
1215 {
1216 lis2dtw12_ctrl6_t reg;
1217 int32_t ret;
1218
1219 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
1220
1221 if (ret == 0)
1222 {
1223 reg.bw_filt = (uint8_t) val;
1224 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
1225 }
1226
1227 return ret;
1228 }
1229
1230 /**
1231 * @brief Accelerometer cutoff filter frequency. Valid for low and
1232 * high pass filter.[get]
1233 *
1234 * @param ctx read / write interface definitions
1235 * @param val Get the values of bw_filt in reg CTRL6
1236 * @retval interface status (MANDATORY: return 0 -> no Error)
1237 *
1238 */
lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t * ctx,lis2dtw12_bw_filt_t * val)1239 int32_t lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t *ctx,
1240 lis2dtw12_bw_filt_t *val)
1241 {
1242 lis2dtw12_ctrl6_t reg;
1243 int32_t ret;
1244
1245 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1);
1246
1247 switch (reg.bw_filt)
1248 {
1249 case LIS2DTW12_ODR_DIV_2:
1250 *val = LIS2DTW12_ODR_DIV_2;
1251 break;
1252
1253 case LIS2DTW12_ODR_DIV_4:
1254 *val = LIS2DTW12_ODR_DIV_4;
1255 break;
1256
1257 case LIS2DTW12_ODR_DIV_10:
1258 *val = LIS2DTW12_ODR_DIV_10;
1259 break;
1260
1261 case LIS2DTW12_ODR_DIV_20:
1262 *val = LIS2DTW12_ODR_DIV_20;
1263 break;
1264
1265 default:
1266 *val = LIS2DTW12_ODR_DIV_2;
1267 break;
1268 }
1269
1270 return ret;
1271 }
1272
1273 /**
1274 * @brief Enable HP filter reference mode.[set]
1275 *
1276 * @param ctx read / write interface definitions
1277 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1278 * @retval interface status (MANDATORY: return 0 -> no Error)
1279 *
1280 */
lis2dtw12_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)1281 int32_t lis2dtw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
1282 {
1283 lis2dtw12_ctrl_reg7_t reg;
1284 int32_t ret;
1285
1286 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1287
1288 if (ret == 0)
1289 {
1290 reg.hp_ref_mode = val;
1291 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1292 }
1293
1294 return ret;
1295 }
1296
1297 /**
1298 * @brief Enable HP filter reference mode.[get]
1299 *
1300 * @param ctx read / write interface definitions
1301 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1302 * @retval interface status (MANDATORY: return 0 -> no Error)
1303 *
1304 */
lis2dtw12_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)1305 int32_t lis2dtw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
1306 {
1307 lis2dtw12_ctrl_reg7_t reg;
1308 int32_t ret;
1309
1310 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1311 *val = reg.hp_ref_mode;
1312
1313 return ret;
1314 }
1315
1316 /**
1317 * @}
1318 *
1319 */
1320
1321 /**
1322 * @defgroup LIS2DTW12_Serial_Interface
1323 * @brief This section groups all the functions concerning main serial
1324 * interface management (not auxiliary)
1325 * @{
1326 *
1327 */
1328
1329 /**
1330 * @brief SPI Serial Interface Mode selection.[set]
1331 *
1332 * @param ctx read / write interface definitions
1333 * @param val change the values of sim in reg CTRL2
1334 * @retval interface status (MANDATORY: return 0 -> no Error)
1335 *
1336 */
lis2dtw12_spi_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_sim_t val)1337 int32_t lis2dtw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_sim_t val)
1338 {
1339 lis2dtw12_ctrl2_t reg;
1340 int32_t ret;
1341
1342 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1343
1344 if (ret == 0)
1345 {
1346 reg.sim = (uint8_t) val;
1347 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1348 }
1349
1350 return ret;
1351 }
1352
1353 /**
1354 * @brief SPI Serial Interface Mode selection.[get]
1355 *
1356 * @param ctx read / write interface definitions
1357 * @param val Get the values of sim in reg CTRL2
1358 * @retval interface status (MANDATORY: return 0 -> no Error)
1359 *
1360 */
lis2dtw12_spi_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_sim_t * val)1361 int32_t lis2dtw12_spi_mode_get(const stmdev_ctx_t *ctx,
1362 lis2dtw12_sim_t *val)
1363 {
1364 lis2dtw12_ctrl2_t reg;
1365 int32_t ret;
1366
1367 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1368
1369 switch (reg.sim)
1370 {
1371 case LIS2DTW12_SPI_4_WIRE:
1372 *val = LIS2DTW12_SPI_4_WIRE;
1373 break;
1374
1375 case LIS2DTW12_SPI_3_WIRE:
1376 *val = LIS2DTW12_SPI_3_WIRE;
1377 break;
1378
1379 default:
1380 *val = LIS2DTW12_SPI_4_WIRE;
1381 break;
1382 }
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @brief Disable / Enable I2C interface.[set]
1389 *
1390 * @param ctx read / write interface definitions
1391 * @param val change the values of i2c_disable in
1392 * reg CTRL2
1393 * @retval interface status (MANDATORY: return 0 -> no Error)
1394 *
1395 */
lis2dtw12_i2c_interface_set(const stmdev_ctx_t * ctx,lis2dtw12_i2c_disable_t val)1396 int32_t lis2dtw12_i2c_interface_set(const stmdev_ctx_t *ctx,
1397 lis2dtw12_i2c_disable_t val)
1398 {
1399 lis2dtw12_ctrl2_t reg;
1400 int32_t ret;
1401
1402 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1403
1404 if (ret == 0)
1405 {
1406 reg.i2c_disable = (uint8_t) val;
1407 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1408 }
1409
1410 return ret;
1411 }
1412
1413 /**
1414 * @brief Disable / Enable I2C interface.[get]
1415 *
1416 * @param ctx read / write interface definitions
1417 * @param val Get the values of i2c_disable in reg CTRL2
1418 * @retval interface status (MANDATORY: return 0 -> no Error)
1419 *
1420 */
lis2dtw12_i2c_interface_get(const stmdev_ctx_t * ctx,lis2dtw12_i2c_disable_t * val)1421 int32_t lis2dtw12_i2c_interface_get(const stmdev_ctx_t *ctx,
1422 lis2dtw12_i2c_disable_t *val)
1423 {
1424 lis2dtw12_ctrl2_t reg;
1425 int32_t ret;
1426
1427 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1428
1429 switch (reg.i2c_disable)
1430 {
1431 case LIS2DTW12_I2C_ENABLE:
1432 *val = LIS2DTW12_I2C_ENABLE;
1433 break;
1434
1435 case LIS2DTW12_I2C_DISABLE:
1436 *val = LIS2DTW12_I2C_DISABLE;
1437 break;
1438
1439 default:
1440 *val = LIS2DTW12_I2C_ENABLE;
1441 break;
1442 }
1443
1444 return ret;
1445 }
1446
1447 /**
1448 * @brief Disconnect CS pull-up.[set]
1449 *
1450 * @param ctx read / write interface definitions
1451 * @param val change the values of cs_pu_disc in reg CTRL2
1452 * @retval interface status (MANDATORY: return 0 -> no Error)
1453 *
1454 */
lis2dtw12_cs_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_cs_pu_disc_t val)1455 int32_t lis2dtw12_cs_mode_set(const stmdev_ctx_t *ctx,
1456 lis2dtw12_cs_pu_disc_t val)
1457 {
1458 lis2dtw12_ctrl2_t reg;
1459 int32_t ret;
1460
1461 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1462
1463 if (ret == 0)
1464 {
1465 reg.cs_pu_disc = (uint8_t) val;
1466 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1467 }
1468
1469 return ret;
1470 }
1471
1472 /**
1473 * @brief Disconnect CS pull-up.[get]
1474 *
1475 * @param ctx read / write interface definitions
1476 * @param val Get the values of cs_pu_disc in reg CTRL2
1477 * @retval interface status (MANDATORY: return 0 -> no Error)
1478 *
1479 */
lis2dtw12_cs_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_cs_pu_disc_t * val)1480 int32_t lis2dtw12_cs_mode_get(const stmdev_ctx_t *ctx,
1481 lis2dtw12_cs_pu_disc_t *val)
1482 {
1483 lis2dtw12_ctrl2_t reg;
1484 int32_t ret;
1485
1486 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1);
1487
1488 switch (reg.cs_pu_disc)
1489 {
1490 case LIS2DTW12_PULL_UP_CONNECT:
1491 *val = LIS2DTW12_PULL_UP_CONNECT;
1492 break;
1493
1494 case LIS2DTW12_PULL_UP_DISCONNECT:
1495 *val = LIS2DTW12_PULL_UP_DISCONNECT;
1496 break;
1497
1498 default:
1499 *val = LIS2DTW12_PULL_UP_CONNECT;
1500 break;
1501 }
1502
1503 return ret;
1504 }
1505
1506 /**
1507 * @}
1508 *
1509 */
1510
1511 /**
1512 * @defgroup LIS2DTW12_Interrupt_Pins
1513 * @brief This section groups all the functions that manage interrupt pins
1514 * @{
1515 *
1516 */
1517
1518 /**
1519 * @brief Interrupt active-high/low.[set]
1520 *
1521 * @param ctx read / write interface definitions
1522 * @param val change the values of h_lactive in reg CTRL3
1523 * @retval interface status (MANDATORY: return 0 -> no Error)
1524 *
1525 */
lis2dtw12_pin_polarity_set(const stmdev_ctx_t * ctx,lis2dtw12_h_lactive_t val)1526 int32_t lis2dtw12_pin_polarity_set(const stmdev_ctx_t *ctx,
1527 lis2dtw12_h_lactive_t val)
1528 {
1529 lis2dtw12_ctrl3_t reg;
1530 int32_t ret;
1531
1532 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1533
1534 if (ret == 0)
1535 {
1536 reg.h_lactive = (uint8_t) val;
1537 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1538 }
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief Interrupt active-high/low.[get]
1545 *
1546 * @param ctx read / write interface definitions
1547 * @param val Get the values of h_lactive in reg CTRL3
1548 * @retval interface status (MANDATORY: return 0 -> no Error)
1549 *
1550 */
lis2dtw12_pin_polarity_get(const stmdev_ctx_t * ctx,lis2dtw12_h_lactive_t * val)1551 int32_t lis2dtw12_pin_polarity_get(const stmdev_ctx_t *ctx,
1552 lis2dtw12_h_lactive_t *val)
1553 {
1554 lis2dtw12_ctrl3_t reg;
1555 int32_t ret;
1556
1557 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1558
1559 switch (reg.h_lactive)
1560 {
1561 case LIS2DTW12_ACTIVE_HIGH:
1562 *val = LIS2DTW12_ACTIVE_HIGH;
1563 break;
1564
1565 case LIS2DTW12_ACTIVE_LOW:
1566 *val = LIS2DTW12_ACTIVE_LOW;
1567 break;
1568
1569 default:
1570 *val = LIS2DTW12_ACTIVE_HIGH;
1571 break;
1572 }
1573
1574 return ret;
1575 }
1576
1577 /**
1578 * @brief Latched/pulsed interrupt.[set]
1579 *
1580 * @param ctx read / write interface definitions
1581 * @param val change the values of lir in reg CTRL3
1582 * @retval interface status (MANDATORY: return 0 -> no Error)
1583 *
1584 */
lis2dtw12_int_notification_set(const stmdev_ctx_t * ctx,lis2dtw12_lir_t val)1585 int32_t lis2dtw12_int_notification_set(const stmdev_ctx_t *ctx,
1586 lis2dtw12_lir_t val)
1587 {
1588 lis2dtw12_ctrl3_t reg;
1589 int32_t ret;
1590
1591 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1592
1593 if (ret == 0)
1594 {
1595 reg.lir = (uint8_t) val;
1596 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1597 }
1598
1599 return ret;
1600 }
1601
1602 /**
1603 * @brief Latched/pulsed interrupt.[get]
1604 *
1605 * @param ctx read / write interface definitions
1606 * @param val Get the values of lir in reg CTRL3
1607 * @retval interface status (MANDATORY: return 0 -> no Error)
1608 *
1609 */
lis2dtw12_int_notification_get(const stmdev_ctx_t * ctx,lis2dtw12_lir_t * val)1610 int32_t lis2dtw12_int_notification_get(const stmdev_ctx_t *ctx,
1611 lis2dtw12_lir_t *val)
1612 {
1613 lis2dtw12_ctrl3_t reg;
1614 int32_t ret;
1615
1616 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1617
1618 switch (reg.lir)
1619 {
1620 case LIS2DTW12_INT_PULSED:
1621 *val = LIS2DTW12_INT_PULSED;
1622 break;
1623
1624 case LIS2DTW12_INT_LATCHED:
1625 *val = LIS2DTW12_INT_LATCHED;
1626 break;
1627
1628 default:
1629 *val = LIS2DTW12_INT_PULSED;
1630 break;
1631 }
1632
1633 return ret;
1634 }
1635
1636 /**
1637 * @brief Push-pull/open drain selection on interrupt pads.[set]
1638 *
1639 * @param ctx read / write interface definitions
1640 * @param val change the values of pp_od in reg CTRL3
1641 * @retval interface status (MANDATORY: return 0 -> no Error)
1642 *
1643 */
lis2dtw12_pin_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_pp_od_t val)1644 int32_t lis2dtw12_pin_mode_set(const stmdev_ctx_t *ctx,
1645 lis2dtw12_pp_od_t val)
1646 {
1647 lis2dtw12_ctrl3_t reg;
1648 int32_t ret;
1649
1650 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1651
1652 if (ret == 0)
1653 {
1654 reg.pp_od = (uint8_t) val;
1655 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1656 }
1657
1658 return ret;
1659 }
1660
1661 /**
1662 * @brief Push-pull/open drain selection on interrupt pads.[get]
1663 *
1664 * @param ctx read / write interface definitions
1665 * @param val Get the values of pp_od in reg CTRL3
1666 * @retval interface status (MANDATORY: return 0 -> no Error)
1667 *
1668 */
lis2dtw12_pin_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_pp_od_t * val)1669 int32_t lis2dtw12_pin_mode_get(const stmdev_ctx_t *ctx,
1670 lis2dtw12_pp_od_t *val)
1671 {
1672 lis2dtw12_ctrl3_t reg;
1673 int32_t ret;
1674
1675 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1);
1676
1677 switch (reg.pp_od)
1678 {
1679 case LIS2DTW12_PUSH_PULL:
1680 *val = LIS2DTW12_PUSH_PULL;
1681 break;
1682
1683 case LIS2DTW12_OPEN_DRAIN:
1684 *val = LIS2DTW12_OPEN_DRAIN;
1685 break;
1686
1687 default:
1688 *val = LIS2DTW12_PUSH_PULL;
1689 break;
1690 }
1691
1692 return ret;
1693 }
1694
1695 /**
1696 * @brief Select the signal that need to route on int1 pad.[set]
1697 *
1698 * @param ctx read / write interface definitions
1699 * @param val register CTRL4_INT1_PAD_CTRL.
1700 * @retval interface status (MANDATORY: return 0 -> no Error)
1701 *
1702 */
lis2dtw12_pin_int1_route_set(const stmdev_ctx_t * ctx,lis2dtw12_ctrl4_int1_pad_ctrl_t * val)1703 int32_t lis2dtw12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1704 lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
1705 {
1706 lis2dtw12_ctrl_reg7_t reg;
1707 int32_t ret;
1708
1709 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1710
1711 if (ret == 0)
1712 {
1713 if ((val->int1_tap | val->int1_ff | val->int1_wu |
1714 val->int1_single_tap |
1715 val->int1_6d) != PROPERTY_DISABLE)
1716 {
1717 reg.interrupts_enable = PROPERTY_ENABLE;
1718 }
1719
1720 else
1721 {
1722 reg.interrupts_enable = PROPERTY_DISABLE;
1723 }
1724
1725 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL4_INT1_PAD_CTRL,
1726 (uint8_t *) val, 1);
1727 }
1728
1729 if (ret == 0)
1730 {
1731 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1732 }
1733
1734 return ret;
1735 }
1736
1737 /**
1738 * @brief Select the signal that need to route on int1 pad.[get]
1739 *
1740 * @param ctx read / write interface definitions
1741 * @param val register CTRL4_INT1_PAD_CTRL.
1742 * @retval interface status (MANDATORY: return 0 -> no Error)
1743 *
1744 */
lis2dtw12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2dtw12_ctrl4_int1_pad_ctrl_t * val)1745 int32_t lis2dtw12_pin_int1_route_get(const stmdev_ctx_t *ctx,
1746 lis2dtw12_ctrl4_int1_pad_ctrl_t *val)
1747 {
1748 int32_t ret;
1749
1750 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL4_INT1_PAD_CTRL,
1751 (uint8_t *) val, 1);
1752
1753 return ret;
1754 }
1755
1756 /**
1757 * @brief Select the signal that need to route on int2 pad.[set]
1758 *
1759 * @param ctx read / write interface definitions
1760 * @param val register CTRL5_INT2_PAD_CTRL.
1761 * @retval interface status (MANDATORY: return 0 -> no Error)
1762 *
1763 */
lis2dtw12_pin_int2_route_set(const stmdev_ctx_t * ctx,lis2dtw12_ctrl5_int2_pad_ctrl_t * val)1764 int32_t lis2dtw12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1765 lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
1766 {
1767 lis2dtw12_ctrl_reg7_t reg;
1768 int32_t ret;
1769
1770 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1771
1772 if (ret == 0)
1773 {
1774 if ((val->int2_sleep_state | val->int2_sleep_chg) !=
1775 PROPERTY_DISABLE)
1776 {
1777 reg.interrupts_enable = PROPERTY_ENABLE;
1778 }
1779
1780 else
1781 {
1782 reg.interrupts_enable = PROPERTY_DISABLE;
1783 }
1784
1785 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL5_INT2_PAD_CTRL,
1786 (uint8_t *) val, 1);
1787 }
1788
1789 if (ret == 0)
1790 {
1791 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1792 }
1793
1794 return ret;
1795 }
1796
1797 /**
1798 * @brief Select the signal that need to route on int2 pad.[get]
1799 *
1800 * @param ctx read / write interface definitions
1801 * @param val register CTRL5_INT2_PAD_CTRL
1802 * @retval interface status (MANDATORY: return 0 -> no Error)
1803 *
1804 */
lis2dtw12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2dtw12_ctrl5_int2_pad_ctrl_t * val)1805 int32_t lis2dtw12_pin_int2_route_get(const stmdev_ctx_t *ctx,
1806 lis2dtw12_ctrl5_int2_pad_ctrl_t *val)
1807 {
1808 int32_t ret;
1809
1810 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL5_INT2_PAD_CTRL,
1811 (uint8_t *) val, 1);
1812
1813 return ret;
1814 }
1815 /**
1816 * @brief All interrupt signals become available on INT1 pin.[set]
1817 *
1818 * @param ctx read / write interface definitions
1819 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1820 * @retval interface status (MANDATORY: return 0 -> no Error)
1821 *
1822 */
lis2dtw12_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)1823 int32_t lis2dtw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
1824 {
1825 lis2dtw12_ctrl_reg7_t reg;
1826 int32_t ret;
1827
1828 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1829
1830 if (ret == 0)
1831 {
1832 reg.int2_on_int1 = val;
1833 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1834 }
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief All interrupt signals become available on INT1 pin.[get]
1841 *
1842 * @param ctx read / write interface definitions
1843 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1844 * @retval interface status (MANDATORY: return 0 -> no Error)
1845 *
1846 */
lis2dtw12_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)1847 int32_t lis2dtw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1848 {
1849 lis2dtw12_ctrl_reg7_t reg;
1850 int32_t ret;
1851
1852 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1853 *val = reg.int2_on_int1;
1854
1855 return ret;
1856 }
1857
1858 /**
1859 * @}
1860 *
1861 */
1862
1863 /**
1864 * @defgroup LIS2DTW12_Wake_Up_Event
1865 * @brief This section groups all the functions that manage the Wake
1866 * Up event generation.
1867 * @{
1868 *
1869 */
1870
1871 /**
1872 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
1873 *
1874 * @param ctx read / write interface definitions
1875 * @param val change the values of wk_ths in reg WAKE_UP_THS
1876 * @retval interface status (MANDATORY: return 0 -> no Error)
1877 *
1878 */
lis2dtw12_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1879 int32_t lis2dtw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1880 {
1881 lis2dtw12_wake_up_ths_t reg;
1882 int32_t ret;
1883
1884 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1885
1886 if (ret == 0)
1887 {
1888 reg.wk_ths = val;
1889 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
1890 (uint8_t *) ®, 1);
1891 }
1892
1893 return ret;
1894 }
1895
1896 /**
1897 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
1898 *
1899 * @param ctx read / write interface definitions
1900 * @param val change the values of wk_ths in reg WAKE_UP_THS
1901 * @retval interface status (MANDATORY: return 0 -> no Error)
1902 *
1903 */
lis2dtw12_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1904 int32_t lis2dtw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1905 {
1906 lis2dtw12_wake_up_ths_t reg;
1907 int32_t ret;
1908
1909 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1910 *val = reg.wk_ths;
1911
1912 return ret;
1913 }
1914
1915 /**
1916 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
1917 *
1918 * @param ctx read / write interface definitions
1919 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1920 * @retval interface status (MANDATORY: return 0 -> no Error)
1921 *
1922 */
lis2dtw12_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1923 int32_t lis2dtw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1924 {
1925 lis2dtw12_wake_up_dur_t reg;
1926 int32_t ret;
1927
1928 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1929
1930 if (ret == 0)
1931 {
1932 reg.wake_dur = val;
1933 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
1934 (uint8_t *) ®, 1);
1935 }
1936
1937 return ret;
1938 }
1939
1940 /**
1941 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
1942 *
1943 * @param ctx read / write interface definitions
1944 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1945 * @retval interface status (MANDATORY: return 0 -> no Error)
1946 *
1947 */
lis2dtw12_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1948 int32_t lis2dtw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1949 {
1950 lis2dtw12_wake_up_dur_t reg;
1951 int32_t ret;
1952
1953 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1954 *val = reg.wake_dur;
1955
1956 return ret;
1957 }
1958
1959 /**
1960 * @brief Data sent to wake-up interrupt function.[set]
1961 *
1962 * @param ctx read / write interface definitions
1963 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
1964 * @retval interface status (MANDATORY: return 0 -> no Error)
1965 *
1966 */
lis2dtw12_wkup_feed_data_set(const stmdev_ctx_t * ctx,lis2dtw12_usr_off_on_wu_t val)1967 int32_t lis2dtw12_wkup_feed_data_set(const stmdev_ctx_t *ctx,
1968 lis2dtw12_usr_off_on_wu_t val)
1969 {
1970 lis2dtw12_ctrl_reg7_t reg;
1971 int32_t ret;
1972
1973 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1974
1975 if (ret == 0)
1976 {
1977 reg.usr_off_on_wu = (uint8_t) val;
1978 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1979 }
1980
1981 return ret;
1982 }
1983
1984 /**
1985 * @brief Data sent to wake-up interrupt function.[get]
1986 *
1987 * @param ctx read / write interface definitions
1988 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
1989 * @retval interface status (MANDATORY: return 0 -> no Error)
1990 *
1991 */
lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t * ctx,lis2dtw12_usr_off_on_wu_t * val)1992 int32_t lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t *ctx,
1993 lis2dtw12_usr_off_on_wu_t *val)
1994 {
1995 lis2dtw12_ctrl_reg7_t reg;
1996 int32_t ret;
1997
1998 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
1999
2000 switch (reg.usr_off_on_wu)
2001 {
2002 case LIS2DTW12_HP_FEED:
2003 *val = LIS2DTW12_HP_FEED;
2004 break;
2005
2006 case LIS2DTW12_USER_OFFSET_FEED:
2007 *val = LIS2DTW12_USER_OFFSET_FEED;
2008 break;
2009
2010 default:
2011 *val = LIS2DTW12_HP_FEED;
2012 break;
2013 }
2014
2015 return ret;
2016 }
2017
2018 /**
2019 * @}
2020 *
2021 */
2022
2023 /**
2024 * @defgroup LIS2DTW12_Activity/Inactivity_Detection
2025 * @brief This section groups all the functions concerning
2026 * activity/inactivity detection.
2027 * @{
2028 *
2029 */
2030
2031 /**
2032 * @brief Config activity / inactivity or
2033 * stationary / motion detection.[set]
2034 *
2035 * @param ctx read / write interface definitions
2036 * @param val change the values of sleep_on / stationary in
2037 * reg WAKE_UP_THS / WAKE_UP_DUR
2038 * @retval interface status (MANDATORY: return 0 -> no Error)
2039 *
2040 */
lis2dtw12_act_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_sleep_on_t val)2041 int32_t lis2dtw12_act_mode_set(const stmdev_ctx_t *ctx,
2042 lis2dtw12_sleep_on_t val)
2043 {
2044 lis2dtw12_wake_up_ths_t wake_up_ths;
2045 lis2dtw12_wake_up_dur_t wake_up_dur;
2046 int32_t ret;
2047
2048 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,
2049 (uint8_t *) &wake_up_ths, 1);
2050
2051 if (ret == 0)
2052 {
2053 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2054 (uint8_t *) &wake_up_dur, 1);
2055 }
2056
2057 if (ret == 0)
2058 {
2059 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
2060 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
2061 (uint8_t *) &wake_up_ths, 1);
2062 }
2063
2064 if (ret == 0)
2065 {
2066 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
2067 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2068 (uint8_t *) &wake_up_dur, 1);
2069 }
2070
2071 return ret;
2072 }
2073
2074 /**
2075 * @brief Config activity / inactivity or
2076 * stationary / motion detection. [get]
2077 *
2078 * @param ctx read / write interface definitions
2079 * @param val Get the values of sleep_on in reg WAKE_UP_THS
2080 * @retval interface status (MANDATORY: return 0 -> no Error)
2081 *
2082 */
lis2dtw12_act_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_sleep_on_t * val)2083 int32_t lis2dtw12_act_mode_get(const stmdev_ctx_t *ctx,
2084 lis2dtw12_sleep_on_t *val)
2085 {
2086 lis2dtw12_wake_up_ths_t wake_up_ths;
2087 lis2dtw12_wake_up_dur_t wake_up_dur;;
2088 int32_t ret;
2089
2090 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS,
2091 (uint8_t *) &wake_up_ths, 1);
2092
2093 if (ret == 0)
2094 {
2095 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2096 (uint8_t *) &wake_up_dur, 1);
2097
2098 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
2099 {
2100 case LIS2DTW12_NO_DETECTION:
2101 *val = LIS2DTW12_NO_DETECTION;
2102 break;
2103
2104 case LIS2DTW12_DETECT_ACT_INACT:
2105 *val = LIS2DTW12_DETECT_ACT_INACT;
2106 break;
2107
2108 case LIS2DTW12_DETECT_STAT_MOTION:
2109 *val = LIS2DTW12_DETECT_STAT_MOTION;
2110 break;
2111
2112 default:
2113 *val = LIS2DTW12_NO_DETECTION;
2114 break;
2115 }
2116 }
2117
2118 return ret;
2119 }
2120
2121 /**
2122 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
2123 *
2124 * @param ctx read / write interface definitions
2125 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2126 * @retval interface status (MANDATORY: return 0 -> no Error)
2127 *
2128 */
lis2dtw12_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2129 int32_t lis2dtw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2130 {
2131 lis2dtw12_wake_up_dur_t reg;
2132 int32_t ret;
2133
2134 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2135
2136 if (ret == 0)
2137 {
2138 reg.sleep_dur = val;
2139 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2140 (uint8_t *) ®, 1);
2141 }
2142
2143 return ret;
2144 }
2145
2146 /**
2147 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
2148 *
2149 * @param ctx read / write interface definitions
2150 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2151 * @retval interface status (MANDATORY: return 0 -> no Error)
2152 *
2153 */
lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2154 int32_t lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2155 {
2156 lis2dtw12_wake_up_dur_t reg;
2157 int32_t ret;
2158
2159 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2160 *val = reg.sleep_dur;
2161
2162 return ret;
2163 }
2164
2165 /**
2166 * @}
2167 *
2168 */
2169
2170 /**
2171 * @defgroup LIS2DTW12_Tap_Generator
2172 * @brief This section groups all the functions that manage the tap
2173 * and double tap event generation.
2174 * @{
2175 *
2176 */
2177
2178 /**
2179 * @brief Threshold for tap recognition.[set]
2180 *
2181 * @param ctx read / write interface definitions
2182 * @param val change the values of tap_thsx in reg TAP_THS_X
2183 * @retval interface status (MANDATORY: return 0 -> no Error)
2184 *
2185 */
lis2dtw12_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)2186 int32_t lis2dtw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
2187 {
2188 lis2dtw12_tap_ths_x_t reg;
2189 int32_t ret;
2190
2191 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2192
2193 if (ret == 0)
2194 {
2195 reg.tap_thsx = val;
2196 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2197 }
2198
2199 return ret;
2200 }
2201
2202 /**
2203 * @brief Threshold for tap recognition.[get]
2204 *
2205 * @param ctx read / write interface definitions
2206 * @param val change the values of tap_thsx in reg TAP_THS_X
2207 * @retval interface status (MANDATORY: return 0 -> no Error)
2208 *
2209 */
lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2210 int32_t lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
2211 {
2212 lis2dtw12_tap_ths_x_t reg;
2213 int32_t ret;
2214
2215 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2216 *val = reg.tap_thsx;
2217
2218 return ret;
2219 }
2220
2221 /**
2222 * @brief Threshold for tap recognition.[set]
2223 *
2224 * @param ctx read / write interface definitions
2225 * @param val change the values of tap_thsy in reg TAP_THS_Y
2226 * @retval interface status (MANDATORY: return 0 -> no Error)
2227 *
2228 */
lis2dtw12_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)2229 int32_t lis2dtw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
2230 {
2231 lis2dtw12_tap_ths_y_t reg;
2232 int32_t ret;
2233
2234 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2235
2236 if (ret == 0)
2237 {
2238 reg.tap_thsy = val;
2239 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2240 }
2241
2242 return ret;
2243 }
2244
2245 /**
2246 * @brief Threshold for tap recognition.[get]
2247 *
2248 * @param ctx read / write interface definitions
2249 * @param val change the values of tap_thsy in reg TAP_THS_Y
2250 * @retval interface status (MANDATORY: return 0 -> no Error)
2251 *
2252 */
lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2253 int32_t lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
2254 {
2255 lis2dtw12_tap_ths_y_t reg;
2256 int32_t ret;
2257
2258 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2259 *val = reg.tap_thsy;
2260
2261 return ret;
2262 }
2263
2264 /**
2265 * @brief Selection of axis priority for TAP detection.[set]
2266 *
2267 * @param ctx read / write interface definitions
2268 * @param val change the values of tap_prior in reg TAP_THS_Y
2269 * @retval interface status (MANDATORY: return 0 -> no Error)
2270 *
2271 */
lis2dtw12_tap_axis_priority_set(const stmdev_ctx_t * ctx,lis2dtw12_tap_prior_t val)2272 int32_t lis2dtw12_tap_axis_priority_set(const stmdev_ctx_t *ctx,
2273 lis2dtw12_tap_prior_t val)
2274 {
2275 lis2dtw12_tap_ths_y_t reg;
2276 int32_t ret;
2277
2278 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2279
2280 if (ret == 0)
2281 {
2282 reg.tap_prior = (uint8_t) val;
2283 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2284 }
2285
2286 return ret;
2287 }
2288
2289 /**
2290 * @brief Selection of axis priority for TAP detection.[get]
2291 *
2292 * @param ctx read / write interface definitions
2293 * @param val Get the values of tap_prior in reg TAP_THS_Y
2294 * @retval interface status (MANDATORY: return 0 -> no Error)
2295 *
2296 */
lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t * ctx,lis2dtw12_tap_prior_t * val)2297 int32_t lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t *ctx,
2298 lis2dtw12_tap_prior_t *val)
2299 {
2300 lis2dtw12_tap_ths_y_t reg;
2301 int32_t ret;
2302
2303 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1);
2304
2305 switch (reg.tap_prior)
2306 {
2307 case LIS2DTW12_XYZ:
2308 *val = LIS2DTW12_XYZ;
2309 break;
2310
2311 case LIS2DTW12_YXZ:
2312 *val = LIS2DTW12_YXZ;
2313 break;
2314
2315 case LIS2DTW12_XZY:
2316 *val = LIS2DTW12_XZY;
2317 break;
2318
2319 case LIS2DTW12_ZYX:
2320 *val = LIS2DTW12_ZYX;
2321 break;
2322
2323 case LIS2DTW12_YZX:
2324 *val = LIS2DTW12_YZX;
2325 break;
2326
2327 case LIS2DTW12_ZXY:
2328 *val = LIS2DTW12_ZXY;
2329 break;
2330
2331 default:
2332 *val = LIS2DTW12_XYZ;
2333 break;
2334 }
2335
2336 return ret;
2337 }
2338
2339 /**
2340 * @brief Threshold for tap recognition.[set]
2341 *
2342 * @param ctx read / write interface definitions
2343 * @param val change the values of tap_thsz in reg TAP_THS_Z
2344 * @retval interface status (MANDATORY: return 0 -> no Error)
2345 *
2346 */
lis2dtw12_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)2347 int32_t lis2dtw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
2348 {
2349 lis2dtw12_tap_ths_z_t reg;
2350 int32_t ret;
2351
2352 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2353
2354 if (ret == 0)
2355 {
2356 reg.tap_thsz = val;
2357 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2358 }
2359
2360 return ret;
2361 }
2362
2363 /**
2364 * @brief Threshold for tap recognition.[get]
2365 *
2366 * @param ctx read / write interface definitions
2367 * @param val change the values of tap_thsz in reg TAP_THS_Z
2368 * @retval interface status (MANDATORY: return 0 -> no Error)
2369 *
2370 */
lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2371 int32_t lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
2372 {
2373 lis2dtw12_tap_ths_z_t reg;
2374 int32_t ret;
2375
2376 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2377 *val = reg.tap_thsz;
2378
2379 return ret;
2380 }
2381
2382 /**
2383 * @brief Enable Z direction in tap recognition.[set]
2384 *
2385 * @param ctx read / write interface definitions
2386 * @param val change the values of tap_z_en in reg TAP_THS_Z
2387 * @retval interface status (MANDATORY: return 0 -> no Error)
2388 *
2389 */
lis2dtw12_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)2390 int32_t lis2dtw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
2391 uint8_t val)
2392 {
2393 lis2dtw12_tap_ths_z_t reg;
2394 int32_t ret;
2395
2396 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2397
2398 if (ret == 0)
2399 {
2400 reg.tap_z_en = val;
2401 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2402 }
2403
2404 return ret;
2405 }
2406
2407 /**
2408 * @brief Enable Z direction in tap recognition.[get]
2409 *
2410 * @param ctx read / write interface definitions
2411 * @param val change the values of tap_z_en in reg TAP_THS_Z
2412 * @retval interface status (MANDATORY: return 0 -> no Error)
2413 *
2414 */
lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2415 int32_t lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
2416 uint8_t *val)
2417 {
2418 lis2dtw12_tap_ths_z_t reg;
2419 int32_t ret;
2420
2421 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2422 *val = reg.tap_z_en;
2423
2424 return ret;
2425 }
2426
2427 /**
2428 * @brief Enable Y direction in tap recognition.[set]
2429 *
2430 * @param ctx read / write interface definitions
2431 * @param val change the values of tap_y_en in reg TAP_THS_Z
2432 * @retval interface status (MANDATORY: return 0 -> no Error)
2433 *
2434 */
lis2dtw12_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)2435 int32_t lis2dtw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
2436 uint8_t val)
2437 {
2438 lis2dtw12_tap_ths_z_t reg;
2439 int32_t ret;
2440
2441 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2442
2443 if (ret == 0)
2444 {
2445 reg.tap_y_en = val;
2446 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2447 }
2448
2449 return ret;
2450 }
2451
2452 /**
2453 * @brief Enable Y direction in tap recognition.[get]
2454 *
2455 * @param ctx read / write interface definitions
2456 * @param val change the values of tap_y_en in reg TAP_THS_Z
2457 * @retval interface status (MANDATORY: return 0 -> no Error)
2458 *
2459 */
lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2460 int32_t lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
2461 uint8_t *val)
2462 {
2463 lis2dtw12_tap_ths_z_t reg;
2464 int32_t ret;
2465
2466 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2467 *val = reg.tap_y_en;
2468
2469 return ret;
2470 }
2471
2472 /**
2473 * @brief Enable X direction in tap recognition.[set]
2474 *
2475 * @param ctx read / write interface definitions
2476 * @param val change the values of tap_x_en in reg TAP_THS_Z
2477 * @retval interface status (MANDATORY: return 0 -> no Error)
2478 *
2479 */
lis2dtw12_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)2480 int32_t lis2dtw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
2481 uint8_t val)
2482 {
2483 lis2dtw12_tap_ths_z_t reg;
2484 int32_t ret;
2485
2486 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2487
2488 if (ret == 0)
2489 {
2490 reg.tap_x_en = val;
2491 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2492 }
2493
2494 return ret;
2495 }
2496
2497 /**
2498 * @brief Enable X direction in tap recognition.[get]
2499 *
2500 * @param ctx read / write interface definitions
2501 * @param val change the values of tap_x_en in reg TAP_THS_Z
2502 * @retval interface status (MANDATORY: return 0 -> no Error)
2503 *
2504 */
lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2505 int32_t lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
2506 uint8_t *val)
2507 {
2508 lis2dtw12_tap_ths_z_t reg;
2509 int32_t ret;
2510
2511 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1);
2512 *val = reg.tap_x_en;
2513
2514 return ret;
2515 }
2516
2517 /**
2518 * @brief Maximum duration is the maximum time of an overthreshold signal
2519 * detection to be recognized as a tap event. The default value
2520 * of these bits is 00b which corresponds to 4*ODR_XL time.
2521 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2522 * corresponds to 8*ODR_XL time.[set]
2523 *
2524 * @param ctx read / write interface definitions
2525 * @param val change the values of shock in reg INT_DUR
2526 * @retval interface status (MANDATORY: return 0 -> no Error)
2527 *
2528 */
lis2dtw12_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)2529 int32_t lis2dtw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
2530 {
2531 lis2dtw12_int_dur_t reg;
2532 int32_t ret;
2533
2534 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2535
2536 if (ret == 0)
2537 {
2538 reg.shock = val;
2539 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2540 }
2541
2542 return ret;
2543 }
2544
2545 /**
2546 * @brief Maximum duration is the maximum time of an overthreshold signal
2547 * detection to be recognized as a tap event. The default value
2548 * of these bits is 00b which corresponds to 4*ODR_XL time.
2549 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2550 * corresponds to 8*ODR_XL time.[get]
2551 *
2552 * @param ctx read / write interface definitions
2553 * @param val change the values of shock in reg INT_DUR
2554 * @retval interface status (MANDATORY: return 0 -> no Error)
2555 *
2556 */
lis2dtw12_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)2557 int32_t lis2dtw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
2558 {
2559 lis2dtw12_int_dur_t reg;
2560 int32_t ret;
2561
2562 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2563 *val = reg.shock;
2564
2565 return ret;
2566 }
2567
2568 /**
2569 * @brief Quiet time is the time after the first detected tap in which
2570 * there must not be any overthreshold event.
2571 * The default value of these bits is 00b which corresponds
2572 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2573 * value, 1LSB corresponds to 4*ODR_XL time.[set]
2574 *
2575 * @param ctx read / write interface definitions
2576 * @param val change the values of quiet in reg INT_DUR
2577 * @retval interface status (MANDATORY: return 0 -> no Error)
2578 *
2579 */
lis2dtw12_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)2580 int32_t lis2dtw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
2581 {
2582 lis2dtw12_int_dur_t reg;
2583 int32_t ret;
2584
2585 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2586
2587 if (ret == 0)
2588 {
2589 reg.quiet = val;
2590 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2591 }
2592
2593 return ret;
2594 }
2595
2596 /**
2597 * @brief Quiet time is the time after the first detected tap in which
2598 * there must not be any overthreshold event.
2599 * The default value of these bits is 00b which corresponds
2600 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2601 * value, 1LSB corresponds to 4*ODR_XL time.[get]
2602 *
2603 * @param ctx read / write interface definitions
2604 * @param val change the values of quiet in reg INT_DUR
2605 * @retval interface status (MANDATORY: return 0 -> no Error)
2606 *
2607 */
lis2dtw12_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)2608 int32_t lis2dtw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
2609 {
2610 lis2dtw12_int_dur_t reg;
2611 int32_t ret;
2612
2613 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2614 *val = reg.quiet;
2615
2616 return ret;
2617 }
2618
2619 /**
2620 * @brief When double tap recognition is enabled, this register expresses
2621 * the maximum time between two consecutive detected taps to
2622 * determine a double tap event.
2623 * The default value of these bits is 0000b which corresponds
2624 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2625 * value, 1LSB corresponds to 32*ODR_XL time.[set]
2626 *
2627 * @param ctx read / write interface definitions
2628 * @param val change the values of latency in reg INT_DUR
2629 * @retval interface status (MANDATORY: return 0 -> no Error)
2630 *
2631 */
lis2dtw12_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2632 int32_t lis2dtw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2633 {
2634 lis2dtw12_int_dur_t reg;
2635 int32_t ret;
2636
2637 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2638
2639 if (ret == 0)
2640 {
2641 reg.latency = val;
2642 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2643 }
2644
2645 return ret;
2646 }
2647
2648 /**
2649 * @brief When double tap recognition is enabled, this register expresses
2650 * the maximum time between two consecutive detected taps to
2651 * determine a double tap event.
2652 * The default value of these bits is 0000b which corresponds
2653 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2654 * value, 1LSB corresponds to 32*ODR_XL time.[get]
2655 *
2656 * @param ctx read / write interface definitions
2657 * @param val change the values of latency in reg INT_DUR
2658 * @retval interface status (MANDATORY: return 0 -> no Error)
2659 *
2660 */
lis2dtw12_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2661 int32_t lis2dtw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2662 {
2663 lis2dtw12_int_dur_t reg;
2664 int32_t ret;
2665
2666 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1);
2667 *val = reg.latency;
2668
2669 return ret;
2670 }
2671
2672 /**
2673 * @brief Single/double-tap event enable.[set]
2674 *
2675 * @param ctx read / write interface definitions
2676 * @param val change the values of single_double_tap in reg WAKE_UP_THS
2677 * @retval interface status (MANDATORY: return 0 -> no Error)
2678 *
2679 */
lis2dtw12_tap_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_single_double_tap_t val)2680 int32_t lis2dtw12_tap_mode_set(const stmdev_ctx_t *ctx,
2681 lis2dtw12_single_double_tap_t val)
2682 {
2683 lis2dtw12_wake_up_ths_t reg;
2684 int32_t ret;
2685
2686 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
2687
2688 if (ret == 0)
2689 {
2690 reg.single_double_tap = (uint8_t) val;
2691 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_THS,
2692 (uint8_t *) ®, 1);
2693 }
2694
2695 return ret;
2696 }
2697
2698 /**
2699 * @brief Single/double-tap event enable.[get]
2700 *
2701 * @param ctx read / write interface definitions
2702 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
2703 * @retval interface status (MANDATORY: return 0 -> no Error)
2704 *
2705 */
lis2dtw12_tap_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_single_double_tap_t * val)2706 int32_t lis2dtw12_tap_mode_get(const stmdev_ctx_t *ctx,
2707 lis2dtw12_single_double_tap_t *val)
2708 {
2709 lis2dtw12_wake_up_ths_t reg;
2710 int32_t ret;
2711
2712 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1);
2713
2714 switch (reg.single_double_tap)
2715 {
2716 case LIS2DTW12_ONLY_SINGLE:
2717 *val = LIS2DTW12_ONLY_SINGLE;
2718 break;
2719
2720 case LIS2DTW12_BOTH_SINGLE_DOUBLE:
2721 *val = LIS2DTW12_BOTH_SINGLE_DOUBLE;
2722 break;
2723
2724 default:
2725 *val = LIS2DTW12_ONLY_SINGLE;
2726 break;
2727 }
2728
2729 return ret;
2730 }
2731
2732 /**
2733 * @brief Read the tap / double tap source register.[get]
2734 *
2735 * @param ctx read / write interface definitions
2736 * @param lis2dtw12_tap_src: union of registers from TAP_SRC to
2737 * @retval interface status (MANDATORY: return 0 -> no Error)
2738 *
2739 */
lis2dtw12_tap_src_get(const stmdev_ctx_t * ctx,lis2dtw12_tap_src_t * val)2740 int32_t lis2dtw12_tap_src_get(const stmdev_ctx_t *ctx,
2741 lis2dtw12_tap_src_t *val)
2742 {
2743 int32_t ret;
2744
2745 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_SRC, (uint8_t *) val, 1);
2746
2747 return ret;
2748 }
2749
2750 /**
2751 * @}
2752 *
2753 */
2754
2755 /**
2756 * @defgroup LIS2DTW12_Six_Position_Detection(6D/4D)
2757 * @brief This section groups all the functions concerning six
2758 * position detection (6D).
2759 * @{
2760 *
2761 */
2762
2763 /**
2764 * @brief Threshold for 4D/6D function.[set]
2765 *
2766 * @param ctx read / write interface definitions
2767 * @param val change the values of 6d_ths in reg TAP_THS_X
2768 * @retval interface status (MANDATORY: return 0 -> no Error)
2769 *
2770 */
lis2dtw12_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2771 int32_t lis2dtw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2772 {
2773 lis2dtw12_tap_ths_x_t reg;
2774 int32_t ret;
2775
2776 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2777
2778 if (ret == 0)
2779 {
2780 reg._6d_ths = val;
2781 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2782 }
2783
2784 return ret;
2785 }
2786
2787 /**
2788 * @brief Threshold for 4D/6D function.[get]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val change the values of 6d_ths in reg TAP_THS_X
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
lis2dtw12_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2795 int32_t lis2dtw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2796 {
2797 lis2dtw12_tap_ths_x_t reg;
2798 int32_t ret;
2799
2800 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2801 *val = reg._6d_ths;
2802
2803 return ret;
2804 }
2805
2806 /**
2807 * @brief 4D orientation detection enable.[set]
2808 *
2809 * @param ctx read / write interface definitions
2810 * @param val change the values of 4d_en in reg TAP_THS_X
2811 * @retval interface status (MANDATORY: return 0 -> no Error)
2812 *
2813 */
lis2dtw12_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2814 int32_t lis2dtw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2815 {
2816 lis2dtw12_tap_ths_x_t reg;
2817 int32_t ret;
2818
2819 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2820
2821 if (ret == 0)
2822 {
2823 reg._4d_en = val;
2824 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2825 }
2826
2827 return ret;
2828 }
2829
2830 /**
2831 * @brief 4D orientation detection enable.[get]
2832 *
2833 * @param ctx read / write interface definitions
2834 * @param val change the values of 4d_en in reg TAP_THS_X
2835 * @retval interface status (MANDATORY: return 0 -> no Error)
2836 *
2837 */
lis2dtw12_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2838 int32_t lis2dtw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2839 {
2840 lis2dtw12_tap_ths_x_t reg;
2841 int32_t ret;
2842
2843 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1);
2844 *val = reg._4d_en;
2845
2846 return ret;
2847 }
2848
2849 /**
2850 * @brief Read the 6D tap source register.[get]
2851 *
2852 * @param ctx read / write interface definitions
2853 * @param val union of registers from SIXD_SRC
2854 * @retval interface status (MANDATORY: return 0 -> no Error)
2855 *
2856 */
lis2dtw12_6d_src_get(const stmdev_ctx_t * ctx,lis2dtw12_sixd_src_t * val)2857 int32_t lis2dtw12_6d_src_get(const stmdev_ctx_t *ctx,
2858 lis2dtw12_sixd_src_t *val)
2859 {
2860 int32_t ret;
2861
2862 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_SIXD_SRC, (uint8_t *) val, 1);
2863
2864 return ret;
2865 }
2866 /**
2867 * @brief Data sent to 6D interrupt function.[set]
2868 *
2869 * @param ctx read / write interface definitions
2870 * @param val change the values of lpass_on6d in reg CTRL_REG7
2871 * @retval interface status (MANDATORY: return 0 -> no Error)
2872 *
2873 */
lis2dtw12_6d_feed_data_set(const stmdev_ctx_t * ctx,lis2dtw12_lpass_on6d_t val)2874 int32_t lis2dtw12_6d_feed_data_set(const stmdev_ctx_t *ctx,
2875 lis2dtw12_lpass_on6d_t val)
2876 {
2877 lis2dtw12_ctrl_reg7_t reg;
2878 int32_t ret;
2879
2880 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
2881
2882 if (ret == 0)
2883 {
2884 reg.lpass_on6d = (uint8_t) val;
2885 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
2886 }
2887
2888 return ret;
2889 }
2890
2891 /**
2892 * @brief Data sent to 6D interrupt function.[get]
2893 *
2894 * @param ctx read / write interface definitions
2895 * @param val Get the values of lpass_on6d in reg CTRL_REG7
2896 * @retval interface status (MANDATORY: return 0 -> no Error)
2897 *
2898 */
lis2dtw12_6d_feed_data_get(const stmdev_ctx_t * ctx,lis2dtw12_lpass_on6d_t * val)2899 int32_t lis2dtw12_6d_feed_data_get(const stmdev_ctx_t *ctx,
2900 lis2dtw12_lpass_on6d_t *val)
2901 {
2902 lis2dtw12_ctrl_reg7_t reg;
2903 int32_t ret;
2904
2905 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1);
2906
2907 switch (reg.lpass_on6d)
2908 {
2909 case LIS2DTW12_ODR_DIV_2_FEED:
2910 *val = LIS2DTW12_ODR_DIV_2_FEED;
2911 break;
2912
2913 case LIS2DTW12_LPF2_FEED:
2914 *val = LIS2DTW12_LPF2_FEED;
2915 break;
2916
2917 default:
2918 *val = LIS2DTW12_ODR_DIV_2_FEED;
2919 break;
2920 }
2921
2922 return ret;
2923 }
2924
2925 /**
2926 * @}
2927 *
2928 */
2929
2930 /**
2931 * @defgroup LIS2DTW12_Free_Fall
2932 * @brief This section group all the functions concerning
2933 * the free fall detection.
2934 * @{
2935 *
2936 */
2937
2938 /**
2939 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
2940 *
2941 * @param ctx read / write interface definitions
2942 * @param val change the values of ff_dur in reg
2943 * WAKE_UP_DUR /F REE_FALL
2944 * @retval interface status (MANDATORY: return 0 -> no Error)
2945 *
2946 */
lis2dtw12_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2947 int32_t lis2dtw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2948 {
2949 lis2dtw12_wake_up_dur_t wake_up_dur;
2950 lis2dtw12_free_fall_t free_fall;
2951 int32_t ret;
2952
2953 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2954 (uint8_t *) &wake_up_dur, 1);
2955
2956 if (ret == 0)
2957 {
2958 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,
2959 (uint8_t *) &free_fall, 1);
2960 }
2961
2962 if (ret == 0)
2963 {
2964 wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
2965 free_fall.ff_dur = (uint8_t) val & 0x1FU;
2966 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2967 (uint8_t *) &wake_up_dur, 1);
2968 }
2969
2970 if (ret == 0)
2971 {
2972 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL,
2973 (uint8_t *) &free_fall, 1);
2974 }
2975
2976 return ret;
2977 }
2978
2979 /**
2980 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
2981 *
2982 * @param ctx read / write interface definitions
2983 * @param val change the values of ff_dur in
2984 * reg WAKE_UP_DUR /F REE_FALL
2985 * @retval interface status (MANDATORY: return 0 -> no Error)
2986 *
2987 */
lis2dtw12_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2988 int32_t lis2dtw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2989 {
2990 lis2dtw12_wake_up_dur_t wake_up_dur;
2991 lis2dtw12_free_fall_t free_fall;
2992 int32_t ret;
2993
2994 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR,
2995 (uint8_t *) &wake_up_dur, 1);
2996
2997 if (ret == 0)
2998 {
2999 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL,
3000 (uint8_t *) &free_fall, 1);
3001 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
3002 }
3003
3004 return ret;
3005 }
3006
3007 /**
3008 * @brief Free fall threshold setting.[set]
3009 *
3010 * @param ctx read / write interface definitions
3011 * @param val change the values of ff_ths in reg FREE_FALL
3012 * @retval interface status (MANDATORY: return 0 -> no Error)
3013 *
3014 */
lis2dtw12_ff_threshold_set(const stmdev_ctx_t * ctx,lis2dtw12_ff_ths_t val)3015 int32_t lis2dtw12_ff_threshold_set(const stmdev_ctx_t *ctx,
3016 lis2dtw12_ff_ths_t val)
3017 {
3018 lis2dtw12_free_fall_t reg;
3019 int32_t ret;
3020
3021 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
3022
3023 if (ret == 0)
3024 {
3025 reg.ff_ths = (uint8_t) val;
3026 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
3027 }
3028
3029 return ret;
3030 }
3031
3032 /**
3033 * @brief Free fall threshold setting.[get]
3034 *
3035 * @param ctx read / write interface definitions
3036 * @param val Get the values of ff_ths in reg FREE_FALL
3037 * @retval interface status (MANDATORY: return 0 -> no Error)
3038 *
3039 */
lis2dtw12_ff_threshold_get(const stmdev_ctx_t * ctx,lis2dtw12_ff_ths_t * val)3040 int32_t lis2dtw12_ff_threshold_get(const stmdev_ctx_t *ctx,
3041 lis2dtw12_ff_ths_t *val)
3042 {
3043 lis2dtw12_free_fall_t reg;
3044 int32_t ret;
3045
3046 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1);
3047
3048 switch (reg.ff_ths)
3049 {
3050 case LIS2DTW12_FF_TSH_5LSb_FS2g:
3051 *val = LIS2DTW12_FF_TSH_5LSb_FS2g;
3052 break;
3053
3054 case LIS2DTW12_FF_TSH_7LSb_FS2g:
3055 *val = LIS2DTW12_FF_TSH_7LSb_FS2g;
3056 break;
3057
3058 case LIS2DTW12_FF_TSH_8LSb_FS2g:
3059 *val = LIS2DTW12_FF_TSH_8LSb_FS2g;
3060 break;
3061
3062 case LIS2DTW12_FF_TSH_10LSb_FS2g:
3063 *val = LIS2DTW12_FF_TSH_10LSb_FS2g;
3064 break;
3065
3066 case LIS2DTW12_FF_TSH_11LSb_FS2g:
3067 *val = LIS2DTW12_FF_TSH_11LSb_FS2g;
3068 break;
3069
3070 case LIS2DTW12_FF_TSH_13LSb_FS2g:
3071 *val = LIS2DTW12_FF_TSH_13LSb_FS2g;
3072 break;
3073
3074 case LIS2DTW12_FF_TSH_15LSb_FS2g:
3075 *val = LIS2DTW12_FF_TSH_15LSb_FS2g;
3076 break;
3077
3078 case LIS2DTW12_FF_TSH_16LSb_FS2g:
3079 *val = LIS2DTW12_FF_TSH_16LSb_FS2g;
3080 break;
3081
3082 default:
3083 *val = LIS2DTW12_FF_TSH_5LSb_FS2g;
3084 break;
3085 }
3086
3087 return ret;
3088 }
3089
3090 /**
3091 * @}
3092 *
3093 */
3094
3095 /**
3096 * @defgroup LIS2DTW12_Fifo
3097 * @brief This section group all the functions concerning the fifo usage
3098 * @{
3099 *
3100 */
3101
3102 /**
3103 * @brief FIFO watermark level selection.[set]
3104 *
3105 * @param ctx read / write interface definitions
3106 * @param val change the values of fth in reg FIFO_CTRL
3107 * @retval interface status (MANDATORY: return 0 -> no Error)
3108 *
3109 */
lis2dtw12_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3110 int32_t lis2dtw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3111 {
3112 lis2dtw12_fifo_ctrl_t reg;
3113 int32_t ret;
3114
3115 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3116
3117 if (ret == 0)
3118 {
3119 reg.fth = val;
3120 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3121 }
3122
3123 return ret;
3124 }
3125
3126 /**
3127 * @brief FIFO watermark level selection.[get]
3128 *
3129 * @param ctx read / write interface definitions
3130 * @param val change the values of fth in reg FIFO_CTRL
3131 * @retval interface status (MANDATORY: return 0 -> no Error)
3132 *
3133 */
lis2dtw12_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3134 int32_t lis2dtw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3135 {
3136 lis2dtw12_fifo_ctrl_t reg;
3137 int32_t ret;
3138
3139 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3140 *val = reg.fth;
3141
3142 return ret;
3143 }
3144
3145 /**
3146 * @brief FIFO mode selection.[set]
3147 *
3148 * @param ctx read / write interface definitions
3149 * @param val change the values of fmode in reg FIFO_CTRL
3150 * @retval interface status (MANDATORY: return 0 -> no Error)
3151 *
3152 */
lis2dtw12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2dtw12_fmode_t val)3153 int32_t lis2dtw12_fifo_mode_set(const stmdev_ctx_t *ctx,
3154 lis2dtw12_fmode_t val)
3155 {
3156 lis2dtw12_fifo_ctrl_t reg;
3157 int32_t ret;
3158
3159 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3160
3161 if (ret == 0)
3162 {
3163 reg.fmode = (uint8_t) val;
3164 ret = lis2dtw12_write_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3165 }
3166
3167 return ret;
3168 }
3169
3170 /**
3171 * @brief FIFO mode selection.[get]
3172 *
3173 * @param ctx read / write interface definitions
3174 * @param val Get the values of fmode in reg FIFO_CTRL
3175 * @retval interface status (MANDATORY: return 0 -> no Error)
3176 *
3177 */
lis2dtw12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2dtw12_fmode_t * val)3178 int32_t lis2dtw12_fifo_mode_get(const stmdev_ctx_t *ctx,
3179 lis2dtw12_fmode_t *val)
3180 {
3181 lis2dtw12_fifo_ctrl_t reg;
3182 int32_t ret;
3183
3184 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1);
3185
3186 switch (reg.fmode)
3187 {
3188 case LIS2DTW12_BYPASS_MODE:
3189 *val = LIS2DTW12_BYPASS_MODE;
3190 break;
3191
3192 case LIS2DTW12_FIFO_MODE:
3193 *val = LIS2DTW12_FIFO_MODE;
3194 break;
3195
3196 case LIS2DTW12_STREAM_TO_FIFO_MODE:
3197 *val = LIS2DTW12_STREAM_TO_FIFO_MODE;
3198 break;
3199
3200 case LIS2DTW12_BYPASS_TO_STREAM_MODE:
3201 *val = LIS2DTW12_BYPASS_TO_STREAM_MODE;
3202 break;
3203
3204 case LIS2DTW12_STREAM_MODE:
3205 *val = LIS2DTW12_STREAM_MODE;
3206 break;
3207
3208 default:
3209 *val = LIS2DTW12_BYPASS_MODE;
3210 break;
3211 }
3212
3213 return ret;
3214 }
3215
3216 /**
3217 * @brief Number of unread samples stored in FIFO.[get]
3218 *
3219 * @param ctx read / write interface definitions
3220 * @param val change the values of diff in reg FIFO_SAMPLES
3221 * @retval interface status (MANDATORY: return 0 -> no Error)
3222 *
3223 */
lis2dtw12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)3224 int32_t lis2dtw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
3225 {
3226 lis2dtw12_fifo_samples_t reg;
3227 int32_t ret;
3228
3229 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
3230 (uint8_t *) ®, 1);
3231 *val = reg.diff;
3232
3233 return ret;
3234 }
3235 /**
3236 * @brief FIFO overrun status.[get]
3237 *
3238 * @param ctx read / write interface definitions
3239 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
3240 * @retval interface status (MANDATORY: return 0 -> no Error)
3241 *
3242 */
lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3243 int32_t lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3244 {
3245 lis2dtw12_fifo_samples_t reg;
3246 int32_t ret;
3247
3248 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
3249 (uint8_t *) ®, 1);
3250 *val = reg.fifo_ovr;
3251
3252 return ret;
3253 }
3254 /**
3255 * @brief FIFO threshold status flag.[get]
3256 *
3257 * @param ctx read / write interface definitions
3258 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
3259 * @retval interface status (MANDATORY: return 0 -> no Error)
3260 *
3261 */
lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3262 int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3263 {
3264 lis2dtw12_fifo_samples_t reg;
3265 int32_t ret;
3266
3267 ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES,
3268 (uint8_t *) ®, 1);
3269 *val = reg.fifo_fth;
3270
3271 return ret;
3272 }
3273 /**
3274 * @}
3275 *
3276 */
3277
3278 /**
3279 * @}
3280 *
3281 */
3282
3283
3284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3285
