1 /**
2 ******************************************************************************
3 * @file lis2ds12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DS12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2ds12_reg.h"
21
22 /**
23 * @defgroup LIS2DS12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2ds12 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DS12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2ds12_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2ds12_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2DS12_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis2ds12_from_fs2g_to_mg(int16_t lsb)93 float_t lis2ds12_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lis2ds12_from_fs4g_to_mg(int16_t lsb)98 float_t lis2ds12_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lis2ds12_from_fs8g_to_mg(int16_t lsb)103 float_t lis2ds12_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lis2ds12_from_fs16g_to_mg(int16_t lsb)108 float_t lis2ds12_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lis2ds12_from_lsb_to_celsius(int16_t lsb)113 float_t lis2ds12_from_lsb_to_celsius(int16_t lsb)
114 {
115 return (((float_t)lsb / 256.0f) + 25.0f);
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup Data generation
125 * @brief This section groups all the functions concerning
126 * data generation
127 * @{
128 *
129 */
130
131 /**
132 * @brief Read all the interrupt/status flag of the device.[get]
133 *
134 * @param ctx read / write interface definitions.(ptr)
135 * @param val Get FIFO_SRC, STATUS_DUP, WAKE_UP_SRC, TAP_SRC,
136 * 6D_SRC, FUNC_CK_GATE, FUNC_SRC.(ptr)
137 *
138 */
lis2ds12_all_sources_get(stmdev_ctx_t * ctx,lis2ds12_all_sources_t * val)139 int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx,
140 lis2ds12_all_sources_t *val)
141 {
142 int32_t ret;
143
144 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC,
145 (uint8_t *) & (val->fifo_src), 1);
146
147 if (ret == 0)
148 {
149 ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS_DUP,
150 (uint8_t *) & (val->status_dup), 1);
151 }
152
153 if (ret == 0)
154 {
155 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_SRC,
156 (uint8_t *) & (val->wake_up_src), 1);
157 }
158
159 if (ret == 0)
160 {
161 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_SRC,
162 (uint8_t *) & (val->tap_src), 1);
163 }
164
165 if (ret == 0)
166 {
167 ret = lis2ds12_read_reg(ctx, LIS2DS12_6D_SRC,
168 (uint8_t *) & (val->_6d_src), 1);
169 }
170
171 if (ret == 0)
172 {
173 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
174 (uint8_t *) & (val->func_ck_gate), 1);
175 }
176
177 if (ret == 0)
178 {
179 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC,
180 (uint8_t *) & (val->func_src), 1);
181 }
182
183 return ret;
184 }
185
186 /**
187 * @brief Blockdataupdate.[set]
188 *
189 * @param ctx read / write interface definitions.(ptr)
190 * @param val change the values of bdu in reg CTRL1
191 * @retval Interface status (MANDATORY: return 0 -> no Error).
192 *
193 */
lis2ds12_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)194 int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
195 {
196 lis2ds12_ctrl1_t ctrl1;
197 int32_t ret;
198
199 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
200
201 if (ret == 0)
202 {
203 ctrl1.bdu = val;
204 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
205 }
206
207 return ret;
208 }
209
210 /**
211 * @brief Blockdataupdate.[get]
212 *
213 * @param ctx read / write interface definitions.(ptr)
214 * @param val get the values of bdu in reg CTRL1(ptr)
215 * @retval Interface status (MANDATORY: return 0 -> no Error).
216 *
217 */
lis2ds12_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)218 int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx,
219 uint8_t *val)
220 {
221 lis2ds12_ctrl1_t ctrl1;
222 int32_t ret;
223
224 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
225 *val = ctrl1.bdu;
226
227 return ret;
228 }
229
230 /**
231 * @brief Accelerometer full-scale selection.[set]
232 *
233 * @param ctx read / write interface definitions.(ptr)
234 * @param val change the values of fs in reg CTRL1
235 * @retval Interface status (MANDATORY: return 0 -> no Error).
236 *
237 */
lis2ds12_xl_full_scale_set(stmdev_ctx_t * ctx,lis2ds12_fs_t val)238 int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx,
239 lis2ds12_fs_t val)
240 {
241 lis2ds12_ctrl1_t ctrl1;
242 int32_t ret;
243
244 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
245
246 if (ret == 0)
247 {
248 ctrl1.fs = (uint8_t)val;
249 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
250 }
251
252 return ret;
253 }
254
255 /**
256 * @brief Accelerometer full-scale selection.[get]
257 *
258 * @param ctx read / write interface definitions.(ptr)
259 * @param val Get the values of fs in reg CTRL1(ptr)
260 * @retval Interface status (MANDATORY: return 0 -> no Error).
261 *
262 */
lis2ds12_xl_full_scale_get(stmdev_ctx_t * ctx,lis2ds12_fs_t * val)263 int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx,
264 lis2ds12_fs_t *val)
265 {
266 lis2ds12_ctrl1_t ctrl1;
267 int32_t ret;
268
269 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
270
271 switch (ctrl1.fs)
272 {
273 case LIS2DS12_2g:
274 *val = LIS2DS12_2g;
275 break;
276
277 case LIS2DS12_16g:
278 *val = LIS2DS12_16g;
279 break;
280
281 case LIS2DS12_4g:
282 *val = LIS2DS12_4g;
283 break;
284
285 case LIS2DS12_8g:
286 *val = LIS2DS12_8g;
287 break;
288
289 default:
290 *val = LIS2DS12_2g;
291 break;
292 }
293
294 return ret;
295 }
296
297 /**
298 * @brief Accelerometer data rate selection.[set]
299 *
300 * @param ctx read / write interface definitions.(ptr)
301 * @param val change the values of odr in reg CTRL1
302 * @retval Interface status (MANDATORY: return 0 -> no Error).
303 *
304 */
lis2ds12_xl_data_rate_set(stmdev_ctx_t * ctx,lis2ds12_odr_t val)305 int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx,
306 lis2ds12_odr_t val)
307 {
308 lis2ds12_ctrl1_t ctrl1;
309 int32_t ret;
310
311 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
312
313 if (ret == 0)
314 {
315 ctrl1.odr = (uint8_t)val & 0x0FU;
316 ctrl1.hf_odr = ((uint8_t)val & 0x10U) >> 4;
317 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
318 }
319
320 return ret;
321 }
322
323 /**
324 * @brief Accelerometer data rate selection.[get]
325 *
326 * @param ctx read / write interface definitions.(ptr)
327 * @param val Get the values of odr in reg CTRL1(ptr)
328 * @retval Interface status (MANDATORY: return 0 -> no Error).
329 *
330 */
lis2ds12_xl_data_rate_get(stmdev_ctx_t * ctx,lis2ds12_odr_t * val)331 int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx,
332 lis2ds12_odr_t *val)
333 {
334 lis2ds12_ctrl1_t ctrl1;
335 int32_t ret;
336
337 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1);
338
339 switch ((ctrl1.hf_odr << 4) + ctrl1.odr)
340 {
341 case LIS2DS12_XL_ODR_OFF:
342 *val = LIS2DS12_XL_ODR_OFF;
343 break;
344
345 case LIS2DS12_XL_ODR_1Hz_LP:
346 *val = LIS2DS12_XL_ODR_1Hz_LP;
347 break;
348
349 case LIS2DS12_XL_ODR_12Hz5_LP:
350 *val = LIS2DS12_XL_ODR_12Hz5_LP;
351 break;
352
353 case LIS2DS12_XL_ODR_25Hz_LP:
354 *val = LIS2DS12_XL_ODR_25Hz_LP;
355 break;
356
357 case LIS2DS12_XL_ODR_50Hz_LP:
358 *val = LIS2DS12_XL_ODR_50Hz_LP;
359 break;
360
361 case LIS2DS12_XL_ODR_100Hz_LP:
362 *val = LIS2DS12_XL_ODR_100Hz_LP;
363 break;
364
365 case LIS2DS12_XL_ODR_200Hz_LP:
366 *val = LIS2DS12_XL_ODR_200Hz_LP;
367 break;
368
369 case LIS2DS12_XL_ODR_400Hz_LP:
370 *val = LIS2DS12_XL_ODR_400Hz_LP;
371 break;
372
373 case LIS2DS12_XL_ODR_800Hz_LP:
374 *val = LIS2DS12_XL_ODR_800Hz_LP;
375 break;
376
377 case LIS2DS12_XL_ODR_12Hz5_HR:
378 *val = LIS2DS12_XL_ODR_12Hz5_HR;
379 break;
380
381 case LIS2DS12_XL_ODR_25Hz_HR:
382 *val = LIS2DS12_XL_ODR_25Hz_HR;
383 break;
384
385 case LIS2DS12_XL_ODR_50Hz_HR:
386 *val = LIS2DS12_XL_ODR_50Hz_HR;
387 break;
388
389 case LIS2DS12_XL_ODR_100Hz_HR:
390 *val = LIS2DS12_XL_ODR_100Hz_HR;
391 break;
392
393 case LIS2DS12_XL_ODR_200Hz_HR:
394 *val = LIS2DS12_XL_ODR_200Hz_HR;
395 break;
396
397 case LIS2DS12_XL_ODR_400Hz_HR:
398 *val = LIS2DS12_XL_ODR_400Hz_HR;
399 break;
400
401 case LIS2DS12_XL_ODR_800Hz_HR:
402 *val = LIS2DS12_XL_ODR_800Hz_HR;
403 break;
404
405 case LIS2DS12_XL_ODR_1k6Hz_HF:
406 *val = LIS2DS12_XL_ODR_1k6Hz_HF;
407 break;
408
409 case LIS2DS12_XL_ODR_3k2Hz_HF:
410 *val = LIS2DS12_XL_ODR_3k2Hz_HF;
411 break;
412
413 case LIS2DS12_XL_ODR_6k4Hz_HF:
414 *val = LIS2DS12_XL_ODR_6k4Hz_HF;
415 break;
416
417 default:
418 *val = LIS2DS12_XL_ODR_OFF;
419 break;
420 }
421
422 return ret;
423 }
424
425 /**
426 * @brief The STATUS_REG register.[get]
427 *
428 * @param ctx read / write interface definitions.(ptr)
429 * @param val Get registers STATUS.(ptr)
430 * @retval Interface status (MANDATORY: return 0 -> no Error).
431 *
432 */
lis2ds12_status_reg_get(stmdev_ctx_t * ctx,lis2ds12_status_t * val)433 int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx,
434 lis2ds12_status_t *val)
435 {
436 int32_t ret;
437
438 ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t *) val, 1);
439
440 return ret;
441 }
442
443 /**
444 * @brief Accelerometer new data available.[get]
445 *
446 * @param ctx read / write interface definitions.(ptr)
447 * @param val get the values of drdy in reg STATUS.(ptr)
448 * @retval Interface status (MANDATORY: return 0 -> no Error).
449 *
450 */
lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)451 int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
452 uint8_t *val)
453 {
454 lis2ds12_status_t status;
455 int32_t ret;
456
457 ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t *)&status, 1);
458 *val = status.drdy;
459
460 return ret;
461 }
462
463 /**
464 * @}
465 *
466 */
467
468 /**
469 * @defgroup Data output
470 * @brief This section groups all the data output functions.
471 * @{
472 *
473 */
474
475 /**
476 * @brief Module output value (8-bit).[get]
477 *
478 * @param ctx read / write interface definitions.(ptr)
479 * @param buff buffer that stores data read.(ptr)
480 * @retval Interface status (MANDATORY: return 0 -> no Error).
481 *
482 */
lis2ds12_acceleration_module_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)483 int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx,
484 uint8_t *buff)
485 {
486 int32_t ret;
487
488 ret = lis2ds12_read_reg(ctx, LIS2DS12_MODULE_8BIT, buff, 1);
489
490 return ret;
491 }
492
493 /**
494 * @brief Temperature data output register (r). L and H registers together
495 * express a 16-bit word in two’s complement.[get]
496 *
497 * @param ctx read / write interface definitions.(ptr)
498 * @param buff buffer that stores data read.(ptr)
499 * @retval Interface status (MANDATORY: return 0 -> no Error).
500 *
501 */
lis2ds12_temperature_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)502 int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
503 {
504 int32_t ret;
505
506 ret = lis2ds12_read_reg(ctx, LIS2DS12_OUT_T, buff, 1);
507
508 return ret;
509 }
510
511 /**
512 * @brief Linear acceleration output register. The value is expressed as a
513 * 16-bit word in two’s complement.[get]
514 *
515 * @param ctx read / write interface definitions.(ptr)
516 * @param buff buffer that stores data read.(ptr)
517 * @retval Interface status (MANDATORY: return 0 -> no Error).
518 *
519 */
lis2ds12_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)520 int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
521 {
522 uint8_t buff[6];
523 int32_t ret;
524
525 ret = lis2ds12_read_reg(ctx, LIS2DS12_OUT_X_L, buff, 6);
526 val[0] = (int16_t)buff[1];
527 val[0] = (val[0] * 256) + (int16_t)buff[0];
528 val[1] = (int16_t)buff[3];
529 val[1] = (val[1] * 256) + (int16_t)buff[2];
530 val[2] = (int16_t)buff[5];
531 val[2] = (val[2] * 256) + (int16_t)buff[4];
532
533 return ret;
534 }
535
536 /**
537 * @brief Number of steps detected by step counter routine.[get]
538 *
539 * @param ctx read / write interface definitions.(ptr)
540 * @param buff buffer that stores data read.(ptr)
541 * @retval Interface status (MANDATORY: return 0 -> no Error).
542 *
543 */
lis2ds12_number_of_steps_get(stmdev_ctx_t * ctx,int16_t * val)544 int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val)
545 {
546 uint8_t buff[2];
547 int32_t ret;
548
549 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_L, buff, 2);
550 *val = (int16_t)buff[1];
551 *val = (*val * 256) + (int16_t)buff[0];
552
553 return ret;
554 }
555
556 /**
557 * @}
558 *
559 */
560
561 /**
562 * @defgroup Common
563 * @brief This section groups common useful functions.
564 * @{
565 *
566 */
567
568 /**
569 * @brief DeviceWhoamI.[get]
570 *
571 * @param ctx read / write interface definitions.(ptr)
572 * @param buff buffer that stores data read.(ptr)
573 * @retval Interface status (MANDATORY: return 0 -> no Error).
574 *
575 */
lis2ds12_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)576 int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
577 {
578 int32_t ret;
579
580 ret = lis2ds12_read_reg(ctx, LIS2DS12_WHO_AM_I, buff, 1);
581
582 return ret;
583 }
584
585 /**
586 * @brief Register address automatically incremented during a multiple byte
587 * access with a serial interface.[set]
588 *
589 * @param ctx read / write interface definitions.(ptr)
590 * @param val change the values of if_add_inc in reg CTRL2
591 * @retval Interface status (MANDATORY: return 0 -> no Error).
592 *
593 */
lis2ds12_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)594 int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
595 {
596 lis2ds12_ctrl2_t ctrl2;
597 int32_t ret;
598
599 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
600
601 if (ret == 0)
602 {
603 ctrl2.if_add_inc = val;
604 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
605 }
606
607 return ret;
608 }
609
610 /**
611 * @brief Register address automatically incremented during a multiple byte
612 * access with a serial interface.[get]
613 *
614 * @param ctx read / write interface definitions.(ptr)
615 * @param val Get the values of if_add_inc in reg CTRL2.(ptr)
616 * @retval Interface status (MANDATORY: return 0 -> no Error).
617 *
618 */
lis2ds12_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)619 int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
620 {
621 lis2ds12_ctrl2_t ctrl2;
622 int32_t ret;
623
624 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
625 *val = ctrl2.if_add_inc;
626
627 return ret;
628 }
629
630 /**
631 * @brief Enable access to the embedded functions/sensor hub configuration
632 * registers.[set]
633 *
634 * @param ctx read / write interface definitions.(ptr)
635 * @param val change the values of func_cfg_en in reg CTRL2
636 * @retval Interface status (MANDATORY: return 0 -> no Error).
637 *
638 */
lis2ds12_mem_bank_set(stmdev_ctx_t * ctx,lis2ds12_func_cfg_en_t val)639 int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx,
640 lis2ds12_func_cfg_en_t val)
641 {
642 lis2ds12_ctrl2_t ctrl2;
643 lis2ds12_ctrl2_adv_t ctrl2_adv;
644 int32_t ret;
645
646
647 if (val == LIS2DS12_ADV_BANK)
648 {
649 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
650
651 if (ret == 0)
652 {
653 ctrl2.func_cfg_en = (uint8_t)val;
654 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
655 }
656 }
657
658 else
659 {
660 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2_ADV,
661 (uint8_t *)&ctrl2_adv, 1);
662
663 if (ret == 0)
664 {
665 ctrl2_adv.func_cfg_en = (uint8_t)val;
666 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2_ADV,
667 (uint8_t *)&ctrl2_adv, 1);
668 }
669 }
670
671 return ret;
672 }
673
674 /**
675 * @brief Software reset. Restore the default values in
676 * user registers.[set]
677 *
678 * @param ctx read / write interface definitions.(ptr)
679 * @param val change the values of soft_reset in reg CTRL2
680 * @retval Interface status (MANDATORY: return 0 -> no Error).
681 *
682 */
lis2ds12_reset_set(stmdev_ctx_t * ctx,uint8_t val)683 int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val)
684 {
685 lis2ds12_ctrl2_t ctrl2;
686 int32_t ret;
687
688 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
689
690 if (ret == 0)
691 {
692 ctrl2.soft_reset = val;
693 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
694 }
695
696 return ret;
697 }
698
699 /**
700 * @brief Software reset. Restore the default values
701 * in user registers.[get]
702 *
703 * @param ctx read / write interface definitions.(ptr)
704 * @param val get the values of soft_reset in reg CTRL2.(ptr)
705 * @retval Interface status (MANDATORY: return 0 -> no Error).
706 *
707 */
lis2ds12_reset_get(stmdev_ctx_t * ctx,uint8_t * val)708 int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
709 {
710 lis2ds12_ctrl2_t ctrl2;
711 int32_t ret;
712
713 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
714 *val = ctrl2.soft_reset;
715
716 return ret;
717 }
718
719 /**
720 * @brief Reboot memory content. Reload the calibration parameters.[set]
721 *
722 * @param ctx read / write interface definitions.(ptr)
723 * @param val change the values of boot in reg CTRL2
724 * @retval Interface status (MANDATORY: return 0 -> no Error).
725 *
726 */
lis2ds12_boot_set(stmdev_ctx_t * ctx,uint8_t val)727 int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
728 {
729 lis2ds12_ctrl2_t ctrl2;
730 int32_t ret;
731
732 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
733
734 if (ret == 0)
735 {
736 ctrl2.boot = val;
737 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
738 }
739
740 return ret;
741 }
742
743 /**
744 * @brief Reboot memory content. Reload the calibration parameters.[get]
745 *
746 * @param ctx read / write interface definitions.(ptr)
747 * @param val get the values of boot in reg CTRL2.(ptr)
748 * @retval Interface status (MANDATORY: return 0 -> no Error).
749 *
750 */
lis2ds12_boot_get(stmdev_ctx_t * ctx,uint8_t * val)751 int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
752 {
753 lis2ds12_ctrl2_t ctrl2;
754 int32_t ret;
755
756 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
757 *val = ctrl2.boot;
758
759 return ret;
760 }
761
762 /**
763 * @brief xl_self_test: [set]
764 *
765 * @param ctx read / write interface definitions.(ptr)
766 * @param val change the values of st in reg CTRL3
767 * @retval Interface status (MANDATORY: return 0 -> no Error).
768 *
769 */
lis2ds12_xl_self_test_set(stmdev_ctx_t * ctx,lis2ds12_st_t val)770 int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx,
771 lis2ds12_st_t val)
772 {
773 lis2ds12_ctrl3_t ctrl3;
774 int32_t ret;
775
776 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
777
778 if (ret == 0)
779 {
780 ctrl3.st = (uint8_t)val;
781 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
782 }
783
784 return ret;
785 }
786
787 /**
788 * @brief xl_self_test [get]
789 *
790 * @param ctx read / write interface definitions.(ptr)
791 * @param val Get the values of st in reg CTRL3.(ptr)
792 * @retval Interface status (MANDATORY: return 0 -> no Error).
793 *
794 */
lis2ds12_xl_self_test_get(stmdev_ctx_t * ctx,lis2ds12_st_t * val)795 int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx,
796 lis2ds12_st_t *val)
797 {
798 lis2ds12_ctrl3_t ctrl3;
799 int32_t ret;
800
801 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
802
803 switch (ctrl3.st)
804 {
805 case LIS2DS12_XL_ST_DISABLE:
806 *val = LIS2DS12_XL_ST_DISABLE;
807 break;
808
809 case LIS2DS12_XL_ST_POSITIVE:
810 *val = LIS2DS12_XL_ST_POSITIVE;
811 break;
812
813 case LIS2DS12_XL_ST_NEGATIVE:
814 *val = LIS2DS12_XL_ST_NEGATIVE;
815 break;
816
817 default:
818 *val = LIS2DS12_XL_ST_DISABLE;
819 break;
820 }
821
822 return ret;
823 }
824
825 /**
826 * @brief data_ready_mode [set]
827 *
828 * @param ctx read / write interface definitions.(ptr)
829 * @param val change the values of drdy_pulsed in reg CTRL5
830 * @retval Interface status (MANDATORY: return 0 -> no Error).
831 *
832 */
lis2ds12_data_ready_mode_set(stmdev_ctx_t * ctx,lis2ds12_drdy_pulsed_t val)833 int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx,
834 lis2ds12_drdy_pulsed_t val)
835 {
836 lis2ds12_ctrl5_t ctrl5;
837 int32_t ret;
838
839 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
840
841 if (ret == 0)
842 {
843 ctrl5.drdy_pulsed = (uint8_t)val;
844 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
845 }
846
847 return ret;
848 }
849
850 /**
851 * @brief data_ready_mode: [get]
852 *
853 * @param ctx read / write interface definitions.(ptr)
854 * @param val Get the values of drdy_pulsed in reg CTRL5.(ptr)
855 * @retval Interface status (MANDATORY: return 0 -> no Error).
856 *
857 */
lis2ds12_data_ready_mode_get(stmdev_ctx_t * ctx,lis2ds12_drdy_pulsed_t * val)858 int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx,
859 lis2ds12_drdy_pulsed_t *val)
860 {
861 lis2ds12_ctrl5_t ctrl5;
862 int32_t ret;
863
864 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
865
866 switch (ctrl5.drdy_pulsed)
867 {
868 case LIS2DS12_DRDY_LATCHED:
869 *val = LIS2DS12_DRDY_LATCHED;
870 break;
871
872 case LIS2DS12_DRDY_PULSED:
873 *val = LIS2DS12_DRDY_PULSED;
874 break;
875
876 default:
877 *val = LIS2DS12_DRDY_LATCHED;
878 break;
879 }
880
881 return ret;
882 }
883
884 /**
885 * @}
886 *
887 */
888
889 /**
890 * @defgroup Filters
891 * @brief This section group all the functions concerning the filters
892 * configuration.
893 * @{
894 *
895 */
896
897 /**
898 * @brief High-pass filter data selection on output register and FIFO.[set]
899 *
900 * @param ctx read / write interface definitions.(ptr)
901 * @param val change the values of fds_slope in reg CTRL2
902 * @retval Interface status (MANDATORY: return 0 -> no Error).
903 *
904 */
lis2ds12_xl_hp_path_set(stmdev_ctx_t * ctx,lis2ds12_fds_slope_t val)905 int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx,
906 lis2ds12_fds_slope_t val)
907 {
908 lis2ds12_ctrl2_t ctrl2;
909 int32_t ret;
910
911 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
912
913 if (ret == 0)
914 {
915 ctrl2.fds_slope = (uint8_t)val;
916 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
917 }
918
919 return ret;
920 }
921
922 /**
923 * @brief High-pass filter data selection on output register and FIFO.[get]
924 *
925 * @param ctx read / write interface definitions.(ptr)
926 * @param val Get the values of fds_slope in reg CTRL2.(ptr)
927 * @retval Interface status (MANDATORY: return 0 -> no Error).
928 *
929 */
lis2ds12_xl_hp_path_get(stmdev_ctx_t * ctx,lis2ds12_fds_slope_t * val)930 int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx,
931 lis2ds12_fds_slope_t *val)
932 {
933 lis2ds12_ctrl2_t ctrl2;
934 int32_t ret;
935
936 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
937
938 switch (ctrl2.fds_slope)
939 {
940 case LIS2DS12_HP_INTERNAL_ONLY:
941 *val = LIS2DS12_HP_INTERNAL_ONLY;
942 break;
943
944 case LIS2DS12_HP_ON_OUTPUTS:
945 *val = LIS2DS12_HP_ON_OUTPUTS;
946 break;
947
948 default:
949 *val = LIS2DS12_HP_INTERNAL_ONLY;
950 break;
951 }
952
953 return ret;
954 }
955
956 /**
957 * @}
958 *
959 */
960
961 /**
962 * @defgroup Auxiliary_interface
963 * @brief This section groups all the functions concerning auxiliary
964 * interface.
965 * @{
966 *
967 */
968
969 /**
970 * @brief SPI Serial Interface Mode selection.[set]
971 *
972 * @param ctx read / write interface definitions.(ptr)
973 * @param val change the values of sim in reg CTRL2
974 * @retval Interface status (MANDATORY: return 0 -> no Error).
975 *
976 */
lis2ds12_spi_mode_set(stmdev_ctx_t * ctx,lis2ds12_sim_t val)977 int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val)
978 {
979 lis2ds12_ctrl2_t ctrl2;
980 int32_t ret;
981
982 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
983
984 if (ret == 0)
985 {
986 ctrl2.sim = (uint8_t)val;
987 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
988 }
989
990 return ret;
991 }
992
993 /**
994 * @brief SPI Serial Interface Mode selection.[get]
995 *
996 * @param ctx read / write interface definitions.(ptr)
997 * @param val Get the values of sim in reg CTRL2.(ptr)
998 * @retval Interface status (MANDATORY: return 0 -> no Error).
999 *
1000 */
lis2ds12_spi_mode_get(stmdev_ctx_t * ctx,lis2ds12_sim_t * val)1001 int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val)
1002 {
1003 lis2ds12_ctrl2_t ctrl2;
1004 int32_t ret;
1005
1006 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
1007
1008 switch (ctrl2.sim)
1009 {
1010 case LIS2DS12_SPI_4_WIRE:
1011 *val = LIS2DS12_SPI_4_WIRE;
1012 break;
1013
1014 case LIS2DS12_SPI_3_WIRE:
1015 *val = LIS2DS12_SPI_3_WIRE;
1016 break;
1017
1018 default:
1019 *val = LIS2DS12_SPI_4_WIRE;
1020 break;
1021 }
1022
1023 return ret;
1024 }
1025
1026 /**
1027 * @brief Disable / Enable I2C interface.[set]
1028 *
1029 * @param ctx read / write interface definitions.(ptr)
1030 * @param val change the values of i2c_disable in reg CTRL2
1031 * @retval Interface status (MANDATORY: return 0 -> no Error).
1032 *
1033 */
lis2ds12_i2c_interface_set(stmdev_ctx_t * ctx,lis2ds12_i2c_disable_t val)1034 int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx,
1035 lis2ds12_i2c_disable_t val)
1036 {
1037 lis2ds12_ctrl2_t ctrl2;
1038 int32_t ret;
1039
1040 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
1041
1042 if (ret == 0)
1043 {
1044 ctrl2.i2c_disable = (uint8_t)val;
1045 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
1046 }
1047
1048 return ret;
1049 }
1050
1051 /**
1052 * @brief Disable / Enable I2C interface.[get]
1053 *
1054 * @param ctx read / write interface definitions.(ptr)
1055 * @param val Get the values of i2c_disable in reg CTRL2.(ptr)
1056 * @retval Interface status (MANDATORY: return 0 -> no Error).
1057 *
1058 */
lis2ds12_i2c_interface_get(stmdev_ctx_t * ctx,lis2ds12_i2c_disable_t * val)1059 int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx,
1060 lis2ds12_i2c_disable_t *val)
1061 {
1062 lis2ds12_ctrl2_t ctrl2;
1063 int32_t ret;
1064
1065 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1);
1066
1067 switch (ctrl2.i2c_disable)
1068 {
1069 case LIS2DS12_I2C_ENABLE:
1070 *val = LIS2DS12_I2C_ENABLE;
1071 break;
1072
1073 case LIS2DS12_I2C_DISABLE:
1074 *val = LIS2DS12_I2C_DISABLE;
1075 break;
1076
1077 default:
1078 *val = LIS2DS12_I2C_ENABLE;
1079 break;
1080 }
1081
1082 return ret;
1083 }
1084
1085 /**
1086 * @brief Connect/Disconnects pull-up in if_cs pad.[set]
1087 *
1088 * @param ctx read / write interface definitions.(ptr)
1089 * @param val change the values of if_cs_pu_dis in reg FIFO_CTRL
1090 * @retval Interface status (MANDATORY: return 0 -> no Error).
1091 *
1092 */
lis2ds12_cs_mode_set(stmdev_ctx_t * ctx,lis2ds12_if_cs_pu_dis_t val)1093 int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx,
1094 lis2ds12_if_cs_pu_dis_t val)
1095 {
1096 lis2ds12_fifo_ctrl_t fifo_ctrl;
1097 int32_t ret;
1098
1099 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
1100 (uint8_t *)&fifo_ctrl, 1);
1101
1102 if (ret == 0)
1103 {
1104 fifo_ctrl.if_cs_pu_dis = (uint8_t)val;
1105 ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
1106 (uint8_t *)&fifo_ctrl, 1);
1107 }
1108
1109 return ret;
1110 }
1111
1112 /**
1113 * @brief Connect/Disconnects pull-up in if_cs pad.[get]
1114 *
1115 * @param ctx read / write interface definitions.(ptr)
1116 * @param val Get the values of if_cs_pu_dis in reg FIFO_CTRL.(ptr)
1117 * @retval Interface status (MANDATORY: return 0 -> no Error).
1118 *
1119 */
lis2ds12_cs_mode_get(stmdev_ctx_t * ctx,lis2ds12_if_cs_pu_dis_t * val)1120 int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx,
1121 lis2ds12_if_cs_pu_dis_t *val)
1122 {
1123 lis2ds12_fifo_ctrl_t fifo_ctrl;
1124 int32_t ret;
1125
1126 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
1127 (uint8_t *)&fifo_ctrl, 1);
1128
1129 switch (fifo_ctrl.if_cs_pu_dis)
1130 {
1131 case LIS2DS12_PULL_UP_CONNECTED:
1132 *val = LIS2DS12_PULL_UP_CONNECTED;
1133 break;
1134
1135 case LIS2DS12_PULL_UP_DISCONNECTED:
1136 *val = LIS2DS12_PULL_UP_DISCONNECTED;
1137 break;
1138
1139 default:
1140 *val = LIS2DS12_PULL_UP_CONNECTED;
1141 break;
1142 }
1143
1144 return ret;
1145 }
1146
1147 /**
1148 * @}
1149 *
1150 */
1151
1152 /**
1153 * @defgroup Serial Interface
1154 * @brief This section groups all the functions concerning main serial
1155 * interface management (not auxiliary)
1156 * @{
1157 *
1158 */
1159
1160 /**
1161 * @brief Push-pull/open-drain selection on interrupt pad.[set]
1162 *
1163 * @param ctx read / write interface definitions.(ptr)
1164 * @param val change the values of pp_od in reg CTRL3
1165 * @retval Interface status (MANDATORY: return 0 -> no Error).
1166 *
1167 */
lis2ds12_pin_mode_set(stmdev_ctx_t * ctx,lis2ds12_pp_od_t val)1168 int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val)
1169 {
1170 lis2ds12_ctrl3_t ctrl3;
1171 int32_t ret;
1172
1173 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1174
1175 if (ret == 0)
1176 {
1177 ctrl3.pp_od = (uint8_t)val;
1178 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1179 }
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Push-pull/open-drain selection on interrupt pad.[get]
1186 *
1187 * @param ctx read / write interface definitions.(ptr)
1188 * @param val Get the values of pp_od in reg CTRL3.(ptr)
1189 * @retval Interface status (MANDATORY: return 0 -> no Error).
1190 *
1191 */
lis2ds12_pin_mode_get(stmdev_ctx_t * ctx,lis2ds12_pp_od_t * val)1192 int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx,
1193 lis2ds12_pp_od_t *val)
1194 {
1195 lis2ds12_ctrl3_t ctrl3;
1196 int32_t ret;
1197
1198 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1199
1200 switch (ctrl3.pp_od)
1201 {
1202 case LIS2DS12_PUSH_PULL:
1203 *val = LIS2DS12_PUSH_PULL;
1204 break;
1205
1206 case LIS2DS12_OPEN_DRAIN:
1207 *val = LIS2DS12_OPEN_DRAIN;
1208 break;
1209
1210 default:
1211 *val = LIS2DS12_PUSH_PULL;
1212 break;
1213 }
1214
1215 return ret;
1216 }
1217
1218 /**
1219 * @brief pin_polarity: Interrupt active-high/low.[set]
1220 *
1221 * @param ctx read / write interface definitions.(ptr)
1222 * @param val change the values of h_lactive in reg CTRL3
1223 * @retval Interface status (MANDATORY: return 0 -> no Error).
1224 *
1225 */
lis2ds12_pin_polarity_set(stmdev_ctx_t * ctx,lis2ds12_h_lactive_t val)1226 int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx,
1227 lis2ds12_h_lactive_t val)
1228 {
1229 lis2ds12_ctrl3_t ctrl3;
1230 int32_t ret;
1231
1232 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1233
1234 if (ret == 0)
1235 {
1236 ctrl3.h_lactive = (uint8_t)val;
1237 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1238 }
1239
1240 return ret;
1241 }
1242
1243 /**
1244 * @brief Interrupt active-high/low.[get]
1245 *
1246 * @param ctx read / write interface definitions.(ptr)
1247 * @param val Get the values of h_lactive in reg CTRL3.(ptr)
1248 * @retval Interface status (MANDATORY: return 0 -> no Error).
1249 *
1250 */
lis2ds12_pin_polarity_get(stmdev_ctx_t * ctx,lis2ds12_h_lactive_t * val)1251 int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx,
1252 lis2ds12_h_lactive_t *val)
1253 {
1254 lis2ds12_ctrl3_t ctrl3;
1255 int32_t ret;
1256
1257 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1258
1259 switch (ctrl3.h_lactive)
1260 {
1261 case LIS2DS12_ACTIVE_HIGH:
1262 *val = LIS2DS12_ACTIVE_HIGH;
1263 break;
1264
1265 case LIS2DS12_ACTIVE_LOW:
1266 *val = LIS2DS12_ACTIVE_LOW;
1267 break;
1268
1269 default:
1270 *val = LIS2DS12_ACTIVE_HIGH;
1271 break;
1272 }
1273
1274 return ret;
1275 }
1276
1277 /**
1278 * @brief Latched/pulsed interrupt.[set]
1279 *
1280 * @param ctx read / write interface definitions.(ptr)
1281 * @param val change the values of lir in reg CTRL3
1282 * @retval Interface status (MANDATORY: return 0 -> no Error).
1283 *
1284 */
lis2ds12_int_notification_set(stmdev_ctx_t * ctx,lis2ds12_lir_t val)1285 int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx,
1286 lis2ds12_lir_t val)
1287 {
1288 lis2ds12_ctrl3_t ctrl3;
1289 int32_t ret;
1290
1291 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1292
1293 if (ret == 0)
1294 {
1295 ctrl3.lir = (uint8_t)val;
1296 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1297 }
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * @brief Latched/pulsed interrupt.[get]
1304 *
1305 * @param ctx read / write interface definitions.(ptr)
1306 * @param val Get the values of lir in reg CTRL3.(ptr)
1307 * @retval Interface status (MANDATORY: return 0 -> no Error).
1308 *
1309 */
lis2ds12_int_notification_get(stmdev_ctx_t * ctx,lis2ds12_lir_t * val)1310 int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx,
1311 lis2ds12_lir_t *val)
1312 {
1313 lis2ds12_ctrl3_t ctrl3;
1314 int32_t ret;
1315
1316 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1317
1318 switch (ctrl3.lir)
1319 {
1320 case LIS2DS12_INT_PULSED:
1321 *val = LIS2DS12_INT_PULSED;
1322 break;
1323
1324 case LIS2DS12_INT_LATCHED:
1325 *val = LIS2DS12_INT_LATCHED;
1326 break;
1327
1328 default:
1329 *val = LIS2DS12_INT_PULSED;
1330 break;
1331 }
1332
1333 return ret;
1334 }
1335
1336 /**
1337 * @brief Select the signal that need to route on int1 pad.[set]
1338 *
1339 * @param ctx read / write interface definitions.(ptr)
1340 * @param val change union of registers from CTRL4 to
1341 * @retval Interface status (MANDATORY: return 0 -> no Error).
1342 *
1343 */
lis2ds12_pin_int1_route_set(stmdev_ctx_t * ctx,lis2ds12_pin_int1_route_t val)1344 int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx,
1345 lis2ds12_pin_int1_route_t val)
1346 {
1347 lis2ds12_wake_up_dur_t wake_up_dur;
1348 lis2ds12_ctrl4_t ctrl4;
1349 int32_t ret;
1350
1351 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
1352
1353 if (ret == 0)
1354 {
1355 ctrl4.int1_drdy = (uint8_t)val.int1_drdy;
1356 ctrl4.int1_fth = (uint8_t)val.int1_fth;
1357 ctrl4.int1_6d = (uint8_t)val.int1_6d;
1358 ctrl4.int1_tap = (uint8_t)val.int1_tap;
1359 ctrl4.int1_ff = (uint8_t)val.int1_ff;
1360 ctrl4.int1_wu = (uint8_t)val.int1_wu;
1361 ctrl4.int1_s_tap = (uint8_t)val.int1_s_tap;
1362 ctrl4.int1_master_drdy = (uint8_t)val.int1_master_drdy;
1363 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
1364 }
1365
1366 if (ret == 0)
1367 {
1368 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1369 (uint8_t *)&wake_up_dur, 1);
1370 }
1371
1372 if (ret == 0)
1373 {
1374 wake_up_dur.int1_fss7 = (uint8_t)val.int1_fss7;
1375 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1376 (uint8_t *)&wake_up_dur, 1);
1377 }
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief Select the signal that need to route on int1 pad.[get]
1384 *
1385 * @param ctx read / write interface definitions.(ptr)
1386 * @param val Get union of registers from CTRL4 to.(ptr)
1387 * @retval Interface status (MANDATORY: return 0 -> no Error).
1388 *
1389 */
lis2ds12_pin_int1_route_get(stmdev_ctx_t * ctx,lis2ds12_pin_int1_route_t * val)1390 int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx,
1391 lis2ds12_pin_int1_route_t *val)
1392 {
1393 lis2ds12_wake_up_dur_t wake_up_dur;
1394 lis2ds12_ctrl4_t ctrl4;
1395 int32_t ret;
1396
1397 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1);
1398
1399 if (ret == 0)
1400 {
1401 val->int1_drdy = ctrl4.int1_drdy;
1402 val->int1_fth = ctrl4.int1_fth;
1403 val->int1_6d = ctrl4.int1_6d;
1404 val->int1_tap = ctrl4.int1_tap;
1405 val->int1_ff = ctrl4.int1_ff;
1406 val->int1_wu = ctrl4.int1_wu;
1407 val->int1_s_tap = ctrl4.int1_s_tap;
1408 val->int1_master_drdy = ctrl4.int1_master_drdy;
1409 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1410 (uint8_t *)&wake_up_dur, 1);
1411 val->int1_fss7 = wake_up_dur.int1_fss7;
1412 }
1413
1414 return ret;
1415 }
1416
1417 /**
1418 * @brief Select the signal that need to route on int2 pad.[set]
1419 *
1420 * @param ctx read / write interface definitions.(ptr)
1421 * @param val change union of registers from CTRL5 to
1422 * @retval Interface status (MANDATORY: return 0 -> no Error).
1423 *
1424 */
lis2ds12_pin_int2_route_set(stmdev_ctx_t * ctx,lis2ds12_pin_int2_route_t val)1425 int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx,
1426 lis2ds12_pin_int2_route_t val)
1427 {
1428 lis2ds12_ctrl5_t ctrl5;
1429 int32_t ret;
1430
1431 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1432
1433 if (ret == 0)
1434 {
1435 ctrl5.int2_boot = val.int2_boot;
1436 ctrl5.int2_tilt = val.int2_tilt;
1437 ctrl5.int2_sig_mot = val.int2_sig_mot;
1438 ctrl5.int2_step_det = val.int2_step_det;
1439 ctrl5.int2_fth = val.int2_fth;
1440 ctrl5.int2_drdy = val.int2_drdy;
1441 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1442 }
1443
1444 return ret;
1445 }
1446
1447 /**
1448 * @brief Select the signal that need to route on int2 pad.[get]
1449 *
1450 * @param ctx read / write interface definitions.(ptr)
1451 * @param val Get union of registers from CTRL5 to.(ptr)
1452 * @retval Interface status (MANDATORY: return 0 -> no Error).
1453 *
1454 */
lis2ds12_pin_int2_route_get(stmdev_ctx_t * ctx,lis2ds12_pin_int2_route_t * val)1455 int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx,
1456 lis2ds12_pin_int2_route_t *val)
1457 {
1458 lis2ds12_ctrl5_t ctrl5;
1459 int32_t ret;
1460
1461 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1462 val->int2_boot = ctrl5.int2_boot;
1463 val->int2_tilt = ctrl5.int2_tilt;
1464 val->int2_sig_mot = ctrl5.int2_sig_mot;
1465 val->int2_step_det = ctrl5.int2_step_det;
1466 val->int2_fth = ctrl5.int2_fth;
1467 val->int2_drdy = ctrl5.int2_drdy;
1468
1469 return ret;
1470 }
1471
1472 /**
1473 * @brief All interrupt signals become available on INT1 pin.[set]
1474 *
1475 * @param ctx read / write interface definitions.(ptr)
1476 * @param val change the values of int2_on_int1 in reg CTRL5
1477 * @retval Interface status (MANDATORY: return 0 -> no Error).
1478 *
1479 */
lis2ds12_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)1480 int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
1481 {
1482 lis2ds12_ctrl5_t ctrl5;
1483 int32_t ret;
1484
1485 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1486
1487 if (ret == 0)
1488 {
1489 ctrl5.int2_on_int1 = val;
1490 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1491 }
1492
1493 return ret;
1494 }
1495
1496 /**
1497 * @brief All interrupt signals become available on INT1 pin.[get]
1498 *
1499 * @param ctx read / write interface definitions.(ptr)
1500 * @param val Get the values of int2_on_int1 in reg CTRL5.(ptr)
1501 * @retval Interface status (MANDATORY: return 0 -> no Error).
1502 *
1503 */
lis2ds12_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)1504 int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
1505 {
1506 lis2ds12_ctrl5_t ctrl5;
1507 int32_t ret;
1508
1509 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1);
1510 *val = ctrl5.int2_on_int1;
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @}
1517 *
1518 */
1519
1520 /**
1521 * @defgroup Interrupt Pins
1522 * @brief This section groups all the functions that manage interrupt pins.
1523 * @{
1524 *
1525 */
1526
1527 /**
1528 * @brief Connect / Disconnect pull-up on auxiliary I2C line.[set]
1529 *
1530 * @param ctx read / write interface definitions.(ptr)
1531 * @param val change the values of tud_en in reg FUNC_CTRL
1532 * @retval Interface status (MANDATORY: return 0 -> no Error).
1533 *
1534 */
lis2ds12_sh_pin_mode_set(stmdev_ctx_t * ctx,lis2ds12_tud_en_t val)1535 int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx,
1536 lis2ds12_tud_en_t val)
1537 {
1538 lis2ds12_func_ctrl_t func_ctrl;
1539 int32_t ret;
1540
1541 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
1542 (uint8_t *)&func_ctrl, 1);
1543
1544 if (ret == 0)
1545 {
1546 func_ctrl.tud_en = (uint8_t)val;
1547 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
1548 (uint8_t *)&func_ctrl, 1);
1549 }
1550
1551 return ret;
1552 }
1553
1554 /**
1555 * @brief Connect / Disconnect pull-up on auxiliary I2C line.[get]
1556 *
1557 * @param ctx read / write interface definitions.(ptr)
1558 * @param val Get the values of tud_en in reg FUNC_CTRL.(ptr)
1559 * @retval Interface status (MANDATORY: return 0 -> no Error).
1560 *
1561 */
lis2ds12_sh_pin_mode_get(stmdev_ctx_t * ctx,lis2ds12_tud_en_t * val)1562 int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx,
1563 lis2ds12_tud_en_t *val)
1564 {
1565 lis2ds12_func_ctrl_t func_ctrl;
1566 int32_t ret;
1567
1568 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
1569 (uint8_t *)&func_ctrl, 1);
1570
1571 switch (func_ctrl.tud_en)
1572 {
1573 case LIS2DS12_EXT_PULL_UP:
1574 *val = LIS2DS12_EXT_PULL_UP;
1575 break;
1576
1577 case LIS2DS12_INTERNAL_PULL_UP:
1578 *val = LIS2DS12_INTERNAL_PULL_UP;
1579 break;
1580
1581 default:
1582 *val = LIS2DS12_EXT_PULL_UP;
1583 break;
1584 }
1585
1586 return ret;
1587 }
1588
1589 /**
1590 * @}
1591 *
1592 */
1593
1594 /**
1595 * @defgroup Wake_Up_event
1596 * @brief This section groups all the functions that manage the Wake Up
1597 * event generation.
1598 * @{
1599 *
1600 */
1601
1602 /**
1603 * @brief Threshold for wakeup [1 LSb = FS_XL / 64].[set]
1604 *
1605 * @param ctx read / write interface definitions.(ptr)
1606 * @param val change the values of wu_ths in reg WAKE_UP_THS
1607 * @retval Interface status (MANDATORY: return 0 -> no Error).
1608 *
1609 */
lis2ds12_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1610 int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1611 {
1612 lis2ds12_wake_up_ths_t wake_up_ths;
1613 int32_t ret;
1614
1615 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
1616 (uint8_t *)&wake_up_ths, 1);
1617
1618 if (ret == 0)
1619 {
1620 wake_up_ths.wu_ths = val;
1621 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
1622 (uint8_t *)&wake_up_ths, 1);
1623 }
1624
1625 return ret;
1626 }
1627
1628 /**
1629 * @brief Threshold for wakeup [1 LSb = FS_XL / 64].[get]
1630 *
1631 * @param ctx read / write interface definitions.(ptr)
1632 * @param val Get the values of wu_ths in reg WAKE_UP_THS.(ptr)
1633 * @retval Interface status (MANDATORY: return 0 -> no Error).
1634 *
1635 */
lis2ds12_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1636 int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1637 {
1638 lis2ds12_wake_up_ths_t wake_up_ths;
1639 int32_t ret;
1640
1641 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
1642 (uint8_t *)&wake_up_ths, 1);
1643 *val = wake_up_ths.wu_ths;
1644
1645 return ret;
1646 }
1647
1648 /**
1649 * @brief Wakeup duration [1 LSb = 1 / ODR].[set]
1650 *
1651 * @param ctx read / write interface definitions.(ptr)
1652 * @param val change the values of wu_dur in reg WAKE_UP_DUR
1653 * @retval Interface status (MANDATORY: return 0 -> no Error).
1654 *
1655 */
lis2ds12_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)1656 int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1657 {
1658 lis2ds12_wake_up_dur_t wake_up_dur;
1659 int32_t ret;
1660
1661 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1662 (uint8_t *)&wake_up_dur, 1);
1663
1664 if (ret == 0)
1665 {
1666 wake_up_dur.wu_dur = val;
1667 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1668 (uint8_t *)&wake_up_dur, 1);
1669 }
1670
1671 return ret;
1672 }
1673
1674 /**
1675 * @brief Wakeup duration [1 LSb = 1 / ODR].[get]
1676 *
1677 * @param ctx read / write interface definitions.(ptr)
1678 * @param val Get the values of wu_dur in reg WAKE_UP_DUR.(ptr)
1679 * @retval Interface status (MANDATORY: return 0 -> no Error).
1680 *
1681 */
lis2ds12_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1682 int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1683 {
1684 lis2ds12_wake_up_dur_t wake_up_dur;
1685 int32_t ret;
1686
1687 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1688 (uint8_t *)&wake_up_dur, 1);
1689 *val = wake_up_dur.wu_dur;
1690
1691 return ret;
1692 }
1693
1694 /**
1695 * @}
1696 *
1697 */
1698
1699 /**
1700 * @defgroup Activity/Inactivity detection
1701 * @brief This section groups all the functions concerning
1702 * activity/inactivity detection.
1703 * @{
1704 *
1705 */
1706
1707 /**
1708 * @brief Enables Sleep mode.[set]
1709 *
1710 * @param ctx read / write interface definitions.(ptr)
1711 * @param val change the values of sleep_on in reg WAKE_UP_THS
1712 * @retval Interface status (MANDATORY: return 0 -> no Error).
1713 *
1714 */
lis2ds12_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)1715 int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
1716 {
1717 lis2ds12_wake_up_ths_t wake_up_ths;
1718 int32_t ret;
1719
1720 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
1721 (uint8_t *)&wake_up_ths, 1);
1722
1723 if (ret == 0)
1724 {
1725 wake_up_ths.sleep_on = val;
1726 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
1727 (uint8_t *)&wake_up_ths, 1);
1728 }
1729
1730 return ret;
1731 }
1732
1733 /**
1734 * @brief Enables Sleep mode.[get]
1735 *
1736 * @param ctx read / write interface definitions.(ptr)
1737 * @param val Get the values of sleep_on in reg WAKE_UP_THS.(ptr)
1738 * @retval Interface status (MANDATORY: return 0 -> no Error).
1739 *
1740 */
lis2ds12_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)1741 int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
1742 {
1743 lis2ds12_wake_up_ths_t wake_up_ths;
1744 int32_t ret;
1745
1746 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
1747 (uint8_t *)&wake_up_ths, 1);
1748 *val = wake_up_ths.sleep_on;
1749
1750 return ret;
1751 }
1752
1753 /**
1754 * @brief Duration to go in sleep mode [1 LSb = 512 / ODR].[set]
1755 *
1756 * @param ctx read / write interface definitions.(ptr)
1757 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
1758 * @retval Interface status (MANDATORY: return 0 -> no Error).
1759 *
1760 */
lis2ds12_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)1761 int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1762 {
1763 lis2ds12_wake_up_dur_t wake_up_dur;
1764 int32_t ret;
1765
1766 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1767 (uint8_t *)&wake_up_dur, 1);
1768
1769 if (ret == 0)
1770 {
1771 wake_up_dur.sleep_dur = val;
1772 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1773 (uint8_t *)&wake_up_dur, 1);
1774 }
1775
1776 return ret;
1777 }
1778
1779 /**
1780 * @brief Duration to go in sleep mode [1 LSb = 512 / ODR].[get]
1781 *
1782 * @param ctx read / write interface definitions.(ptr)
1783 * @param val Get the values of sleep_dur in reg WAKE_UP_DUR.(ptr)
1784 * @retval Interface status (MANDATORY: return 0 -> no Error).
1785 *
1786 */
lis2ds12_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1787 int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1788 {
1789 lis2ds12_wake_up_dur_t wake_up_dur;
1790 int32_t ret;
1791
1792 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
1793 (uint8_t *)&wake_up_dur, 1);
1794 *val = wake_up_dur.sleep_dur;
1795
1796 return ret;
1797 }
1798
1799 /**
1800 * @}
1801 *
1802 */
1803
1804 /**
1805 * @defgroup Tap Generator
1806 * @brief This section groups all the functions that manage the tap and
1807 * double tap event generation.
1808 * @{
1809 *
1810 */
1811
1812 /**
1813 * @brief Enable Z direction in tap recognition.[set]
1814 *
1815 * @param ctx read / write interface definitions.(ptr)
1816 * @param val change the values of tap_z_en in reg CTRL3
1817 * @retval Interface status (MANDATORY: return 0 -> no Error).
1818 *
1819 */
lis2ds12_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)1820 int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx,
1821 uint8_t val)
1822 {
1823 lis2ds12_ctrl3_t ctrl3;
1824 int32_t ret;
1825
1826 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1827
1828 if (ret == 0)
1829 {
1830 ctrl3.tap_z_en = val;
1831 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1832 }
1833
1834 return ret;
1835 }
1836
1837 /**
1838 * @brief Enable Z direction in tap recognition.[get]
1839 *
1840 * @param ctx read / write interface definitions.(ptr)
1841 * @param val Get the values of tap_z_en in reg CTRL3.(ptr)
1842 * @retval Interface status (MANDATORY: return 0 -> no Error).
1843 *
1844 */
lis2ds12_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)1845 int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx,
1846 uint8_t *val)
1847 {
1848 lis2ds12_ctrl3_t ctrl3;
1849 int32_t ret;
1850
1851 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1852 *val = ctrl3.tap_z_en;
1853
1854 return ret;
1855 }
1856
1857 /**
1858 * @brief Enable Y direction in tap recognition.[set]
1859 *
1860 * @param ctx read / write interface definitions.(ptr)
1861 * @param val change the values of tap_y_en in reg CTRL3
1862 * @retval Interface status (MANDATORY: return 0 -> no Error).
1863 *
1864 */
lis2ds12_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)1865 int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx,
1866 uint8_t val)
1867 {
1868 lis2ds12_ctrl3_t ctrl3;
1869 int32_t ret;
1870
1871 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1872
1873 if (ret == 0)
1874 {
1875 ctrl3.tap_y_en = val;
1876 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1877 }
1878
1879 return ret;
1880 }
1881
1882 /**
1883 * @brief Enable Y direction in tap recognition.[get]
1884 *
1885 * @param ctx read / write interface definitions.(ptr)
1886 * @param val Get the values of tap_y_en in reg CTRL3.(ptr)
1887 * @retval Interface status (MANDATORY: return 0 -> no Error).
1888 *
1889 */
lis2ds12_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)1890 int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx,
1891 uint8_t *val)
1892 {
1893 lis2ds12_ctrl3_t ctrl3;
1894 int32_t ret;
1895
1896 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1897 *val = ctrl3.tap_y_en;
1898
1899 return ret;
1900 }
1901
1902 /**
1903 * @brief Enable X direction in tap recognition.[set]
1904 *
1905 * @param ctx read / write interface definitions.(ptr)
1906 * @param val change the values of tap_x_en in reg CTRL3
1907 * @retval Interface status (MANDATORY: return 0 -> no Error).
1908 *
1909 */
lis2ds12_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)1910 int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx,
1911 uint8_t val)
1912 {
1913 lis2ds12_ctrl3_t ctrl3;
1914 int32_t ret;
1915
1916 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1917
1918 if (ret == 0)
1919 {
1920 ctrl3.tap_x_en = val;
1921 ret = lis2ds12_write_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1922 }
1923
1924 return ret;
1925 }
1926
1927 /**
1928 * @brief Enable X direction in tap recognition.[get]
1929 *
1930 * @param ctx read / write interface definitions.(ptr)
1931 * @param val Get the values of tap_x_en in reg CTRL3.(ptr)
1932 * @retval Interface status (MANDATORY: return 0 -> no Error).
1933 *
1934 */
lis2ds12_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)1935 int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx,
1936 uint8_t *val)
1937 {
1938 lis2ds12_ctrl3_t ctrl3;
1939 int32_t ret;
1940
1941 ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1);
1942 *val = ctrl3.tap_x_en;
1943
1944 return ret;
1945 }
1946
1947 /**
1948 * @brief Threshold for tap recognition [1 LSb = FS/32].[set]
1949 *
1950 * @param ctx read / write interface definitions.(ptr)
1951 * @param val change the values of tap_ths in reg TAP_6D_THS
1952 * @retval Interface status (MANDATORY: return 0 -> no Error).
1953 *
1954 */
lis2ds12_tap_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1955 int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1956 {
1957 lis2ds12_tap_6d_ths_t tap_6d_ths;
1958 int32_t ret;
1959
1960 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
1961 (uint8_t *)&tap_6d_ths, 1);
1962
1963 if (ret == 0)
1964 {
1965 tap_6d_ths.tap_ths = val;
1966 ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
1967 (uint8_t *)&tap_6d_ths, 1);
1968 }
1969
1970 return ret;
1971 }
1972
1973 /**
1974 * @brief Threshold for tap recognition [1 LSb = FS/32].[get]
1975 *
1976 * @param ctx read / write interface definitions.(ptr)
1977 * @param val Get the values of tap_ths in reg TAP_6D_THS.(ptr)
1978 * @retval Interface status (MANDATORY: return 0 -> no Error).
1979 *
1980 */
lis2ds12_tap_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1981 int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1982 {
1983 lis2ds12_tap_6d_ths_t tap_6d_ths;
1984 int32_t ret;
1985
1986 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
1987 (uint8_t *)&tap_6d_ths, 1);
1988 *val = tap_6d_ths.tap_ths;
1989
1990 return ret;
1991 }
1992
1993 /**
1994 * @brief Maximum duration is the maximum time of an overthreshold signal
1995 * detection to be recognized as a tap event. The default value of
1996 * these bits is 00b which corresponds to 4*ODR_XL time.
1997 * If the SHOCK[1:0] bits are set to a different value, 1LSB
1998 * corresponds to 8*ODR_XL time.[set]
1999 *
2000 * @param ctx read / write interface definitions.(ptr)
2001 * @param val change the values of shock in reg INT_DUR
2002 * @retval Interface status (MANDATORY: return 0 -> no Error).
2003 *
2004 */
lis2ds12_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)2005 int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
2006 {
2007 lis2ds12_int_dur_t int_dur;
2008 int32_t ret;
2009
2010 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2011
2012 if (ret == 0)
2013 {
2014 int_dur.shock = val;
2015 ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2016 }
2017
2018 return ret;
2019 }
2020
2021 /**
2022 * @brief Maximum duration is the maximum time of an overthreshold signal
2023 * detection to be recognized as a tap event. The default value of
2024 * these bits is 00b which corresponds to 4*ODR_XL time.
2025 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2026 * corresponds to 8*ODR_XL time.[get]
2027 *
2028 * @param ctx read / write interface definitions.(ptr)
2029 * @param val Get the values of shock in reg INT_DUR.(ptr)
2030 * @retval Interface status (MANDATORY: return 0 -> no Error).
2031 *
2032 */
lis2ds12_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)2033 int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
2034 {
2035 lis2ds12_int_dur_t int_dur;
2036 int32_t ret;
2037
2038 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2039 *val = int_dur.shock;
2040
2041 return ret;
2042 }
2043
2044 /**
2045 * @brief Quiet time is the time after the first detected tap in which there
2046 * must not be any overthreshold event. The default value of these
2047 * bits is 00b which corresponds to 2*ODR_XL time.
2048 * If the QUIET[1:0] bits are set to a different value, 1LSB
2049 * corresponds to 4*ODR_XL time.[set]
2050 *
2051 * @param ctx read / write interface definitions.(ptr)
2052 * @param val change the values of quiet in reg INT_DUR
2053 * @retval Interface status (MANDATORY: return 0 -> no Error).
2054 *
2055 */
lis2ds12_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)2056 int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
2057 {
2058 lis2ds12_int_dur_t int_dur;
2059 int32_t ret;
2060
2061 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2062
2063 if (ret == 0)
2064 {
2065 int_dur.quiet = val;
2066 ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2067 }
2068
2069 return ret;
2070 }
2071
2072 /**
2073 * @brief Quiet time is the time after the first detected tap in which there
2074 * must not be any overthreshold event. The default value of these
2075 * bits is 00b which corresponds to 2*ODR_XL time.
2076 * If the QUIET[1:0] bits are set to a different value, 1LSB
2077 * corresponds to 4*ODR_XL time.[get]
2078 *
2079 * @param ctx read / write interface definitions.(ptr)
2080 * @param val Get the values of quiet in reg INT_DUR.(ptr)
2081 * @retval Interface status (MANDATORY: return 0 -> no Error).
2082 *
2083 */
lis2ds12_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)2084 int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
2085 {
2086 lis2ds12_int_dur_t int_dur;
2087 int32_t ret;
2088
2089 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2090 *val = int_dur.quiet;
2091
2092 return ret;
2093 }
2094
2095 /**
2096 * @brief When double tap recognition is enabled, this register expresses the
2097 * maximum time between two consecutive detected taps to determine a
2098 * double tap event. The default value of these bits is 0000b which
2099 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to a
2100 * different value, 1LSB corresponds to 32*ODR_XL time.[set]
2101 *
2102 * @param ctx read / write interface definitions.(ptr)
2103 * @param val change the values of lat in reg INT_DUR
2104 * @retval Interface status (MANDATORY: return 0 -> no Error).
2105 *
2106 */
lis2ds12_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)2107 int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2108 {
2109 lis2ds12_int_dur_t int_dur;
2110 int32_t ret;
2111
2112 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2113
2114 if (ret == 0)
2115 {
2116 int_dur.lat = val;
2117 ret = lis2ds12_write_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2118 }
2119
2120 return ret;
2121 }
2122
2123 /**
2124 * @brief When double tap recognition is enabled, this register expresses the
2125 * maximum time between two consecutive detected taps to determine a
2126 * double tap event. The default value of these bits is 0000b which
2127 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to a
2128 * different value, 1LSB corresponds to 32*ODR_XL time.[get]
2129 *
2130 * @param ctx read / write interface definitions.(ptr)
2131 * @param val Get the values of lat in reg INT_DUR.(ptr)
2132 * @retval Interface status (MANDATORY: return 0 -> no Error).
2133 *
2134 */
lis2ds12_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2135 int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2136 {
2137 lis2ds12_int_dur_t int_dur;
2138 int32_t ret;
2139
2140 ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1);
2141 *val = int_dur.lat;
2142
2143 return ret;
2144 }
2145
2146 /**
2147 * @brief Single/double-tap event enable/disable.[set]
2148 *
2149 * @param ctx read / write interface definitions.(ptr)
2150 * @param val change the values of single_double_tap in regWAKE_UP_THS
2151 * @retval Interface status (MANDATORY: return 0 -> no Error).
2152 *
2153 */
lis2ds12_tap_mode_set(stmdev_ctx_t * ctx,lis2ds12_single_double_tap_t val)2154 int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx,
2155 lis2ds12_single_double_tap_t val)
2156 {
2157 lis2ds12_wake_up_ths_t wake_up_ths;
2158 int32_t ret;
2159
2160 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
2161 (uint8_t *)&wake_up_ths, 1);
2162
2163 if (ret == 0)
2164 {
2165 wake_up_ths.single_double_tap = (uint8_t)val;
2166 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_THS,
2167 (uint8_t *)&wake_up_ths, 1);
2168 }
2169
2170 return ret;
2171 }
2172
2173 /**
2174 * @brief Single/double-tap event enable/disable.[get]
2175 *
2176 * @param ctx read / write interface definitions.(ptr)
2177 * @param val Get the values of single_double_tap in reg WAKE_UP_THS.(ptr)
2178 * @retval Interface status (MANDATORY: return 0 -> no Error).
2179 *
2180 */
lis2ds12_tap_mode_get(stmdev_ctx_t * ctx,lis2ds12_single_double_tap_t * val)2181 int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx,
2182 lis2ds12_single_double_tap_t *val)
2183 {
2184 lis2ds12_wake_up_ths_t wake_up_ths;
2185 int32_t ret;
2186
2187 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS,
2188 (uint8_t *)&wake_up_ths, 1);
2189
2190 switch (wake_up_ths.single_double_tap)
2191 {
2192 case LIS2DS12_ONLY_SINGLE:
2193 *val = LIS2DS12_ONLY_SINGLE;
2194 break;
2195
2196 case LIS2DS12_ONLY_DOUBLE:
2197 *val = LIS2DS12_ONLY_DOUBLE;
2198 break;
2199
2200 default:
2201 *val = LIS2DS12_ONLY_SINGLE;
2202 break;
2203 }
2204
2205 return ret;
2206 }
2207
2208 /**
2209 * @brief TAP source register[get]
2210 *
2211 * @param ctx read / write interface definitions.(ptr)
2212 * @param val Get registers TAP_SRC.(ptr)
2213 * @retval Interface status (MANDATORY: return 0 -> no Error).
2214 *
2215 */
lis2ds12_tap_src_get(stmdev_ctx_t * ctx,lis2ds12_tap_src_t * val)2216 int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx,
2217 lis2ds12_tap_src_t *val)
2218 {
2219 int32_t ret;
2220
2221 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_SRC, (uint8_t *) val, 1);
2222
2223 return ret;
2224 }
2225
2226 /**
2227 * @}
2228 *
2229 */
2230
2231 /**
2232 * @defgroup Six_position_detection(6D/4D)
2233 * @brief This section groups all the functions concerning six
2234 * position detection (6D).
2235 * @{
2236 *
2237 */
2238
2239 /**
2240 * @brief Threshold for 4D/6D function.[set]
2241 *
2242 * @param ctx read / write interface definitions.(ptr)
2243 * @param val change the values of 6d_ths in reg TAP_6D_THS
2244 * @retval Interface status (MANDATORY: return 0 -> no Error).
2245 *
2246 */
lis2ds12_6d_threshold_set(stmdev_ctx_t * ctx,lis2ds12_6d_ths_t val)2247 int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx,
2248 lis2ds12_6d_ths_t val)
2249 {
2250 lis2ds12_tap_6d_ths_t tap_6d_ths;
2251 int32_t ret;
2252
2253 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
2254 (uint8_t *)&tap_6d_ths, 1);
2255
2256 if (ret == 0)
2257 {
2258 tap_6d_ths._6d_ths = (uint8_t)val;
2259 ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
2260 (uint8_t *)&tap_6d_ths, 1);
2261 }
2262
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief Threshold for 4D/6D function.[get]
2268 *
2269 * @param ctx read / write interface definitions.(ptr)
2270 * @param val Get the values of 6d_ths in reg TAP_6D_THS.(ptr)
2271 * @retval Interface status (MANDATORY: return 0 -> no Error).
2272 *
2273 */
lis2ds12_6d_threshold_get(stmdev_ctx_t * ctx,lis2ds12_6d_ths_t * val)2274 int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx,
2275 lis2ds12_6d_ths_t *val)
2276 {
2277 lis2ds12_tap_6d_ths_t tap_6d_ths;
2278 int32_t ret;
2279
2280 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
2281 (uint8_t *)&tap_6d_ths, 1);
2282
2283 switch (tap_6d_ths._6d_ths)
2284 {
2285 case LIS2DS12_DEG_80:
2286 *val = LIS2DS12_DEG_80;
2287 break;
2288
2289 case LIS2DS12_DEG_70:
2290 *val = LIS2DS12_DEG_70;
2291 break;
2292
2293 case LIS2DS12_DEG_60:
2294 *val = LIS2DS12_DEG_60;
2295 break;
2296
2297 case LIS2DS12_DEG_50:
2298 *val = LIS2DS12_DEG_50;
2299 break;
2300
2301 default:
2302 *val = LIS2DS12_DEG_80;
2303 break;
2304 }
2305
2306 return ret;
2307 }
2308
2309 /**
2310 * @brief 4D orientation detection enable.[set]
2311 *
2312 * @param ctx read / write interface definitions.(ptr)
2313 * @param val change the values of 4d_en in reg TAP_6D_THS
2314 * @retval Interface status (MANDATORY: return 0 -> no Error).
2315 *
2316 */
lis2ds12_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)2317 int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
2318 {
2319 lis2ds12_tap_6d_ths_t tap_6d_ths;
2320 int32_t ret;
2321
2322 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
2323 (uint8_t *)& tap_6d_ths, 1);
2324
2325 if (ret == 0)
2326 {
2327 tap_6d_ths._4d_en = val;
2328 ret = lis2ds12_write_reg(ctx, LIS2DS12_TAP_6D_THS,
2329 (uint8_t *)& tap_6d_ths, 1);
2330 }
2331
2332 return ret;
2333 }
2334
2335 /**
2336 * @brief 4D orientation detection enable.[get]
2337 *
2338 * @param ctx read / write interface definitions.(ptr)
2339 * @param val Get the values of 4d_en in reg TAP_6D_THS.(ptr)
2340 * @retval Interface status (MANDATORY: return 0 -> no Error).
2341 *
2342 */
lis2ds12_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)2343 int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
2344 {
2345 lis2ds12_tap_6d_ths_t tap_6d_ths;
2346 int32_t ret;
2347
2348 ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS,
2349 (uint8_t *)&tap_6d_ths, 1);
2350 *val = tap_6d_ths._4d_en;
2351
2352 return ret;
2353 }
2354
2355 /**
2356 * @brief 6D source register.[get]
2357 *
2358 * @param ctx read / write interface definitions.(ptr)
2359 * @param val Get union of registers from 6D_SRC to.(ptr)
2360 * @retval Interface status (MANDATORY: return 0 -> no Error).
2361 *
2362 */
lis2ds12_6d_src_get(stmdev_ctx_t * ctx,lis2ds12_6d_src_t * val)2363 int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val)
2364 {
2365 int32_t ret;
2366
2367 ret = lis2ds12_read_reg(ctx, LIS2DS12_6D_SRC, (uint8_t *) val, 1);
2368
2369 return ret;
2370 }
2371
2372 /**
2373 * @}
2374 *
2375 */
2376
2377 /**
2378 * @defgroup free_fall
2379 * @brief This section group all the functions concerning the
2380 * free fall detection.
2381 * @{
2382 *
2383 */
2384
2385 /**
2386 * @brief Free-fall duration [1 LSb = 1 / ODR].[set]
2387 *
2388 * @param ctx read / write interface definitions.(ptr)
2389 * @param val change the values of ff_dur in reg WAKE_UP_DUR/FREE_FALL
2390 * @retval Interface status (MANDATORY: return 0 -> no Error).
2391 *
2392 */
lis2ds12_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)2393 int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2394 {
2395 lis2ds12_free_fall_t free_fall;
2396 lis2ds12_wake_up_dur_t wake_up_dur;
2397 int32_t ret;
2398
2399 ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
2400 (uint8_t *)&free_fall, 1);
2401
2402 if (ret == 0)
2403 {
2404 free_fall.ff_dur = val & 0x1FU;
2405 ret = lis2ds12_write_reg(ctx, LIS2DS12_FREE_FALL,
2406 (uint8_t *)&free_fall, 1);
2407 }
2408
2409 if (ret == 0)
2410 {
2411 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
2412 (uint8_t *)&wake_up_dur, 1);
2413 }
2414
2415 if (ret == 0)
2416 {
2417 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
2418 ret = lis2ds12_write_reg(ctx, LIS2DS12_WAKE_UP_DUR,
2419 (uint8_t *)&wake_up_dur, 1);
2420 }
2421
2422 return ret;
2423 }
2424
2425 /**
2426 * @brief Free-fall duration [1 LSb = 1 / ODR].[get]
2427 *
2428 * @param ctx read / write interface definitions.(ptr)
2429 * @param val Get the values of ff_dur in reg WAKE_UP_DUR/FREE_FALL.(ptr)
2430 * @retval Interface status (MANDATORY: return 0 -> no Error).
2431 *
2432 */
lis2ds12_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2433 int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2434 {
2435 lis2ds12_free_fall_t free_fall;
2436 lis2ds12_wake_up_dur_t wake_up_dur;
2437 int32_t ret;
2438
2439 ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
2440 (uint8_t *)&free_fall, 1);
2441
2442 if (ret == 0)
2443 {
2444 ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR,
2445 (uint8_t *)&wake_up_dur, 1);
2446 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
2447 }
2448
2449 return ret;
2450 }
2451
2452 /**
2453 * @brief Free-fall threshold [1 LSB = 31.25 mg].[set]
2454 *
2455 * @param ctx read / write interface definitions.(ptr)
2456 * @param val change the values of ff_ths in reg FREE_FALL
2457 * @retval Interface status (MANDATORY: return 0 -> no Error).
2458 *
2459 */
lis2ds12_ff_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2460 int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2461 {
2462 lis2ds12_free_fall_t free_fall;
2463 int32_t ret;
2464
2465 ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
2466 (uint8_t *)&free_fall, 1);
2467
2468 if (ret == 0)
2469 {
2470 free_fall.ff_ths = val;
2471 ret = lis2ds12_write_reg(ctx, LIS2DS12_FREE_FALL,
2472 (uint8_t *)&free_fall, 1);
2473 }
2474
2475 return ret;
2476 }
2477
2478 /**
2479 * @brief Free-fall threshold [1 LSB = 31.25 mg].[get]
2480 *
2481 * @param ctx read / write interface definitions.(ptr)
2482 * @param val Get the values of ff_ths in reg FREE_FALL.(ptr)
2483 * @retval Interface status (MANDATORY: return 0 -> no Error).
2484 *
2485 */
lis2ds12_ff_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2486 int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2487 {
2488 lis2ds12_free_fall_t free_fall;
2489 int32_t ret;
2490
2491 ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL,
2492 (uint8_t *)&free_fall, 1);
2493 *val = free_fall.ff_ths;
2494
2495 return ret;
2496 }
2497
2498 /**
2499 * @}
2500 *
2501 */
2502
2503 /**
2504 * @defgroup Fifo
2505 * @brief This section group all the functions concerning the fifo usage
2506 * @{
2507 *
2508 */
2509
2510 /**
2511 * @brief Module routine result is send to FIFO instead of X,Y,Z
2512 * acceleration data[set]
2513 *
2514 * @param ctx read / write interface definitions.(ptr)
2515 * @param val change the values of module_to_fifo in reg FIFO_CTRL
2516 * @retval Interface status (MANDATORY: return 0 -> no Error).
2517 *
2518 */
lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t * ctx,uint8_t val)2519 int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx,
2520 uint8_t val)
2521 {
2522 lis2ds12_fifo_ctrl_t fifo_ctrl;
2523 int32_t ret;
2524
2525 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
2526 (uint8_t *)&fifo_ctrl, 1);
2527
2528 if (ret == 0)
2529 {
2530 fifo_ctrl.module_to_fifo = val;
2531 ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
2532 (uint8_t *)&fifo_ctrl, 1);
2533 }
2534
2535 return ret;
2536 }
2537
2538 /**
2539 * @brief Module routine result is send to FIFO instead of X,Y,Z
2540 * acceleration data[get]
2541 *
2542 * @param ctx read / write interface definitions.(ptr)
2543 * @param val Get the values of module_to_fifo in reg FIFO_CTRL.(ptr)
2544 * @retval Interface status (MANDATORY: return 0 -> no Error).
2545 *
2546 */
lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t * ctx,uint8_t * val)2547 int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx,
2548 uint8_t *val)
2549 {
2550 lis2ds12_fifo_ctrl_t fifo_ctrl;
2551 int32_t ret;
2552
2553 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
2554 (uint8_t *)&fifo_ctrl, 1);
2555 *val = fifo_ctrl.module_to_fifo;
2556
2557 return ret;
2558 }
2559
2560 /**
2561 * @brief FIFO mode selection.[set]
2562 *
2563 * @param ctx read / write interface definitions.(ptr)
2564 * @param val change the values of fmode in reg FIFO_CTRL
2565 * @retval Interface status (MANDATORY: return 0 -> no Error).
2566 *
2567 */
lis2ds12_fifo_mode_set(stmdev_ctx_t * ctx,lis2ds12_fmode_t val)2568 int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx,
2569 lis2ds12_fmode_t val)
2570 {
2571 lis2ds12_fifo_ctrl_t fifo_ctrl;
2572 int32_t ret;
2573
2574 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
2575 (uint8_t *)&fifo_ctrl, 1);
2576
2577 if (ret == 0)
2578 {
2579 fifo_ctrl.fmode = (uint8_t)val;
2580 ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_CTRL,
2581 (uint8_t *)&fifo_ctrl, 1);
2582 }
2583
2584 return ret;
2585 }
2586
2587 /**
2588 * @brief FIFO mode selection.[get]
2589 *
2590 * @param ctx read / write interface definitions.(ptr)
2591 * @param val Get the values of fmode in reg FIFO_CTRL.(ptr)
2592 * @retval Interface status (MANDATORY: return 0 -> no Error).
2593 *
2594 */
lis2ds12_fifo_mode_get(stmdev_ctx_t * ctx,lis2ds12_fmode_t * val)2595 int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx,
2596 lis2ds12_fmode_t *val)
2597 {
2598 lis2ds12_fifo_ctrl_t fifo_ctrl;
2599 int32_t ret;
2600
2601 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL,
2602 (uint8_t *)&fifo_ctrl, 1);
2603
2604 switch (fifo_ctrl.fmode)
2605 {
2606 case LIS2DS12_BYPASS_MODE:
2607 *val = LIS2DS12_BYPASS_MODE;
2608 break;
2609
2610 case LIS2DS12_FIFO_MODE:
2611 *val = LIS2DS12_FIFO_MODE;
2612 break;
2613
2614 case LIS2DS12_STREAM_TO_FIFO_MODE:
2615 *val = LIS2DS12_STREAM_TO_FIFO_MODE;
2616 break;
2617
2618 case LIS2DS12_BYPASS_TO_STREAM_MODE:
2619 *val = LIS2DS12_BYPASS_TO_STREAM_MODE;
2620 break;
2621
2622 case LIS2DS12_STREAM_MODE:
2623 *val = LIS2DS12_STREAM_MODE;
2624 break;
2625
2626 default:
2627 *val = LIS2DS12_BYPASS_MODE;
2628 break;
2629 }
2630
2631 return ret;
2632 }
2633
2634 /**
2635 * @brief FIFO watermark level selection.[set]
2636 *
2637 * @param ctx read / write interface definitions.(ptr)
2638 * @param val change the values of fifo_watermark in reg FIFO_THS
2639 * @retval Interface status (MANDATORY: return 0 -> no Error).
2640 *
2641 */
lis2ds12_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)2642 int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
2643 {
2644 int32_t ret;
2645
2646 ret = lis2ds12_write_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t *)&val, 1);
2647
2648 return ret;
2649 }
2650
2651 /**
2652 * @brief FIFO watermark level selection.[get]
2653 *
2654 * @param ctx read / write interface definitions.(ptr)
2655 * @param val Get the values of fifo_watermark in reg FIFO_THS.(ptr)
2656 * @retval Interface status (MANDATORY: return 0 -> no Error).
2657 *
2658 */
lis2ds12_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)2659 int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
2660 {
2661 int32_t ret;
2662
2663 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, val, 1);
2664
2665 return ret;
2666 }
2667
2668 /**
2669 * @brief FIFO full, 256 unread samples.[get]
2670 *
2671 * @param ctx read / write interface definitions.(ptr)
2672 * @param val Get the values of diff in reg FIFO_SRC.(ptr)
2673 * @retval Interface status (MANDATORY: return 0 -> no Error).
2674 *
2675 */
lis2ds12_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2676 int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2677 {
2678 lis2ds12_fifo_src_t fifo_src;
2679 int32_t ret;
2680
2681 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2682 *val = fifo_src.diff;
2683
2684 return ret;
2685 }
2686
2687 /**
2688 * @brief FIFO overrun status.[get]
2689 *
2690 * @param ctx read / write interface definitions.(ptr)
2691 * @param val Get the values of fifo_ovr in reg FIFO_SRC.(ptr)
2692 * @retval Interface status (MANDATORY: return 0 -> no Error).
2693 *
2694 */
lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2695 int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2696 {
2697 lis2ds12_fifo_src_t fifo_src;
2698 int32_t ret;
2699
2700 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2701 *val = fifo_src.fifo_ovr;
2702
2703 return ret;
2704 }
2705
2706 /**
2707 * @brief FIFO threshold status.[get]
2708 *
2709 * @param ctx read / write interface definitions.(ptr)
2710 * @param val Get the values of fth in reg FIFO_SRC.(ptr)
2711 * @retval Interface status (MANDATORY: return 0 -> no Error).
2712 *
2713 */
lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2714 int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2715 {
2716 lis2ds12_fifo_src_t fifo_src;
2717 int32_t ret;
2718
2719 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2720 *val = fifo_src.fth;
2721
2722 return ret;
2723 }
2724
2725 /**
2726 * @brief The number of unread samples stored in FIFO.[get]
2727 *
2728 * @param ctx read / write interface definitions.(ptr)
2729 * @param val Get the values of diff in reg FIFO_SAMPLES.(ptr)
2730 * @retval Interface status (MANDATORY: return 0 -> no Error).
2731 *
2732 */
lis2ds12_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)2733 int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
2734 {
2735 lis2ds12_fifo_ths_t fifo_ths;
2736 lis2ds12_fifo_src_t fifo_src;
2737 int32_t ret;
2738
2739 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t *)&fifo_ths, 1);
2740
2741 if (ret == 0)
2742 {
2743 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2744 *val = fifo_src.diff;
2745 *val = (*val * 256U) + fifo_ths.fth;
2746 }
2747
2748 return ret;
2749 }
2750
2751 /**
2752 * @brief FIFO_SRCregister.[get]
2753 *
2754 * @param ctx read / write interface definitions.(ptr)
2755 * @param val Get registers FIFO_SRC.(ptr)
2756 * @retval Interface status (MANDATORY: return 0 -> no Error).
2757 *
2758 */
lis2ds12_fifo_src_get(stmdev_ctx_t * ctx,lis2ds12_fifo_src_t * val)2759 int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx,
2760 lis2ds12_fifo_src_t *val)
2761 {
2762 int32_t ret;
2763
2764 ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *) val, 1);
2765
2766 return ret;
2767 }
2768
2769 /**
2770 * @}
2771 *
2772 */
2773
2774 /**
2775 * @defgroup Pedometer
2776 * @brief This section groups all the functions that manage pedometer.
2777 * @{
2778 *
2779 */
2780
2781 /**
2782 * @brief Minimum threshold value for step counter routine.[set]
2783 *
2784 * @param ctx read / write interface definitions.(ptr)
2785 * @param val change the values of sc_mths in reg STEP_COUNTER_MINTHS
2786 * @retval Interface status (MANDATORY: return 0 -> no Error).
2787 *
2788 */
lis2ds12_pedo_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2789 int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2790 {
2791 lis2ds12_step_counter_minths_t step_counter_minths;
2792 int32_t ret;
2793
2794 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2795 (uint8_t *)&step_counter_minths, 1);
2796
2797 if (ret == 0)
2798 {
2799 step_counter_minths.sc_mths = val;
2800 ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2801 (uint8_t *)&step_counter_minths, 1);
2802 }
2803
2804 return ret;
2805 }
2806
2807 /**
2808 * @brief Minimum threshold value for step counter routine.[get]
2809 *
2810 * @param ctx read / write interface definitions.(ptr)
2811 * @param val Get the values of sc_mths in reg STEP_COUNTER_MINTHS.(ptr)
2812 * @retval Interface status (MANDATORY: return 0 -> no Error).
2813 *
2814 */
lis2ds12_pedo_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2815 int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2816 {
2817 lis2ds12_step_counter_minths_t step_counter_minths;
2818 int32_t ret;
2819
2820 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2821 (uint8_t *)&step_counter_minths, 1);
2822 *val = step_counter_minths.sc_mths;
2823
2824 return ret;
2825 }
2826
2827 /**
2828 * @brief Pedometer data range.[set]
2829 *
2830 * @param ctx read / write interface definitions.(ptr)
2831 * @param val change the values of pedo4g in reg STEP_COUNTER_MINTHS
2832 * @retval Interface status (MANDATORY: return 0 -> no Error).
2833 *
2834 */
lis2ds12_pedo_full_scale_set(stmdev_ctx_t * ctx,lis2ds12_pedo4g_t val)2835 int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx,
2836 lis2ds12_pedo4g_t val)
2837 {
2838 lis2ds12_step_counter_minths_t step_counter_minths;
2839 int32_t ret;
2840
2841 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2842 (uint8_t *)&step_counter_minths, 1);
2843
2844 if (ret == 0)
2845 {
2846 step_counter_minths.pedo4g = (uint8_t)val;
2847 ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2848 (uint8_t *)&step_counter_minths, 1);
2849 }
2850
2851 return ret;
2852 }
2853
2854 /**
2855 * @brief Pedometer data range.[get]
2856 *
2857 * @param ctx read / write interface definitions.(ptr)
2858 * @param val Get the values of pedo4g in reg STEP_COUNTER_MINTHS.(ptr)
2859 * @retval Interface status (MANDATORY: return 0 -> no Error).
2860 *
2861 */
lis2ds12_pedo_full_scale_get(stmdev_ctx_t * ctx,lis2ds12_pedo4g_t * val)2862 int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx,
2863 lis2ds12_pedo4g_t *val)
2864 {
2865 lis2ds12_step_counter_minths_t step_counter_minths;
2866 int32_t ret;
2867
2868 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2869 (uint8_t *)&step_counter_minths, 1);
2870
2871 switch (step_counter_minths.pedo4g)
2872 {
2873 case LIS2DS12_PEDO_AT_2g:
2874 *val = LIS2DS12_PEDO_AT_2g;
2875 break;
2876
2877 case LIS2DS12_PEDO_AT_4g:
2878 *val = LIS2DS12_PEDO_AT_4g;
2879 break;
2880
2881 default:
2882 *val = LIS2DS12_PEDO_AT_2g;
2883 break;
2884 }
2885
2886 return ret;
2887 }
2888
2889 /**
2890 * @brief Reset pedometer step counter.[set]
2891 *
2892 * @param ctx read / write interface definitions.(ptr)
2893 * @param val change the values of rst_nstep in reg STEP_COUNTER_MINTHS
2894 * @retval Interface status (MANDATORY: return 0 -> no Error).
2895 *
2896 */
lis2ds12_pedo_step_reset_set(stmdev_ctx_t * ctx,uint8_t val)2897 int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2898 {
2899 lis2ds12_step_counter_minths_t step_counter_minths;
2900 int32_t ret;
2901
2902 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2903 (uint8_t *)&step_counter_minths, 1);
2904
2905 if (ret == 0)
2906 {
2907 step_counter_minths.rst_nstep = val;
2908 ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2909 (uint8_t *)&step_counter_minths, 1);
2910 }
2911
2912 return ret;
2913 }
2914
2915 /**
2916 * @brief Reset pedometer step counter.[get]
2917 *
2918 * @param ctx read / write interface definitions.(ptr)
2919 * @param val Get the values of rst_nstep in reg STEP_COUNTER_MINTHS.(ptr)
2920 * @retval Interface status (MANDATORY: return 0 -> no Error).
2921 *
2922 */
lis2ds12_pedo_step_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2923 int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2924 {
2925 lis2ds12_step_counter_minths_t step_counter_minths;
2926 int32_t ret;
2927
2928 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS,
2929 (uint8_t *)&step_counter_minths, 1);
2930 *val = step_counter_minths.rst_nstep;
2931
2932 return ret;
2933 }
2934
2935 /**
2936 * @brief Step detection flag.[get]
2937 *
2938 * @param ctx read / write interface definitions.(ptr)
2939 * @param val Get the values of step_detect in reg FUNC_CK_GATE.(ptr)
2940 * @retval Interface status (MANDATORY: return 0 -> no Error).
2941 *
2942 */
lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2943 int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx,
2944 uint8_t *val)
2945 {
2946 lis2ds12_func_ck_gate_t func_ck_gate;
2947 int32_t ret;
2948
2949 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
2950 (uint8_t *)&func_ck_gate, 1);
2951 *val = func_ck_gate.step_detect;
2952
2953 return ret;
2954 }
2955
2956 /**
2957 * @brief Enable pedometer algorithm.[set]
2958 *
2959 * @param ctx read / write interface definitions.(ptr)
2960 * @param val change the values of step_cnt_on in reg FUNC_CTRL
2961 * @retval Interface status (MANDATORY: return 0 -> no Error).
2962 *
2963 */
lis2ds12_pedo_sens_set(stmdev_ctx_t * ctx,uint8_t val)2964 int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
2965 {
2966 lis2ds12_func_ctrl_t func_ctrl;
2967 int32_t ret;
2968
2969 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
2970 (uint8_t *)&func_ctrl, 1);
2971
2972 if (ret == 0)
2973 {
2974 func_ctrl.step_cnt_on = val;
2975 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
2976 (uint8_t *)&func_ctrl, 1);
2977 }
2978
2979 return ret;
2980 }
2981
2982 /**
2983 * @brief Enable pedometer algorithm.[get]
2984 *
2985 * @param ctx read / write interface definitions.(ptr)
2986 * @param val Get the values of step_cnt_on in reg FUNC_CTRL.(ptr)
2987 * @retval Interface status (MANDATORY: return 0 -> no Error).
2988 *
2989 */
lis2ds12_pedo_sens_get(stmdev_ctx_t * ctx,uint8_t * val)2990 int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
2991 {
2992 lis2ds12_func_ctrl_t func_ctrl;
2993 int32_t ret;
2994
2995 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
2996 (uint8_t *)&func_ctrl, 1);
2997 *val = func_ctrl.step_cnt_on;
2998
2999 return ret;
3000 }
3001
3002 /**
3003 * @brief Minimum number of steps to start the increment step counter.[set]
3004 *
3005 * @param ctx read / write interface definitions.(ptr)
3006 * @param val change the values of deb_step in reg PEDO_DEB_REG
3007 * @retval Interface status (MANDATORY: return 0 -> no Error).
3008 *
3009 */
lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t val)3010 int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
3011 uint8_t val)
3012 {
3013 lis2ds12_pedo_deb_reg_t pedo_deb_reg;
3014 int32_t ret;
3015
3016 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3017
3018 if (ret == 0)
3019 {
3020 ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3021 (uint8_t *)&pedo_deb_reg, 1);
3022 }
3023
3024 if (ret == 0)
3025 {
3026 pedo_deb_reg.deb_step = val;
3027 ret = lis2ds12_write_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3028 (uint8_t *)&pedo_deb_reg, 1);
3029 }
3030
3031 if (ret == 0)
3032 {
3033 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3034 }
3035
3036 return ret;
3037 }
3038
3039 /**
3040 * @brief Minimum number of steps to start the increment step counter.[get]
3041 *
3042 * @param ctx read / write interface definitions.(ptr)
3043 * @param val Get the values of deb_step in reg PEDO_DEB_REG.(ptr)
3044 * @retval Interface status (MANDATORY: return 0 -> no Error).
3045 *
3046 */
lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * val)3047 int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
3048 uint8_t *val)
3049 {
3050 lis2ds12_pedo_deb_reg_t pedo_deb_reg;
3051 int32_t ret;
3052
3053 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3054
3055 if (ret == 0)
3056 {
3057 ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3058 (uint8_t *)&pedo_deb_reg, 1);
3059 }
3060
3061 if (ret == 0)
3062 {
3063 *val = pedo_deb_reg.deb_step;
3064 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3065 }
3066
3067 return ret;
3068 }
3069
3070 /**
3071 * @brief Debounce time. If the time between two consecutive steps is greater
3072 * than DEB_TIME*80ms, the debouncer is reactivated.
3073 * Default value: 01101[set]
3074 *
3075 * @param ctx read / write interface definitions.(ptr)
3076 * @param val change the values of deb_time in reg PEDO_DEB_REG
3077 * @retval Interface status (MANDATORY: return 0 -> no Error).
3078 *
3079 */
lis2ds12_pedo_timeout_set(stmdev_ctx_t * ctx,uint8_t val)3080 int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
3081 {
3082 lis2ds12_pedo_deb_reg_t pedo_deb_reg;
3083 int32_t ret;
3084
3085 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3086
3087 if (ret == 0)
3088 {
3089 ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3090 (uint8_t *)&pedo_deb_reg, 1);
3091 }
3092
3093 if (ret == 0)
3094 {
3095 pedo_deb_reg.deb_time = val;
3096 ret = lis2ds12_write_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3097 (uint8_t *)&pedo_deb_reg, 1);
3098 }
3099
3100 if (ret == 0)
3101 {
3102 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3103 }
3104
3105 return ret;
3106 }
3107
3108 /**
3109 * @brief Debounce time. If the time between two consecutive steps is
3110 * greater than DEB_TIME*80ms, the debouncer is reactivated.
3111 * Default value: 01101[get]
3112 *
3113 * @param ctx read / write interface definitions.(ptr)
3114 * @param val Get the values of deb_time in reg PEDO_DEB_REG.(ptr)
3115 * @retval Interface status (MANDATORY: return 0 -> no Error).
3116 *
3117 */
lis2ds12_pedo_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)3118 int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
3119 {
3120 lis2ds12_pedo_deb_reg_t pedo_deb_reg;
3121 int32_t ret;
3122
3123 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3124
3125 if (ret == 0)
3126 {
3127 ret = lis2ds12_read_reg(ctx, LIS2DS12_PEDO_DEB_REG,
3128 (uint8_t *)&pedo_deb_reg, 1);
3129 }
3130
3131 if (ret == 0)
3132 {
3133 *val = pedo_deb_reg.deb_time;
3134 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3135 }
3136
3137 return ret;
3138 }
3139
3140 /**
3141 * @brief Period of time to detect at least one step to generate step
3142 * recognition [1 LSb = 1.6384 s].[set]
3143 *
3144 * @param ctx read / write interface definitions.(ptr)
3145 * @param buff buffer that contains data to write.(ptr)
3146 * @retval Interface status (MANDATORY: return 0 -> no Error).
3147 *
3148 */
lis2ds12_pedo_steps_period_set(stmdev_ctx_t * ctx,uint8_t * buff)3149 int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx,
3150 uint8_t *buff)
3151 {
3152 int32_t ret;
3153
3154 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3155
3156 if (ret == 0)
3157 {
3158 ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1);
3159 }
3160
3161 if (ret == 0)
3162 {
3163 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3164 }
3165
3166 return ret;
3167 }
3168
3169 /**
3170 * @brief Period of time to detect at least one step to generate step
3171 * recognition [1 LSb = 1.6384 s].[get]
3172 *
3173 * @param ctx read / write interface definitions.(ptr)
3174 * @param buff buffer that stores data read.(ptr)
3175 * @retval Interface status (MANDATORY: return 0 -> no Error).
3176 *
3177 */
lis2ds12_pedo_steps_period_get(stmdev_ctx_t * ctx,uint8_t * buff)3178 int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx,
3179 uint8_t *buff)
3180 {
3181 int32_t ret;
3182
3183 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3184
3185 if (ret == 0)
3186 {
3187 ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1);
3188 }
3189
3190 if (ret == 0)
3191 {
3192 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3193 }
3194
3195 return ret;
3196 }
3197
3198 /**
3199 * @}
3200 *
3201 */
3202
3203 /**
3204 * @defgroup significant_motion
3205 * @brief This section groups all the functions that manage the
3206 * significant motion detection.
3207 * @{
3208 *
3209 */
3210
3211 /**
3212 * @brief Significant motion event detection status.[get]
3213 *
3214 * @param ctx read / write interface definitions.(ptr)
3215 * @param val Get the values of sig_mot_detect in reg FUNC_CK_GATE.(ptr)
3216 * @retval Interface status (MANDATORY: return 0 -> no Error).
3217 *
3218 */
lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t * ctx,uint8_t * val)3219 int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx,
3220 uint8_t *val)
3221 {
3222 lis2ds12_func_ck_gate_t func_ck_gate;
3223 int32_t ret;
3224
3225 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
3226 (uint8_t *)&func_ck_gate, 1);
3227 *val = func_ck_gate.sig_mot_detect;
3228
3229 return ret;
3230 }
3231
3232 /**
3233 * @brief Enable significant motion detection function.[set]
3234 *
3235 * @param ctx read / write interface definitions.(ptr)
3236 * @param val change the values of sign_mot_on in reg FUNC_CTRL
3237 * @retval Interface status (MANDATORY: return 0 -> no Error).
3238 *
3239 */
lis2ds12_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)3240 int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
3241 {
3242 lis2ds12_func_ctrl_t func_ctrl;
3243 int32_t ret;
3244
3245 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3246 (uint8_t *)&func_ctrl, 1);
3247
3248 if (ret == 0)
3249 {
3250 func_ctrl.sign_mot_on = val;
3251 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
3252 (uint8_t *)&func_ctrl, 1);
3253 }
3254
3255 return ret;
3256 }
3257
3258 /**
3259 * @brief Enable significant motion detection function.[get]
3260 *
3261 * @param ctx read / write interface definitions.(ptr)
3262 * @param val Get the values of sign_mot_on in reg FUNC_CTRL.(ptr)
3263 * @retval Interface status (MANDATORY: return 0 -> no Error).
3264 *
3265 */
lis2ds12_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)3266 int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
3267 {
3268 lis2ds12_func_ctrl_t func_ctrl;
3269 int32_t ret;
3270
3271 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3272 (uint8_t *)&func_ctrl, 1);
3273 *val = func_ctrl.sign_mot_on;
3274
3275 return ret;
3276 }
3277
3278 /**
3279 * @brief These bits define the threshold value which corresponds to the
3280 * number of steps to be performed by the user upon a change of
3281 * location before the significant motion interrupt is generated.
3282 * It is expressed as an 8-bit unsigned value.
3283 * The default value of this field is equal to 6 (= 00000110b).[set]
3284 *
3285 * @param ctx read / write interface definitions.(ptr)
3286 * @param val change the values of sm_ths in reg SM_THS
3287 * @retval Interface status (MANDATORY: return 0 -> no Error).
3288 *
3289 */
lis2ds12_motion_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3290 int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3291 {
3292 lis2ds12_sm_ths_t sm_ths;
3293 int32_t ret;
3294
3295 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3296
3297 if (ret == 0)
3298 {
3299 ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
3300 }
3301
3302 if (ret == 0)
3303 {
3304 sm_ths.sm_ths = val;
3305 ret = lis2ds12_write_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
3306 }
3307
3308 if (ret == 0)
3309 {
3310 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3311 }
3312
3313 return ret;
3314 }
3315
3316 /**
3317 * @brief These bits define the threshold value which corresponds to the
3318 * number of steps to be performed by the user upon a change of
3319 * location before the significant motion interrupt is generated.
3320 * It is expressed as an 8-bit unsigned value.
3321 * The default value of this field is equal to 6 (= 00000110b).[get]
3322 *
3323 * @param ctx read / write interface definitions.(ptr)
3324 * @param val Get the values of sm_ths in reg SM_THS.(ptr)
3325 * @retval Interface status (MANDATORY: return 0 -> no Error).
3326 *
3327 */
lis2ds12_motion_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3328 int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3329 {
3330 lis2ds12_sm_ths_t sm_ths;
3331 int32_t ret;
3332
3333 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3334
3335 if (ret == 0)
3336 {
3337 ret = lis2ds12_read_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1);
3338 }
3339
3340 if (ret == 0)
3341 {
3342 *val = sm_ths.sm_ths;
3343 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3344 }
3345
3346 return ret;
3347 }
3348
3349 /**
3350 * @}
3351 *
3352 */
3353
3354 /**
3355 * @defgroup tilt_detection
3356 * @brief This section groups all the functions that manage the tilt
3357 * event detection.
3358 * @{
3359 *
3360 */
3361
3362 /**
3363 * @brief Tilt event detection status.[get]
3364 *
3365 * @param ctx read / write interface definitions.(ptr)
3366 * @param val Get the values of tilt_int in reg FUNC_CK_GATE.(ptr)
3367 * @retval Interface status (MANDATORY: return 0 -> no Error).
3368 *
3369 */
lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t * ctx,uint8_t * val)3370 int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx,
3371 uint8_t *val)
3372 {
3373 lis2ds12_func_ck_gate_t func_ck_gate;
3374 int32_t ret;
3375
3376 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE,
3377 (uint8_t *)&func_ck_gate, 1);
3378 *val = func_ck_gate.tilt_int;
3379
3380 return ret;
3381 }
3382
3383 /**
3384 * @brief Enable tilt calculation.[set]
3385 *
3386 * @param ctx read / write interface definitions.(ptr)
3387 * @param val change the values of tilt_on in reg FUNC_CTRL
3388 * @retval Interface status (MANDATORY: return 0 -> no Error).
3389 *
3390 */
lis2ds12_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)3391 int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
3392 {
3393 lis2ds12_func_ctrl_t func_ctrl;
3394 int32_t ret;
3395
3396 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3397 (uint8_t *)&func_ctrl, 1);
3398
3399 if (ret == 0)
3400 {
3401 func_ctrl.tilt_on = val;
3402 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
3403 (uint8_t *)&func_ctrl, 1);
3404 }
3405
3406 return ret;
3407 }
3408
3409 /**
3410 * @brief Enable tilt calculation.[get]
3411 *
3412 * @param ctx read / write interface definitions.(ptr)
3413 * @param val Get the values of tilt_on in reg FUNC_CTRL.(ptr)
3414 * @retval Interface status (MANDATORY: return 0 -> no Error).
3415 *
3416 */
lis2ds12_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)3417 int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
3418 {
3419 lis2ds12_func_ctrl_t func_ctrl;
3420 int32_t ret;
3421
3422 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3423 (uint8_t *)&func_ctrl, 1);
3424 *val = func_ctrl.tilt_on;
3425
3426 return ret;
3427 }
3428
3429 /**
3430 * @}
3431 *
3432 */
3433
3434 /**
3435 * @defgroup module
3436 * @brief This section groups all the functions that manage
3437 * module calculation
3438 * @{
3439 *
3440 */
3441
3442 /**
3443 * @brief Module processing enable.[set]
3444 *
3445 * @param ctx read / write interface definitions.(ptr)
3446 * @param val change the values of module_on in reg FUNC_CTRL
3447 * @retval Interface status (MANDATORY: return 0 -> no Error).
3448 *
3449 */
lis2ds12_module_sens_set(stmdev_ctx_t * ctx,uint8_t val)3450 int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val)
3451 {
3452 lis2ds12_func_ctrl_t func_ctrl;
3453 int32_t ret;
3454
3455 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3456 (uint8_t *)&func_ctrl, 1);
3457
3458 if (ret == 0)
3459 {
3460 func_ctrl.module_on = val;
3461 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
3462 (uint8_t *)&func_ctrl, 1);
3463 }
3464
3465 return ret;
3466 }
3467
3468 /**
3469 * @brief Module processing enable.[get]
3470 *
3471 * @param ctx read / write interface definitions.(ptr)
3472 * @param val Get the values of module_on in reg FUNC_CTRL.(ptr)
3473 * @retval Interface status (MANDATORY: return 0 -> no Error).
3474 *
3475 */
lis2ds12_module_sens_get(stmdev_ctx_t * ctx,uint8_t * val)3476 int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
3477 {
3478 lis2ds12_func_ctrl_t func_ctrl;
3479 int32_t ret;
3480
3481 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3482 (uint8_t *)&func_ctrl, 1);
3483 *val = func_ctrl.module_on;
3484
3485 return ret;
3486 }
3487
3488 /**
3489 * @}
3490 *
3491 */
3492
3493 /**
3494 * @defgroup Sensor_hub
3495 * @brief This section groups all the functions that manage the sensor
3496 * hub functionality.
3497 * @{
3498 *
3499 */
3500
3501 /**
3502 * @brief Sensor hub output registers.[get]
3503 *
3504 * @param ctx read / write interface definitions.(ptr)
3505 * @param val Get registers from SENSORHUB1_REG to SENSORHUB6_REG.(ptr)
3506 * @retval Interface status (MANDATORY: return 0 -> no Error).
3507 *
3508 */
lis2ds12_sh_read_data_raw_get(stmdev_ctx_t * ctx,lis2ds12_sh_read_data_raw_t * val)3509 int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx,
3510 lis2ds12_sh_read_data_raw_t *val)
3511 {
3512 int32_t ret;
3513
3514 ret = lis2ds12_read_reg(ctx, LIS2DS12_SENSORHUB1_REG, (uint8_t *) val,
3515 6);
3516
3517 return ret;
3518 }
3519
3520 /**
3521 * @brief Sensor hub I2C master enable.[set]
3522 *
3523 * @param ctx read / write interface definitions.(ptr)
3524 * @param val change the values of master_on in reg FUNC_CTRL
3525 * @retval Interface status (MANDATORY: return 0 -> no Error).
3526 *
3527 */
lis2ds12_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)3528 int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
3529 {
3530 lis2ds12_func_ctrl_t func_ctrl;
3531 int32_t ret;
3532
3533 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3534 (uint8_t *)&func_ctrl, 1);
3535
3536 if (ret == 0)
3537 {
3538 func_ctrl.master_on = val;
3539 ret = lis2ds12_write_reg(ctx, LIS2DS12_FUNC_CTRL,
3540 (uint8_t *)&func_ctrl, 1);
3541 }
3542
3543 return ret;
3544 }
3545
3546 /**
3547 * @brief Sensor hub I2C master enable.[get]
3548 *
3549 * @param ctx read / write interface definitions.(ptr)
3550 * @param val Get the values of master_on in reg FUNC_CTRL.(ptr)
3551 * @retval Interface status (MANDATORY: return 0 -> no Error).
3552 *
3553 */
lis2ds12_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)3554 int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
3555 {
3556 lis2ds12_func_ctrl_t func_ctrl;
3557 int32_t ret;
3558
3559 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL,
3560 (uint8_t *)&func_ctrl, 1);
3561 *val = func_ctrl.master_on;
3562
3563 return ret;
3564 }
3565
3566 /**
3567 * @brief Configure slave to perform a write.[set]
3568 *
3569 * @param ctx read / write interface definitions.(ptr)
3570 * @param val change a structure:
3571 * - uint8_t slv_add; 8 bit i2c device address
3572 * - uint8_t slv_subadd; 8 bit register device address
3573 * - uint8_t slv_data; 8 bit data to write
3574 * @retval Interface status (MANDATORY: return 0 -> no Error).
3575 *
3576 */
lis2ds12_sh_cfg_write(stmdev_ctx_t * ctx,lis2ds12_sh_cfg_write_t * val)3577 int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx,
3578 lis2ds12_sh_cfg_write_t *val)
3579 {
3580 lis2ds12_slv0_add_t slv0_add;
3581 int32_t ret;
3582
3583 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3584
3585 if (ret == 0)
3586 {
3587 slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
3588 slv0_add.rw_0 = 0;
3589 ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_ADD,
3590 (uint8_t *)&slv0_add, 1);
3591 }
3592
3593 if (ret == 0)
3594 {
3595 ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_SUBADD,
3596 &(val->slv_subadd), 1);
3597 }
3598
3599 if (ret == 0)
3600 {
3601 ret = lis2ds12_write_reg(ctx, LIS2DS12_DATAWRITE_SLV0,
3602 &(val->slv_data), 1);
3603 }
3604
3605 if (ret == 0)
3606 {
3607 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3608 }
3609
3610 return ret;
3611 }
3612
3613 /**
3614 * @brief Configure slave 0 for perform a write/read.[get]
3615 *
3616 * @param ctx read / write interface definitions.(ptr)
3617 * @param val Get a structure(ptr):
3618 * - uint8_t slv_add; 8 bit i2c device address
3619 * - uint8_t slv_subadd; 8 bit register device address
3620 * - uint8_t slv_len; num of bit to read
3621 * @retval Interface status (MANDATORY: return 0 -> no Error).
3622 *
3623 */
lis2ds12_sh_slv_cfg_read(stmdev_ctx_t * ctx,lis2ds12_sh_cfg_read_t * val)3624 int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx,
3625 lis2ds12_sh_cfg_read_t *val)
3626 {
3627 lis2ds12_slv0_add_t slv0_add;
3628 lis2ds12_slv0_config_t slv0_config;
3629 int32_t ret;
3630
3631 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_ADV_BANK);
3632
3633 if (ret == 0)
3634 {
3635 slv0_add.slave0_add = (val->slv_add & 0xFEU) >> 1;
3636 slv0_add.rw_0 = 1;
3637 ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_ADD,
3638 (uint8_t *)&slv0_add, 1);
3639 }
3640
3641 if (ret == 0)
3642 {
3643 ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_SUBADD,
3644 &(val->slv_subadd), 1);
3645 }
3646
3647 if (ret == 0)
3648 {
3649 ret = lis2ds12_read_reg(ctx, LIS2DS12_SLV0_CONFIG,
3650 (uint8_t *)&slv0_config, 1);
3651 }
3652
3653 if (ret == 0)
3654 {
3655 slv0_config.slave0_numop = val->slv_len;
3656 ret = lis2ds12_write_reg(ctx, LIS2DS12_SLV0_CONFIG,
3657 (uint8_t *)&slv0_config, 1);
3658 }
3659
3660 if (ret == 0)
3661 {
3662 ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK);
3663 }
3664
3665 return ret;
3666 }
3667
3668 /**
3669 * @brief Sensor hub communication status.[get]
3670 *
3671 * @param ctx read / write interface definitions.(ptr)
3672 * @param val Get the values of sensorhub_end_op.(ptr)
3673 * @retval Interface status (MANDATORY: return 0 -> no Error).
3674 *
3675 */
lis2ds12_sh_end_op_flag_get(stmdev_ctx_t * ctx,uint8_t * val)3676 int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
3677 {
3678 lis2ds12_func_src_t func_src;
3679 int32_t ret;
3680
3681 ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC, (uint8_t *)&func_src, 1);
3682 *val = func_src.sensorhub_end_op;
3683
3684 return ret;
3685 }
3686
3687 /**
3688 * @}
3689 *
3690 */
3691
3692 /**
3693 * @}
3694 *
3695 */
3696
3697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3698
