1 /**
2 ******************************************************************************
3 * @file lis2dh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2dh_reg.h"
21
22 /**
23 * @defgroup LIS2DH
24 * @brief This file provides a set of functions needed to drive the
25 * lis2dh enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2dh_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2dh_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2DH_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis2dh_from_fs2_hr_to_mg(int16_t lsb)93 float_t lis2dh_from_fs2_hr_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb / 16.0f) * 1.0f;
96 }
97
lis2dh_from_fs4_hr_to_mg(int16_t lsb)98 float_t lis2dh_from_fs4_hr_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb / 16.0f) * 2.0f;
101 }
102
lis2dh_from_fs8_hr_to_mg(int16_t lsb)103 float_t lis2dh_from_fs8_hr_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb / 16.0f) * 4.0f;
106 }
107
lis2dh_from_fs16_hr_to_mg(int16_t lsb)108 float_t lis2dh_from_fs16_hr_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb / 16.0f) * 12.0f;
111 }
112
lis2dh_from_lsb_hr_to_celsius(int16_t lsb)113 float_t lis2dh_from_lsb_hr_to_celsius(int16_t lsb)
114 {
115 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
116 }
117
lis2dh_from_fs2_nm_to_mg(int16_t lsb)118 float_t lis2dh_from_fs2_nm_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb / 64.0f) * 4.0f;
121 }
122
lis2dh_from_fs4_nm_to_mg(int16_t lsb)123 float_t lis2dh_from_fs4_nm_to_mg(int16_t lsb)
124 {
125 return ((float_t)lsb / 64.0f) * 8.0f;
126 }
127
lis2dh_from_fs8_nm_to_mg(int16_t lsb)128 float_t lis2dh_from_fs8_nm_to_mg(int16_t lsb)
129 {
130 return ((float_t)lsb / 64.0f) * 16.0f;
131 }
132
lis2dh_from_fs16_nm_to_mg(int16_t lsb)133 float_t lis2dh_from_fs16_nm_to_mg(int16_t lsb)
134 {
135 return ((float_t)lsb / 64.0f) * 48.0f;
136 }
137
lis2dh_from_lsb_nm_to_celsius(int16_t lsb)138 float_t lis2dh_from_lsb_nm_to_celsius(int16_t lsb)
139 {
140 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
141 }
142
lis2dh_from_fs2_lp_to_mg(int16_t lsb)143 float_t lis2dh_from_fs2_lp_to_mg(int16_t lsb)
144 {
145 return ((float_t)lsb / 256.0f) * 16.0f;
146 }
147
lis2dh_from_fs4_lp_to_mg(int16_t lsb)148 float_t lis2dh_from_fs4_lp_to_mg(int16_t lsb)
149 {
150 return ((float_t)lsb / 256.0f) * 32.0f;
151 }
152
lis2dh_from_fs8_lp_to_mg(int16_t lsb)153 float_t lis2dh_from_fs8_lp_to_mg(int16_t lsb)
154 {
155 return ((float_t)lsb / 256.0f) * 64.0f;
156 }
157
lis2dh_from_fs16_lp_to_mg(int16_t lsb)158 float_t lis2dh_from_fs16_lp_to_mg(int16_t lsb)
159 {
160 return ((float_t)lsb / 256.0f) * 192.0f;
161 }
162
lis2dh_from_lsb_lp_to_celsius(int16_t lsb)163 float_t lis2dh_from_lsb_lp_to_celsius(int16_t lsb)
164 {
165 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
166 }
167
168 /**
169 * @}
170 *
171 */
172
173 /**
174 * @defgroup LIS2DH_Data_generation
175 * @brief This section group all the functions concerning data generation.
176 * @{
177 *
178 */
179
180 /**
181 * @brief Interrupt event counter.[get]
182 *
183 * @param ctx read / write interface definitions
184 * @param val get the value of INT_COUNTER
185 * @retval interface status (MANDATORY: return 0 -> no Error)
186 *
187 */
lis2dh_int_count_get(stmdev_ctx_t * ctx,uint8_t * val)188 int32_t lis2dh_int_count_get(stmdev_ctx_t *ctx, uint8_t *val)
189 {
190 int32_t ret;
191
192 ret = lis2dh_read_reg(ctx, LIS2DH_INT_COUNTER, val, 1);
193
194 return ret;
195 }
196
197 /**
198 * @brief Temperature status register.[get]
199 *
200 * @param ctx read / write interface definitions
201 * @param buff buffer that stores data read
202 * @retval interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
lis2dh_temp_status_reg_get(stmdev_ctx_t * ctx,uint8_t * buff)205 int32_t lis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
206 {
207 int32_t ret;
208
209 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX, buff, 1);
210
211 return ret;
212 }
213 /**
214 * @brief Temperature data available.[get]
215 *
216 * @param ctx read / write interface definitions
217 * @param val change the values of tda in reg STATUS_REG_AUX
218 * @retval interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
lis2dh_temp_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)221 int32_t lis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
222 {
223 lis2dh_status_reg_aux_t status_reg_aux;
224 int32_t ret;
225
226 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX,
227 (uint8_t *)&status_reg_aux, 1);
228 *val = status_reg_aux.tda;
229
230 return ret;
231 }
232
233 /**
234 * @brief Temperature data overrun.[get]
235 *
236 * @param ctx read / write interface definitions
237 * @param val change the values of tor in reg STATUS_REG_AUX
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
lis2dh_temp_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)241 int32_t lis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
242 {
243 lis2dh_status_reg_aux_t status_reg_aux;
244 int32_t ret;
245
246 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX,
247 (uint8_t *)&status_reg_aux, 1);
248 *val = status_reg_aux.tor;
249
250 return ret;
251 }
252 /**
253 * @brief Temperature output value.[get]
254 *
255 * @param ctx read / write interface definitions
256 * @param buff buffer that stores data read
257 * @retval interface status (MANDATORY: return 0 -> no Error)
258 *
259 */
lis2dh_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)260 int32_t lis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
261 {
262 uint8_t buff[2];
263 int32_t ret;
264
265 ret = lis2dh_read_reg(ctx, LIS2DH_OUT_TEMP_L, buff, 2);
266 *val = (int16_t)buff[1];
267 *val = (*val * 256) + (int16_t)buff[0];
268
269 return ret;
270 }
271 /**
272 * @brief Temperature sensor enable.[set]
273 *
274 * @param ctx read / write interface definitions
275 * @param val change the values of temp_en in reg TEMP_CFG_REG
276 * @retval interface status (MANDATORY: return 0 -> no Error)
277 *
278 */
lis2dh_temperature_meas_set(stmdev_ctx_t * ctx,lis2dh_temp_en_t val)279 int32_t lis2dh_temperature_meas_set(stmdev_ctx_t *ctx,
280 lis2dh_temp_en_t val)
281 {
282 lis2dh_temp_cfg_reg_t temp_cfg_reg;
283 int32_t ret;
284
285 ret = lis2dh_read_reg(ctx, LIS2DH_TEMP_CFG_REG,
286 (uint8_t *)&temp_cfg_reg, 1);
287
288 if (ret == 0)
289 {
290 temp_cfg_reg.temp_en = (uint8_t) val;
291 ret = lis2dh_write_reg(ctx, LIS2DH_TEMP_CFG_REG,
292 (uint8_t *)&temp_cfg_reg, 1);
293 }
294
295 return ret;
296 }
297
298 /**
299 * @brief Temperature sensor enable.[get]
300 *
301 * @param ctx read / write interface definitions
302 * @param val get the values of temp_en in reg TEMP_CFG_REG
303 * @retval interface status (MANDATORY: return 0 -> no Error)
304 *
305 */
lis2dh_temperature_meas_get(stmdev_ctx_t * ctx,lis2dh_temp_en_t * val)306 int32_t lis2dh_temperature_meas_get(stmdev_ctx_t *ctx,
307 lis2dh_temp_en_t *val)
308 {
309 lis2dh_temp_cfg_reg_t temp_cfg_reg;
310 int32_t ret;
311
312 ret = lis2dh_read_reg(ctx, LIS2DH_TEMP_CFG_REG,
313 (uint8_t *)&temp_cfg_reg, 1);
314
315 switch (temp_cfg_reg.temp_en)
316 {
317 case LIS2DH_TEMP_DISABLE:
318 *val = LIS2DH_TEMP_DISABLE;
319 break;
320
321 case LIS2DH_TEMP_ENABLE:
322 *val = LIS2DH_TEMP_ENABLE;
323 break;
324
325 default:
326 *val = LIS2DH_TEMP_DISABLE;
327 break;
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Operating mode selection.[set]
335 *
336 * @param ctx read / write interface definitions
337 * @param val change the values of lpen in reg CTRL_REG1
338 * and HR in reg CTRL_REG4
339 * @retval interface status (MANDATORY: return 0 -> no Error)
340 *
341 */
lis2dh_operating_mode_set(stmdev_ctx_t * ctx,lis2dh_op_md_t val)342 int32_t lis2dh_operating_mode_set(stmdev_ctx_t *ctx,
343 lis2dh_op_md_t val)
344 {
345 lis2dh_ctrl_reg1_t ctrl_reg1;
346 lis2dh_ctrl_reg4_t ctrl_reg4;
347 int32_t ret;
348
349 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1,
350 (uint8_t *)&ctrl_reg1, 1);
351
352 if (ret == 0)
353 {
354 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
355 (uint8_t *)&ctrl_reg4, 1);
356 }
357
358 if (ret == 0)
359 {
360 if (val == LIS2DH_HR_12bit)
361 {
362 ctrl_reg1.lpen = 0;
363 ctrl_reg4.hr = 1;
364 }
365
366 if (val == LIS2DH_NM_10bit)
367 {
368 ctrl_reg1.lpen = 0;
369 ctrl_reg4.hr = 0;
370 }
371
372 if (val == LIS2DH_LP_8bit)
373 {
374 ctrl_reg1.lpen = 1;
375 ctrl_reg4.hr = 0;
376 }
377
378 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG1,
379 (uint8_t *)&ctrl_reg1, 1);
380 }
381
382 if (ret == 0)
383 {
384 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
385 (uint8_t *)&ctrl_reg4, 1);
386 }
387
388 return ret;
389 }
390
391 /**
392 * @brief Operating mode selection.[get]
393 *
394 * @param ctx read / write interface definitions
395 * @param val change the values of lpen in reg CTRL_REG1
396 * @retval interface status (MANDATORY: return 0 -> no Error)
397 *
398 */
lis2dh_operating_mode_get(stmdev_ctx_t * ctx,lis2dh_op_md_t * val)399 int32_t lis2dh_operating_mode_get(stmdev_ctx_t *ctx,
400 lis2dh_op_md_t *val)
401 {
402 lis2dh_ctrl_reg1_t ctrl_reg1;
403 lis2dh_ctrl_reg4_t ctrl_reg4;
404 int32_t ret;
405
406 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1,
407 (uint8_t *)&ctrl_reg1, 1);
408
409 if (ret == 0)
410 {
411 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
412 (uint8_t *)&ctrl_reg4, 1);
413
414 if (ctrl_reg1.lpen == PROPERTY_ENABLE)
415 {
416 *val = LIS2DH_LP_8bit;
417 }
418
419 else if (ctrl_reg4.hr == PROPERTY_ENABLE)
420 {
421 *val = LIS2DH_HR_12bit;
422 }
423
424 else
425 {
426 *val = LIS2DH_NM_10bit;
427 }
428 }
429
430 return ret;
431 }
432
433 /**
434 * @brief Output data rate selection.[set]
435 *
436 * @param ctx read / write interface definitions
437 * @param val change the values of odr in reg CTRL_REG1
438 * @retval interface status (MANDATORY: return 0 -> no Error)
439 *
440 */
lis2dh_data_rate_set(stmdev_ctx_t * ctx,lis2dh_odr_t val)441 int32_t lis2dh_data_rate_set(stmdev_ctx_t *ctx, lis2dh_odr_t val)
442 {
443 lis2dh_ctrl_reg1_t ctrl_reg1;
444 int32_t ret;
445
446 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1,
447 (uint8_t *)&ctrl_reg1, 1);
448
449 if (ret == 0)
450 {
451 ctrl_reg1.odr = (uint8_t)val;
452 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG1,
453 (uint8_t *)&ctrl_reg1, 1);
454 }
455
456 return ret;
457 }
458
459 /**
460 * @brief Output data rate selection.[get]
461 *
462 * @param ctx read / write interface definitions
463 * @param val get the values of odr in reg CTRL_REG1
464 * @retval interface status (MANDATORY: return 0 -> no Error)
465 *
466 */
lis2dh_data_rate_get(stmdev_ctx_t * ctx,lis2dh_odr_t * val)467 int32_t lis2dh_data_rate_get(stmdev_ctx_t *ctx, lis2dh_odr_t *val)
468 {
469 lis2dh_ctrl_reg1_t ctrl_reg1;
470 int32_t ret;
471
472 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1,
473 (uint8_t *)&ctrl_reg1, 1);
474
475 switch (ctrl_reg1.odr)
476 {
477 case LIS2DH_POWER_DOWN:
478 *val = LIS2DH_POWER_DOWN;
479 break;
480
481 case LIS2DH_ODR_1Hz:
482 *val = LIS2DH_ODR_1Hz;
483 break;
484
485 case LIS2DH_ODR_10Hz:
486 *val = LIS2DH_ODR_10Hz;
487 break;
488
489 case LIS2DH_ODR_25Hz:
490 *val = LIS2DH_ODR_25Hz;
491 break;
492
493 case LIS2DH_ODR_50Hz:
494 *val = LIS2DH_ODR_50Hz;
495 break;
496
497 case LIS2DH_ODR_100Hz:
498 *val = LIS2DH_ODR_100Hz;
499 break;
500
501 case LIS2DH_ODR_200Hz:
502 *val = LIS2DH_ODR_200Hz;
503 break;
504
505 case LIS2DH_ODR_400Hz:
506 *val = LIS2DH_ODR_400Hz;
507 break;
508
509 case LIS2DH_ODR_1kHz620_LP:
510 *val = LIS2DH_ODR_1kHz620_LP;
511 break;
512
513 case LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP:
514 *val = LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP;
515 break;
516
517 default:
518 *val = LIS2DH_POWER_DOWN;
519 break;
520 }
521
522 return ret;
523 }
524
525 /**
526 * @brief High pass data from internal filter sent to output register
527 * and FIFO.
528 *
529 * @param ctx read / write interface definitions
530 * @param val change the values of fds in reg CTRL_REG2
531 * @retval interface status (MANDATORY: return 0 -> no Error)
532 *
533 */
lis2dh_high_pass_on_outputs_set(stmdev_ctx_t * ctx,uint8_t val)534 int32_t lis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
535 uint8_t val)
536 {
537 lis2dh_ctrl_reg2_t ctrl_reg2;
538 int32_t ret;
539
540 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
541 (uint8_t *)&ctrl_reg2, 1);
542
543 if (ret == 0)
544 {
545 ctrl_reg2.fds = val;
546 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2,
547 (uint8_t *)&ctrl_reg2, 1);
548 }
549
550 return ret;
551 }
552
553 /**
554 * @brief High pass data from internal filter sent to output register
555 * and FIFO.[get]
556 *
557 * @param ctx read / write interface definitions
558 * @param val change the values of fds in reg CTRL_REG2
559 * @retval interface status (MANDATORY: return 0 -> no Error)
560 *
561 */
lis2dh_high_pass_on_outputs_get(stmdev_ctx_t * ctx,uint8_t * val)562 int32_t lis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
563 uint8_t *val)
564 {
565 lis2dh_ctrl_reg2_t ctrl_reg2;
566 int32_t ret;
567
568 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
569 (uint8_t *)&ctrl_reg2, 1);
570 *val = (uint8_t)ctrl_reg2.fds;
571
572 return ret;
573 }
574
575 /**
576 * @brief High-pass filter cutoff frequency selection.[set]
577 *
578 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
579 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
580 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
581 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
582 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
583 *
584 * @param ctx read / write interface definitions
585 * @param val change the values of hpcf in reg CTRL_REG2
586 * @retval interface status (MANDATORY: return 0 -> no Error)
587 *
588 */
lis2dh_high_pass_bandwidth_set(stmdev_ctx_t * ctx,lis2dh_hpcf_t val)589 int32_t lis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
590 lis2dh_hpcf_t val)
591 {
592 lis2dh_ctrl_reg2_t ctrl_reg2;
593 int32_t ret;
594
595 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
596 (uint8_t *)&ctrl_reg2, 1);
597
598 if (ret == 0)
599 {
600 ctrl_reg2.hpcf = (uint8_t)val;
601 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2,
602 (uint8_t *)&ctrl_reg2, 1);
603 }
604
605 return ret;
606 }
607
608 /**
609 * @brief High-pass filter cutoff frequency selection.[get]
610 *
611 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
612 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
613 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
614 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
615 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
616 *
617 * @param ctx read / write interface definitions
618 * @param val get the values of hpcf in reg CTRL_REG2
619 * @retval interface status (MANDATORY: return 0 -> no Error)
620 *
621 */
lis2dh_high_pass_bandwidth_get(stmdev_ctx_t * ctx,lis2dh_hpcf_t * val)622 int32_t lis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
623 lis2dh_hpcf_t *val)
624 {
625 lis2dh_ctrl_reg2_t ctrl_reg2;
626 int32_t ret;
627
628 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
629 (uint8_t *)&ctrl_reg2, 1);
630
631 switch (ctrl_reg2.hpcf)
632 {
633 case LIS2DH_AGGRESSIVE:
634 *val = LIS2DH_AGGRESSIVE;
635 break;
636
637 case LIS2DH_STRONG:
638 *val = LIS2DH_STRONG;
639 break;
640
641 case LIS2DH_MEDIUM:
642 *val = LIS2DH_MEDIUM;
643 break;
644
645 case LIS2DH_LIGHT:
646 *val = LIS2DH_LIGHT;
647 break;
648
649 default:
650 *val = LIS2DH_LIGHT;
651 break;
652 }
653
654 return ret;
655 }
656
657 /**
658 * @brief High-pass filter mode selection.[set]
659 *
660 * @param ctx read / write interface definitions
661 * @param val change the values of hpm in reg CTRL_REG2
662 * @retval interface status (MANDATORY: return 0 -> no Error)
663 *
664 */
lis2dh_high_pass_mode_set(stmdev_ctx_t * ctx,lis2dh_hpm_t val)665 int32_t lis2dh_high_pass_mode_set(stmdev_ctx_t *ctx,
666 lis2dh_hpm_t val)
667 {
668 lis2dh_ctrl_reg2_t ctrl_reg2;
669 int32_t ret;
670
671 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
672 (uint8_t *)&ctrl_reg2, 1);
673
674 if (ret == 0)
675 {
676 ctrl_reg2.hpm = (uint8_t)val;
677 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2,
678 (uint8_t *)&ctrl_reg2, 1);
679 }
680
681 return ret;
682 }
683
684 /**
685 * @brief High-pass filter mode selection.[get]
686 *
687 * @param ctx read / write interface definitions
688 * @param val get the values of hpm in reg CTRL_REG2
689 * @retval interface status (MANDATORY: return 0 -> no Error)
690 *
691 */
lis2dh_high_pass_mode_get(stmdev_ctx_t * ctx,lis2dh_hpm_t * val)692 int32_t lis2dh_high_pass_mode_get(stmdev_ctx_t *ctx,
693 lis2dh_hpm_t *val)
694 {
695 lis2dh_ctrl_reg2_t ctrl_reg2;
696 int32_t ret;
697
698 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
699 (uint8_t *)&ctrl_reg2, 1);
700
701 switch (ctrl_reg2.hpm)
702 {
703 case LIS2DH_NORMAL_WITH_RST:
704 *val = LIS2DH_NORMAL_WITH_RST;
705 break;
706
707 case LIS2DH_REFERENCE_MODE:
708 *val = LIS2DH_REFERENCE_MODE;
709 break;
710
711 case LIS2DH_NORMAL:
712 *val = LIS2DH_NORMAL;
713 break;
714
715 case LIS2DH_AUTORST_ON_INT:
716 *val = LIS2DH_AUTORST_ON_INT;
717 break;
718
719 default:
720 *val = LIS2DH_NORMAL_WITH_RST;
721 break;
722 }
723
724 return ret;
725 }
726
727 /**
728 * @brief Full-scale configuration.[set]
729 *
730 * @param ctx read / write interface definitions
731 * @param val change the values of fs in reg CTRL_REG4
732 * @retval interface status (MANDATORY: return 0 -> no Error)
733 *
734 */
lis2dh_full_scale_set(stmdev_ctx_t * ctx,lis2dh_fs_t val)735 int32_t lis2dh_full_scale_set(stmdev_ctx_t *ctx, lis2dh_fs_t val)
736 {
737 lis2dh_ctrl_reg4_t ctrl_reg4;
738 int32_t ret;
739
740 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
741 (uint8_t *)&ctrl_reg4, 1);
742
743 if (ret == 0)
744 {
745 ctrl_reg4.fs = (uint8_t)val;
746 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
747 (uint8_t *)&ctrl_reg4, 1);
748 }
749
750 return ret;
751 }
752
753 /**
754 * @brief Full-scale configuration.[get]
755 *
756 * @param ctx read / write interface definitions
757 * @param val get the values of fs in reg CTRL_REG4
758 * @retval interface status (MANDATORY: return 0 -> no Error)
759 *
760 */
lis2dh_full_scale_get(stmdev_ctx_t * ctx,lis2dh_fs_t * val)761 int32_t lis2dh_full_scale_get(stmdev_ctx_t *ctx, lis2dh_fs_t *val)
762 {
763 lis2dh_ctrl_reg4_t ctrl_reg4;
764 int32_t ret;
765
766 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
767 (uint8_t *)&ctrl_reg4, 1);
768
769 switch (ctrl_reg4.fs)
770 {
771 case LIS2DH_2g:
772 *val = LIS2DH_2g;
773 break;
774
775 case LIS2DH_4g:
776 *val = LIS2DH_4g;
777 break;
778
779 case LIS2DH_8g:
780 *val = LIS2DH_8g;
781 break;
782
783 case LIS2DH_16g:
784 *val = LIS2DH_16g;
785 break;
786
787 default:
788 *val = LIS2DH_2g;
789 break;
790 }
791
792 return ret;
793 }
794
795 /**
796 * @brief Block Data Update.[set]
797 *
798 * @param ctx read / write interface definitions
799 * @param val change the values of bdu in reg CTRL_REG4
800 * @retval interface status (MANDATORY: return 0 -> no Error)
801 *
802 */
lis2dh_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)803 int32_t lis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
804 {
805 lis2dh_ctrl_reg4_t ctrl_reg4;
806 int32_t ret;
807
808 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
809 (uint8_t *)&ctrl_reg4, 1);
810
811 if (ret == 0)
812 {
813 ctrl_reg4.bdu = val;
814 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
815 (uint8_t *)&ctrl_reg4, 1);
816 }
817
818 return ret;
819 }
820
821 /**
822 * @brief Block Data Update.[get]
823 *
824 * @param ctx read / write interface definitions
825 * @param val change the values of bdu in reg CTRL_REG4
826 * @retval interface status (MANDATORY: return 0 -> no Error)
827 *
828 */
lis2dh_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)829 int32_t lis2dh_block_data_update_get(stmdev_ctx_t *ctx,
830 uint8_t *val)
831 {
832 lis2dh_ctrl_reg4_t ctrl_reg4;
833 int32_t ret;
834
835 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
836 (uint8_t *)&ctrl_reg4, 1);
837 *val = (uint8_t)ctrl_reg4.bdu;
838
839 return ret;
840 }
841
842 /**
843 * @brief Reference value for interrupt generation.[set]
844 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
845 *
846 * @param ctx read / write interface definitions
847 * @param buff buffer that contains data to write
848 * @retval interface status (MANDATORY: return 0 -> no Error)
849 *
850 */
lis2dh_filter_reference_set(stmdev_ctx_t * ctx,uint8_t * buff)851 int32_t lis2dh_filter_reference_set(stmdev_ctx_t *ctx,
852 uint8_t *buff)
853 {
854 int32_t ret;
855
856 ret = lis2dh_write_reg(ctx, LIS2DH_REFERENCE, buff, 1);
857
858 return ret;
859 }
860
861 /**
862 * @brief Reference value for interrupt generation.[get]
863 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
864 *
865 * @param ctx read / write interface definitions
866 * @param buff buffer that stores data read
867 * @retval interface status (MANDATORY: return 0 -> no Error)
868 *
869 */
lis2dh_filter_reference_get(stmdev_ctx_t * ctx,uint8_t * buff)870 int32_t lis2dh_filter_reference_get(stmdev_ctx_t *ctx,
871 uint8_t *buff)
872 {
873 int32_t ret;
874
875 ret = lis2dh_read_reg(ctx, LIS2DH_REFERENCE, buff, 1);
876
877 return ret;
878 }
879 /**
880 * @brief Acceleration set of data available.[get]
881 *
882 * @param ctx read / write interface definitions
883 * @param val change the values of zyxda in reg STATUS_REG
884 * @retval interface status (MANDATORY: return 0 -> no Error)
885 *
886 */
lis2dh_xl_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)887 int32_t lis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
888 {
889 lis2dh_status_reg_t status_reg;
890 int32_t ret;
891
892 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG,
893 (uint8_t *)&status_reg, 1);
894 *val = status_reg.zyxda;
895
896 return ret;
897 }
898 /**
899 * @brief Acceleration set of data overrun.[get]
900 *
901 * @param ctx read / write interface definitions
902 * @param val change the values of zyxor in reg STATUS_REG
903 * @retval interface status (MANDATORY: return 0 -> no Error)
904 *
905 */
lis2dh_xl_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)906 int32_t lis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
907 {
908 lis2dh_status_reg_t status_reg;
909 int32_t ret;
910
911 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG,
912 (uint8_t *)&status_reg, 1);
913 *val = status_reg.zyxor;
914
915 return ret;
916 }
917 /**
918 * @brief Acceleration output value.[get]
919 *
920 * @param ctx read / write interface definitions
921 * @param buff buffer that stores data read
922 * @retval interface status (MANDATORY: return 0 -> no Error)
923 *
924 */
lis2dh_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)925 int32_t lis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
926 {
927 uint8_t buff[6];
928 int32_t ret;
929
930 ret = lis2dh_read_reg(ctx, LIS2DH_OUT_X_L, buff, 6);
931 val[0] = (int16_t)buff[1];
932 val[0] = (val[0] * 256) + (int16_t)buff[0];
933 val[1] = (int16_t)buff[3];
934 val[1] = (val[1] * 256) + (int16_t)buff[2];
935 val[2] = (int16_t)buff[5];
936 val[2] = (val[2] * 256) + (int16_t)buff[4];
937
938 return ret;
939 }
940 /**
941 * @}
942 *
943 */
944
945 /**
946 * @defgroup LIS2DH_Common
947 * @brief This section group common useful functions
948 * @{
949 *
950 */
951
952 /**
953 * @brief DeviceWhoamI .[get]
954 *
955 * @param ctx read / write interface definitions
956 * @param buff buffer that stores data read
957 * @retval interface status (MANDATORY: return 0 -> no Error)
958 *
959 */
lis2dh_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)960 int32_t lis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
961 {
962 int32_t ret;
963
964 ret = lis2dh_read_reg(ctx, LIS2DH_WHO_AM_I, buff, 1);
965
966 return ret;
967 }
968 /**
969 * @brief Self Test.[set]
970 *
971 * @param ctx read / write interface definitions
972 * @param val change the values of st in reg CTRL_REG4
973 * @retval interface status (MANDATORY: return 0 -> no Error)
974 *
975 */
lis2dh_self_test_set(stmdev_ctx_t * ctx,lis2dh_st_t val)976 int32_t lis2dh_self_test_set(stmdev_ctx_t *ctx, lis2dh_st_t val)
977 {
978 lis2dh_ctrl_reg4_t ctrl_reg4;
979 int32_t ret;
980
981 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
982 (uint8_t *)&ctrl_reg4, 1);
983
984 if (ret == 0)
985 {
986 ctrl_reg4.st = (uint8_t)val;
987 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
988 (uint8_t *)&ctrl_reg4, 1);
989 }
990
991 return ret;
992 }
993
994 /**
995 * @brief Self Test.[get]
996 *
997 * @param ctx read / write interface definitions
998 * @param val Get the values of st in reg CTRL_REG4
999 * @retval interface status (MANDATORY: return 0 -> no Error)
1000 *
1001 */
lis2dh_self_test_get(stmdev_ctx_t * ctx,lis2dh_st_t * val)1002 int32_t lis2dh_self_test_get(stmdev_ctx_t *ctx, lis2dh_st_t *val)
1003 {
1004 lis2dh_ctrl_reg4_t ctrl_reg4;
1005 int32_t ret;
1006
1007 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
1008 (uint8_t *)&ctrl_reg4, 1);
1009
1010 switch (ctrl_reg4.st)
1011 {
1012 case LIS2DH_ST_DISABLE:
1013 *val = LIS2DH_ST_DISABLE;
1014 break;
1015
1016 case LIS2DH_ST_POSITIVE:
1017 *val = LIS2DH_ST_POSITIVE;
1018 break;
1019
1020 case LIS2DH_ST_NEGATIVE:
1021 *val = LIS2DH_ST_NEGATIVE;
1022 break;
1023
1024 default:
1025 *val = LIS2DH_ST_DISABLE;
1026 break;
1027 }
1028
1029 return ret;
1030 }
1031
1032 /**
1033 * @brief Big/Little Endian data selection.[set]
1034 *
1035 * @param ctx read / write interface definitions
1036 * @param val change the values of ble in reg CTRL_REG4
1037 * @retval interface status (MANDATORY: return 0 -> no Error)
1038 *
1039 */
lis2dh_data_format_set(stmdev_ctx_t * ctx,lis2dh_ble_t val)1040 int32_t lis2dh_data_format_set(stmdev_ctx_t *ctx,
1041 lis2dh_ble_t val)
1042 {
1043 lis2dh_ctrl_reg4_t ctrl_reg4;
1044 int32_t ret;
1045
1046 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
1047 (uint8_t *)&ctrl_reg4, 1);
1048
1049 if (ret == 0)
1050 {
1051 ctrl_reg4.ble = (uint8_t)val;
1052 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
1053 (uint8_t *)&ctrl_reg4, 1);
1054 }
1055
1056 return ret;
1057 }
1058
1059 /**
1060 * @brief Big/Little Endian data selection.[get]
1061 *
1062 * @param ctx read / write interface definitions
1063 * @param val get the values of ble in reg CTRL_REG4
1064 * @retval interface status (MANDATORY: return 0 -> no Error)
1065 *
1066 */
lis2dh_data_format_get(stmdev_ctx_t * ctx,lis2dh_ble_t * val)1067 int32_t lis2dh_data_format_get(stmdev_ctx_t *ctx,
1068 lis2dh_ble_t *val)
1069 {
1070 lis2dh_ctrl_reg4_t ctrl_reg4;
1071 int32_t ret;
1072
1073 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
1074 (uint8_t *)&ctrl_reg4, 1);
1075
1076 switch (ctrl_reg4.ble)
1077 {
1078 case LIS2DH_LSB_AT_LOW_ADD:
1079 *val = LIS2DH_LSB_AT_LOW_ADD;
1080 break;
1081
1082 case LIS2DH_MSB_AT_LOW_ADD:
1083 *val = LIS2DH_MSB_AT_LOW_ADD;
1084 break;
1085
1086 default:
1087 *val = LIS2DH_LSB_AT_LOW_ADD;
1088 break;
1089 }
1090
1091 return ret;
1092 }
1093
1094 /**
1095 * @brief Reboot memory content. Reload the calibration parameters.[set]
1096 *
1097 * @param ctx read / write interface definitions
1098 * @param val change the values of boot in reg CTRL_REG5
1099 * @retval interface status (MANDATORY: return 0 -> no Error)
1100 *
1101 */
lis2dh_boot_set(stmdev_ctx_t * ctx,uint8_t val)1102 int32_t lis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1103 {
1104 lis2dh_ctrl_reg5_t ctrl_reg5;
1105 int32_t ret;
1106
1107 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1108 (uint8_t *)&ctrl_reg5, 1);
1109
1110 if (ret == 0)
1111 {
1112 ctrl_reg5.boot = val;
1113 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1114 (uint8_t *)&ctrl_reg5, 1);
1115 }
1116
1117 return ret;
1118 }
1119
1120 /**
1121 * @brief Reboot memory content. Reload the calibration parameters.[get]
1122 *
1123 * @param ctx read / write interface definitions
1124 * @param val change the values of boot in reg CTRL_REG5
1125 * @retval interface status (MANDATORY: return 0 -> no Error)
1126 *
1127 */
lis2dh_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1128 int32_t lis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1129 {
1130 lis2dh_ctrl_reg5_t ctrl_reg5;
1131 int32_t ret;
1132
1133 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1134 (uint8_t *)&ctrl_reg5, 1);
1135 *val = (uint8_t)ctrl_reg5.boot;
1136
1137 return ret;
1138 }
1139
1140 /**
1141 * @brief Info about device status.[get]
1142 *
1143 * @param ctx read / write interface definitions
1144 * @param val register STATUS_REG
1145 * @retval interface status (MANDATORY: return 0 -> no Error)
1146 *
1147 */
lis2dh_status_get(stmdev_ctx_t * ctx,lis2dh_status_reg_t * val)1148 int32_t lis2dh_status_get(stmdev_ctx_t *ctx,
1149 lis2dh_status_reg_t *val)
1150 {
1151 int32_t ret;
1152
1153 ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG, (uint8_t *) val, 1);
1154
1155 return ret;
1156 }
1157 /**
1158 * @}
1159 *
1160 */
1161
1162 /**
1163 * @defgroup LIS2DH_Interrupts_generator_1
1164 * @brief This section group all the functions that manage the first
1165 * interrupts generator
1166 * @{
1167 *
1168 */
1169
1170 /**
1171 * @brief Interrupt generator 1 configuration register.[set]
1172 *
1173 * @param ctx read / write interface definitions
1174 * @param val register INT1_CFG
1175 * @retval interface status (MANDATORY: return 0 -> no Error)
1176 *
1177 */
lis2dh_int1_gen_conf_set(stmdev_ctx_t * ctx,lis2dh_int1_cfg_t * val)1178 int32_t lis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
1179 lis2dh_int1_cfg_t *val)
1180 {
1181 int32_t ret;
1182
1183 ret = lis2dh_write_reg(ctx, LIS2DH_INT1_CFG, (uint8_t *) val, 1);
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Interrupt generator 1 configuration register.[get]
1190 *
1191 * @param ctx read / write interface definitions
1192 * @param val register INT1_CFG
1193 * @retval interface status (MANDATORY: return 0 -> no Error)
1194 *
1195 */
lis2dh_int1_gen_conf_get(stmdev_ctx_t * ctx,lis2dh_int1_cfg_t * val)1196 int32_t lis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
1197 lis2dh_int1_cfg_t *val)
1198 {
1199 int32_t ret;
1200
1201 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_CFG, (uint8_t *) val, 1);
1202
1203 return ret;
1204 }
1205
1206 /**
1207 * @brief Interrupt generator 1 source register.[get]
1208 *
1209 * @param ctx read / write interface definitions
1210 * @param val Registers INT1_SRC
1211 * @retval interface status (MANDATORY: return 0 -> no Error)
1212 *
1213 */
lis2dh_int1_gen_source_get(stmdev_ctx_t * ctx,lis2dh_int1_src_t * val)1214 int32_t lis2dh_int1_gen_source_get(stmdev_ctx_t *ctx,
1215 lis2dh_int1_src_t *val)
1216 {
1217 int32_t ret;
1218
1219 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_SRC, (uint8_t *) val, 1);
1220
1221 return ret;
1222 }
1223 /**
1224 * @brief User-defined threshold value for xl interrupt event on
1225 * generator 1.[set]
1226 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1227 *
1228 * @param ctx read / write interface definitions
1229 * @param val change the values of ths in reg INT1_THS
1230 * @retval interface status (MANDATORY: return 0 -> no Error)
1231 *
1232 */
lis2dh_int1_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1233 int32_t lis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx,
1234 uint8_t val)
1235 {
1236 lis2dh_int1_ths_t int1_ths;
1237 int32_t ret;
1238
1239 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1240
1241 if (ret == 0)
1242 {
1243 int1_ths.ths = val;
1244 ret = lis2dh_write_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1245 }
1246
1247 return ret;
1248 }
1249
1250 /**
1251 * @brief User-defined threshold value for xl interrupt event on
1252 * generator 1.[get]
1253 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1254 *
1255 * @param ctx read / write interface definitions
1256 * @param val change the values of ths in reg INT1_THS
1257 * @retval interface status (MANDATORY: return 0 -> no Error)
1258 *
1259 */
lis2dh_int1_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1260 int32_t lis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx,
1261 uint8_t *val)
1262 {
1263 lis2dh_int1_ths_t int1_ths;
1264 int32_t ret;
1265
1266 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1267 *val = (uint8_t)int1_ths.ths;
1268
1269 return ret;
1270 }
1271
1272 /**
1273 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1274 * recognized.[set]
1275 *
1276 * @param ctx read / write interface definitions
1277 * @param val change the values of d in reg INT1_DURATION
1278 * @retval interface status (MANDATORY: return 0 -> no Error)
1279 *
1280 */
lis2dh_int1_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1281 int32_t lis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1282 {
1283 lis2dh_int1_duration_t int1_duration;
1284 int32_t ret;
1285
1286 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_DURATION,
1287 (uint8_t *)&int1_duration, 1);
1288
1289 if (ret == 0)
1290 {
1291 int1_duration.d = val;
1292 ret = lis2dh_write_reg(ctx, LIS2DH_INT1_DURATION,
1293 (uint8_t *)&int1_duration, 1);
1294 }
1295
1296 return ret;
1297 }
1298
1299 /**
1300 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1301 * recognized.[get]
1302 *
1303 * @param ctx read / write interface definitions
1304 * @param val change the values of d in reg INT1_DURATION
1305 * @retval interface status (MANDATORY: return 0 -> no Error)
1306 *
1307 */
lis2dh_int1_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1308 int32_t lis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx,
1309 uint8_t *val)
1310 {
1311 lis2dh_int1_duration_t int1_duration;
1312 int32_t ret;
1313
1314 ret = lis2dh_read_reg(ctx, LIS2DH_INT1_DURATION,
1315 (uint8_t *)&int1_duration, 1);
1316 *val = (uint8_t)int1_duration.d;
1317
1318 return ret;
1319 }
1320
1321 /**
1322 * @}
1323 *
1324 */
1325
1326 /**
1327 * @defgroup LIS2DH_Interrupts_generator_2
1328 * @brief This section group all the functions that manage the second
1329 * interrupts generator
1330 * @{
1331 *
1332 */
1333
1334 /**
1335 * @brief Interrupt generator 2 configuration register.[set]
1336 *
1337 * @param ctx read / write interface definitions
1338 * @param val registers INT2_CFG
1339 * @retval interface status (MANDATORY: return 0 -> no Error)
1340 *
1341 */
lis2dh_int2_gen_conf_set(stmdev_ctx_t * ctx,lis2dh_int2_cfg_t * val)1342 int32_t lis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
1343 lis2dh_int2_cfg_t *val)
1344 {
1345 int32_t ret;
1346
1347 ret = lis2dh_write_reg(ctx, LIS2DH_INT2_CFG, (uint8_t *) val, 1);
1348
1349 return ret;
1350 }
1351
1352 /**
1353 * @brief Interrupt generator 2 configuration register.[get]
1354 *
1355 * @param ctx read / write interface definitions
1356 * @param val registers INT2_CFG
1357 * @retval interface status (MANDATORY: return 0 -> no Error)
1358 *
1359 */
lis2dh_int2_gen_conf_get(stmdev_ctx_t * ctx,lis2dh_int2_cfg_t * val)1360 int32_t lis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
1361 lis2dh_int2_cfg_t *val)
1362 {
1363 int32_t ret;
1364
1365 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_CFG, (uint8_t *) val, 1);
1366
1367 return ret;
1368 }
1369 /**
1370 * @brief Interrupt generator 2 source register.[get]
1371 *
1372 * @param ctx read / write interface definitions
1373 * @param val registers INT2_SRC
1374 * @retval interface status (MANDATORY: return 0 -> no Error)
1375 *
1376 */
lis2dh_int2_gen_source_get(stmdev_ctx_t * ctx,lis2dh_int2_src_t * val)1377 int32_t lis2dh_int2_gen_source_get(stmdev_ctx_t *ctx,
1378 lis2dh_int2_src_t *val)
1379 {
1380 int32_t ret;
1381
1382 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_SRC, (uint8_t *) val, 1);
1383
1384 return ret;
1385 }
1386 /**
1387 * @brief User-defined threshold value for xl interrupt event on
1388 * generator 2.[set]
1389 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1390 *
1391 * @param ctx read / write interface definitions
1392 * @param val change the values of ths in reg INT2_THS
1393 * @retval interface status (MANDATORY: return 0 -> no Error)
1394 *
1395 */
lis2dh_int2_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1396 int32_t lis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx,
1397 uint8_t val)
1398 {
1399 lis2dh_int2_ths_t int2_ths;
1400 int32_t ret;
1401
1402 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1403
1404 if (ret == 0)
1405 {
1406 int2_ths.ths = val;
1407 ret = lis2dh_write_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1408 }
1409
1410 return ret;
1411 }
1412
1413 /**
1414 * @brief User-defined threshold value for xl interrupt event on
1415 * generator 2.[get]
1416 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1417 *
1418 * @param ctx read / write interface definitions
1419 * @param val change the values of ths in reg INT2_THS
1420 * @retval interface status (MANDATORY: return 0 -> no Error)
1421 *
1422 */
lis2dh_int2_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1423 int32_t lis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx,
1424 uint8_t *val)
1425 {
1426 lis2dh_int2_ths_t int2_ths;
1427 int32_t ret;
1428
1429 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1430 *val = (uint8_t)int2_ths.ths;
1431
1432 return ret;
1433 }
1434
1435 /**
1436 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1437 * recognized .[set]
1438 *
1439 * @param ctx read / write interface definitions
1440 * @param val change the values of d in reg INT2_DURATION
1441 * @retval interface status (MANDATORY: return 0 -> no Error)
1442 *
1443 */
lis2dh_int2_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1444 int32_t lis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1445 {
1446 lis2dh_int2_duration_t int2_duration;
1447 int32_t ret;
1448
1449 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_DURATION,
1450 (uint8_t *)&int2_duration, 1);
1451
1452 if (ret == 0)
1453 {
1454 int2_duration.d = val;
1455 ret = lis2dh_write_reg(ctx, LIS2DH_INT2_DURATION,
1456 (uint8_t *)&int2_duration, 1);
1457 }
1458
1459 return ret;
1460 }
1461
1462 /**
1463 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1464 * recognized.[get]
1465 *
1466 * @param ctx read / write interface definitions
1467 * @param val change the values of d in reg INT2_DURATION
1468 * @retval interface status (MANDATORY: return 0 -> no Error)
1469 *
1470 */
lis2dh_int2_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1471 int32_t lis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx,
1472 uint8_t *val)
1473 {
1474 lis2dh_int2_duration_t int2_duration;
1475 int32_t ret;
1476
1477 ret = lis2dh_read_reg(ctx, LIS2DH_INT2_DURATION,
1478 (uint8_t *)&int2_duration, 1);
1479 *val = (uint8_t)int2_duration.d;
1480
1481 return ret;
1482 }
1483
1484 /**
1485 * @}
1486 *
1487 */
1488
1489 /**
1490 * @defgroup LIS2DH_Interrupt_pins
1491 * @brief This section group all the functions that manage interrupt pins
1492 * @{
1493 *
1494 */
1495
1496 /**
1497 * @brief High-pass filter on interrupts/tap generator.[set]
1498 *
1499 * @param ctx read / write interface definitions
1500 * @param val change the values of hp in reg CTRL_REG2
1501 * @retval interface status (MANDATORY: return 0 -> no Error)
1502 *
1503 */
lis2dh_high_pass_int_conf_set(stmdev_ctx_t * ctx,lis2dh_hp_t val)1504 int32_t lis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
1505 lis2dh_hp_t val)
1506 {
1507 lis2dh_ctrl_reg2_t ctrl_reg2;
1508 int32_t ret;
1509
1510 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
1511 (uint8_t *)&ctrl_reg2, 1);
1512
1513 if (ret == 0)
1514 {
1515 ctrl_reg2.hp = (uint8_t)val;
1516 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2,
1517 (uint8_t *)&ctrl_reg2, 1);
1518 }
1519
1520 return ret;
1521 }
1522
1523 /**
1524 * @brief High-pass filter on interrupts/tap generator.[get]
1525 *
1526 * @param ctx read / write interface definitions
1527 * @param val Get the values of hp in reg CTRL_REG2
1528 * @retval interface status (MANDATORY: return 0 -> no Error)
1529 *
1530 */
lis2dh_high_pass_int_conf_get(stmdev_ctx_t * ctx,lis2dh_hp_t * val)1531 int32_t lis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
1532 lis2dh_hp_t *val)
1533 {
1534 lis2dh_ctrl_reg2_t ctrl_reg2;
1535 int32_t ret;
1536
1537 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2,
1538 (uint8_t *)&ctrl_reg2, 1);
1539
1540 switch (ctrl_reg2.hp)
1541 {
1542 case LIS2DH_DISC_FROM_INT_GENERATOR:
1543 *val = LIS2DH_DISC_FROM_INT_GENERATOR;
1544 break;
1545
1546 case LIS2DH_ON_INT1_GEN:
1547 *val = LIS2DH_ON_INT1_GEN;
1548 break;
1549
1550 case LIS2DH_ON_INT2_GEN:
1551 *val = LIS2DH_ON_INT2_GEN;
1552 break;
1553
1554 case LIS2DH_ON_TAP_GEN:
1555 *val = LIS2DH_ON_TAP_GEN;
1556 break;
1557
1558 case LIS2DH_ON_INT1_INT2_GEN:
1559 *val = LIS2DH_ON_INT1_INT2_GEN;
1560 break;
1561
1562 case LIS2DH_ON_INT1_TAP_GEN:
1563 *val = LIS2DH_ON_INT1_TAP_GEN;
1564 break;
1565
1566 case LIS2DH_ON_INT2_TAP_GEN:
1567 *val = LIS2DH_ON_INT2_TAP_GEN;
1568 break;
1569
1570 case LIS2DH_ON_INT1_INT2_TAP_GEN:
1571 *val = LIS2DH_ON_INT1_INT2_TAP_GEN;
1572 break;
1573
1574 default:
1575 *val = LIS2DH_DISC_FROM_INT_GENERATOR;
1576 break;
1577 }
1578
1579 return ret;
1580 }
1581
1582 /**
1583 * @brief Int1 pin routing configuration register.[set]
1584 *
1585 * @param ctx read / write interface definitions
1586 * @param val registers CTRL_REG3
1587 * @retval interface status (MANDATORY: return 0 -> no Error)
1588 *
1589 */
lis2dh_pin_int1_config_set(stmdev_ctx_t * ctx,lis2dh_ctrl_reg3_t * val)1590 int32_t lis2dh_pin_int1_config_set(stmdev_ctx_t *ctx,
1591 lis2dh_ctrl_reg3_t *val)
1592 {
1593 int32_t ret;
1594
1595 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1596
1597 return ret;
1598 }
1599
1600 /**
1601 * @brief Int1 pin routing configuration register.[get]
1602 *
1603 * @param ctx read / write interface definitions
1604 * @param val registers CTRL_REG3
1605 * @retval interface status (MANDATORY: return 0 -> no Error)
1606 *
1607 */
lis2dh_pin_int1_config_get(stmdev_ctx_t * ctx,lis2dh_ctrl_reg3_t * val)1608 int32_t lis2dh_pin_int1_config_get(stmdev_ctx_t *ctx,
1609 lis2dh_ctrl_reg3_t *val)
1610 {
1611 int32_t ret;
1612
1613 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1614
1615 return ret;
1616 }
1617 /**
1618 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1619 * on INT2 pin when 6D bit on
1620 * INT2_CFG (34h) is set to 1.
1621 *
1622 * @param ctx read / write interface definitions
1623 * @param val change the values of d4d_int2 in reg CTRL_REG5
1624 * @retval interface status (MANDATORY: return 0 -> no Error)
1625 *
1626 */
lis2dh_int2_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1627 int32_t lis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
1628 uint8_t val)
1629 {
1630 lis2dh_ctrl_reg5_t ctrl_reg5;
1631 int32_t ret;
1632
1633 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1634 (uint8_t *)&ctrl_reg5, 1);
1635
1636 if (ret == 0)
1637 {
1638 ctrl_reg5.d4d_int2 = val;
1639 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1640 (uint8_t *)&ctrl_reg5, 1);
1641 }
1642
1643 return ret;
1644 }
1645
1646 /**
1647 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1648 * INT2_CFG (34h) is set to 1.[get]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param val change the values of d4d_int2 in reg CTRL_REG5
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lis2dh_int2_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1655 int32_t lis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
1656 uint8_t *val)
1657 {
1658 lis2dh_ctrl_reg5_t ctrl_reg5;
1659 int32_t ret;
1660
1661 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1662 (uint8_t *)&ctrl_reg5, 1);
1663 *val = (uint8_t)ctrl_reg5.d4d_int2;
1664
1665 return ret;
1666 }
1667
1668 /**
1669 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1670 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1671 * itself.[set]
1672 *
1673 * @param ctx read / write interface definitions
1674 * @param val change the values of lir_int2 in reg CTRL_REG5
1675 * @retval interface status (MANDATORY: return 0 -> no Error)
1676 *
1677 */
lis2dh_int2_pin_notification_mode_set(stmdev_ctx_t * ctx,lis2dh_lir_int2_t val)1678 int32_t lis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
1679 lis2dh_lir_int2_t val)
1680 {
1681 lis2dh_ctrl_reg5_t ctrl_reg5;
1682 int32_t ret;
1683
1684 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1685 (uint8_t *)&ctrl_reg5, 1);
1686
1687 if (ret == 0)
1688 {
1689 ctrl_reg5.lir_int2 = (uint8_t)val;
1690 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1691 (uint8_t *)&ctrl_reg5, 1);
1692 }
1693
1694 return ret;
1695 }
1696
1697 /**
1698 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1699 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1700 * itself.[get]
1701 *
1702 * @param ctx read / write interface definitions
1703 * @param val Get the values of lir_int2 in reg CTRL_REG5
1704 * @retval interface status (MANDATORY: return 0 -> no Error)
1705 *
1706 */
lis2dh_int2_pin_notification_mode_get(stmdev_ctx_t * ctx,lis2dh_lir_int2_t * val)1707 int32_t lis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
1708 lis2dh_lir_int2_t *val)
1709 {
1710 lis2dh_ctrl_reg5_t ctrl_reg5;
1711 int32_t ret;
1712
1713 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1714 (uint8_t *)&ctrl_reg5, 1);
1715
1716 switch (ctrl_reg5.lir_int2)
1717 {
1718 case LIS2DH_INT2_PULSED:
1719 *val = LIS2DH_INT2_PULSED;
1720 break;
1721
1722 case LIS2DH_INT2_LATCHED:
1723 *val = LIS2DH_INT2_LATCHED;
1724 break;
1725
1726 default:
1727 *val = LIS2DH_INT2_PULSED;
1728 break;
1729 }
1730
1731 return ret;
1732 }
1733
1734 /**
1735 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1736 * on INT1_CFG(30h) is set to 1.[set]
1737 *
1738 * @param ctx read / write interface definitions
1739 * @param val change the values of d4d_int1 in reg CTRL_REG5
1740 * @retval interface status (MANDATORY: return 0 -> no Error)
1741 *
1742 */
lis2dh_int1_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1743 int32_t lis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
1744 uint8_t val)
1745 {
1746 lis2dh_ctrl_reg5_t ctrl_reg5;
1747 int32_t ret;
1748
1749 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1750 (uint8_t *)&ctrl_reg5, 1);
1751
1752 if (ret == 0)
1753 {
1754 ctrl_reg5.d4d_int1 = val;
1755 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1756 (uint8_t *)&ctrl_reg5, 1);
1757 }
1758
1759 return ret;
1760 }
1761
1762 /**
1763 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1764 * INT1_CFG(30h) is set to 1.[get]
1765 *
1766 * @param ctx read / write interface definitions
1767 * @param val change the values of d4d_int1 in reg CTRL_REG5
1768 * @retval interface status (MANDATORY: return 0 -> no Error)
1769 *
1770 */
lis2dh_int1_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1771 int32_t lis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
1772 uint8_t *val)
1773 {
1774 lis2dh_ctrl_reg5_t ctrl_reg5;
1775 int32_t ret;
1776
1777 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1778 (uint8_t *)&ctrl_reg5, 1);
1779 *val = (uint8_t)ctrl_reg5.d4d_int1;
1780
1781 return ret;
1782 }
1783
1784 /**
1785 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1786 * register cleared by reading INT1_SRC (31h) itself.[set]
1787 *
1788 * @param ctx read / write interface definitions
1789 * @param val change the values of lir_int1 in reg CTRL_REG5
1790 * @retval interface status (MANDATORY: return 0 -> no Error)
1791 *
1792 */
lis2dh_int1_pin_notification_mode_set(stmdev_ctx_t * ctx,lis2dh_lir_int1_t val)1793 int32_t lis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
1794 lis2dh_lir_int1_t val)
1795 {
1796 lis2dh_ctrl_reg5_t ctrl_reg5;
1797 int32_t ret;
1798
1799 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1800 (uint8_t *)&ctrl_reg5, 1);
1801
1802 if (ret == 0)
1803 {
1804 ctrl_reg5.lir_int1 = (uint8_t)val;
1805 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1806 (uint8_t *)&ctrl_reg5, 1);
1807 }
1808
1809 return ret;
1810 }
1811
1812 /**
1813 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1814 * register cleared by reading INT1_SRC (31h) itself.[get]
1815 *
1816 * @param ctx read / write interface definitions
1817 * @param val Get the values of lir_int1 in reg CTRL_REG5
1818 * @retval interface status (MANDATORY: return 0 -> no Error)
1819 *
1820 */
lis2dh_int1_pin_notification_mode_get(stmdev_ctx_t * ctx,lis2dh_lir_int1_t * val)1821 int32_t lis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
1822 lis2dh_lir_int1_t *val)
1823 {
1824 lis2dh_ctrl_reg5_t ctrl_reg5;
1825 int32_t ret;
1826
1827 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1828 (uint8_t *)&ctrl_reg5, 1);
1829
1830 switch (ctrl_reg5.lir_int1)
1831 {
1832 case LIS2DH_INT1_PULSED:
1833 *val = LIS2DH_INT1_PULSED;
1834 break;
1835
1836 case LIS2DH_INT1_LATCHED:
1837 *val = LIS2DH_INT1_LATCHED;
1838 break;
1839
1840 default:
1841 *val = LIS2DH_INT1_PULSED;
1842 break;
1843 }
1844
1845 return ret;
1846 }
1847
1848 /**
1849 * @brief Int2 pin routing configuration register.[set]
1850 *
1851 * @param ctx read / write interface definitions
1852 * @param val registers CTRL_REG6
1853 * @retval interface status (MANDATORY: return 0 -> no Error)
1854 *
1855 */
lis2dh_pin_int2_config_set(stmdev_ctx_t * ctx,lis2dh_ctrl_reg6_t * val)1856 int32_t lis2dh_pin_int2_config_set(stmdev_ctx_t *ctx,
1857 lis2dh_ctrl_reg6_t *val)
1858 {
1859 int32_t ret;
1860
1861 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief Int2 pin routing configuration register.[get]
1868 *
1869 * @param ctx read / write interface definitions
1870 * @param val registers CTRL_REG6
1871 * @retval interface status (MANDATORY: return 0 -> no Error)
1872 *
1873 */
lis2dh_pin_int2_config_get(stmdev_ctx_t * ctx,lis2dh_ctrl_reg6_t * val)1874 int32_t lis2dh_pin_int2_config_get(stmdev_ctx_t *ctx,
1875 lis2dh_ctrl_reg6_t *val)
1876 {
1877 int32_t ret;
1878
1879 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1880
1881 return ret;
1882 }
1883 /**
1884 * @}
1885 *
1886 */
1887
1888 /**
1889 * @defgroup LIS2DH_Fifo
1890 * @brief This section group all the functions concerning the fifo usage
1891 * @{
1892 *
1893 */
1894
1895 /**
1896 * @brief FIFO enable.[set]
1897 *
1898 * @param ctx read / write interface definitions
1899 * @param val change the values of fifo_en in reg CTRL_REG5
1900 * @retval interface status (MANDATORY: return 0 -> no Error)
1901 *
1902 */
lis2dh_fifo_set(stmdev_ctx_t * ctx,uint8_t val)1903 int32_t lis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
1904 {
1905 lis2dh_ctrl_reg5_t ctrl_reg5;
1906 int32_t ret;
1907
1908 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1909 (uint8_t *)&ctrl_reg5, 1);
1910
1911 if (ret == 0)
1912 {
1913 ctrl_reg5.fifo_en = val;
1914 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5,
1915 (uint8_t *)&ctrl_reg5, 1);
1916 }
1917
1918 return ret;
1919 }
1920
1921 /**
1922 * @brief FIFO enable.[get]
1923 *
1924 * @param ctx read / write interface definitions
1925 * @param val change the values of fifo_en in reg CTRL_REG5
1926 * @retval interface status (MANDATORY: return 0 -> no Error)
1927 *
1928 */
lis2dh_fifo_get(stmdev_ctx_t * ctx,uint8_t * val)1929 int32_t lis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
1930 {
1931 lis2dh_ctrl_reg5_t ctrl_reg5;
1932 int32_t ret;
1933
1934 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5,
1935 (uint8_t *)&ctrl_reg5, 1);
1936 *val = (uint8_t)ctrl_reg5.fifo_en;
1937
1938 return ret;
1939 }
1940
1941 /**
1942 * @brief FIFO watermark level selection.[set]
1943 *
1944 * @param ctx read / write interface definitions
1945 * @param val change the values of fth in reg FIFO_CTRL_REG
1946 * @retval interface status (MANDATORY: return 0 -> no Error)
1947 *
1948 */
lis2dh_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)1949 int32_t lis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
1950 {
1951 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1952 int32_t ret;
1953
1954 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
1955 (uint8_t *)&fifo_ctrl_reg, 1);
1956
1957 if (ret == 0)
1958 {
1959 fifo_ctrl_reg.fth = val;
1960 ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG,
1961 (uint8_t *)&fifo_ctrl_reg, 1);
1962 }
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @brief FIFO watermark level selection.[get]
1969 *
1970 * @param ctx read / write interface definitions
1971 * @param val change the values of fth in reg FIFO_CTRL_REG
1972 * @retval interface status (MANDATORY: return 0 -> no Error)
1973 *
1974 */
lis2dh_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)1975 int32_t lis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
1976 {
1977 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1978 int32_t ret;
1979
1980 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
1981 (uint8_t *)&fifo_ctrl_reg, 1);
1982 *val = (uint8_t)fifo_ctrl_reg.fth;
1983
1984 return ret;
1985 }
1986
1987 /**
1988 * @brief Trigger FIFO selection.[set]
1989 *
1990 * @param ctx read / write interface definitions
1991 * @param val change the values of tr in reg FIFO_CTRL_REG
1992 * @retval interface status (MANDATORY: return 0 -> no Error)
1993 *
1994 */
lis2dh_fifo_trigger_event_set(stmdev_ctx_t * ctx,lis2dh_tr_t val)1995 int32_t lis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
1996 lis2dh_tr_t val)
1997 {
1998 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1999 int32_t ret;
2000
2001 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2002 (uint8_t *)&fifo_ctrl_reg, 1);
2003
2004 if (ret == 0)
2005 {
2006 fifo_ctrl_reg.tr = (uint8_t)val;
2007 ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2008 (uint8_t *)&fifo_ctrl_reg, 1);
2009 }
2010
2011 return ret;
2012 }
2013
2014 /**
2015 * @brief Trigger FIFO selection.[get]
2016 *
2017 * @param ctx read / write interface definitions
2018 * @param val Get the values of tr in reg FIFO_CTRL_REG
2019 * @retval interface status (MANDATORY: return 0 -> no Error)
2020 *
2021 */
lis2dh_fifo_trigger_event_get(stmdev_ctx_t * ctx,lis2dh_tr_t * val)2022 int32_t lis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
2023 lis2dh_tr_t *val)
2024 {
2025 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2026 int32_t ret;
2027
2028 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2029 (uint8_t *)&fifo_ctrl_reg, 1);
2030
2031 switch (fifo_ctrl_reg.tr)
2032 {
2033 case LIS2DH_INT1_GEN:
2034 *val = LIS2DH_INT1_GEN;
2035 break;
2036
2037 case LIS2DH_INT2_GEN:
2038 *val = LIS2DH_INT2_GEN;
2039 break;
2040
2041 default:
2042 *val = LIS2DH_INT1_GEN;
2043 break;
2044 }
2045
2046 return ret;
2047 }
2048
2049 /**
2050 * @brief FIFO mode selection.[set]
2051 *
2052 * @param ctx read / write interface definitions
2053 * @param val change the values of fm in reg FIFO_CTRL_REG
2054 * @retval interface status (MANDATORY: return 0 -> no Error)
2055 *
2056 */
lis2dh_fifo_mode_set(stmdev_ctx_t * ctx,lis2dh_fm_t val)2057 int32_t lis2dh_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh_fm_t val)
2058 {
2059 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2060 int32_t ret;
2061
2062 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2063 (uint8_t *)&fifo_ctrl_reg, 1);
2064
2065 if (ret == 0)
2066 {
2067 fifo_ctrl_reg.fm = (uint8_t)val;
2068 ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2069 (uint8_t *)&fifo_ctrl_reg, 1);
2070 }
2071
2072 return ret;
2073 }
2074
2075 /**
2076 * @brief FIFO mode selection.[get]
2077 *
2078 * @param ctx read / write interface definitions
2079 * @param val Get the values of fm in reg FIFO_CTRL_REG
2080 * @retval interface status (MANDATORY: return 0 -> no Error)
2081 *
2082 */
lis2dh_fifo_mode_get(stmdev_ctx_t * ctx,lis2dh_fm_t * val)2083 int32_t lis2dh_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh_fm_t *val)
2084 {
2085 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2086 int32_t ret;
2087
2088 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG,
2089 (uint8_t *)&fifo_ctrl_reg, 1);
2090
2091 switch (fifo_ctrl_reg.fm)
2092 {
2093 case LIS2DH_BYPASS_MODE:
2094 *val = LIS2DH_BYPASS_MODE;
2095 break;
2096
2097 case LIS2DH_FIFO_MODE:
2098 *val = LIS2DH_FIFO_MODE;
2099 break;
2100
2101 case LIS2DH_DYNAMIC_STREAM_MODE:
2102 *val = LIS2DH_DYNAMIC_STREAM_MODE;
2103 break;
2104
2105 case LIS2DH_STREAM_TO_FIFO_MODE:
2106 *val = LIS2DH_STREAM_TO_FIFO_MODE;
2107 break;
2108
2109 default:
2110 *val = LIS2DH_BYPASS_MODE;
2111 break;
2112 }
2113
2114 return ret;
2115 }
2116
2117 /**
2118 * @brief FIFO status register.[get]
2119 *
2120 * @param ctx read / write interface definitions
2121 * @param val registers FIFO_SRC_REG
2122 * @retval interface status (MANDATORY: return 0 -> no Error)
2123 *
2124 */
lis2dh_fifo_status_get(stmdev_ctx_t * ctx,lis2dh_fifo_src_reg_t * val)2125 int32_t lis2dh_fifo_status_get(stmdev_ctx_t *ctx,
2126 lis2dh_fifo_src_reg_t *val)
2127 {
2128 int32_t ret;
2129
2130 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, (uint8_t *) val, 1);
2131
2132 return ret;
2133 }
2134 /**
2135 * @brief FIFO stored data level.[get]
2136 *
2137 * @param ctx read / write interface definitions
2138 * @param val change the values of fss in reg FIFO_SRC_REG
2139 * @retval interface status (MANDATORY: return 0 -> no Error)
2140 *
2141 */
lis2dh_fifo_data_level_get(stmdev_ctx_t * ctx,uint8_t * val)2142 int32_t lis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
2143 {
2144 lis2dh_fifo_src_reg_t fifo_src_reg;
2145 int32_t ret;
2146
2147 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG,
2148 (uint8_t *)&fifo_src_reg, 1);
2149 *val = (uint8_t)fifo_src_reg.fss;
2150
2151 return ret;
2152 }
2153 /**
2154 * @brief Empty FIFO status flag.[get]
2155 *
2156 * @param ctx read / write interface definitions
2157 * @param val change the values of empty in reg FIFO_SRC_REG
2158 * @retval interface status (MANDATORY: return 0 -> no Error)
2159 *
2160 */
lis2dh_fifo_empty_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2161 int32_t lis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2162 {
2163 lis2dh_fifo_src_reg_t fifo_src_reg;
2164 int32_t ret;
2165
2166 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG,
2167 (uint8_t *)&fifo_src_reg, 1);
2168 *val = (uint8_t)fifo_src_reg.empty;
2169
2170 return ret;
2171 }
2172 /**
2173 * @brief FIFO overrun status flag.[get]
2174 *
2175 * @param ctx read / write interface definitions
2176 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
2177 * @retval interface status (MANDATORY: return 0 -> no Error)
2178 *
2179 */
lis2dh_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2180 int32_t lis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2181 {
2182 lis2dh_fifo_src_reg_t fifo_src_reg;
2183 int32_t ret;
2184
2185 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG,
2186 (uint8_t *)&fifo_src_reg, 1);
2187 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
2188
2189 return ret;
2190 }
2191 /**
2192 * @brief FIFO watermark status.[get]
2193 *
2194 * @param ctx read / write interface definitions
2195 * @param val change the values of wtm in reg FIFO_SRC_REG
2196 * @retval interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
lis2dh_fifo_fth_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2199 int32_t lis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2200 {
2201 lis2dh_fifo_src_reg_t fifo_src_reg;
2202 int32_t ret;
2203
2204 ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG,
2205 (uint8_t *)&fifo_src_reg, 1);
2206 *val = (uint8_t)fifo_src_reg.wtm;
2207
2208 return ret;
2209 }
2210 /**
2211 * @}
2212 *
2213 */
2214
2215 /**
2216 * @defgroup LIS2DH_Tap_generator
2217 * @brief This section group all the functions that manage the tap and
2218 * double tap event generation
2219 * @{
2220 *
2221 */
2222
2223 /**
2224 * @brief Tap/Double Tap generator configuration register.[set]
2225 *
2226 * @param ctx read / write interface definitions
2227 * @param val registers CLICK_CFG
2228 * @retval interface status (MANDATORY: return 0 -> no Error)
2229 *
2230 */
lis2dh_tap_conf_set(stmdev_ctx_t * ctx,lis2dh_click_cfg_t * val)2231 int32_t lis2dh_tap_conf_set(stmdev_ctx_t *ctx,
2232 lis2dh_click_cfg_t *val)
2233 {
2234 int32_t ret;
2235
2236 ret = lis2dh_write_reg(ctx, LIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2237
2238 return ret;
2239 }
2240
2241 /**
2242 * @brief Tap/Double Tap generator configuration register.[get]
2243 *
2244 * @param ctx read / write interface definitions
2245 * @param val registers CLICK_CFG
2246 * @retval interface status (MANDATORY: return 0 -> no Error)
2247 *
2248 */
lis2dh_tap_conf_get(stmdev_ctx_t * ctx,lis2dh_click_cfg_t * val)2249 int32_t lis2dh_tap_conf_get(stmdev_ctx_t *ctx,
2250 lis2dh_click_cfg_t *val)
2251 {
2252 int32_t ret;
2253
2254 ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2255
2256 return ret;
2257 }
2258 /**
2259 * @brief Tap/Double Tap generator source register.[get]
2260 *
2261 * @param ctx read / write interface definitions
2262 * @param val registers CLICK_SRC
2263 * @retval interface status (MANDATORY: return 0 -> no Error)
2264 *
2265 */
lis2dh_tap_source_get(stmdev_ctx_t * ctx,lis2dh_click_src_t * val)2266 int32_t lis2dh_tap_source_get(stmdev_ctx_t *ctx,
2267 lis2dh_click_src_t *val)
2268 {
2269 int32_t ret;
2270
2271 ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_SRC, (uint8_t *) val, 1);
2272
2273 return ret;
2274 }
2275 /**
2276 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2277 * 1 LSB = full scale/128
2278 *
2279 * @param ctx read / write interface definitions
2280 * @param val change the values of ths in reg CLICK_THS
2281 * @retval interface status (MANDATORY: return 0 -> no Error)
2282 *
2283 */
lis2dh_tap_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2284 int32_t lis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2285 {
2286 lis2dh_click_ths_t click_ths;
2287 int32_t ret;
2288
2289 ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_THS,
2290 (uint8_t *)&click_ths, 1);
2291
2292 if (ret == 0)
2293 {
2294 click_ths.ths = val;
2295 ret = lis2dh_write_reg(ctx, LIS2DH_CLICK_THS,
2296 (uint8_t *)&click_ths, 1);
2297 }
2298
2299 return ret;
2300 }
2301
2302 /**
2303 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2304 * 1 LSB = full scale/128
2305 *
2306 * @param ctx read / write interface definitions
2307 * @param val change the values of ths in reg CLICK_THS
2308 * @retval interface status (MANDATORY: return 0 -> no Error)
2309 *
2310 */
lis2dh_tap_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2311 int32_t lis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2312 {
2313 lis2dh_click_ths_t click_ths;
2314 int32_t ret;
2315
2316 ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_THS,
2317 (uint8_t *)&click_ths, 1);
2318 *val = (uint8_t)click_ths.ths;
2319
2320 return ret;
2321 }
2322
2323 /**
2324 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2325 * between the start of the click-detection procedure and when the
2326 * acceleration falls back below the threshold.[set]
2327 *
2328 * @param ctx read / write interface definitions
2329 * @param val change the values of tli in reg TIME_LIMIT
2330 * @retval interface status (MANDATORY: return 0 -> no Error)
2331 *
2332 */
lis2dh_shock_dur_set(stmdev_ctx_t * ctx,uint8_t val)2333 int32_t lis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2334 {
2335 lis2dh_time_limit_t time_limit;
2336 int32_t ret;
2337
2338 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LIMIT,
2339 (uint8_t *)&time_limit, 1);
2340
2341 if (ret == 0)
2342 {
2343 time_limit.tli = val;
2344 ret = lis2dh_write_reg(ctx, LIS2DH_TIME_LIMIT,
2345 (uint8_t *)&time_limit, 1);
2346 }
2347
2348 return ret;
2349 }
2350
2351 /**
2352 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2353 * the start of the click-detection procedure and when the
2354 * acceleration falls back below the threshold.[get]
2355 *
2356 * @param ctx read / write interface definitions
2357 * @param val change the values of tli in reg TIME_LIMIT
2358 * @retval interface status (MANDATORY: return 0 -> no Error)
2359 *
2360 */
lis2dh_shock_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2361 int32_t lis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2362 {
2363 lis2dh_time_limit_t time_limit;
2364 int32_t ret;
2365
2366 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LIMIT,
2367 (uint8_t *)&time_limit, 1);
2368 *val = (uint8_t)time_limit.tli;
2369
2370 return ret;
2371 }
2372
2373 /**
2374 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2375 * click detection where the click-detection procedure is
2376 * disabled, in cases where the device is configured for
2377 * double-click detection.[set]
2378 *
2379 * @param ctx read / write interface definitions
2380 * @param val change the values of tla in reg TIME_LATENCY
2381 * @retval interface status (MANDATORY: return 0 -> no Error)
2382 *
2383 */
lis2dh_quiet_dur_set(stmdev_ctx_t * ctx,uint8_t val)2384 int32_t lis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2385 {
2386 lis2dh_time_latency_t time_latency;
2387 int32_t ret;
2388
2389 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LATENCY,
2390 (uint8_t *)&time_latency, 1);
2391
2392 if (ret == 0)
2393 {
2394 time_latency.tla = val;
2395 ret = lis2dh_write_reg(ctx, LIS2DH_TIME_LATENCY,
2396 (uint8_t *)&time_latency, 1);
2397 }
2398
2399 return ret;
2400 }
2401
2402 /**
2403 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2404 * click detection where the click-detection procedure is
2405 * disabled, in cases where the device is configured for
2406 * double-click detection.[get]
2407 *
2408 * @param ctx read / write interface definitions
2409 * @param val change the values of tla in reg TIME_LATENCY
2410 * @retval interface status (MANDATORY: return 0 -> no Error)
2411 *
2412 */
lis2dh_quiet_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2413 int32_t lis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2414 {
2415 lis2dh_time_latency_t time_latency;
2416 int32_t ret;
2417
2418 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LATENCY,
2419 (uint8_t *)&time_latency, 1);
2420 *val = (uint8_t)time_latency.tla;
2421
2422 return ret;
2423 }
2424
2425 /**
2426 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2427 * after the end of the latency interval in which the click-detection
2428 * procedure can start, in cases where the device is configured
2429 * for double-click detection.[set]
2430 *
2431 * @param ctx read / write interface definitions
2432 * @param val change the values of tw in reg TIME_WINDOW
2433 * @retval interface status (MANDATORY: return 0 -> no Error)
2434 *
2435 */
lis2dh_double_tap_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2436 int32_t lis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx,
2437 uint8_t val)
2438 {
2439 lis2dh_time_window_t time_window;
2440 int32_t ret;
2441
2442 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_WINDOW,
2443 (uint8_t *)&time_window, 1);
2444
2445 if (ret == 0)
2446 {
2447 time_window.tw = val;
2448 ret = lis2dh_write_reg(ctx, LIS2DH_TIME_WINDOW,
2449 (uint8_t *)&time_window, 1);
2450 }
2451
2452 return ret;
2453 }
2454
2455 /**
2456 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2457 * after the end of the latency interval in which the
2458 * click-detection procedure can start, in cases where the device
2459 * is configured for double-click detection.[get]
2460 *
2461 * @param ctx read / write interface definitions
2462 * @param val change the values of tw in reg TIME_WINDOW
2463 * @retval interface status (MANDATORY: return 0 -> no Error)
2464 *
2465 */
lis2dh_double_tap_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2466 int32_t lis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx,
2467 uint8_t *val)
2468 {
2469 lis2dh_time_window_t time_window;
2470 int32_t ret;
2471
2472 ret = lis2dh_read_reg(ctx, LIS2DH_TIME_WINDOW,
2473 (uint8_t *)&time_window, 1);
2474 *val = (uint8_t)time_window.tw;
2475
2476 return ret;
2477 }
2478
2479 /**
2480 * @}
2481 *
2482 */
2483
2484 /**
2485 * @defgroup LIS2DH_Activity_inactivity
2486 * @brief This section group all the functions concerning activity
2487 * inactivity functionality
2488 * @{
2489 *
2490 */
2491
2492 /**
2493 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2494 * low-power mode.[set]
2495 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2496 *
2497 * @param ctx read / write interface definitions
2498 * @param val change the values of acth in reg ACT_THS
2499 * @retval interface status (MANDATORY: return 0 -> no Error)
2500 *
2501 */
lis2dh_act_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2502 int32_t lis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2503 {
2504 lis2dh_act_ths_t act_ths;
2505 int32_t ret;
2506
2507 ret = lis2dh_read_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2508
2509 if (ret == 0)
2510 {
2511 act_ths.acth = val;
2512 ret = lis2dh_write_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2513 }
2514
2515 return ret;
2516 }
2517
2518 /**
2519 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2520 * mode.[get]
2521 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2522 *
2523 * @param ctx read / write interface definitions
2524 * @param val change the values of acth in reg ACT_THS
2525 * @retval interface status (MANDATORY: return 0 -> no Error)
2526 *
2527 */
lis2dh_act_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2528 int32_t lis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2529 {
2530 lis2dh_act_ths_t act_ths;
2531 int32_t ret;
2532
2533 ret = lis2dh_read_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2534 *val = (uint8_t)act_ths.acth;
2535
2536 return ret;
2537 }
2538
2539 /**
2540 * @brief Sleep-to-wake, return-to-sleep.[set]
2541 * duration = (8*1[LSb]+1)/ODR
2542 *
2543 * @param ctx read / write interface definitions
2544 * @param val change the values of actd in reg ACT_DUR
2545 * @retval interface status (MANDATORY: return 0 -> no Error)
2546 *
2547 */
lis2dh_act_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2548 int32_t lis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2549 {
2550 lis2dh_act_dur_t act_dur;
2551 int32_t ret;
2552
2553 ret = lis2dh_read_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2554
2555 if (ret == 0)
2556 {
2557 act_dur.actd = val;
2558 ret = lis2dh_write_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2559 }
2560
2561 return ret;
2562 }
2563
2564 /**
2565 * @brief Sleep-to-wake, return-to-sleep.[get]
2566 * duration = (8*1[LSb]+1)/ODR
2567 *
2568 * @param ctx read / write interface definitions
2569 * @param val change the values of actd in reg ACT_DUR
2570 * @retval interface status (MANDATORY: return 0 -> no Error)
2571 *
2572 */
lis2dh_act_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2573 int32_t lis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2574 {
2575 lis2dh_act_dur_t act_dur;
2576 int32_t ret;
2577
2578 ret = lis2dh_read_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2579 *val = (uint8_t)act_dur.actd;
2580
2581 return ret;
2582 }
2583
2584 /**
2585 * @}
2586 *
2587 */
2588
2589 /**
2590 * @defgroup LIS2DH_Serial_interface
2591 * @brief This section group all the functions concerning serial
2592 * interface management
2593 * @{
2594 *
2595 */
2596
2597 /**
2598 * @brief SPI Serial Interface Mode selection.[set]
2599 *
2600 * @param ctx read / write interface definitions
2601 * @param val change the values of sim in reg CTRL_REG4
2602 * @retval interface status (MANDATORY: return 0 -> no Error)
2603 *
2604 */
lis2dh_spi_mode_set(stmdev_ctx_t * ctx,lis2dh_sim_t val)2605 int32_t lis2dh_spi_mode_set(stmdev_ctx_t *ctx, lis2dh_sim_t val)
2606 {
2607 lis2dh_ctrl_reg4_t ctrl_reg4;
2608 int32_t ret;
2609
2610 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
2611 (uint8_t *)&ctrl_reg4, 1);
2612
2613 if (ret == 0)
2614 {
2615 ctrl_reg4.sim = (uint8_t)val;
2616 ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4,
2617 (uint8_t *)&ctrl_reg4, 1);
2618 }
2619
2620 return ret;
2621 }
2622
2623 /**
2624 * @brief SPI Serial Interface Mode selection.[get]
2625 *
2626 * @param ctx read / write interface definitions
2627 * @param val Get the values of sim in reg CTRL_REG4
2628 * @retval interface status (MANDATORY: return 0 -> no Error)
2629 *
2630 */
lis2dh_spi_mode_get(stmdev_ctx_t * ctx,lis2dh_sim_t * val)2631 int32_t lis2dh_spi_mode_get(stmdev_ctx_t *ctx, lis2dh_sim_t *val)
2632 {
2633 lis2dh_ctrl_reg4_t ctrl_reg4;
2634 int32_t ret;
2635
2636 ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4,
2637 (uint8_t *)&ctrl_reg4, 1);
2638
2639 switch (ctrl_reg4.sim)
2640 {
2641 case LIS2DH_SPI_4_WIRE:
2642 *val = LIS2DH_SPI_4_WIRE;
2643 break;
2644
2645 case LIS2DH_SPI_3_WIRE:
2646 *val = LIS2DH_SPI_3_WIRE;
2647 break;
2648
2649 default:
2650 *val = LIS2DH_SPI_4_WIRE;
2651 break;
2652 }
2653
2654 return ret;
2655 }
2656
2657 /**
2658 * @}
2659 *
2660 */
2661
2662 /**
2663 * @}
2664 *
2665 */
2666
2667
2668 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2669
