1 /**
2 ******************************************************************************
3 * @file lis2de12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DE12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2de12_reg.h"
21
22 /**
23 * @defgroup LIS2DE12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2de12 enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DE12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2de12_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2de12_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2DE12_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis2de12_from_fs2_to_mg(int16_t lsb)93 float_t lis2de12_from_fs2_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb / 256.0f) * 15.6f;
96 }
97
lis2de12_from_fs4_to_mg(int16_t lsb)98 float_t lis2de12_from_fs4_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb / 256.0f) * 31.2f;
101 }
102
lis2de12_from_fs8_to_mg(int16_t lsb)103 float_t lis2de12_from_fs8_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb / 256.0f) * 62.5f;
106 }
107
lis2de12_from_fs16_to_mg(int16_t lsb)108 float_t lis2de12_from_fs16_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb / 256.0f) * 187.5f;
111 }
112
lis2de12_from_lsb_to_celsius(int16_t lsb)113 float_t lis2de12_from_lsb_to_celsius(int16_t lsb)
114 {
115 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup LIS2DE12_Data_generation
125 * @brief This section group all the functions concerning data generation.
126 * @{
127 *
128 */
129
130 /**
131 * @brief Temperature status register.[get]
132 *
133 * @param ctx read / write interface definitions
134 * @param buff buffer that stores data read
135 * @retval interface status (MANDATORY: return 0 -> no Error)
136 *
137 */
lis2de12_temp_status_reg_get(stmdev_ctx_t * ctx,uint8_t * buff)138 int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
139 {
140 int32_t ret;
141
142 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX, buff, 1);
143
144 return ret;
145 }
146 /**
147 * @brief Temperature data available.[get]
148 *
149 * @param ctx read / write interface definitions
150 * @param val change the values of tda in reg STATUS_REG_AUX
151 * @retval interface status (MANDATORY: return 0 -> no Error)
152 *
153 */
lis2de12_temp_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)154 int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
155 {
156 lis2de12_status_reg_aux_t status_reg_aux;
157 int32_t ret;
158
159 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
160 (uint8_t *)&status_reg_aux, 1);
161 *val = status_reg_aux.tda;
162
163 return ret;
164 }
165 /**
166 * @brief Temperature data overrun.[get]
167 *
168 * @param ctx read / write interface definitions
169 * @param val change the values of tor in reg STATUS_REG_AUX
170 * @retval interface status (MANDATORY: return 0 -> no Error)
171 *
172 */
lis2de12_temp_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)173 int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
174 {
175 lis2de12_status_reg_aux_t status_reg_aux;
176 int32_t ret;
177
178 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
179 (uint8_t *)&status_reg_aux, 1);
180 *val = status_reg_aux.tor;
181
182 return ret;
183 }
184 /**
185 * @brief Temperature output value.[get]
186 *
187 * @param ctx read / write interface definitions
188 * @param buff buffer that stores data read
189 * @retval interface status (MANDATORY: return 0 -> no Error)
190 *
191 */
lis2de12_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)192 int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
193 {
194 uint8_t buff[2];
195 int32_t ret;
196
197 ret = lis2de12_read_reg(ctx, LIS2DE12_OUT_TEMP_L, buff, 2);
198 *val = (int16_t)buff[1];
199 *val = (*val * 256) + (int16_t)buff[0];
200
201 return ret;
202 }
203 /**
204 * @brief Temperature sensor enable.[set]
205 *
206 * @param ctx read / write interface definitions
207 * @param val change the values of temp_en in reg TEMP_CFG_REG
208 * @retval interface status (MANDATORY: return 0 -> no Error)
209 *
210 */
lis2de12_temperature_meas_set(stmdev_ctx_t * ctx,lis2de12_temp_en_t val)211 int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx,
212 lis2de12_temp_en_t val)
213 {
214 lis2de12_temp_cfg_reg_t temp_cfg_reg;
215 int32_t ret;
216
217 ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
218 (uint8_t *)&temp_cfg_reg, 1);
219
220 if (ret == 0)
221 {
222 temp_cfg_reg.temp_en = (uint8_t) val;
223 ret = lis2de12_write_reg(ctx, LIS2DE12_TEMP_CFG_REG,
224 (uint8_t *)&temp_cfg_reg, 1);
225 }
226
227 return ret;
228 }
229
230 /**
231 * @brief Temperature sensor enable.[get]
232 *
233 * @param ctx read / write interface definitions
234 * @param val get the values of temp_en in reg TEMP_CFG_REG
235 * @retval interface status (MANDATORY: return 0 -> no Error)
236 *
237 */
lis2de12_temperature_meas_get(stmdev_ctx_t * ctx,lis2de12_temp_en_t * val)238 int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx,
239 lis2de12_temp_en_t *val)
240 {
241 lis2de12_temp_cfg_reg_t temp_cfg_reg;
242 int32_t ret;
243
244 ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
245 (uint8_t *)&temp_cfg_reg, 1);
246
247 switch (temp_cfg_reg.temp_en)
248 {
249 case LIS2DE12_TEMP_DISABLE:
250 *val = LIS2DE12_TEMP_DISABLE;
251 break;
252
253 case LIS2DE12_TEMP_ENABLE:
254 *val = LIS2DE12_TEMP_ENABLE;
255 break;
256
257 default:
258 *val = LIS2DE12_TEMP_DISABLE;
259 break;
260 }
261
262 return ret;
263 }
264
265 /**
266 * @brief Output data rate selection.[set]
267 *
268 * @param ctx read / write interface definitions
269 * @param val change the values of odr in reg CTRL_REG1
270 * @retval interface status (MANDATORY: return 0 -> no Error)
271 *
272 */
lis2de12_data_rate_set(stmdev_ctx_t * ctx,lis2de12_odr_t val)273 int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val)
274 {
275 lis2de12_ctrl_reg1_t ctrl_reg1;
276 int32_t ret;
277
278 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
279 (uint8_t *)&ctrl_reg1, 1);
280
281 if (ret == 0)
282 {
283 ctrl_reg1.lpen = PROPERTY_ENABLE;
284 ctrl_reg1.odr = (uint8_t)val;
285 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG1,
286 (uint8_t *)&ctrl_reg1, 1);
287 }
288
289 return ret;
290 }
291
292 /**
293 * @brief Output data rate selection.[get]
294 *
295 * @param ctx read / write interface definitions
296 * @param val get the values of odr in reg CTRL_REG1
297 * @retval interface status (MANDATORY: return 0 -> no Error)
298 *
299 */
lis2de12_data_rate_get(stmdev_ctx_t * ctx,lis2de12_odr_t * val)300 int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val)
301 {
302 lis2de12_ctrl_reg1_t ctrl_reg1;
303 int32_t ret;
304
305 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
306 (uint8_t *)&ctrl_reg1, 1);
307
308 switch (ctrl_reg1.odr)
309 {
310 case LIS2DE12_POWER_DOWN:
311 *val = LIS2DE12_POWER_DOWN;
312 break;
313
314 case LIS2DE12_ODR_1Hz:
315 *val = LIS2DE12_ODR_1Hz;
316 break;
317
318 case LIS2DE12_ODR_10Hz:
319 *val = LIS2DE12_ODR_10Hz;
320 break;
321
322 case LIS2DE12_ODR_25Hz:
323 *val = LIS2DE12_ODR_25Hz;
324 break;
325
326 case LIS2DE12_ODR_50Hz:
327 *val = LIS2DE12_ODR_50Hz;
328 break;
329
330 case LIS2DE12_ODR_100Hz:
331 *val = LIS2DE12_ODR_100Hz;
332 break;
333
334 case LIS2DE12_ODR_200Hz:
335 *val = LIS2DE12_ODR_200Hz;
336 break;
337
338 case LIS2DE12_ODR_400Hz:
339 *val = LIS2DE12_ODR_400Hz;
340 break;
341
342 case LIS2DE12_ODR_1kHz620_LP:
343 *val = LIS2DE12_ODR_1kHz620_LP;
344 break;
345
346 case LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP:
347 *val = LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP;
348 break;
349
350 default:
351 *val = LIS2DE12_POWER_DOWN;
352 break;
353 }
354
355 return ret;
356 }
357
358 /**
359 * @brief High pass data from internal filter sent to output register
360 * and FIFO.
361 *
362 * @param ctx read / write interface definitions
363 * @param val change the values of fds in reg CTRL_REG2
364 * @retval interface status (MANDATORY: return 0 -> no Error)
365 *
366 */
lis2de12_high_pass_on_outputs_set(stmdev_ctx_t * ctx,uint8_t val)367 int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
368 uint8_t val)
369 {
370 lis2de12_ctrl_reg2_t ctrl_reg2;
371 int32_t ret;
372
373 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
374 (uint8_t *)&ctrl_reg2, 1);
375
376 if (ret == 0)
377 {
378 ctrl_reg2.fds = val;
379 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
380 (uint8_t *)&ctrl_reg2, 1);
381 }
382
383 return ret;
384 }
385
386 /**
387 * @brief High pass data from internal filter sent to output register
388 * and FIFO.[get]
389 *
390 * @param ctx read / write interface definitions
391 * @param val change the values of fds in reg CTRL_REG2
392 * @retval interface status (MANDATORY: return 0 -> no Error)
393 *
394 */
lis2de12_high_pass_on_outputs_get(stmdev_ctx_t * ctx,uint8_t * val)395 int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
396 uint8_t *val)
397 {
398 lis2de12_ctrl_reg2_t ctrl_reg2;
399 int32_t ret;
400
401 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
402 (uint8_t *)&ctrl_reg2, 1);
403 *val = (uint8_t)ctrl_reg2.fds;
404
405 return ret;
406 }
407
408 /**
409 * @brief High-pass filter cutoff frequency selection.[set]
410 *
411 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
412 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
413 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
414 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
415 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
416 *
417 * @param ctx read / write interface definitions
418 * @param val change the values of hpcf in reg CTRL_REG2
419 * @retval interface status (MANDATORY: return 0 -> no Error)
420 *
421 */
lis2de12_high_pass_bandwidth_set(stmdev_ctx_t * ctx,lis2de12_hpcf_t val)422 int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
423 lis2de12_hpcf_t val)
424 {
425 lis2de12_ctrl_reg2_t ctrl_reg2;
426 int32_t ret;
427
428 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
429 (uint8_t *)&ctrl_reg2, 1);
430
431 if (ret == 0)
432 {
433 ctrl_reg2.hpcf = (uint8_t)val;
434 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
435 (uint8_t *)&ctrl_reg2, 1);
436 }
437
438 return ret;
439 }
440
441 /**
442 * @brief High-pass filter cutoff frequency selection.[get]
443 *
444 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
445 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
446 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
447 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
448 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
449 *
450 * @param ctx read / write interface definitions
451 * @param val get the values of hpcf in reg CTRL_REG2
452 * @retval interface status (MANDATORY: return 0 -> no Error)
453 *
454 */
lis2de12_high_pass_bandwidth_get(stmdev_ctx_t * ctx,lis2de12_hpcf_t * val)455 int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
456 lis2de12_hpcf_t *val)
457 {
458 lis2de12_ctrl_reg2_t ctrl_reg2;
459 int32_t ret;
460
461 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
462 (uint8_t *)&ctrl_reg2, 1);
463
464 switch (ctrl_reg2.hpcf)
465 {
466 case LIS2DE12_AGGRESSIVE:
467 *val = LIS2DE12_AGGRESSIVE;
468 break;
469
470 case LIS2DE12_STRONG:
471 *val = LIS2DE12_STRONG;
472 break;
473
474 case LIS2DE12_MEDIUM:
475 *val = LIS2DE12_MEDIUM;
476 break;
477
478 case LIS2DE12_LIGHT:
479 *val = LIS2DE12_LIGHT;
480 break;
481
482 default:
483 *val = LIS2DE12_LIGHT;
484 break;
485 }
486
487 return ret;
488 }
489
490 /**
491 * @brief High-pass filter mode selection.[set]
492 *
493 * @param ctx read / write interface definitions
494 * @param val change the values of hpm in reg CTRL_REG2
495 * @retval interface status (MANDATORY: return 0 -> no Error)
496 *
497 */
lis2de12_high_pass_mode_set(stmdev_ctx_t * ctx,lis2de12_hpm_t val)498 int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx,
499 lis2de12_hpm_t val)
500 {
501 lis2de12_ctrl_reg2_t ctrl_reg2;
502 int32_t ret;
503
504 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
505 (uint8_t *)&ctrl_reg2, 1);
506
507 if (ret == 0)
508 {
509 ctrl_reg2.hpm = (uint8_t)val;
510 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
511 (uint8_t *)&ctrl_reg2, 1);
512 }
513
514 return ret;
515 }
516
517 /**
518 * @brief High-pass filter mode selection.[get]
519 *
520 * @param ctx read / write interface definitions
521 * @param val get the values of hpm in reg CTRL_REG2
522 * @retval interface status (MANDATORY: return 0 -> no Error)
523 *
524 */
lis2de12_high_pass_mode_get(stmdev_ctx_t * ctx,lis2de12_hpm_t * val)525 int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx,
526 lis2de12_hpm_t *val)
527 {
528 lis2de12_ctrl_reg2_t ctrl_reg2;
529 int32_t ret;
530
531 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
532 (uint8_t *)&ctrl_reg2, 1);
533
534 switch (ctrl_reg2.hpm)
535 {
536 case LIS2DE12_NORMAL_WITH_RST:
537 *val = LIS2DE12_NORMAL_WITH_RST;
538 break;
539
540 case LIS2DE12_REFERENCE_MODE:
541 *val = LIS2DE12_REFERENCE_MODE;
542 break;
543
544 case LIS2DE12_NORMAL:
545 *val = LIS2DE12_NORMAL;
546 break;
547
548 case LIS2DE12_AUTORST_ON_INT:
549 *val = LIS2DE12_AUTORST_ON_INT;
550 break;
551
552 default:
553 *val = LIS2DE12_NORMAL_WITH_RST;
554 break;
555 }
556
557 return ret;
558 }
559
560 /**
561 * @brief Full-scale configuration.[set]
562 *
563 * @param ctx read / write interface definitions
564 * @param val change the values of fs in reg CTRL_REG4
565 * @retval interface status (MANDATORY: return 0 -> no Error)
566 *
567 */
lis2de12_full_scale_set(stmdev_ctx_t * ctx,lis2de12_fs_t val)568 int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val)
569 {
570 lis2de12_ctrl_reg4_t ctrl_reg4;
571 int32_t ret;
572
573 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
574 (uint8_t *)&ctrl_reg4, 1);
575
576 if (ret == 0)
577 {
578 ctrl_reg4.fs = (uint8_t)val;
579 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
580 (uint8_t *)&ctrl_reg4, 1);
581 }
582
583 return ret;
584 }
585
586 /**
587 * @brief Full-scale configuration.[get]
588 *
589 * @param ctx read / write interface definitions
590 * @param val get the values of fs in reg CTRL_REG4
591 * @retval interface status (MANDATORY: return 0 -> no Error)
592 *
593 */
lis2de12_full_scale_get(stmdev_ctx_t * ctx,lis2de12_fs_t * val)594 int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, lis2de12_fs_t *val)
595 {
596 lis2de12_ctrl_reg4_t ctrl_reg4;
597 int32_t ret;
598
599 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
600 (uint8_t *)&ctrl_reg4, 1);
601
602 switch (ctrl_reg4.fs)
603 {
604 case LIS2DE12_2g:
605 *val = LIS2DE12_2g;
606 break;
607
608 case LIS2DE12_4g:
609 *val = LIS2DE12_4g;
610 break;
611
612 case LIS2DE12_8g:
613 *val = LIS2DE12_8g;
614 break;
615
616 case LIS2DE12_16g:
617 *val = LIS2DE12_16g;
618 break;
619
620 default:
621 *val = LIS2DE12_2g;
622 break;
623 }
624
625 return ret;
626 }
627
628 /**
629 * @brief Block Data Update.[set]
630 *
631 * @param ctx read / write interface definitions
632 * @param val change the values of bdu in reg CTRL_REG4
633 * @retval interface status (MANDATORY: return 0 -> no Error)
634 *
635 */
lis2de12_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)636 int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
637 {
638 lis2de12_ctrl_reg4_t ctrl_reg4;
639 int32_t ret;
640
641 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
642 (uint8_t *)&ctrl_reg4, 1);
643
644 if (ret == 0)
645 {
646 ctrl_reg4.bdu = val;
647 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
648 (uint8_t *)&ctrl_reg4, 1);
649 }
650
651 return ret;
652 }
653
654 /**
655 * @brief Block Data Update.[get]
656 *
657 * @param ctx read / write interface definitions
658 * @param val change the values of bdu in reg CTRL_REG4
659 * @retval interface status (MANDATORY: return 0 -> no Error)
660 *
661 */
lis2de12_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)662 int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx,
663 uint8_t *val)
664 {
665 lis2de12_ctrl_reg4_t ctrl_reg4;
666 int32_t ret;
667
668 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
669 (uint8_t *)&ctrl_reg4, 1);
670 *val = (uint8_t)ctrl_reg4.bdu;
671
672 return ret;
673 }
674
675 /**
676 * @brief Reference value for interrupt generation.[set]
677 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
678 *
679 * @param ctx read / write interface definitions
680 * @param buff buffer that contains data to write
681 * @retval interface status (MANDATORY: return 0 -> no Error)
682 *
683 */
lis2de12_filter_reference_set(stmdev_ctx_t * ctx,uint8_t * buff)684 int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx,
685 uint8_t *buff)
686 {
687 int32_t ret;
688
689 ret = lis2de12_write_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
690
691 return ret;
692 }
693
694 /**
695 * @brief Reference value for interrupt generation.[get]
696 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
697 *
698 * @param ctx read / write interface definitions
699 * @param buff buffer that stores data read
700 * @retval interface status (MANDATORY: return 0 -> no Error)
701 *
702 */
lis2de12_filter_reference_get(stmdev_ctx_t * ctx,uint8_t * buff)703 int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx,
704 uint8_t *buff)
705 {
706 int32_t ret;
707
708 ret = lis2de12_read_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
709
710 return ret;
711 }
712 /**
713 * @brief Acceleration set of data available.[get]
714 *
715 * @param ctx read / write interface definitions
716 * @param val change the values of zyxda in reg STATUS_REG
717 * @retval interface status (MANDATORY: return 0 -> no Error)
718 *
719 */
lis2de12_xl_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)720 int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
721 {
722 lis2de12_status_reg_t status_reg;
723 int32_t ret;
724
725 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
726 (uint8_t *)&status_reg, 1);
727 *val = status_reg.zyxda;
728
729 return ret;
730 }
731 /**
732 * @brief Acceleration set of data overrun.[get]
733 *
734 * @param ctx read / write interface definitions
735 * @param val change the values of zyxor in reg STATUS_REG
736 * @retval interface status (MANDATORY: return 0 -> no Error)
737 *
738 */
lis2de12_xl_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)739 int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
740 {
741 lis2de12_status_reg_t status_reg;
742 int32_t ret;
743
744 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
745 (uint8_t *)&status_reg, 1);
746 *val = status_reg.zyxor;
747
748 return ret;
749 }
750 /**
751 * @brief Acceleration output value.[get]
752 *
753 * @param ctx read / write interface definitions
754 * @param buff buffer that stores data read
755 * @retval interface status (MANDATORY: return 0 -> no Error)
756 *
757 */
lis2de12_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)758 int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
759 {
760 uint8_t buff[6];
761 int32_t ret;
762
763 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_READ_START, buff, 6);
764 val[0] = (int16_t)buff[1];
765 val[0] = (val[0] * 256) + (int16_t)buff[0];
766 val[1] = (int16_t)buff[3];
767 val[1] = (val[1] * 256) + (int16_t)buff[2];
768 val[2] = (int16_t)buff[5];
769 val[2] = (val[2] * 256) + (int16_t)buff[4];
770
771 return ret;
772 }
773 /**
774 * @}
775 *
776 */
777
778 /**
779 * @defgroup LIS2DE12_Common
780 * @brief This section group common useful functions
781 * @{
782 *
783 */
784
785 /**
786 * @brief DeviceWhoamI .[get]
787 *
788 * @param ctx read / write interface definitions
789 * @param buff buffer that stores data read
790 * @retval interface status (MANDATORY: return 0 -> no Error)
791 *
792 */
lis2de12_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)793 int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
794 {
795 int32_t ret;
796
797 ret = lis2de12_read_reg(ctx, LIS2DE12_WHO_AM_I, buff, 1);
798
799 return ret;
800 }
801 /**
802 * @brief Self Test.[set]
803 *
804 * @param ctx read / write interface definitions
805 * @param val change the values of st in reg CTRL_REG4
806 * @retval interface status (MANDATORY: return 0 -> no Error)
807 *
808 */
lis2de12_self_test_set(stmdev_ctx_t * ctx,lis2de12_st_t val)809 int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val)
810 {
811 lis2de12_ctrl_reg4_t ctrl_reg4;
812 int32_t ret;
813
814 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
815 (uint8_t *)&ctrl_reg4, 1);
816
817 if (ret == 0)
818 {
819 ctrl_reg4.st = (uint8_t)val;
820 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
821 (uint8_t *)&ctrl_reg4, 1);
822 }
823
824 return ret;
825 }
826
827 /**
828 * @brief Self Test.[get]
829 *
830 * @param ctx read / write interface definitions
831 * @param val Get the values of st in reg CTRL_REG4
832 * @retval interface status (MANDATORY: return 0 -> no Error)
833 *
834 */
lis2de12_self_test_get(stmdev_ctx_t * ctx,lis2de12_st_t * val)835 int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val)
836 {
837 lis2de12_ctrl_reg4_t ctrl_reg4;
838 int32_t ret;
839
840 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
841 (uint8_t *)&ctrl_reg4, 1);
842
843 switch (ctrl_reg4.st)
844 {
845 case LIS2DE12_ST_DISABLE:
846 *val = LIS2DE12_ST_DISABLE;
847 break;
848
849 case LIS2DE12_ST_POSITIVE:
850 *val = LIS2DE12_ST_POSITIVE;
851 break;
852
853 case LIS2DE12_ST_NEGATIVE:
854 *val = LIS2DE12_ST_NEGATIVE;
855 break;
856
857 default:
858 *val = LIS2DE12_ST_DISABLE;
859 break;
860 }
861
862 return ret;
863 }
864
865 /**
866 * @brief Reboot memory content. Reload the calibration parameters.[set]
867 *
868 * @param ctx read / write interface definitions
869 * @param val change the values of boot in reg CTRL_REG5
870 * @retval interface status (MANDATORY: return 0 -> no Error)
871 *
872 */
lis2de12_boot_set(stmdev_ctx_t * ctx,uint8_t val)873 int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val)
874 {
875 lis2de12_ctrl_reg5_t ctrl_reg5;
876 int32_t ret;
877
878 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
879 (uint8_t *)&ctrl_reg5, 1);
880
881 if (ret == 0)
882 {
883 ctrl_reg5.boot = val;
884 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
885 (uint8_t *)&ctrl_reg5, 1);
886 }
887
888 return ret;
889 }
890
891 /**
892 * @brief Reboot memory content. Reload the calibration parameters.[get]
893 *
894 * @param ctx read / write interface definitions
895 * @param val change the values of boot in reg CTRL_REG5
896 * @retval interface status (MANDATORY: return 0 -> no Error)
897 *
898 */
lis2de12_boot_get(stmdev_ctx_t * ctx,uint8_t * val)899 int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
900 {
901 lis2de12_ctrl_reg5_t ctrl_reg5;
902 int32_t ret;
903
904 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
905 (uint8_t *)&ctrl_reg5, 1);
906 *val = (uint8_t)ctrl_reg5.boot;
907
908 return ret;
909 }
910
911 /**
912 * @brief Info about device status.[get]
913 *
914 * @param ctx read / write interface definitions
915 * @param val register STATUS_REG
916 * @retval interface status (MANDATORY: return 0 -> no Error)
917 *
918 */
lis2de12_status_get(stmdev_ctx_t * ctx,lis2de12_status_reg_t * val)919 int32_t lis2de12_status_get(stmdev_ctx_t *ctx,
920 lis2de12_status_reg_t *val)
921 {
922 int32_t ret;
923
924 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t *) val, 1);
925
926 return ret;
927 }
928 /**
929 * @}
930 *
931 */
932
933 /**
934 * @defgroup LIS2DE12_Interrupts_generator_1
935 * @brief This section group all the functions that manage the first
936 * interrupts generator
937 * @{
938 *
939 */
940
941 /**
942 * @brief Interrupt generator 1 configuration register.[set]
943 *
944 * @param ctx read / write interface definitions
945 * @param val register INT1_CFG
946 * @retval interface status (MANDATORY: return 0 -> no Error)
947 *
948 */
lis2de12_int1_gen_conf_set(stmdev_ctx_t * ctx,lis2de12_int1_cfg_t * val)949 int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx,
950 lis2de12_int1_cfg_t *val)
951 {
952 int32_t ret;
953
954 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
955
956 return ret;
957 }
958
959 /**
960 * @brief Interrupt generator 1 configuration register.[get]
961 *
962 * @param ctx read / write interface definitions
963 * @param val register INT1_CFG
964 * @retval interface status (MANDATORY: return 0 -> no Error)
965 *
966 */
lis2de12_int1_gen_conf_get(stmdev_ctx_t * ctx,lis2de12_int1_cfg_t * val)967 int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx,
968 lis2de12_int1_cfg_t *val)
969 {
970 int32_t ret;
971
972 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
973
974 return ret;
975 }
976
977 /**
978 * @brief Interrupt generator 1 source register.[get]
979 *
980 * @param ctx read / write interface definitions
981 * @param val Registers INT1_SRC
982 * @retval interface status (MANDATORY: return 0 -> no Error)
983 *
984 */
lis2de12_int1_gen_source_get(stmdev_ctx_t * ctx,lis2de12_int1_src_t * val)985 int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx,
986 lis2de12_int1_src_t *val)
987 {
988 int32_t ret;
989
990 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_SRC, (uint8_t *) val, 1);
991
992 return ret;
993 }
994 /**
995 * @brief User-defined threshold value for xl interrupt event on
996 * generator 1.[set]
997 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
998 *
999 * @param ctx read / write interface definitions
1000 * @param val change the values of ths in reg INT1_THS
1001 * @retval interface status (MANDATORY: return 0 -> no Error)
1002 *
1003 */
lis2de12_int1_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1004 int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx,
1005 uint8_t val)
1006 {
1007 lis2de12_int1_ths_t int1_ths;
1008 int32_t ret;
1009
1010 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1011
1012 if (ret == 0)
1013 {
1014 int1_ths.ths = val;
1015 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1016 }
1017
1018 return ret;
1019 }
1020
1021 /**
1022 * @brief User-defined threshold value for xl interrupt event on
1023 * generator 1.[get]
1024 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1025 *
1026 * @param ctx read / write interface definitions
1027 * @param val change the values of ths in reg INT1_THS
1028 * @retval interface status (MANDATORY: return 0 -> no Error)
1029 *
1030 */
lis2de12_int1_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1031 int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx,
1032 uint8_t *val)
1033 {
1034 lis2de12_int1_ths_t int1_ths;
1035 int32_t ret;
1036
1037 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1038 *val = (uint8_t)int1_ths.ths;
1039
1040 return ret;
1041 }
1042
1043 /**
1044 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1045 * recognized.[set]
1046 *
1047 * @param ctx read / write interface definitions
1048 * @param val change the values of d in reg INT1_DURATION
1049 * @retval interface status (MANDATORY: return 0 -> no Error)
1050 *
1051 */
lis2de12_int1_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1052 int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1053 {
1054 lis2de12_int1_duration_t int1_duration;
1055 int32_t ret;
1056
1057 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
1058 (uint8_t *)&int1_duration, 1);
1059
1060 if (ret == 0)
1061 {
1062 int1_duration.d = val;
1063 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_DURATION,
1064 (uint8_t *)&int1_duration, 1);
1065 }
1066
1067 return ret;
1068 }
1069
1070 /**
1071 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1072 * recognized.[get]
1073 *
1074 * @param ctx read / write interface definitions
1075 * @param val change the values of d in reg INT1_DURATION
1076 * @retval interface status (MANDATORY: return 0 -> no Error)
1077 *
1078 */
lis2de12_int1_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1079 int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx,
1080 uint8_t *val)
1081 {
1082 lis2de12_int1_duration_t int1_duration;
1083 int32_t ret;
1084
1085 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
1086 (uint8_t *)&int1_duration, 1);
1087 *val = (uint8_t)int1_duration.d;
1088
1089 return ret;
1090 }
1091
1092 /**
1093 * @}
1094 *
1095 */
1096
1097 /**
1098 * @defgroup LIS2DE12_Interrupts_generator_2
1099 * @brief This section group all the functions that manage the second
1100 * interrupts generator
1101 * @{
1102 *
1103 */
1104
1105 /**
1106 * @brief Interrupt generator 2 configuration register.[set]
1107 *
1108 * @param ctx read / write interface definitions
1109 * @param val registers INT2_CFG
1110 * @retval interface status (MANDATORY: return 0 -> no Error)
1111 *
1112 */
lis2de12_int2_gen_conf_set(stmdev_ctx_t * ctx,lis2de12_int2_cfg_t * val)1113 int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx,
1114 lis2de12_int2_cfg_t *val)
1115 {
1116 int32_t ret;
1117
1118 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
1119
1120 return ret;
1121 }
1122
1123 /**
1124 * @brief Interrupt generator 2 configuration register.[get]
1125 *
1126 * @param ctx read / write interface definitions
1127 * @param val registers INT2_CFG
1128 * @retval interface status (MANDATORY: return 0 -> no Error)
1129 *
1130 */
lis2de12_int2_gen_conf_get(stmdev_ctx_t * ctx,lis2de12_int2_cfg_t * val)1131 int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx,
1132 lis2de12_int2_cfg_t *val)
1133 {
1134 int32_t ret;
1135
1136 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
1137
1138 return ret;
1139 }
1140 /**
1141 * @brief Interrupt generator 2 source register.[get]
1142 *
1143 * @param ctx read / write interface definitions
1144 * @param val registers INT2_SRC
1145 * @retval interface status (MANDATORY: return 0 -> no Error)
1146 *
1147 */
lis2de12_int2_gen_source_get(stmdev_ctx_t * ctx,lis2de12_int2_src_t * val)1148 int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx,
1149 lis2de12_int2_src_t *val)
1150 {
1151 int32_t ret;
1152
1153 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_SRC, (uint8_t *) val, 1);
1154
1155 return ret;
1156 }
1157 /**
1158 * @brief User-defined threshold value for xl interrupt event on
1159 * generator 2.[set]
1160 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1161 *
1162 * @param ctx read / write interface definitions
1163 * @param val change the values of ths in reg INT2_THS
1164 * @retval interface status (MANDATORY: return 0 -> no Error)
1165 *
1166 */
lis2de12_int2_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1167 int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx,
1168 uint8_t val)
1169 {
1170 lis2de12_int2_ths_t int2_ths;
1171 int32_t ret;
1172
1173 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1174
1175 if (ret == 0)
1176 {
1177 int2_ths.ths = val;
1178 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1179 }
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief User-defined threshold value for xl interrupt event on
1186 * generator 2.[get]
1187 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1188 *
1189 * @param ctx read / write interface definitions
1190 * @param val change the values of ths in reg INT2_THS
1191 * @retval interface status (MANDATORY: return 0 -> no Error)
1192 *
1193 */
lis2de12_int2_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1194 int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx,
1195 uint8_t *val)
1196 {
1197 lis2de12_int2_ths_t int2_ths;
1198 int32_t ret;
1199
1200 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1201 *val = (uint8_t)int2_ths.ths;
1202
1203 return ret;
1204 }
1205
1206 /**
1207 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1208 * recognized .[set]
1209 *
1210 * @param ctx read / write interface definitions
1211 * @param val change the values of d in reg INT2_DURATION
1212 * @retval interface status (MANDATORY: return 0 -> no Error)
1213 *
1214 */
lis2de12_int2_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1215 int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1216 {
1217 lis2de12_int2_duration_t int2_duration;
1218 int32_t ret;
1219
1220 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
1221 (uint8_t *)&int2_duration, 1);
1222
1223 if (ret == 0)
1224 {
1225 int2_duration.d = val;
1226 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_DURATION,
1227 (uint8_t *)&int2_duration, 1);
1228 }
1229
1230 return ret;
1231 }
1232
1233 /**
1234 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1235 * recognized.[get]
1236 *
1237 * @param ctx read / write interface definitions
1238 * @param val change the values of d in reg INT2_DURATION
1239 * @retval interface status (MANDATORY: return 0 -> no Error)
1240 *
1241 */
lis2de12_int2_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1242 int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx,
1243 uint8_t *val)
1244 {
1245 lis2de12_int2_duration_t int2_duration;
1246 int32_t ret;
1247
1248 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
1249 (uint8_t *)&int2_duration, 1);
1250 *val = (uint8_t)int2_duration.d;
1251
1252 return ret;
1253 }
1254
1255 /**
1256 * @}
1257 *
1258 */
1259
1260 /**
1261 * @defgroup LIS2DE12_Interrupt_pins
1262 * @brief This section group all the functions that manage interrupt pins
1263 * @{
1264 *
1265 */
1266
1267 /**
1268 * @brief High-pass filter on interrupts/tap generator.[set]
1269 *
1270 * @param ctx read / write interface definitions
1271 * @param val change the values of hp in reg CTRL_REG2
1272 * @retval interface status (MANDATORY: return 0 -> no Error)
1273 *
1274 */
lis2de12_high_pass_int_conf_set(stmdev_ctx_t * ctx,lis2de12_hp_t val)1275 int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx,
1276 lis2de12_hp_t val)
1277 {
1278 lis2de12_ctrl_reg2_t ctrl_reg2;
1279 int32_t ret;
1280
1281 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
1282 (uint8_t *)&ctrl_reg2, 1);
1283
1284 if (ret == 0)
1285 {
1286 ctrl_reg2.hp = (uint8_t)val;
1287 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
1288 (uint8_t *)&ctrl_reg2, 1);
1289 }
1290
1291 return ret;
1292 }
1293
1294 /**
1295 * @brief High-pass filter on interrupts/tap generator.[get]
1296 *
1297 * @param ctx read / write interface definitions
1298 * @param val Get the values of hp in reg CTRL_REG2
1299 * @retval interface status (MANDATORY: return 0 -> no Error)
1300 *
1301 */
lis2de12_high_pass_int_conf_get(stmdev_ctx_t * ctx,lis2de12_hp_t * val)1302 int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx,
1303 lis2de12_hp_t *val)
1304 {
1305 lis2de12_ctrl_reg2_t ctrl_reg2;
1306 int32_t ret;
1307
1308 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
1309 (uint8_t *)&ctrl_reg2, 1);
1310
1311 switch (ctrl_reg2.hp)
1312 {
1313 case LIS2DE12_DISC_FROM_INT_GENERATOR:
1314 *val = LIS2DE12_DISC_FROM_INT_GENERATOR;
1315 break;
1316
1317 case LIS2DE12_ON_INT1_GEN:
1318 *val = LIS2DE12_ON_INT1_GEN;
1319 break;
1320
1321 case LIS2DE12_ON_INT2_GEN:
1322 *val = LIS2DE12_ON_INT2_GEN;
1323 break;
1324
1325 case LIS2DE12_ON_TAP_GEN:
1326 *val = LIS2DE12_ON_TAP_GEN;
1327 break;
1328
1329 case LIS2DE12_ON_INT1_INT2_GEN:
1330 *val = LIS2DE12_ON_INT1_INT2_GEN;
1331 break;
1332
1333 case LIS2DE12_ON_INT1_TAP_GEN:
1334 *val = LIS2DE12_ON_INT1_TAP_GEN;
1335 break;
1336
1337 case LIS2DE12_ON_INT2_TAP_GEN:
1338 *val = LIS2DE12_ON_INT2_TAP_GEN;
1339 break;
1340
1341 case LIS2DE12_ON_INT1_INT2_TAP_GEN:
1342 *val = LIS2DE12_ON_INT1_INT2_TAP_GEN;
1343 break;
1344
1345 default:
1346 *val = LIS2DE12_DISC_FROM_INT_GENERATOR;
1347 break;
1348 }
1349
1350 return ret;
1351 }
1352
1353 /**
1354 * @brief Int1 pin routing configuration register.[set]
1355 *
1356 * @param ctx read / write interface definitions
1357 * @param val registers CTRL_REG3
1358 * @retval interface status (MANDATORY: return 0 -> no Error)
1359 *
1360 */
lis2de12_pin_int1_config_set(stmdev_ctx_t * ctx,lis2de12_ctrl_reg3_t * val)1361 int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx,
1362 lis2de12_ctrl_reg3_t *val)
1363 {
1364 int32_t ret;
1365
1366 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
1367
1368 return ret;
1369 }
1370
1371 /**
1372 * @brief Int1 pin routing configuration register.[get]
1373 *
1374 * @param ctx read / write interface definitions
1375 * @param val registers CTRL_REG3
1376 * @retval interface status (MANDATORY: return 0 -> no Error)
1377 *
1378 */
lis2de12_pin_int1_config_get(stmdev_ctx_t * ctx,lis2de12_ctrl_reg3_t * val)1379 int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx,
1380 lis2de12_ctrl_reg3_t *val)
1381 {
1382 int32_t ret;
1383
1384 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
1385
1386 return ret;
1387 }
1388 /**
1389 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1390 * on INT2 pin when 6D bit on
1391 * INT2_CFG (34h) is set to 1.
1392 *
1393 * @param ctx read / write interface definitions
1394 * @param val change the values of d4d_int2 in reg CTRL_REG5
1395 * @retval interface status (MANDATORY: return 0 -> no Error)
1396 *
1397 */
lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1398 int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx,
1399 uint8_t val)
1400 {
1401 lis2de12_ctrl_reg5_t ctrl_reg5;
1402 int32_t ret;
1403
1404 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1405 (uint8_t *)&ctrl_reg5, 1);
1406
1407 if (ret == 0)
1408 {
1409 ctrl_reg5.d4d_int2 = val;
1410 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1411 (uint8_t *)&ctrl_reg5, 1);
1412 }
1413
1414 return ret;
1415 }
1416
1417 /**
1418 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1419 * INT2_CFG (34h) is set to 1.[get]
1420 *
1421 * @param ctx read / write interface definitions
1422 * @param val change the values of d4d_int2 in reg CTRL_REG5
1423 * @retval interface status (MANDATORY: return 0 -> no Error)
1424 *
1425 */
lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1426 int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx,
1427 uint8_t *val)
1428 {
1429 lis2de12_ctrl_reg5_t ctrl_reg5;
1430 int32_t ret;
1431
1432 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1433 (uint8_t *)&ctrl_reg5, 1);
1434 *val = (uint8_t)ctrl_reg5.d4d_int2;
1435
1436 return ret;
1437 }
1438
1439 /**
1440 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1441 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1442 * itself.[set]
1443 *
1444 * @param ctx read / write interface definitions
1445 * @param val change the values of lir_int2 in reg CTRL_REG5
1446 * @retval interface status (MANDATORY: return 0 -> no Error)
1447 *
1448 */
lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t * ctx,lis2de12_lir_int2_t val)1449 int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
1450 lis2de12_lir_int2_t val)
1451 {
1452 lis2de12_ctrl_reg5_t ctrl_reg5;
1453 int32_t ret;
1454
1455 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1456 (uint8_t *)&ctrl_reg5, 1);
1457
1458 if (ret == 0)
1459 {
1460 ctrl_reg5.lir_int2 = (uint8_t)val;
1461 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1462 (uint8_t *)&ctrl_reg5, 1);
1463 }
1464
1465 return ret;
1466 }
1467
1468 /**
1469 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1470 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1471 * itself.[get]
1472 *
1473 * @param ctx read / write interface definitions
1474 * @param val Get the values of lir_int2 in reg CTRL_REG5
1475 * @retval interface status (MANDATORY: return 0 -> no Error)
1476 *
1477 */
lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t * ctx,lis2de12_lir_int2_t * val)1478 int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
1479 lis2de12_lir_int2_t *val)
1480 {
1481 lis2de12_ctrl_reg5_t ctrl_reg5;
1482 int32_t ret;
1483
1484 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1485 (uint8_t *)&ctrl_reg5, 1);
1486
1487 switch (ctrl_reg5.lir_int2)
1488 {
1489 case LIS2DE12_INT2_PULSED:
1490 *val = LIS2DE12_INT2_PULSED;
1491 break;
1492
1493 case LIS2DE12_INT2_LATCHED:
1494 *val = LIS2DE12_INT2_LATCHED;
1495 break;
1496
1497 default:
1498 *val = LIS2DE12_INT2_PULSED;
1499 break;
1500 }
1501
1502 return ret;
1503 }
1504
1505 /**
1506 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1507 * on INT1_CFG(30h) is set to 1.[set]
1508 *
1509 * @param ctx read / write interface definitions
1510 * @param val change the values of d4d_int1 in reg CTRL_REG5
1511 * @retval interface status (MANDATORY: return 0 -> no Error)
1512 *
1513 */
lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1514 int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx,
1515 uint8_t val)
1516 {
1517 lis2de12_ctrl_reg5_t ctrl_reg5;
1518 int32_t ret;
1519
1520 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1521 (uint8_t *)&ctrl_reg5, 1);
1522
1523 if (ret == 0)
1524 {
1525 ctrl_reg5.d4d_int1 = val;
1526 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1527 (uint8_t *)&ctrl_reg5, 1);
1528 }
1529
1530 return ret;
1531 }
1532
1533 /**
1534 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1535 * INT1_CFG(30h) is set to 1.[get]
1536 *
1537 * @param ctx read / write interface definitions
1538 * @param val change the values of d4d_int1 in reg CTRL_REG5
1539 * @retval interface status (MANDATORY: return 0 -> no Error)
1540 *
1541 */
lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1542 int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx,
1543 uint8_t *val)
1544 {
1545 lis2de12_ctrl_reg5_t ctrl_reg5;
1546 int32_t ret;
1547
1548 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1549 (uint8_t *)&ctrl_reg5, 1);
1550 *val = (uint8_t)ctrl_reg5.d4d_int1;
1551
1552 return ret;
1553 }
1554
1555 /**
1556 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1557 * register cleared by reading INT1_SRC (31h) itself.[set]
1558 *
1559 * @param ctx read / write interface definitions
1560 * @param val change the values of lir_int1 in reg CTRL_REG5
1561 * @retval interface status (MANDATORY: return 0 -> no Error)
1562 *
1563 */
lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t * ctx,lis2de12_lir_int1_t val)1564 int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
1565 lis2de12_lir_int1_t val)
1566 {
1567 lis2de12_ctrl_reg5_t ctrl_reg5;
1568 int32_t ret;
1569
1570 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1571 (uint8_t *)&ctrl_reg5, 1);
1572
1573 if (ret == 0)
1574 {
1575 ctrl_reg5.lir_int1 = (uint8_t)val;
1576 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1577 (uint8_t *)&ctrl_reg5, 1);
1578 }
1579
1580 return ret;
1581 }
1582
1583 /**
1584 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1585 * register cleared by reading INT1_SRC (31h) itself.[get]
1586 *
1587 * @param ctx read / write interface definitions
1588 * @param val Get the values of lir_int1 in reg CTRL_REG5
1589 * @retval interface status (MANDATORY: return 0 -> no Error)
1590 *
1591 */
lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t * ctx,lis2de12_lir_int1_t * val)1592 int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
1593 lis2de12_lir_int1_t *val)
1594 {
1595 lis2de12_ctrl_reg5_t ctrl_reg5;
1596 int32_t ret;
1597
1598 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1599 (uint8_t *)&ctrl_reg5, 1);
1600
1601 switch (ctrl_reg5.lir_int1)
1602 {
1603 case LIS2DE12_INT1_PULSED:
1604 *val = LIS2DE12_INT1_PULSED;
1605 break;
1606
1607 case LIS2DE12_INT1_LATCHED:
1608 *val = LIS2DE12_INT1_LATCHED;
1609 break;
1610
1611 default:
1612 *val = LIS2DE12_INT1_PULSED;
1613 break;
1614 }
1615
1616 return ret;
1617 }
1618
1619 /**
1620 * @brief Int2 pin routing configuration register.[set]
1621 *
1622 * @param ctx read / write interface definitions
1623 * @param val registers CTRL_REG6
1624 * @retval interface status (MANDATORY: return 0 -> no Error)
1625 *
1626 */
lis2de12_pin_int2_config_set(stmdev_ctx_t * ctx,lis2de12_ctrl_reg6_t * val)1627 int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx,
1628 lis2de12_ctrl_reg6_t *val)
1629 {
1630 int32_t ret;
1631
1632 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
1633
1634 return ret;
1635 }
1636
1637 /**
1638 * @brief Int2 pin routing configuration register.[get]
1639 *
1640 * @param ctx read / write interface definitions
1641 * @param val registers CTRL_REG6
1642 * @retval interface status (MANDATORY: return 0 -> no Error)
1643 *
1644 */
lis2de12_pin_int2_config_get(stmdev_ctx_t * ctx,lis2de12_ctrl_reg6_t * val)1645 int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx,
1646 lis2de12_ctrl_reg6_t *val)
1647 {
1648 int32_t ret;
1649
1650 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
1651
1652 return ret;
1653 }
1654 /**
1655 * @}
1656 *
1657 */
1658
1659 /**
1660 * @defgroup LIS2DE12_Fifo
1661 * @brief This section group all the functions concerning the fifo usage
1662 * @{
1663 *
1664 */
1665
1666 /**
1667 * @brief FIFO enable.[set]
1668 *
1669 * @param ctx read / write interface definitions
1670 * @param val change the values of fifo_en in reg CTRL_REG5
1671 * @retval interface status (MANDATORY: return 0 -> no Error)
1672 *
1673 */
lis2de12_fifo_set(stmdev_ctx_t * ctx,uint8_t val)1674 int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
1675 {
1676 lis2de12_ctrl_reg5_t ctrl_reg5;
1677 int32_t ret;
1678
1679 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1680 (uint8_t *)&ctrl_reg5, 1);
1681
1682 if (ret == 0)
1683 {
1684 ctrl_reg5.fifo_en = val;
1685 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1686 (uint8_t *)&ctrl_reg5, 1);
1687 }
1688
1689 return ret;
1690 }
1691
1692 /**
1693 * @brief FIFO enable.[get]
1694 *
1695 * @param ctx read / write interface definitions
1696 * @param val change the values of fifo_en in reg CTRL_REG5
1697 * @retval interface status (MANDATORY: return 0 -> no Error)
1698 *
1699 */
lis2de12_fifo_get(stmdev_ctx_t * ctx,uint8_t * val)1700 int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
1701 {
1702 lis2de12_ctrl_reg5_t ctrl_reg5;
1703 int32_t ret;
1704
1705 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1706 (uint8_t *)&ctrl_reg5, 1);
1707 *val = (uint8_t)ctrl_reg5.fifo_en;
1708
1709 return ret;
1710 }
1711
1712 /**
1713 * @brief FIFO watermark level selection.[set]
1714 *
1715 * @param ctx read / write interface definitions
1716 * @param val change the values of fth in reg FIFO_CTRL_REG
1717 * @retval interface status (MANDATORY: return 0 -> no Error)
1718 *
1719 */
lis2de12_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)1720 int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
1721 {
1722 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1723 int32_t ret;
1724
1725 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1726 (uint8_t *)&fifo_ctrl_reg, 1);
1727
1728 if (ret == 0)
1729 {
1730 fifo_ctrl_reg.fth = val;
1731 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1732 (uint8_t *)&fifo_ctrl_reg, 1);
1733 }
1734
1735 return ret;
1736 }
1737
1738 /**
1739 * @brief FIFO watermark level selection.[get]
1740 *
1741 * @param ctx read / write interface definitions
1742 * @param val change the values of fth in reg FIFO_CTRL_REG
1743 * @retval interface status (MANDATORY: return 0 -> no Error)
1744 *
1745 */
lis2de12_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)1746 int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
1747 {
1748 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1749 int32_t ret;
1750
1751 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1752 (uint8_t *)&fifo_ctrl_reg, 1);
1753 *val = (uint8_t)fifo_ctrl_reg.fth;
1754
1755 return ret;
1756 }
1757
1758 /**
1759 * @brief Trigger FIFO selection.[set]
1760 *
1761 * @param ctx read / write interface definitions
1762 * @param val change the values of tr in reg FIFO_CTRL_REG
1763 * @retval interface status (MANDATORY: return 0 -> no Error)
1764 *
1765 */
lis2de12_fifo_trigger_event_set(stmdev_ctx_t * ctx,lis2de12_tr_t val)1766 int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx,
1767 lis2de12_tr_t val)
1768 {
1769 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1770 int32_t ret;
1771
1772 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1773 (uint8_t *)&fifo_ctrl_reg, 1);
1774
1775 if (ret == 0)
1776 {
1777 fifo_ctrl_reg.tr = (uint8_t)val;
1778 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1779 (uint8_t *)&fifo_ctrl_reg, 1);
1780 }
1781
1782 return ret;
1783 }
1784
1785 /**
1786 * @brief Trigger FIFO selection.[get]
1787 *
1788 * @param ctx read / write interface definitions
1789 * @param val Get the values of tr in reg FIFO_CTRL_REG
1790 * @retval interface status (MANDATORY: return 0 -> no Error)
1791 *
1792 */
lis2de12_fifo_trigger_event_get(stmdev_ctx_t * ctx,lis2de12_tr_t * val)1793 int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx,
1794 lis2de12_tr_t *val)
1795 {
1796 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1797 int32_t ret;
1798
1799 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1800 (uint8_t *)&fifo_ctrl_reg, 1);
1801
1802 switch (fifo_ctrl_reg.tr)
1803 {
1804 case LIS2DE12_INT1_GEN:
1805 *val = LIS2DE12_INT1_GEN;
1806 break;
1807
1808 case LIS2DE12_INT2_GEN:
1809 *val = LIS2DE12_INT2_GEN;
1810 break;
1811
1812 default:
1813 *val = LIS2DE12_INT1_GEN;
1814 break;
1815 }
1816
1817 return ret;
1818 }
1819
1820 /**
1821 * @brief FIFO mode selection.[set]
1822 *
1823 * @param ctx read / write interface definitions
1824 * @param val change the values of fm in reg FIFO_CTRL_REG
1825 * @retval interface status (MANDATORY: return 0 -> no Error)
1826 *
1827 */
lis2de12_fifo_mode_set(stmdev_ctx_t * ctx,lis2de12_fm_t val)1828 int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val)
1829 {
1830 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1831 int32_t ret;
1832
1833 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1834 (uint8_t *)&fifo_ctrl_reg, 1);
1835
1836 if (ret == 0)
1837 {
1838 fifo_ctrl_reg.fm = (uint8_t)val;
1839 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1840 (uint8_t *)&fifo_ctrl_reg, 1);
1841 }
1842
1843 return ret;
1844 }
1845
1846 /**
1847 * @brief FIFO mode selection.[get]
1848 *
1849 * @param ctx read / write interface definitions
1850 * @param val Get the values of fm in reg FIFO_CTRL_REG
1851 * @retval interface status (MANDATORY: return 0 -> no Error)
1852 *
1853 */
lis2de12_fifo_mode_get(stmdev_ctx_t * ctx,lis2de12_fm_t * val)1854 int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val)
1855 {
1856 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1857 int32_t ret;
1858
1859 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1860 (uint8_t *)&fifo_ctrl_reg, 1);
1861
1862 switch (fifo_ctrl_reg.fm)
1863 {
1864 case LIS2DE12_BYPASS_MODE:
1865 *val = LIS2DE12_BYPASS_MODE;
1866 break;
1867
1868 case LIS2DE12_FIFO_MODE:
1869 *val = LIS2DE12_FIFO_MODE;
1870 break;
1871
1872 case LIS2DE12_DYNAMIC_STREAM_MODE:
1873 *val = LIS2DE12_DYNAMIC_STREAM_MODE;
1874 break;
1875
1876 case LIS2DE12_STREAM_TO_FIFO_MODE:
1877 *val = LIS2DE12_STREAM_TO_FIFO_MODE;
1878 break;
1879
1880 default:
1881 *val = LIS2DE12_BYPASS_MODE;
1882 break;
1883 }
1884
1885 return ret;
1886 }
1887
1888 /**
1889 * @brief FIFO status register.[get]
1890 *
1891 * @param ctx read / write interface definitions
1892 * @param val registers FIFO_SRC_REG
1893 * @retval interface status (MANDATORY: return 0 -> no Error)
1894 *
1895 */
lis2de12_fifo_status_get(stmdev_ctx_t * ctx,lis2de12_fifo_src_reg_t * val)1896 int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx,
1897 lis2de12_fifo_src_reg_t *val)
1898 {
1899 int32_t ret;
1900
1901 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *) val, 1);
1902
1903 return ret;
1904 }
1905 /**
1906 * @brief FIFO stored data level.[get]
1907 *
1908 * @param ctx read / write interface definitions
1909 * @param val change the values of fss in reg FIFO_SRC_REG
1910 * @retval interface status (MANDATORY: return 0 -> no Error)
1911 *
1912 */
lis2de12_fifo_data_level_get(stmdev_ctx_t * ctx,uint8_t * val)1913 int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
1914 {
1915 lis2de12_fifo_src_reg_t fifo_src_reg;
1916 int32_t ret;
1917
1918 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1919 (uint8_t *)&fifo_src_reg, 1);
1920 *val = (uint8_t)fifo_src_reg.fss;
1921
1922 return ret;
1923 }
1924 /**
1925 * @brief Empty FIFO status flag.[get]
1926 *
1927 * @param ctx read / write interface definitions
1928 * @param val change the values of empty in reg FIFO_SRC_REG
1929 * @retval interface status (MANDATORY: return 0 -> no Error)
1930 *
1931 */
lis2de12_fifo_empty_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1932 int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1933 {
1934 lis2de12_fifo_src_reg_t fifo_src_reg;
1935 int32_t ret;
1936
1937 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1938 (uint8_t *)&fifo_src_reg, 1);
1939 *val = (uint8_t)fifo_src_reg.empty;
1940
1941 return ret;
1942 }
1943 /**
1944 * @brief FIFO overrun status flag.[get]
1945 *
1946 * @param ctx read / write interface definitions
1947 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
1948 * @retval interface status (MANDATORY: return 0 -> no Error)
1949 *
1950 */
lis2de12_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1951 int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1952 {
1953 lis2de12_fifo_src_reg_t fifo_src_reg;
1954 int32_t ret;
1955
1956 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1957 (uint8_t *)&fifo_src_reg, 1);
1958 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
1959
1960 return ret;
1961 }
1962 /**
1963 * @brief FIFO watermark status.[get]
1964 *
1965 * @param ctx read / write interface definitions
1966 * @param val change the values of wtm in reg FIFO_SRC_REG
1967 * @retval interface status (MANDATORY: return 0 -> no Error)
1968 *
1969 */
lis2de12_fifo_fth_flag_get(stmdev_ctx_t * ctx,uint8_t * val)1970 int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
1971 {
1972 lis2de12_fifo_src_reg_t fifo_src_reg;
1973 int32_t ret;
1974
1975 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1976 (uint8_t *)&fifo_src_reg, 1);
1977 *val = (uint8_t)fifo_src_reg.wtm;
1978
1979 return ret;
1980 }
1981 /**
1982 * @}
1983 *
1984 */
1985
1986 /**
1987 * @defgroup LIS2DE12_Tap_generator
1988 * @brief This section group all the functions that manage the tap and
1989 * double tap event generation
1990 * @{
1991 *
1992 */
1993
1994 /**
1995 * @brief Tap/Double Tap generator configuration register.[set]
1996 *
1997 * @param ctx read / write interface definitions
1998 * @param val registers CLICK_CFG
1999 * @retval interface status (MANDATORY: return 0 -> no Error)
2000 *
2001 */
lis2de12_tap_conf_set(stmdev_ctx_t * ctx,lis2de12_click_cfg_t * val)2002 int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx,
2003 lis2de12_click_cfg_t *val)
2004 {
2005 int32_t ret;
2006
2007 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
2008
2009 return ret;
2010 }
2011
2012 /**
2013 * @brief Tap/Double Tap generator configuration register.[get]
2014 *
2015 * @param ctx read / write interface definitions
2016 * @param val registers CLICK_CFG
2017 * @retval interface status (MANDATORY: return 0 -> no Error)
2018 *
2019 */
lis2de12_tap_conf_get(stmdev_ctx_t * ctx,lis2de12_click_cfg_t * val)2020 int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx,
2021 lis2de12_click_cfg_t *val)
2022 {
2023 int32_t ret;
2024
2025 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
2026
2027 return ret;
2028 }
2029 /**
2030 * @brief Tap/Double Tap generator source register.[get]
2031 *
2032 * @param ctx read / write interface definitions
2033 * @param val registers CLICK_SRC
2034 * @retval interface status (MANDATORY: return 0 -> no Error)
2035 *
2036 */
lis2de12_tap_source_get(stmdev_ctx_t * ctx,lis2de12_click_src_t * val)2037 int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx,
2038 lis2de12_click_src_t *val)
2039 {
2040 int32_t ret;
2041
2042 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_SRC, (uint8_t *) val, 1);
2043
2044 return ret;
2045 }
2046 /**
2047 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2048 * 1 LSB = full scale/128
2049 *
2050 * @param ctx read / write interface definitions
2051 * @param val change the values of ths in reg CLICK_THS
2052 * @retval interface status (MANDATORY: return 0 -> no Error)
2053 *
2054 */
lis2de12_tap_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2055 int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2056 {
2057 lis2de12_click_ths_t click_ths;
2058 int32_t ret;
2059
2060 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2061 (uint8_t *)&click_ths, 1);
2062
2063 if (ret == 0)
2064 {
2065 click_ths.ths = val;
2066 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
2067 (uint8_t *)&click_ths, 1);
2068 }
2069
2070 return ret;
2071 }
2072
2073 /**
2074 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2075 * 1 LSB = full scale/128
2076 *
2077 * @param ctx read / write interface definitions
2078 * @param val change the values of ths in reg CLICK_THS
2079 * @retval interface status (MANDATORY: return 0 -> no Error)
2080 *
2081 */
lis2de12_tap_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2082 int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2083 {
2084 lis2de12_click_ths_t click_ths;
2085 int32_t ret;
2086
2087 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2088 (uint8_t *)&click_ths, 1);
2089 *val = (uint8_t)click_ths.ths;
2090
2091 return ret;
2092 }
2093
2094 /**
2095 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2096 * for the duration of the latency window.
2097 * If the LIR_Click bit is set, the interrupt is kept high until the
2098 * CLICK_SRC(39h) register is read.[set]
2099 *
2100 * @param ctx read / write interface definitions
2101 * @param val change the values of lir_click in reg CLICK_THS
2102 * @retval interface status (MANDATORY: return 0 -> no Error)
2103 *
2104 */
lis2de12_tap_notification_mode_set(stmdev_ctx_t * ctx,lis2de12_lir_click_t val)2105 int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx,
2106 lis2de12_lir_click_t val)
2107 {
2108 lis2de12_click_ths_t click_ths;
2109 int32_t ret;
2110
2111 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2112 (uint8_t *)&click_ths, 1);
2113
2114 if (ret == 0)
2115 {
2116 click_ths.lir_click = (uint8_t)val;
2117 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
2118 (uint8_t *)&click_ths, 1);
2119 }
2120
2121 return ret;
2122 }
2123
2124 /**
2125 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2126 * for the duration of the latency window.
2127 * If the LIR_Click bit is set, the interrupt is kept high until the
2128 * CLICK_SRC(39h) register is read.[get]
2129 *
2130 * @param ctx read / write interface definitions
2131 * @param val Get the values of lir_click in reg CLICK_THS
2132 * @retval interface status (MANDATORY: return 0 -> no Error)
2133 *
2134 */
lis2de12_tap_notification_mode_get(stmdev_ctx_t * ctx,lis2de12_lir_click_t * val)2135 int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx,
2136 lis2de12_lir_click_t *val)
2137 {
2138 lis2de12_click_ths_t click_ths;
2139 int32_t ret;
2140
2141 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2142 (uint8_t *)&click_ths, 1);
2143
2144 switch (click_ths.lir_click)
2145 {
2146 case LIS2DE12_TAP_PULSED:
2147 *val = LIS2DE12_TAP_PULSED;
2148 break;
2149
2150 case LIS2DE12_TAP_LATCHED:
2151 *val = LIS2DE12_TAP_LATCHED;
2152 break;
2153
2154 default:
2155 *val = LIS2DE12_TAP_PULSED;
2156 break;
2157 }
2158
2159 return ret;
2160 }
2161
2162 /**
2163 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2164 * between the start of the click-detection procedure and when the
2165 * acceleration falls back below the threshold.[set]
2166 *
2167 * @param ctx read / write interface definitions
2168 * @param val change the values of tli in reg TIME_LIMIT
2169 * @retval interface status (MANDATORY: return 0 -> no Error)
2170 *
2171 */
lis2de12_shock_dur_set(stmdev_ctx_t * ctx,uint8_t val)2172 int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2173 {
2174 lis2de12_time_limit_t time_limit;
2175 int32_t ret;
2176
2177 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
2178 (uint8_t *)&time_limit, 1);
2179
2180 if (ret == 0)
2181 {
2182 time_limit.tli = val;
2183 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LIMIT,
2184 (uint8_t *)&time_limit, 1);
2185 }
2186
2187 return ret;
2188 }
2189
2190 /**
2191 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2192 * the start of the click-detection procedure and when the
2193 * acceleration falls back below the threshold.[get]
2194 *
2195 * @param ctx read / write interface definitions
2196 * @param val change the values of tli in reg TIME_LIMIT
2197 * @retval interface status (MANDATORY: return 0 -> no Error)
2198 *
2199 */
lis2de12_shock_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2200 int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2201 {
2202 lis2de12_time_limit_t time_limit;
2203 int32_t ret;
2204
2205 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
2206 (uint8_t *)&time_limit, 1);
2207 *val = (uint8_t)time_limit.tli;
2208
2209 return ret;
2210 }
2211
2212 /**
2213 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2214 * click detection where the click-detection procedure is
2215 * disabled, in cases where the device is configured for
2216 * double-click detection.[set]
2217 *
2218 * @param ctx read / write interface definitions
2219 * @param val change the values of tla in reg TIME_LATENCY
2220 * @retval interface status (MANDATORY: return 0 -> no Error)
2221 *
2222 */
lis2de12_quiet_dur_set(stmdev_ctx_t * ctx,uint8_t val)2223 int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2224 {
2225 lis2de12_time_latency_t time_latency;
2226 int32_t ret;
2227
2228 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
2229 (uint8_t *)&time_latency, 1);
2230
2231 if (ret == 0)
2232 {
2233 time_latency.tla = val;
2234 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LATENCY,
2235 (uint8_t *)&time_latency, 1);
2236 }
2237
2238 return ret;
2239 }
2240
2241 /**
2242 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2243 * click detection where the click-detection procedure is
2244 * disabled, in cases where the device is configured for
2245 * double-click detection.[get]
2246 *
2247 * @param ctx read / write interface definitions
2248 * @param val change the values of tla in reg TIME_LATENCY
2249 * @retval interface status (MANDATORY: return 0 -> no Error)
2250 *
2251 */
lis2de12_quiet_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2252 int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2253 {
2254 lis2de12_time_latency_t time_latency;
2255 int32_t ret;
2256
2257 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
2258 (uint8_t *)&time_latency, 1);
2259 *val = (uint8_t)time_latency.tla;
2260
2261 return ret;
2262 }
2263
2264 /**
2265 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2266 * after the end of the latency interval in which the click-detection
2267 * procedure can start, in cases where the device is configured
2268 * for double-click detection.[set]
2269 *
2270 * @param ctx read / write interface definitions
2271 * @param val change the values of tw in reg TIME_WINDOW
2272 * @retval interface status (MANDATORY: return 0 -> no Error)
2273 *
2274 */
lis2de12_double_tap_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2275 int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx,
2276 uint8_t val)
2277 {
2278 lis2de12_time_window_t time_window;
2279 int32_t ret;
2280
2281 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
2282 (uint8_t *)&time_window, 1);
2283
2284 if (ret == 0)
2285 {
2286 time_window.tw = val;
2287 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_WINDOW,
2288 (uint8_t *)&time_window, 1);
2289 }
2290
2291 return ret;
2292 }
2293
2294 /**
2295 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2296 * after the end of the latency interval in which the
2297 * click-detection procedure can start, in cases where the device
2298 * is configured for double-click detection.[get]
2299 *
2300 * @param ctx read / write interface definitions
2301 * @param val change the values of tw in reg TIME_WINDOW
2302 * @retval interface status (MANDATORY: return 0 -> no Error)
2303 *
2304 */
lis2de12_double_tap_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2305 int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx,
2306 uint8_t *val)
2307 {
2308 lis2de12_time_window_t time_window;
2309 int32_t ret;
2310
2311 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
2312 (uint8_t *)&time_window, 1);
2313 *val = (uint8_t)time_window.tw;
2314
2315 return ret;
2316 }
2317
2318 /**
2319 * @}
2320 *
2321 */
2322
2323 /**
2324 * @defgroup LIS2DE12_Activity_inactivity
2325 * @brief This section group all the functions concerning activity
2326 * inactivity functionality
2327 * @{
2328 *
2329 */
2330
2331 /**
2332 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2333 * low-power mode.[set]
2334 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2335 *
2336 * @param ctx read / write interface definitions
2337 * @param val change the values of acth in reg ACT_THS
2338 * @retval interface status (MANDATORY: return 0 -> no Error)
2339 *
2340 */
lis2de12_act_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2341 int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2342 {
2343 lis2de12_act_ths_t act_ths;
2344 int32_t ret;
2345
2346 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2347
2348 if (ret == 0)
2349 {
2350 act_ths.acth = val;
2351 ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2352 }
2353
2354 return ret;
2355 }
2356
2357 /**
2358 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2359 * mode.[get]
2360 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2361 *
2362 * @param ctx read / write interface definitions
2363 * @param val change the values of acth in reg ACT_THS
2364 * @retval interface status (MANDATORY: return 0 -> no Error)
2365 *
2366 */
lis2de12_act_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2367 int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2368 {
2369 lis2de12_act_ths_t act_ths;
2370 int32_t ret;
2371
2372 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2373 *val = (uint8_t)act_ths.acth;
2374
2375 return ret;
2376 }
2377
2378 /**
2379 * @brief Sleep-to-wake, return-to-sleep.[set]
2380 * duration = (8*1[LSb]+1)/ODR
2381 *
2382 * @param ctx read / write interface definitions
2383 * @param val change the values of actd in reg ACT_DUR
2384 * @retval interface status (MANDATORY: return 0 -> no Error)
2385 *
2386 */
lis2de12_act_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2387 int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2388 {
2389 lis2de12_act_dur_t act_dur;
2390 int32_t ret;
2391
2392 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2393
2394 if (ret == 0)
2395 {
2396 act_dur.actd = val;
2397 ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2398 }
2399
2400 return ret;
2401 }
2402
2403 /**
2404 * @brief Sleep-to-wake, return-to-sleep.[get]
2405 * duration = (8*1[LSb]+1)/ODR
2406 *
2407 * @param ctx read / write interface definitions
2408 * @param val change the values of actd in reg ACT_DUR
2409 * @retval interface status (MANDATORY: return 0 -> no Error)
2410 *
2411 */
lis2de12_act_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2412 int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2413 {
2414 lis2de12_act_dur_t act_dur;
2415 int32_t ret;
2416
2417 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2418 *val = (uint8_t)act_dur.actd;
2419
2420 return ret;
2421 }
2422
2423 /**
2424 * @}
2425 *
2426 */
2427
2428 /**
2429 * @defgroup LIS2DE12_Serial_interface
2430 * @brief This section group all the functions concerning serial
2431 * interface management
2432 * @{
2433 *
2434 */
2435
2436 /**
2437 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2438 *
2439 * @param ctx read / write interface definitions
2440 * @param val change the values of sdo_pu_disc in reg CTRL_REG0
2441 * @retval interface status (MANDATORY: return 0 -> no Error)
2442 *
2443 */
lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lis2de12_sdo_pu_disc_t val)2444 int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
2445 lis2de12_sdo_pu_disc_t val)
2446 {
2447 lis2de12_ctrl_reg0_t ctrl_reg0;
2448 int32_t ret;
2449
2450 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
2451 (uint8_t *)&ctrl_reg0, 1);
2452
2453 if (ret == 0)
2454 {
2455 ctrl_reg0.sdo_pu_disc = (uint8_t)val;
2456 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG0,
2457 (uint8_t *)&ctrl_reg0, 1);
2458 }
2459
2460 return ret;
2461 }
2462
2463 /**
2464 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2465 *
2466 * @param ctx read / write interface definitions
2467 * @param val Get the values of sdo_pu_disc in reg CTRL_REG0
2468 * @retval interface status (MANDATORY: return 0 -> no Error)
2469 *
2470 */
lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lis2de12_sdo_pu_disc_t * val)2471 int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
2472 lis2de12_sdo_pu_disc_t *val)
2473 {
2474 lis2de12_ctrl_reg0_t ctrl_reg0;
2475 int32_t ret;
2476
2477 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
2478 (uint8_t *)&ctrl_reg0, 1);
2479
2480 switch (ctrl_reg0.sdo_pu_disc)
2481 {
2482 case LIS2DE12_PULL_UP_DISCONNECT:
2483 *val = LIS2DE12_PULL_UP_DISCONNECT;
2484 break;
2485
2486 case LIS2DE12_PULL_UP_CONNECT:
2487 *val = LIS2DE12_PULL_UP_CONNECT;
2488 break;
2489
2490 default:
2491 *val = LIS2DE12_PULL_UP_DISCONNECT;
2492 break;
2493 }
2494
2495 return ret;
2496 }
2497
2498 /**
2499 * @brief SPI Serial Interface Mode selection.[set]
2500 *
2501 * @param ctx read / write interface definitions
2502 * @param val change the values of sim in reg CTRL_REG4
2503 * @retval interface status (MANDATORY: return 0 -> no Error)
2504 *
2505 */
lis2de12_spi_mode_set(stmdev_ctx_t * ctx,lis2de12_sim_t val)2506 int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val)
2507 {
2508 lis2de12_ctrl_reg4_t ctrl_reg4;
2509 int32_t ret;
2510
2511 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
2512 (uint8_t *)&ctrl_reg4, 1);
2513
2514 if (ret == 0)
2515 {
2516 ctrl_reg4.sim = (uint8_t)val;
2517 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
2518 (uint8_t *)&ctrl_reg4, 1);
2519 }
2520
2521 return ret;
2522 }
2523
2524 /**
2525 * @brief SPI Serial Interface Mode selection.[get]
2526 *
2527 * @param ctx read / write interface definitions
2528 * @param val Get the values of sim in reg CTRL_REG4
2529 * @retval interface status (MANDATORY: return 0 -> no Error)
2530 *
2531 */
lis2de12_spi_mode_get(stmdev_ctx_t * ctx,lis2de12_sim_t * val)2532 int32_t lis2de12_spi_mode_get(stmdev_ctx_t *ctx, lis2de12_sim_t *val)
2533 {
2534 lis2de12_ctrl_reg4_t ctrl_reg4;
2535 int32_t ret;
2536
2537 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
2538 (uint8_t *)&ctrl_reg4, 1);
2539
2540 switch (ctrl_reg4.sim)
2541 {
2542 case LIS2DE12_SPI_4_WIRE:
2543 *val = LIS2DE12_SPI_4_WIRE;
2544 break;
2545
2546 case LIS2DE12_SPI_3_WIRE:
2547 *val = LIS2DE12_SPI_3_WIRE;
2548 break;
2549
2550 default:
2551 *val = LIS2DE12_SPI_4_WIRE;
2552 break;
2553 }
2554
2555 return ret;
2556 }
2557
2558 /**
2559 * @}
2560 *
2561 */
2562
2563 /**
2564 * @}
2565 *
2566 */
2567
2568 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2569
