1/* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <nordic/nrf_common.dtsi> 9 10/delete-node/ &sw_pwm; 11 12/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ 13#define NRF_DOMAIN_ID_APPLICATION 0 14#define NRF_DOMAIN_ID_FLPR 1 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpuapp: cpu@0 { 25 compatible = "arm,cortex-m33f"; 26 reg = <0>; 27 device_type = "cpu"; 28 clock-frequency = <DT_FREQ_M(128)>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 itm: itm@e0000000 { 32 compatible = "arm,armv8m-itm"; 33 reg = <0xe0000000 0x1000>; 34 swo-ref-frequency = <DT_FREQ_M(128)>; 35 }; 36 }; 37 38 cpuflpr: cpu@1 { 39 compatible = "nordic,vpr"; 40 reg = <1>; 41 device_type = "cpu"; 42 clock-frequency = <DT_FREQ_M(128)>; 43 riscv,isa = "rv32emc"; 44 nordic,bus-width = <32>; 45 }; 46 }; 47 48 clocks { 49 lfxo: lfxo { 50 compatible = "nordic,nrf-lfxo"; 51 #clock-cells = <0>; 52 clock-frequency = <32768>; 53 }; 54 55 hfxo: hfxo { 56 compatible = "nordic,nrf-hfxo"; 57 #clock-cells = <0>; 58 clock-frequency = <DT_FREQ_M(32)>; 59 }; 60 }; 61 62 soc { 63 #address-cells = <1>; 64 #size-cells = <1>; 65 66#ifdef USE_NON_SECURE_ADDRESS_MAP 67 /* intentionally empty because UICR is hardware fixed to Secure */ 68#else 69 uicr: uicr@ffd000 { 70 compatible = "nordic,nrf-uicr"; 71 reg = <0xffd000 0x1000>; 72 }; 73#endif 74 ficr: ficr@ffc000 { 75 compatible = "nordic,nrf-ficr"; 76 reg = <0xffc000 0x1000>; 77 #nordic,ficr-cells = <1>; 78 }; 79 80 cpuapp_sram: memory@20000000 { 81 compatible = "mmio-sram"; 82 reg = <0x20000000 DT_SIZE_K(188)>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x0 0x20000000 0x2f000>; 86 }; 87 88 cpuflpr_sram: memory@2002f000 { 89 compatible = "mmio-sram"; 90 reg = <0x2002f000 DT_SIZE_K(68)>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0x0 0x2002f000 0x11000>; 94 }; 95 96#ifdef USE_NON_SECURE_ADDRESS_MAP 97 global_peripherals: peripheral@40000000 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 ranges = <0x0 0x40000000 0x10000000>; 101#else 102 global_peripherals: peripheral@50000000 { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges = <0x0 0x50000000 0x10000000>; 106#endif 107 108 dppic00: dppic@42000 { 109 compatible = "nordic,nrf-dppic"; 110 reg = <0x42000 0x808>; 111 status = "disabled"; 112 }; 113 114 spi00: spi@4a000 { 115 /* 116 * This spi node can be either SPIM or SPIS, 117 * for the user to pick: 118 * compatible = "nordic,nrf-spim" or 119 * "nordic,nrf-spis". 120 */ 121 compatible = "nordic,nrf-spim"; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <0x4a000 0x1000>; 125 interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; 126 max-frequency = <DT_FREQ_M(32)>; 127 easydma-maxcnt-bits = <16>; 128 rx-delay-supported; 129 rx-delay = <1>; 130 status = "disabled"; 131 }; 132 133 uart00: uart@4a000 { 134 compatible = "nordic,nrf-uarte"; 135 reg = <0x4a000 0x1000>; 136 interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; 137 status = "disabled"; 138 }; 139 140 cpuflpr_vpr: vpr@4c000 { 141 compatible = "nordic,nrf-vpr-coprocessor"; 142 reg = <0x4c000 0x1000>; 143 ranges = <0x0 0x4c000 0x1000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 status = "disabled"; 147 148 cpuflpr_clic: interrupt-controller@f0000000 { 149 compatible = "nordic,nrf-clic"; 150 reg = <0xf0000000 0x1780>; 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 #address-cells = <1>; 154 status = "disabled"; 155 }; 156 }; 157 158 gpio2: gpio@50400 { 159 compatible = "nordic,nrf-gpio"; 160 gpio-controller; 161 reg = <0x50400 0x300>; 162 #gpio-cells = <2>; 163 ngpios = <11>; 164 status = "disabled"; 165 port = <2>; 166 }; 167 168 timer00: timer@55000 { 169 compatible = "nordic,nrf-timer"; 170 status = "disabled"; 171 reg = <0x55000 0x1000>; 172 cc-num = <6>; 173 max-bit-width = <32>; 174 interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>; 175 max-frequency = <DT_FREQ_M(128)>; 176 prescaler = <0>; 177 }; 178 179 dppic10: dppic@82000 { 180 compatible = "nordic,nrf-dppic"; 181 reg = <0x82000 0x808>; 182 status = "disabled"; 183 }; 184 185 timer10: timer@85000 { 186 compatible = "nordic,nrf-timer"; 187 status = "disabled"; 188 reg = <0x85000 0x1000>; 189 cc-num = <8>; 190 max-bit-width = <32>; 191 interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>; 192 max-frequency = <DT_FREQ_M(32)>; 193 prescaler = <0>; 194 }; 195 196 egu10: egu@87000 { 197 compatible = "nordic,nrf-egu"; 198 reg = <0x87000 0x1000>; 199 interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>; 200 status = "disabled"; 201 }; 202 203 radio: radio@8a000 { 204 compatible = "nordic,nrf-radio"; 205 reg = <0x8a000 0x1000>; 206 interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>; 207 status = "disabled"; 208 dfe-supported; 209 ieee802154-supported; 210 ble-2mbps-supported; 211 ble-coded-phy-supported; 212 213 ieee802154: ieee802154 { 214 compatible = "nordic,nrf-ieee802154"; 215 status = "disabled"; 216 }; 217 218 /* Note: In the nRF Connect SDK the SoftDevice Controller 219 * is added and set as the default Bluetooth Controller. 220 */ 221 bt_hci_controller: bt_hci_controller { 222 compatible = "zephyr,bt-hci-ll-sw-split"; 223 status = "disabled"; 224 }; 225 }; 226 227 dppic20: dppic@c2000 { 228 compatible = "nordic,nrf-dppic"; 229 reg = <0xc2000 0x808>; 230 status = "disabled"; 231 }; 232 233 i2c20: i2c@c6000 { 234 compatible = "nordic,nrf-twim"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <0xc6000 0x1000>; 238 clock-frequency = <I2C_BITRATE_STANDARD>; 239 interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; 240 easydma-maxcnt-bits = <16>; 241 status = "disabled"; 242 }; 243 244 spi20: spi@c6000 { 245 /* 246 * This spi node can be either SPIM or SPIS, 247 * for the user to pick: 248 * compatible = "nordic,nrf-spim" or 249 * "nordic,nrf-spis". 250 */ 251 compatible = "nordic,nrf-spim"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0xc6000 0x1000>; 255 interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; 256 max-frequency = <DT_FREQ_M(8)>; 257 easydma-maxcnt-bits = <16>; 258 rx-delay-supported; 259 rx-delay = <1>; 260 status = "disabled"; 261 }; 262 263 uart20: uart@c6000 { 264 compatible = "nordic,nrf-uarte"; 265 reg = <0xc6000 0x1000>; 266 interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; 267 status = "disabled"; 268 }; 269 270 i2c21: i2c@c7000 { 271 compatible = "nordic,nrf-twim"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0xc7000 0x1000>; 275 clock-frequency = <I2C_BITRATE_STANDARD>; 276 interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; 277 easydma-maxcnt-bits = <16>; 278 status = "disabled"; 279 }; 280 281 spi21: spi@c7000 { 282 /* 283 * This spi node can be either SPIM or SPIS, 284 * for the user to pick: 285 * compatible = "nordic,nrf-spim" or 286 * "nordic,nrf-spis". 287 */ 288 compatible = "nordic,nrf-spim"; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0xc7000 0x1000>; 292 interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; 293 max-frequency = <DT_FREQ_M(8)>; 294 easydma-maxcnt-bits = <16>; 295 rx-delay-supported; 296 rx-delay = <1>; 297 status = "disabled"; 298 }; 299 300 uart21: uart@c7000 { 301 compatible = "nordic,nrf-uarte"; 302 reg = <0xc7000 0x1000>; 303 interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; 304 status = "disabled"; 305 }; 306 307 i2c22: i2c@c8000 { 308 compatible = "nordic,nrf-twim"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0xc8000 0x1000>; 312 clock-frequency = <I2C_BITRATE_STANDARD>; 313 interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; 314 easydma-maxcnt-bits = <16>; 315 status = "disabled"; 316 }; 317 318 spi22: spi@c8000 { 319 /* 320 * This spi node can be either SPIM or SPIS, 321 * for the user to pick: 322 * compatible = "nordic,nrf-spim" or 323 * "nordic,nrf-spis". 324 */ 325 compatible = "nordic,nrf-spim"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 reg = <0xc8000 0x1000>; 329 interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; 330 max-frequency = <DT_FREQ_M(8)>; 331 easydma-maxcnt-bits = <16>; 332 rx-delay-supported; 333 rx-delay = <1>; 334 status = "disabled"; 335 }; 336 337 uart22: uart@c8000 { 338 compatible = "nordic,nrf-uarte"; 339 reg = <0xc8000 0x1000>; 340 interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; 341 status = "disabled"; 342 }; 343 344 egu20: egu@c9000 { 345 compatible = "nordic,nrf-egu"; 346 reg = <0xc9000 0x1000>; 347 interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>; 348 status = "disabled"; 349 }; 350 351 timer20: timer@ca000 { 352 compatible = "nordic,nrf-timer"; 353 status = "disabled"; 354 reg = <0xca000 0x1000>; 355 cc-num = <6>; 356 max-bit-width = <32>; 357 interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>; 358 prescaler = <0>; 359 }; 360 361 timer21: timer@cb000 { 362 compatible = "nordic,nrf-timer"; 363 status = "disabled"; 364 reg = <0xcb000 0x1000>; 365 cc-num = <6>; 366 max-bit-width = <32>; 367 interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>; 368 prescaler = <0>; 369 }; 370 371 timer22: timer@cc000 { 372 compatible = "nordic,nrf-timer"; 373 status = "disabled"; 374 reg = <0xcc000 0x1000>; 375 cc-num = <6>; 376 max-bit-width = <32>; 377 interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>; 378 prescaler = <0>; 379 }; 380 381 timer23: timer@cd000 { 382 compatible = "nordic,nrf-timer"; 383 status = "disabled"; 384 reg = <0xcd000 0x1000>; 385 cc-num = <6>; 386 max-bit-width = <32>; 387 interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>; 388 prescaler = <0>; 389 }; 390 391 timer24: timer@ce000 { 392 compatible = "nordic,nrf-timer"; 393 status = "disabled"; 394 reg = <0xce000 0x1000>; 395 cc-num = <6>; 396 max-bit-width = <32>; 397 interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>; 398 prescaler = <0>; 399 }; 400 401 pwm20: pwm@d2000 { 402 compatible = "nordic,nrf-pwm"; 403 status = "disabled"; 404 reg = <0xd2000 0x1000>; 405 interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>; 406 #pwm-cells = <3>; 407 }; 408 409 pwm21: pwm@d3000 { 410 compatible = "nordic,nrf-pwm"; 411 status = "disabled"; 412 reg = <0xd3000 0x1000>; 413 interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>; 414 #pwm-cells = <3>; 415 }; 416 417 pwm22: pwm@d4000 { 418 compatible = "nordic,nrf-pwm"; 419 status = "disabled"; 420 reg = <0xd4000 0x1000>; 421 interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; 422 #pwm-cells = <3>; 423 }; 424 425 adc: adc@d5000 { 426 compatible = "nordic,nrf-saadc"; 427 reg = <0xd5000 0x1000>; 428 interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>; 429 status = "disabled"; 430 #io-channel-cells = <1>; 431 }; 432 433 nfct: nfct@d6000 { 434 compatible = "nordic,nrf-nfct"; 435 reg = <0xd6000 0x1000>; 436 interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>; 437 status = "disabled"; 438 }; 439 440 temp: temp@d7000 { 441 compatible = "nordic,nrf-temp"; 442 reg = <0xd7000 0x1000>; 443 interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>; 444 status = "disabled"; 445 }; 446 447 gpio1: gpio@d8200 { 448 compatible = "nordic,nrf-gpio"; 449 gpio-controller; 450 reg = <0xd8200 0x300>; 451 #gpio-cells = <2>; 452 ngpios = <16>; 453 status = "disabled"; 454 port = <1>; 455 gpiote-instance = <&gpiote20>; 456 }; 457 458 gpiote20: gpiote@da000 { 459 compatible = "nordic,nrf-gpiote"; 460 reg = <0xda000 0x1000>; 461 status = "disabled"; 462 instance = <20>; 463 }; 464 465 i2s20: i2s@dd000 { 466 compatible = "nordic,nrf-i2s"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0xdd000 0x1000>; 470 interrupts = <221 NRF_DEFAULT_IRQ_PRIORITY>; 471 status = "disabled"; 472 }; 473 474 qdec20: qdec@e0000 { 475 compatible = "nordic,nrf-qdec"; 476 reg = <0xe0000 0x1000>; 477 interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>; 478 status = "disabled"; 479 }; 480 481 qdec21: qdec@e1000 { 482 compatible = "nordic,nrf-qdec"; 483 reg = <0xe1000 0x1000>; 484 interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>; 485 status = "disabled"; 486 }; 487 488 grtc: grtc@e2000 { 489 compatible = "nordic,nrf-grtc"; 490 reg = <0xe2000 0x1000>; 491 cc-num = <12>; 492 status = "disabled"; 493 }; 494 495 dppic30: dppic@102000 { 496 compatible = "nordic,nrf-dppic"; 497 reg = <0x102000 0x808>; 498 status = "disabled"; 499 }; 500 501 i2c30: i2c@104000 { 502 compatible = "nordic,nrf-twim"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <0x104000 0x1000>; 506 clock-frequency = <I2C_BITRATE_STANDARD>; 507 interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; 508 easydma-maxcnt-bits = <16>; 509 status = "disabled"; 510 }; 511 512 spi30: spi@104000 { 513 /* 514 * This spi node can be either SPIM or SPIS, 515 * for the user to pick: 516 * compatible = "nordic,nrf-spim" or 517 * "nordic,nrf-spis". 518 */ 519 compatible = "nordic,nrf-spim"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 reg = <0x104000 0x1000>; 523 interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; 524 max-frequency = <DT_FREQ_M(8)>; 525 easydma-maxcnt-bits = <16>; 526 rx-delay-supported; 527 rx-delay = <1>; 528 status = "disabled"; 529 }; 530 531 uart30: uart@104000 { 532 compatible = "nordic,nrf-uarte"; 533 reg = <0x104000 0x1000>; 534 interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; 535 status = "disabled"; 536 }; 537 538#ifdef USE_NON_SECURE_ADDRESS_MAP 539 /* intentionally empty because WDT30 is hardware fixed to Secure */ 540#else 541 wdt30: watchdog@108000 { 542 compatible = "nordic,nrf-wdt"; 543 reg = <0x108000 0x620>; 544 interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>; 545 status = "disabled"; 546 }; 547#endif 548 549 wdt31: watchdog@109000 { 550 compatible = "nordic,nrf-wdt"; 551 reg = <0x109000 0x620>; 552 interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>; 553 status = "disabled"; 554 }; 555 556 gpio0: gpio@10a000 { 557 compatible = "nordic,nrf-gpio"; 558 gpio-controller; 559 reg = <0x10a000 0x300>; 560 #gpio-cells = <2>; 561 ngpios = <5>; 562 status = "disabled"; 563 port = <0>; 564 gpiote-instance = <&gpiote30>; 565 }; 566 567 gpiote30: gpiote@10c000 { 568 compatible = "nordic,nrf-gpiote"; 569 reg = <0x10c000 0x1000>; 570 status = "disabled"; 571 instance = <30>; 572 }; 573 574 clock: clock@10e000 { 575 compatible = "nordic,nrf-clock"; 576 reg = <0x10e000 0x1000>; 577 interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>; 578 status = "disabled"; 579 }; 580 }; 581 582 rram_controller: rram-controller@5004b000 { 583 compatible = "nordic,rram-controller"; 584 reg = <0x5004b000 0x1000>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>; 588 589 cpuapp_rram: rram@0 { 590 compatible = "soc-nv-flash"; 591 reg = <0x0 DT_SIZE_K(1428)>; 592 erase-block-size = <4096>; 593 write-block-size = <16>; 594 }; 595 cpuflpr_rram: rram@165000 { 596 compatible = "soc-nv-flash"; 597 reg = <0x165000 DT_SIZE_K(96)>; 598 erase-block-size = <4096>; 599 write-block-size = <16>; 600 }; 601 }; 602 603 cpuapp_ppb: cpuapp-ppb-bus { 604 #address-cells = <1>; 605 #size-cells = <1>; 606 607 cpuapp_nvic: interrupt-controller@e000e100 { 608 #address-cells = <1>; 609 compatible = "arm,v8m-nvic"; 610 reg = <0xe000e100 0xc00>; 611 arm,num-irq-priority-bits = <3>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 cpuapp_systick: timer@e000e010 { 617 compatible = "arm,armv8m-systick"; 618 reg = <0xe000e010 0x10>; 619 status = "disabled"; 620 }; 621 }; 622 }; 623}; 624
