1 /* dw_i2c.h - header for Design Ware I2C operations */ 2 3 /* 4 * Copyright (c) 2015 Intel Corporation 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 #ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_H_ 9 #define ZEPHYR_DRIVERS_I2C_I2C_DW_H_ 10 11 #include <zephyr/drivers/i2c.h> 12 #include <stdbool.h> 13 14 #define DT_DRV_COMPAT snps_designware_i2c 15 16 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) 17 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE"); 18 #include <zephyr/drivers/pcie/pcie.h> 19 #endif 20 21 #if defined(CONFIG_RESET) 22 #include <zephyr/drivers/reset.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define I2C_DW_MAGIC_KEY 0x44570140 30 31 32 typedef void (*i2c_isr_cb_t)(const struct device *port); 33 34 35 #define IC_ACTIVITY (1 << 0) 36 #define IC_ENABLE_BIT (1 << 0) 37 38 39 /* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */ 40 #define I2C_DW_STATE_READY (0) 41 #define I2C_DW_CMD_SEND (1 << 0) 42 #define I2C_DW_CMD_RECV (1 << 1) 43 #define I2C_DW_CMD_ERROR (1 << 2) 44 #define I2C_DW_BUSY (1 << 3) 45 46 47 #define DW_ENABLE_TX_INT_I2C_MASTER (DW_INTR_STAT_TX_OVER | \ 48 DW_INTR_STAT_TX_EMPTY | \ 49 DW_INTR_STAT_TX_ABRT | \ 50 DW_INTR_STAT_STOP_DET) 51 #define DW_ENABLE_RX_INT_I2C_MASTER (DW_INTR_STAT_RX_UNDER | \ 52 DW_INTR_STAT_RX_OVER | \ 53 DW_INTR_STAT_RX_FULL | \ 54 DW_INTR_STAT_STOP_DET) 55 56 #define DW_ENABLE_TX_INT_I2C_SLAVE (DW_INTR_STAT_RD_REQ | \ 57 DW_INTR_STAT_TX_ABRT | \ 58 DW_INTR_STAT_STOP_DET) 59 #define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | \ 60 DW_INTR_STAT_STOP_DET) 61 62 #define DW_DISABLE_ALL_I2C_INT 0x00000000 63 64 65 /* IC_CON Low count and high count default values */ 66 /* TODO verify values for high and fast speed */ 67 #define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4) 68 #define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5) 69 #define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) 70 #define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) 71 #define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) 72 #define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) 73 74 /* 75 * DesignWare speed values don't directly translate from the Zephyr speed 76 * selections in include/i2c.h so here we do a little translation 77 */ 78 #define I2C_DW_SPEED_STANDARD 0x1 79 #define I2C_DW_SPEED_FAST 0x2 80 #define I2C_DW_SPEED_FAST_PLUS 0x2 81 #define I2C_DW_SPEED_HIGH 0x3 82 83 84 /* 85 * These values have been randomly selected. It would be good to test different 86 * watermark levels for performance capabilities 87 */ 88 #define I2C_DW_TX_WATERMARK 2 89 #define I2C_DW_RX_WATERMARK 7 90 91 92 struct i2c_dw_rom_config { 93 DEVICE_MMIO_ROM; 94 i2c_isr_cb_t config_func; 95 uint32_t bitrate; 96 97 #if defined(CONFIG_PINCTRL) 98 const struct pinctrl_dev_config *pcfg; 99 #endif 100 #if defined(CONFIG_RESET) 101 const struct reset_dt_spec reset; 102 #endif 103 104 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) 105 struct pcie_dev *pcie; 106 #endif /* I2C_DW_PCIE_ENABLED */ 107 108 #ifdef CONFIG_I2C_DW_LPSS_DMA 109 const struct device *dma_dev; 110 #endif 111 }; 112 113 struct i2c_dw_dev_config { 114 DEVICE_MMIO_RAM; 115 struct k_sem device_sync_sem; 116 struct k_mutex bus_mutex; 117 uint32_t app_config; 118 119 uint8_t *xfr_buf; 120 uint32_t xfr_len; 121 uint32_t rx_pending; 122 123 uint16_t hcnt; 124 uint16_t lcnt; 125 126 volatile uint8_t state; /* last direction of transfer */ 127 uint8_t request_bytes; 128 uint8_t xfr_flags; 129 bool support_hs_mode; 130 #ifdef CONFIG_I2C_DW_LPSS_DMA 131 uintptr_t phy_addr; 132 uintptr_t base_addr; 133 /* For dma transfer */ 134 bool xfr_status; 135 #endif 136 137 struct i2c_target_config *slave_cfg; 138 }; 139 140 #define Z_REG_READ(__sz) sys_read##__sz 141 #define Z_REG_WRITE(__sz) sys_write##__sz 142 #define Z_REG_SET_BIT sys_set_bit 143 #define Z_REG_CLEAR_BIT sys_clear_bit 144 #define Z_REG_TEST_BIT sys_test_bit 145 146 #define DEFINE_MM_REG_READ(__reg, __off, __sz) \ 147 static inline uint32_t read_##__reg(uint32_t addr) \ 148 { \ 149 return Z_REG_READ(__sz)(addr + __off); \ 150 } 151 #define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ 152 static inline void write_##__reg(uint32_t data, uint32_t addr) \ 153 { \ 154 Z_REG_WRITE(__sz)(data, addr + __off); \ 155 } 156 157 #define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \ 158 static inline void set_bit_##__reg_bit(uint32_t addr) \ 159 { \ 160 Z_REG_SET_BIT(addr + __reg_off, __bit); \ 161 } 162 163 #define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \ 164 static inline void clear_bit_##__reg_bit(uint32_t addr) \ 165 { \ 166 Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \ 167 } 168 169 #define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \ 170 static inline int test_bit_##__reg_bit(uint32_t addr) \ 171 { \ 172 return Z_REG_TEST_BIT(addr + __reg_off, __bit); \ 173 } 174 175 #ifdef __cplusplus 176 } 177 #endif 178 179 #endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_H_ */ 180
