1 /* 2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: LCD Configuration Register */ 14 /** Type of lcd_clock register 15 * LCD clock register 16 */ 17 typedef union { 18 struct { 19 /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; 20 * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. 21 */ 22 uint32_t lcd_clkcnt_n: 6; 23 /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; 24 * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). 25 */ 26 uint32_t lcd_clk_equ_sysclk: 1; 27 /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; 28 * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. 29 */ 30 uint32_t lcd_ck_idle_edge: 1; 31 /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; 32 * 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock 33 * cycle. 34 */ 35 uint32_t lcd_ck_out_edge: 1; 36 /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; 37 * Integral LCD clock divider value 38 */ 39 uint32_t lcd_clkm_div_num: 8; 40 /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; 41 * Fractional clock divider numerator value 42 */ 43 uint32_t lcd_clkm_div_b: 6; 44 /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; 45 * Fractional clock divider denominator value 46 */ 47 uint32_t lcd_clkm_div_a: 6; 48 /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; 49 * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. 50 */ 51 uint32_t lcd_clk_sel: 2; 52 /** clk_en : R/W; bitpos: [31]; default: 0; 53 * Set this bit to enable clk gate 54 */ 55 uint32_t clk_en: 1; 56 }; 57 uint32_t val; 58 } lcd_cam_lcd_clock_reg_t; 59 60 /** Type of lcd_rgb_yuv register 61 * LCD configuration register 62 */ 63 typedef union { 64 struct { 65 uint32_t reserved_0: 20; 66 /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; 67 * 1:invert every two 8bits input data. 2. disabled. 68 */ 69 uint32_t lcd_conv_8bits_data_inv: 1; 70 /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; 71 * 0: txtorx mode off. 1: txtorx mode on. 72 */ 73 uint32_t lcd_conv_txtorx: 1; 74 /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; 75 * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, 76 * trans_mode must be set to 1. 77 */ 78 uint32_t lcd_conv_yuv2yuv_mode: 2; 79 /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; 80 * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv 81 * mode of Data_in 82 */ 83 uint32_t lcd_conv_yuv_mode: 2; 84 /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; 85 * 0:BT601. 1:BT709. 86 */ 87 uint32_t lcd_conv_protocol_mode: 1; 88 /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; 89 * LIMIT or FULL mode of Data out. 0: limit. 1: full 90 */ 91 uint32_t lcd_conv_data_out_mode: 1; 92 /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; 93 * LIMIT or FULL mode of Data in. 0: limit. 1: full 94 */ 95 uint32_t lcd_conv_data_in_mode: 1; 96 /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; 97 * 0: 16bits mode. 1: 8bits mode. 98 */ 99 uint32_t lcd_conv_mode_8bits_on: 1; 100 /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; 101 * 0: YUV to RGB. 1: RGB to YUV. 102 */ 103 uint32_t lcd_conv_trans_mode: 1; 104 /** lcd_conv_bypass : R/W; bitpos: [31]; default: 0; 105 * 0: Bypass converter. 1: Enable converter. 106 */ 107 uint32_t lcd_conv_bypass: 1; 108 }; 109 uint32_t val; 110 } lcd_cam_lcd_rgb_yuv_reg_t; 111 112 /** Type of lcd_user register 113 * LCD configuration register 114 */ 115 typedef union { 116 struct { 117 /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; 118 * The output data cycles minus 1 of LCD module. 119 */ 120 uint32_t lcd_dout_cyclelen: 13; 121 /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; 122 * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or 123 * reg_lcd_reset is set. 124 */ 125 uint32_t lcd_always_out_en: 1; 126 uint32_t reserved_14: 5; 127 /** lcd_8bits_order : R/W; bitpos: [19]; default: 0; 128 * 1: invert every two data byte, valid in 1 byte mode. 0: Not change. 129 */ 130 uint32_t lcd_8bits_order: 1; 131 /** lcd_update_reg : R/W; bitpos: [20]; default: 0; 132 * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. 133 */ 134 uint32_t lcd_update: 1; 135 /** lcd_bit_order : R/W; bitpos: [21]; default: 0; 136 * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte 137 * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. 138 */ 139 uint32_t lcd_bit_order: 1; 140 /** lcd_byte_order : R/W; bitpos: [22]; default: 0; 141 * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. 142 */ 143 uint32_t lcd_byte_order: 1; 144 /** lcd_2byte_en : R/W; bitpos: [23]; default: 0; 145 * 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data 146 * is 0~8. 147 */ 148 uint32_t lcd_2byte_en: 1; 149 /** lcd_dout : R/W; bitpos: [24]; default: 0; 150 * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. 151 */ 152 uint32_t lcd_dout: 1; 153 /** lcd_dummy : R/W; bitpos: [25]; default: 0; 154 * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. 155 */ 156 uint32_t lcd_dummy: 1; 157 /** lcd_cmd : R/W; bitpos: [26]; default: 0; 158 * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. 159 */ 160 uint32_t lcd_cmd: 1; 161 /** lcd_start : R/W; bitpos: [27]; default: 0; 162 * LCD start sending data enable signal, valid in high level. 163 */ 164 uint32_t lcd_start: 1; 165 /** lcd_reset : WO; bitpos: [28]; default: 0; 166 * The value of command. 167 */ 168 uint32_t lcd_reset: 1; 169 /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; 170 * The dummy cycle length minus 1. 171 */ 172 uint32_t lcd_dummy_cyclelen: 2; 173 /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; 174 * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. 175 */ 176 uint32_t lcd_cmd_2_cycle_en: 1; 177 }; 178 uint32_t val; 179 } lcd_cam_lcd_user_reg_t; 180 181 /** Type of lcd_misc register 182 * LCD configuration register 183 */ 184 typedef union { 185 struct { 186 uint32_t reserved_0: 1; 187 /** lcd_afifo_threshold_num : R/W; bitpos: [5:1]; default: 11; 188 * The awfull threshold number of lcd_afifo. 189 */ 190 uint32_t lcd_afifo_threshold_num: 5; 191 /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; 192 * The setup cycle length minus 1 in LCD non-RGB mode. 193 */ 194 uint32_t lcd_vfk_cyclelen: 6; 195 /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; 196 * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold 197 * time cycle length in LCD non-RGB mode. 198 */ 199 uint32_t lcd_vbk_cyclelen: 13; 200 /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; 201 * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when 202 * the current frame is sent out. 203 */ 204 uint32_t lcd_next_frame_en: 1; 205 /** lcd_bk_en : R/W; bitpos: [26]; default: 0; 206 * 1: Enable blank region when LCD sends data out. 0: No blank region. 207 */ 208 uint32_t lcd_bk_en: 1; 209 /** lcd_afifo_reset : WO; bitpos: [27]; default: 0; 210 * LCD AFIFO reset signal. 211 */ 212 uint32_t lcd_afifo_reset: 1; 213 /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; 214 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = 215 * reg_cd_idle_edge. 216 */ 217 uint32_t lcd_cd_data_set: 1; 218 /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; 219 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = 220 * reg_cd_idle_edge. 221 */ 222 uint32_t lcd_cd_dummy_set: 1; 223 /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; 224 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = 225 * reg_cd_idle_edge. 226 */ 227 uint32_t lcd_cd_cmd_set: 1; 228 /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; 229 * The default value of LCD_CD. 230 */ 231 uint32_t lcd_cd_idle_edge: 1; 232 }; 233 uint32_t val; 234 } lcd_cam_lcd_misc_reg_t; 235 236 /** Type of lcd_ctrl register 237 * LCD configuration register 238 */ 239 typedef union { 240 struct { 241 /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; 242 * It is the horizontal blank front porch of a frame. 243 */ 244 uint32_t lcd_hb_front: 11; 245 /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; 246 * It is the vertical active height of a frame. 247 */ 248 uint32_t lcd_va_height: 10; 249 /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; 250 * It is the vertical total height of a frame. 251 */ 252 uint32_t lcd_vt_height: 10; 253 /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; 254 * 1: Enable reg mode input vsync, hsync, de. 0: Disable. 255 */ 256 uint32_t lcd_rgb_mode_en: 1; 257 }; 258 uint32_t val; 259 } lcd_cam_lcd_ctrl_reg_t; 260 261 /** Type of lcd_ctrl1 register 262 * LCD configuration register 263 */ 264 typedef union { 265 struct { 266 /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; 267 * It is the vertical blank front porch of a frame. 268 */ 269 uint32_t lcd_vb_front: 8; 270 /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; 271 * It is the horizontal active width of a frame. 272 */ 273 uint32_t lcd_ha_width: 12; 274 /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; 275 * It is the horizontal total width of a frame. 276 */ 277 uint32_t lcd_ht_width: 12; 278 }; 279 uint32_t val; 280 } lcd_cam_lcd_ctrl1_reg_t; 281 282 /** Type of lcd_ctrl2 register 283 * LCD configuration register 284 */ 285 typedef union { 286 struct { 287 /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; 288 * It is the position of LCD_VSYNC active pulse in a line. 289 */ 290 uint32_t lcd_vsync_width: 7; 291 /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; 292 * It is the idle value of LCD_VSYNC. 293 */ 294 uint32_t lcd_vsync_idle_pol: 1; 295 /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; 296 * It is the idle value of LCD_DE. 297 */ 298 uint32_t lcd_de_idle_pol: 1; 299 /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; 300 * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC 301 * pulse is valid only in active region lines in RGB mode. 302 */ 303 uint32_t lcd_hs_blank_en: 1; 304 uint32_t reserved_10: 6; 305 /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; 306 * It is the position of LCD_HSYNC active pulse in a line. 307 */ 308 uint32_t lcd_hsync_width: 7; 309 /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; 310 * It is the idle value of LCD_HSYNC. 311 */ 312 uint32_t lcd_hsync_idle_pol: 1; 313 /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; 314 * It is the position of LCD_HSYNC active pulse in a line. 315 */ 316 uint32_t lcd_hsync_position: 8; 317 }; 318 uint32_t val; 319 } lcd_cam_lcd_ctrl2_reg_t; 320 321 /** Type of lcd_cmd_val register 322 * LCD configuration register 323 */ 324 typedef union { 325 struct { 326 /** lcd_cmd_value : R/W; bitpos: [31:0]; default: 0; 327 * The LCD write command value. 328 */ 329 uint32_t lcd_cmd_value: 32; 330 }; 331 uint32_t val; 332 } lcd_cam_lcd_cmd_val_reg_t; 333 334 /** Type of lcd_dly_mode register 335 * LCD configuration register 336 */ 337 typedef union { 338 struct { 339 /** lcd_cd_mode : R/W; bitpos: [1:0]; default: 0; 340 * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: 341 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 342 */ 343 uint32_t lcd_cd_mode: 2; 344 /** lcd_de_mode : R/W; bitpos: [3:2]; default: 0; 345 * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: 346 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 347 */ 348 uint32_t lcd_de_mode: 2; 349 /** lcd_hsync_mode : R/W; bitpos: [5:4]; default: 0; 350 * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 351 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 352 */ 353 uint32_t lcd_hsync_mode: 2; 354 /** lcd_vsync_mode : R/W; bitpos: [7:6]; default: 0; 355 * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 356 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 357 */ 358 uint32_t lcd_vsync_mode: 2; 359 uint32_t reserved_8: 24; 360 }; 361 uint32_t val; 362 } lcd_cam_lcd_dly_mode_reg_t; 363 364 /** Type of lcd_data_dout_mode register 365 * LCD configuration register 366 */ 367 typedef union { 368 struct { 369 /** dout0_mode : R/W; bitpos: [1:0]; default: 0; 370 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 371 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 372 * LCD_CLK. 373 */ 374 uint32_t dout0_mode: 2; 375 /** dout1_mode : R/W; bitpos: [3:2]; default: 0; 376 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 377 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 378 * LCD_CLK. 379 */ 380 uint32_t dout1_mode: 2; 381 /** dout2_mode : R/W; bitpos: [5:4]; default: 0; 382 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 383 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 384 * LCD_CLK. 385 */ 386 uint32_t dout2_mode: 2; 387 /** dout3_mode : R/W; bitpos: [7:6]; default: 0; 388 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 389 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 390 * LCD_CLK. 391 */ 392 uint32_t dout3_mode: 2; 393 /** dout4_mode : R/W; bitpos: [9:8]; default: 0; 394 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 395 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 396 * LCD_CLK. 397 */ 398 uint32_t dout4_mode: 2; 399 /** dout5_mode : R/W; bitpos: [11:10]; default: 0; 400 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 401 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 402 * LCD_CLK. 403 */ 404 uint32_t dout5_mode: 2; 405 /** dout6_mode : R/W; bitpos: [13:12]; default: 0; 406 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 407 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 408 * LCD_CLK. 409 */ 410 uint32_t dout6_mode: 2; 411 /** dout7_mode : R/W; bitpos: [15:14]; default: 0; 412 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 413 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 414 * LCD_CLK. 415 */ 416 uint32_t dout7_mode: 2; 417 /** dout8_mode : R/W; bitpos: [17:16]; default: 0; 418 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 419 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 420 * LCD_CLK. 421 */ 422 uint32_t dout8_mode: 2; 423 /** dout9_mode : R/W; bitpos: [19:18]; default: 0; 424 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 425 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 426 * LCD_CLK. 427 */ 428 uint32_t dout9_mode: 2; 429 /** dout10_mode : R/W; bitpos: [21:20]; default: 0; 430 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 431 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 432 * LCD_CLK. 433 */ 434 uint32_t dout10_mode: 2; 435 /** dout11_mode : R/W; bitpos: [23:22]; default: 0; 436 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 437 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 438 * LCD_CLK. 439 */ 440 uint32_t dout11_mode: 2; 441 /** dout12_mode : R/W; bitpos: [25:24]; default: 0; 442 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 443 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 444 * LCD_CLK. 445 */ 446 uint32_t dout12_mode: 2; 447 /** dout13_mode : R/W; bitpos: [27:26]; default: 0; 448 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 449 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 450 * LCD_CLK. 451 */ 452 uint32_t dout13_mode: 2; 453 /** dout14_mode : R/W; bitpos: [29:28]; default: 0; 454 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 455 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 456 * LCD_CLK. 457 */ 458 uint32_t dout14_mode: 2; 459 /** dout15_mode : R/W; bitpos: [31:30]; default: 0; 460 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 461 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 462 * LCD_CLK. 463 */ 464 uint32_t dout15_mode: 2; 465 }; 466 uint32_t val; 467 } lcd_cam_lcd_data_dout_mode_reg_t; 468 469 470 /** Group: Camera Configuration Register */ 471 /** Type of cam_ctrl register 472 * Camera configuration register 473 */ 474 typedef union { 475 struct { 476 /** cam_stop_en : R/W; bitpos: [0]; default: 0; 477 * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. 478 */ 479 uint32_t cam_stop_en: 1; 480 /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; 481 * Filter threshold value for CAM_VSYNC signal. 482 */ 483 uint32_t cam_vsync_filter_thres: 3; 484 /** cam_update_reg : R/W; bitpos: [4]; default: 0; 485 * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. 486 */ 487 uint32_t cam_update: 1; 488 /** cam_byte_order : R/W; bitpos: [5]; default: 0; 489 * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte 490 * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. 491 */ 492 uint32_t cam_byte_order: 1; 493 /** cam_bit_order : R/W; bitpos: [6]; default: 0; 494 * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. 495 */ 496 uint32_t cam_bit_order: 1; 497 /** cam_line_int_en : R/W; bitpos: [7]; default: 0; 498 * 1: Enable to generate CAM_HS_INT. 0: Disable. 499 */ 500 uint32_t cam_line_int_en: 1; 501 /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; 502 * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by 503 * reg_cam_rec_data_cyclelen. 504 */ 505 uint32_t cam_vs_eof_en: 1; 506 /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; 507 * Integral Camera clock divider value 508 */ 509 uint32_t cam_clkm_div_num: 8; 510 /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; 511 * Fractional clock divider numerator value 512 */ 513 uint32_t cam_clkm_div_b: 6; 514 /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; 515 * Fractional clock divider denominator value 516 */ 517 uint32_t cam_clkm_div_a: 6; 518 /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; 519 * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. 520 */ 521 uint32_t cam_clk_sel: 2; 522 uint32_t reserved_31: 1; 523 }; 524 uint32_t val; 525 } lcd_cam_cam_ctrl_reg_t; 526 527 /** Type of cam_ctrl1 register 528 * Camera configuration register 529 */ 530 typedef union { 531 struct { 532 /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; 533 * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. 534 */ 535 uint32_t cam_rec_data_bytelen: 16; 536 /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; 537 * The line number minus 1 to generate cam_hs_int. 538 */ 539 uint32_t cam_line_int_num: 6; 540 /** cam_clk_inv : R/W; bitpos: [22]; default: 0; 541 * 1: Invert the input signal CAM_PCLK. 0: Not invert. 542 */ 543 uint32_t cam_clk_inv: 1; 544 /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; 545 * 1: Enable CAM_VSYNC filter function. 0: bypass. 546 */ 547 uint32_t cam_vsync_filter_en: 1; 548 /** cam_2byte_en : R/W; bitpos: [24]; default: 0; 549 * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. 550 */ 551 uint32_t cam_2byte_en: 1; 552 /** cam_de_inv : R/W; bitpos: [25]; default: 0; 553 * CAM_DE invert enable signal, valid in high level. 554 */ 555 uint32_t cam_de_inv: 1; 556 /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; 557 * CAM_HSYNC invert enable signal, valid in high level. 558 */ 559 uint32_t cam_hsync_inv: 1; 560 /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; 561 * CAM_VSYNC invert enable signal, valid in high level. 562 */ 563 uint32_t cam_vsync_inv: 1; 564 /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; 565 * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control 566 * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. 567 */ 568 uint32_t cam_vh_de_mode_en: 1; 569 /** cam_start : R/W; bitpos: [29]; default: 0; 570 * Camera module start signal. 571 */ 572 uint32_t cam_start: 1; 573 /** cam_reset : WO; bitpos: [30]; default: 0; 574 * Camera module reset signal. 575 */ 576 uint32_t cam_reset: 1; 577 /** cam_afifo_reset : WO; bitpos: [31]; default: 0; 578 * Camera AFIFO reset signal. 579 */ 580 uint32_t cam_afifo_reset: 1; 581 }; 582 uint32_t val; 583 } lcd_cam_cam_ctrl1_reg_t; 584 585 /** Type of cam_rgb_yuv register 586 * Camera configuration register 587 */ 588 typedef union { 589 struct { 590 uint32_t reserved_0: 21; 591 /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; 592 * 1:invert every two 8bits input data. 2. disabled. 593 */ 594 uint32_t cam_conv_8bits_data_inv: 1; 595 /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; 596 * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, 597 * trans_mode must be set to 1. 598 */ 599 uint32_t cam_conv_yuv2yuv_mode: 2; 600 /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; 601 * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv 602 * mode of Data_in 603 */ 604 uint32_t cam_conv_yuv_mode: 2; 605 /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; 606 * 0:BT601. 1:BT709. 607 */ 608 uint32_t cam_conv_protocol_mode: 1; 609 /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; 610 * LIMIT or FULL mode of Data out. 0: limit. 1: full 611 */ 612 uint32_t cam_conv_data_out_mode: 1; 613 /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; 614 * LIMIT or FULL mode of Data in. 0: limit. 1: full 615 */ 616 uint32_t cam_conv_data_in_mode: 1; 617 /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; 618 * 0: 16bits mode. 1: 8bits mode. 619 */ 620 uint32_t cam_conv_mode_8bits_on: 1; 621 /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; 622 * 0: YUV to RGB. 1: RGB to YUV. 623 */ 624 uint32_t cam_conv_trans_mode: 1; 625 /** cam_conv_bypass : R/W; bitpos: [31]; default: 0; 626 * 0: Bypass converter. 1: Enable converter. 627 */ 628 uint32_t cam_conv_bypass: 1; 629 }; 630 uint32_t val; 631 } lcd_cam_cam_rgb_yuv_reg_t; 632 633 634 /** Group: Interrupt Register */ 635 /** Type of lc_dma_int_ena register 636 * LCD_camera DMA inturrupt enable register 637 */ 638 typedef union { 639 struct { 640 /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; 641 * The enable bit for LCD frame end interrupt. 642 */ 643 uint32_t lcd_vsync_int_ena: 1; 644 /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; 645 * The enable bit for lcd transfer end interrupt. 646 */ 647 uint32_t lcd_trans_done_int_ena: 1; 648 /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; 649 * The enable bit for Camera frame end interrupt. 650 */ 651 uint32_t cam_vsync_int_ena: 1; 652 /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; 653 * The enable bit for Camera line interrupt. 654 */ 655 uint32_t cam_hs_int_ena: 1; 656 uint32_t reserved_4: 28; 657 }; 658 uint32_t val; 659 } lcd_cam_lc_dma_int_ena_reg_t; 660 661 /** Type of lc_dma_int_raw register 662 * LCD_camera DMA raw inturrupt status register 663 */ 664 typedef union { 665 struct { 666 /** lcd_vsync_int_raw : RO; bitpos: [0]; default: 0; 667 * The raw bit for LCD frame end interrupt. 668 */ 669 uint32_t lcd_vsync_int_raw: 1; 670 /** lcd_trans_done_int_raw : RO; bitpos: [1]; default: 0; 671 * The raw bit for lcd transfer end interrupt. 672 */ 673 uint32_t lcd_trans_done_int_raw: 1; 674 /** cam_vsync_int_raw : RO; bitpos: [2]; default: 0; 675 * The raw bit for Camera frame end interrupt. 676 */ 677 uint32_t cam_vsync_int_raw: 1; 678 /** cam_hs_int_raw : RO; bitpos: [3]; default: 0; 679 * The raw bit for Camera line interrupt. 680 */ 681 uint32_t cam_hs_int_raw: 1; 682 uint32_t reserved_4: 28; 683 }; 684 uint32_t val; 685 } lcd_cam_lc_dma_int_raw_reg_t; 686 687 /** Type of lc_dma_int_st register 688 * LCD_camera DMA masked inturrupt status register 689 */ 690 typedef union { 691 struct { 692 /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; 693 * The status bit for LCD frame end interrupt. 694 */ 695 uint32_t lcd_vsync_int_st: 1; 696 /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; 697 * The status bit for lcd transfer end interrupt. 698 */ 699 uint32_t lcd_trans_done_int_st: 1; 700 /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; 701 * The status bit for Camera frame end interrupt. 702 */ 703 uint32_t cam_vsync_int_st: 1; 704 /** cam_hs_int_st : RO; bitpos: [3]; default: 0; 705 * The status bit for Camera transfer end interrupt. 706 */ 707 uint32_t cam_hs_int_st: 1; 708 uint32_t reserved_4: 28; 709 }; 710 uint32_t val; 711 } lcd_cam_lc_dma_int_st_reg_t; 712 713 /** Type of lc_dma_int_clr register 714 * LCD_camera DMA inturrupt clear register 715 */ 716 typedef union { 717 struct { 718 /** lcd_vsync_int_clr : WO; bitpos: [0]; default: 0; 719 * The clear bit for LCD frame end interrupt. 720 */ 721 uint32_t lcd_vsync_int_clr: 1; 722 /** lcd_trans_done_int_clr : WO; bitpos: [1]; default: 0; 723 * The clear bit for lcd transfer end interrupt. 724 */ 725 uint32_t lcd_trans_done_int_clr: 1; 726 /** cam_vsync_int_clr : WO; bitpos: [2]; default: 0; 727 * The clear bit for Camera frame end interrupt. 728 */ 729 uint32_t cam_vsync_int_clr: 1; 730 /** cam_hs_int_clr : WO; bitpos: [3]; default: 0; 731 * The clear bit for Camera line interrupt. 732 */ 733 uint32_t cam_hs_int_clr: 1; 734 uint32_t reserved_4: 28; 735 }; 736 uint32_t val; 737 } lcd_cam_lc_dma_int_clr_reg_t; 738 739 740 /** Group: Version Register */ 741 /** Type of lc_reg_date register 742 * Version register 743 */ 744 typedef union { 745 struct { 746 /** lc_date : R/W; bitpos: [27:0]; default: 33566752; 747 * LCD_CAM version control register 748 */ 749 uint32_t lc_date: 28; 750 uint32_t reserved_28: 4; 751 }; 752 uint32_t val; 753 } lcd_cam_lc_reg_date_reg_t; 754 755 756 typedef struct lcd_cam_dev_t { 757 volatile lcd_cam_lcd_clock_reg_t lcd_clock; 758 volatile lcd_cam_cam_ctrl_reg_t cam_ctrl; 759 volatile lcd_cam_cam_ctrl1_reg_t cam_ctrl1; 760 volatile lcd_cam_cam_rgb_yuv_reg_t cam_rgb_yuv; 761 volatile lcd_cam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; 762 volatile lcd_cam_lcd_user_reg_t lcd_user; 763 volatile lcd_cam_lcd_misc_reg_t lcd_misc; 764 volatile lcd_cam_lcd_ctrl_reg_t lcd_ctrl; 765 volatile lcd_cam_lcd_ctrl1_reg_t lcd_ctrl1; 766 volatile lcd_cam_lcd_ctrl2_reg_t lcd_ctrl2; 767 volatile lcd_cam_lcd_cmd_val_reg_t lcd_cmd_val; 768 uint32_t reserved_02c; 769 volatile lcd_cam_lcd_dly_mode_reg_t lcd_dly_mode; 770 uint32_t reserved_034; 771 volatile lcd_cam_lcd_data_dout_mode_reg_t lcd_data_dout_mode; 772 uint32_t reserved_03c[10]; 773 volatile lcd_cam_lc_dma_int_ena_reg_t lc_dma_int_ena; 774 volatile lcd_cam_lc_dma_int_raw_reg_t lc_dma_int_raw; 775 volatile lcd_cam_lc_dma_int_st_reg_t lc_dma_int_st; 776 volatile lcd_cam_lc_dma_int_clr_reg_t lc_dma_int_clr; 777 uint32_t reserved_074[34]; 778 volatile lcd_cam_lc_reg_date_reg_t lc_reg_date; 779 } lcd_cam_dev_t; 780 781 #ifndef __cplusplus 782 _Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcd_cam_dev_t structure"); 783 #endif 784 785 extern lcd_cam_dev_t LCD_CAM; 786 787 #ifdef __cplusplus 788 } 789 #endif 790
