1 /******************************************************************************* 2 * @file rsi_ipmu.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 /** 31 * Includes 32 */ 33 #ifndef __RSI_IPMU_H__ 34 #define __RSI_IPMU_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define AT_EFUSE_DATA_1P19 41 #include "rsi_ccp_common.h" 42 #include "rsi_error.h" 43 44 /****************************************************** 45 * * Macros 46 * ******************************************************/ 47 #define RET_LDO_VOL_DECREASE 1 48 #define RET_LDO_TRIM_VALUE_CHECK 2 49 50 #define REG_GSPI_BASE 0x24050000 51 #define NPSS_BASE_ADDR 0x24048000 52 #define NPSS_NWP_BASE_ADDR 0x41300000 53 #define MCURET_BOOTSTATUS (volatile uint32_t *)(NPSS_BASE_ADDR + 0x604) 54 #define MCU_BBFF_STORAGE1_ADDR (volatile uint32_t *)(NPSS_NWP_BASE_ADDR + 0x580) 55 #define TA_MANF_DATA_BASE_ADDR 0x04000000 56 #define MCU_MANF_DATA_BASE_ADDR 0x08000000 57 #define TA_FLASH 1 58 59 /*IPMU power gates */ 60 #define CMP_NPSS_PG_ENB BIT(16) /*Power gate enable for BOD CORE*/ 61 #define ULP_ANG_CLKS_PG_ENB BIT(15) /*Power gate enable for CLKS CORE*/ 62 #define ULP_ANG_PWRSUPPLY_PG_ENB BIT(14) /*Power gate enable for BG SPI*/ 63 #define WURX_PG_ENB BIT(13) /*Power gate enable for WURX*/ 64 #define WURX_CORR_PG_ENB BIT(12) /*Power gate enable for WURX CORRELATION BLOCK*/ 65 #define AUXADC_PG_ENB BIT(11) /*Power gate enable for AUXADC*/ 66 #define AUXADC_BYPASS_ISO_GEN BIT(10) /*power gate bypass for AUXADC*/ 67 #define AUXADC_ISOLATION_ENABLE BIT(9) /*power gate isolation for AUXADC*/ 68 #define AUXDAC_PG_ENB BIT(8) /*Power gate enable for AUXDAC*/ 69 #define AUXDAC_BYPASS_ISO_GEN BIT(7) /*power gate bypass for AUXDAC*/ 70 #define AUXDAC_ISOLATION_ENABLE BIT(6) /*power gate isolation for AUXDAC*/ 71 #define AUX_SUPPLY_ISOLATION_ENABLE BIT(5) /*Given to analog peripherals indicating the supply state*/ 72 #define PMU_ANA_BYPASS_PWRGATE_EN_N BIT(4) /*To ON or OFF analog blocks in PMU when pwr manager is bypassed*/ 73 #define PMU_SPI_BYPASS_ISO_GEN BIT(3) /*Bypass power manager for PMU_SPI*/ 74 #define PMU_SPI_ISOLATION_ENABLE BIT(2) /*Bypass isoaltion enable signal for PMU_SPI isoaltion cells*/ 75 #define PMU_BUCK_BYPASS_ISO_GEN BIT(1) /*Bypass power manager for PMU BUCK*/ 76 #define PMU_BUCK_BYPASS_ISOLATION_ENABLE BIT(0) /*Bypass isoaltion enable signal for PMU_BUCK isoaltion cells*/ 77 78 /*IPMU configuration defines*/ 79 #define LATCH_TOP_SPI BIT(4) 80 #define LATCH_TRANSPARENT_HF BIT(3) 81 #define LATCH_TRANSPARENT_LF BIT(2) 82 83 /*BG_SCDC_PROG_REG_1 defines*/ 84 #define REF_SEL_LP_DCDC 0xFFFFFC7F 85 86 /*Registers */ 87 #define BG_SCDC_PROG_REG_1 0x127 88 #define SELECT_BG_CLK 0x144 89 #define BG_SCDC_PROG_REG_2 0x128 90 //#define WURX_CORR_CALIB_REG 0x088 91 #define POWERGATE_REG_WRITE 0x142 92 //#define ULPCLKS_REFCLK_REG 0x106 93 //#define WURX_CORR_CALIB_REG 0x088 94 95 #define GSPI_CTRL_REG1 *(volatile uint32_t *)(REG_GSPI_BASE + 0x02) 96 #define SPI_ACTIVE BIT(8) 97 98 #define POSITION_BITS_MASK 0x1F 99 #define LSB_POSITION 22 100 #define MSB_POSITION 27 101 #define MAX_BIT_LEN 22 102 103 #define ULPCLKS_32KRC_CLK_REG_ADDR 0x103 104 105 #define ENABLE_CALIB_DOMAIN 0x005200 106 #define SELECT_RO_CALIB 0x002310 107 #define TRIM_VALUE_BITS 0x0003f800 108 #define MASK_TRIM_VALUE_WRITE_BITS 0x1FC000 109 #define ULPCLKS_TRIM_SEL_REG_DEFAULT 0x005a14 110 111 #define MAX_RESP_BUF_FOR_IAP 3 112 113 #define BASE_OFFSET_BB_RF_IN_FLASH 424 114 115 #define PMU_SPI_BASE_ADDR 0x24050000 116 117 //! PMU 118 #define PMU_SPI_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0x8000 + ((_x) << 2)) 119 //! IPMU 120 #define PMU_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xA000 + ((_x) << 2)) 121 #define PMU_SPI 1 122 123 #define RC_CLK_MODE 1 124 125 #define XTAL_SEL 1 126 127 #define TS_SLOPE_SET_OFFSET 0x04 128 #define PMU_1P3_CTRL_REG_OFFSET 0x1D0 129 #define PMU_PFM_REG_OFFSET 0x1D1 130 #define PMU_ADC_REG_OFFSET 0x1D2 131 #define PMU_PID_REG1_OFFSET 0x1D3 132 #define PMU_PTAT_REG_OFFSET 0x1D5 133 #define PMU_LDO_REG_OFFSET 0x1D6 134 #define PMU_PWRTRAIN_REG_OFFSET 0x1D8 135 #define PMU_TESTMUX_REG1_OFFSET 0x1D9 136 #define PMU_TEST_MODES_OFFSET 0x1DA 137 #define SPARE_REG_1_OFFSET 0x1DC 138 #define SPARE_REG_2_OFFSET 0x1DD 139 #define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE 140 #define SPARE_REG_3_OFFSET 0x1DF 141 142 #ifdef CHIP_9118 143 //FLASH OFFSET 144 #define __CALIB_DATA_OFFSET_ 1024 145 #define IPMU_VALUES_OFFSET (__CALIB_DATA_OFFSET_ + 168) 146 #define DUAL_FLASH_IPMU_VALUES_OFFSET MCU_MANF_DATA_BASE_ADDR 147 #endif 148 149 #if defined(SLI_SI917) || defined(SLI_SI915) 150 #if (((defined SLI_SI917 || defined SLI_SI915) && (defined SLI_SI917B0 || defined SLI_SI915)) \ 151 || (defined CHIP_917_6x6 && (defined SLI_SI917B0 || defined SLI_SI915))) 152 #ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE 153 #define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x8160292 154 #define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x8160293 155 #define COMMON_FLASH_IPMU_VALUES_OFFSET 0x8160258 156 #else 157 #define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x81F0292 158 #define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x81F0293 159 #define COMMON_FLASH_IPMU_VALUES_OFFSET 0x81F0258 160 #endif 161 #define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x800059B 162 #define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x800059C 163 #define DUAL_FLASH_IPMU_VALUES_OFFSET 0x8000561 164 #endif 165 #if ((defined SLI_SI917) && (!(defined SLI_SI917B0))) 166 #define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x82001DE 167 #define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x82001DF 168 #define COMMON_FLASH_IPMU_VALUES_OFFSET 0x82001A4 169 #define COMMON_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(COMMON_FLASH_IPMU_VALUES_OFFSET)) 170 171 #define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x80004E0 172 #define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x80004E1 173 #define DUAL_FLASH_IPMU_VALUES_OFFSET 0x80004A6 174 #define DUAL_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(DUAL_FLASH_IPMU_VALUES_OFFSET)) 175 #endif 176 #define IPMU_VALUES_OFFSET 0 177 #endif 178 #define HP_LDO_MODE 1 179 #define SCDC_MODE 0 180 #ifdef ENABLE_1P8V 181 #define IPMU_MODE_VALUE HP_LDO_MODE 182 #else 183 #define IPMU_MODE_VALUE SCDC_MODE 184 #endif 185 186 #ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE 187 #define MANF_DATA_BASE_ADDR COMMON_FLASH_IPMU_VALUES_OFFSET 188 #else 189 #define MANF_DATA_BASE_ADDR DUAL_FLASH_IPMU_VALUES_OFFSET 190 #endif 191 192 /* After changes */ 193 #define MAGIC_WORD 0x5a 194 195 #define NWP_AHB_ADDR 0x41300000 196 #define ULP_TASS_MISC_CONFIG_REG 0x24041400 197 #define AUX_BASE_ADDR 0x24043800 198 #define TEMP_SENSOR_BASE_ADDRESS 0x24048500 199 #define TS_NOMINAL_SETTINGS_OFFSET 0x08 200 #define DIRECT 2 201 202 #define MASK_BITS(A, B) (((1U << A) - 1) << B) 203 #define ULP_SPI 0 204 #define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 205 #define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 206 #define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 207 #define ULPCLKS_MRC_CLK_REG_OFFSET 0x104 208 #define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 209 #define ULPCLKS_REFCLK_REG_ADDR 0x106 210 #define ULPCLKS_TRIM_SEL_REG_ADDR 0x107 211 #define ULPCLKS_CALIB_REG_ADDR 0x10A 212 #define ULPCLKS_CALIB_REF_REG 0x10B 213 #define ULPCLKS_CALIB_DONE_REG_ADDR 0x10C 214 #define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E 215 #define BG_SCDC_PROG_REG_1_OFFSET 0x127 216 #define iPMU_SPARE_REG1_OFFSET 0x140 217 #if defined(SLI_SI917) || defined(SLI_SI915) 218 #define BG_SCDC_PROG_REG_3_ADDR 0x12B 219 #endif 220 221 #define HF_RC_CLK_MODE 1 222 #define MCU_PWR_CTRL_BASE_ADDR 0x24048400 223 #define MCU_PMU_LDO_CTRL_CLEAR_REG_1 *(volatile uint32 *)(MCU_PWR_CTRL_BASE_ADDR + 0x6C) 224 #define TEMP_SENSOR_BASE_ADDRESS 0x24048500 225 #define MCU_FSM_BASE_ADDRESS 0x24048100 226 227 //! ULP SPI (0x2405A000) 228 #define ULPCLKS_ADAPTIVE_REG_OFFSET 0x100 229 #define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 230 #define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 231 #define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 232 #define ULPCLKS_MRC_CLK_REG_OFFSET 0x104 233 #define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 234 #define ULPCLKS_REF_CLK_REG_OFFSET 0x106 235 #define ULPCLKS_TRIM_SEL_REG_OFFSET 0x107 236 #define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E 237 #define BG_SLEEP_TIMER_REG_OFFSET 0x125 238 #define SCDC_CTRL_REG_0_OFFSET 0x126 239 #define BG_SCDC_PROG_REG_1_OFFSET 0x127 240 #define BG_SCDC_PROG_REG_2_OFFSET 0x128 241 #define BG_LDO_REG_OFFSET 0x129 242 #define BG_SCDC_READ_BACK_OFFSET 0x12A 243 #define BG_BLACKOUT_REG_OFFSET 0x12B 244 #define iPMU_SPARE_REG1_OFFSET 0x140 245 #define iPMU_SPARE_REG2_OFFSET 0x141 246 #define POWERGATE_REG_WRITE_OFFSET 0x142 247 #define SELECT_BG_CLK_OFFSET 0x144 248 #define BOD_TEST_PG_VBATT_STATUS_REG_OFFSET 0x1E3 249 #define POWERGATE_REG_READ_OFFSET 0x342 250 251 //! PMU SPI (0x24058000) 252 #define PMU_1P3_CTRL_REG_OFFSET 0x1D0 253 #define PMU_PFM_REG_OFFSET 0x1D1 254 #define PMU_ADC_REG_OFFSET 0x1D2 255 #define PMU_PID_REG1_OFFSET 0x1D3 256 #define PMU_PTAT_REG_OFFSET 0x1D5 257 #define PMU_LDO_REG_OFFSET 0x1D6 258 #define PMU_PWRTRAIN_REG_OFFSET 0x1D8 259 #define PMU_TESTMUX_REG1_OFFSET 0x1D9 260 #define PMU_TEST_MODES_OFFSET 0x1DA 261 #define SPARE_REG_1_OFFSET 0x1DC 262 #define SPARE_REG_2_OFFSET 0x1DD 263 #define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE 264 #define SPARE_REG_3_OFFSET 0x1DF 265 #define PMU_FREQ_MODE_REG 0x1CE 266 #define LOW_FREQ_PWM BIT(2) 267 #define MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_OFFSET 0x20 268 #define MCU_FSM_PMU_STATUS_REG_OFFSET 0x40 269 270 //! NWP_PMU_CTRLS defines 271 #define scdcdc_lp_mode_en BIT(0) 272 #define bgpmu_sleep_en BIT(1) 273 #define standby_dc1p3 BIT(19) 274 275 #define MCU_AON_BASE_ADDR 0x24048000 276 #define MCU_FSM_PMU_CTRL *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x140) 277 #define MCUAON_GEN_CTRLS_REG *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x14) 278 #define MCUAON_SHELF_MODE *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x10) 279 280 //! MCUAON_GEN_CTRLS register defines 281 #define NPSS_SUPPLY_0P9_BIT BIT(17) 282 #define ENABLE_PDO_BIT BIT(16) 283 284 #define NWP_AHB_ADDR 0x41300000 285 #define ULP_DIRECT_ACCESS(_x) *(uint32 *)(NWP_AHB_ADDR + (_x)) 286 #define NWPAON_POR_CTRL_BITS_REG 0x3C 287 #define NWP_FSM_FIRST_BOOTUP 0x0120 288 289 //! NWP_FSM_FIRST_BOOTUP defines 290 #define nwp_ulp_32khz_xtal_clk_en BIT(18) 291 #define nwp_ulp_mhz_rc_clk_en BIT(19) 292 #define nwp_ulp_20mhz_ring_osc_clk_en BIT(20) 293 #define nwp_ulp_doubler_clk_en BIT(21) 294 295 #define TASS_PWR_CTRL_BASE_ADDR 0x41300400 296 #define TASS_FSM_CTRL_BYPASS *(volatile uint32 *)(TASS_PWR_CTRL_BASE_ADDR + 0x1C) 297 //! TASS_FSM_CTRL_BYPASS defines 298 #define ta_xtal_en_40MHz_bypass_cntrl BIT(0) 299 #define ta_xtal_en_40MHz_bypass BIT(1) 300 #define ta_pmu_shut_down_bypass_cntrl BIT(2) 301 #define ta_pmu_shut_down_bypass BIT(3) 302 #define ta_buck_boost_enable_bypass_cntrl BIT(4) 303 #define ta_buck_boost_enable_bypass BIT(5) 304 305 //! ULPCLKS_ADAPTIVE_REG defines 306 #define adapt_powergate_en BIT(3) 307 308 //! ULPCLKS_DOUBLER_XTAL_REG defines 309 #define doubler_en BIT(21) 310 311 //! ULPCLKS_32MRC_CLK_REG defines 312 #define rc_mhz_en BIT(21) 313 314 //! ULPCLKS_HF_RO_CLK_REG defines 315 #define ro_hf_en BIT(21) 316 317 //! ULPCLKS_TRIM_SEL_REG defines 318 #define calib_powergate_en BIT(9) 319 320 //! ULPCLKS_32KXTAL_CLK_REG defines 321 #define xtal_32khz_en BIT(21) 322 323 #define pass_clk_40m_buffer_enable BIT(15) 324 325 //! iPMU_SPARE_REG2 defines 326 #define wurx_lvl_shift_en BIT(20) 327 #define wurx_pg_en_1 BIT(21) 328 329 //! POWERGATE_REG_WRITE defines 330 #define auxdac_pg_enb BIT(8) 331 #define auxadc_pg_enb BIT(11) 332 #define wurx_corr_pg_enb BIT(12) 333 #define wurx_pg_enb BIT(13) 334 #define ulp_ang_pwrsupply_pg_enb BIT(14) 335 #define ulp_ang_clks_pg_enb BIT(15) 336 #define cmp_npss_pg_enb BIT(16) 337 338 #define IPMU_HIGH_POWER_MODE 0 339 #define IPMU_LOW_POWER_MODE 1 340 341 //! SELECT_BG_CLK defines 342 #define latch_transparent_lf BIT(2) 343 #define latch_transparent_hf BIT(3) 344 #define latch_top_spi BIT(4) 345 346 //! PMU_PFM_REG defines 347 #define ext_pfm_en1p3 BIT(17) 348 349 //! PMU_PTAT_REG defines 350 #define test_pfm_mode1p3 BIT(4) 351 352 //! PMU_LDO_REG defines 353 #define LDOSOC_DEFAULT_MODE_EN BIT(5) 354 355 //! PMU_PWRTRAIN_REG defines 356 #define BYPASS_LDORF_CTRL BIT(2) 357 358 //! BOD_TEST_PG_VBATT_STATUS_REG defines 359 #define bod_pwrgate_en_n_ulp_button_calib BIT(15) 360 361 //! MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP defines 362 #define mcu_ulp_32khz_xtal_clk_en BIT(18) 363 #define mcu_ulp_mhz_rc_clk_en BIT(19) 364 #define mcu_ulp_20mhz_ring_osc_clk_en BIT(20) 365 #define mcu_ulp_doubler_clk_en BIT(21) 366 367 //! NWPAON_POR_CTRL_BITS defines 368 #define poc_cntrl_reg_0 BIT(0) 369 370 #define MCU_FSM_DIRECT_ACCESS(_x) *(volatile uint32 *)(MCU_FSM_BASE_ADDRESS + (_x)) 371 372 #define TEMP_SENSOR_BJT *(volatile uint32 *)(0x240439E0) 373 #define temp_sens_en BIT(0) 374 375 #define TS_SLOPE_SET_OFFSET 0x04 376 #define TS_NOMINAL_SETTINGS_OFFSET 0x08 377 378 //! BG_SCDC_PROG_REG_2 defines 379 #define scdcdc_sel BIT(21) 380 #define testmode_0_en BIT(20) 381 382 //! SCDC_CTRL_REG_0 defines 383 #define ext_cap_en BIT(21) 384 385 //! PMU_LDO_REG defines 386 #define LDORF_DEFAULT_MODE_EN BIT(11) 387 388 #define LS_SHIFT 22 389 #define MS_SHIFT 27 390 #define IPMU_DATAMASK 0x3fffff 391 392 #define mcu_dcdc_lvl BIT(18) 393 #define mcu_soc_ldo_lvl BIT(17) 394 395 /*32khz rc clock define */ 396 #define RC_TRIM_VALUE_LF 0x7F0 397 #define RO_TRIM_VALUE_LF 0x1F0 398 #define MASK32KRO_TRIM_VALUE_WRITE_BITS 0x1F0000 399 #define MASK32KRC_TRIM_VALUE_WRITE_BITS 0x1FC000 400 #define TRIM_MSB_MHZ 20 401 #define TRIM_LSB_MHZ 14 402 #define PARTICULAR_FREQ_MIN 10 403 #define PARTICULAR_FREQ_MAX 100 404 #define MIN_DIFF_FREQ 3 405 406 /* 64khz rc clock define */ 407 #define ENABLE_32KHZ_CLOCK_TRIM 0x40F03000 408 #define NPSS_REF_CLOCK_40MSOC 0x41A48000 409 #define NUMBER_HIGH_FRQ_CLOCK 0x42C4E390 410 #define LOW_FREQ_CLOCK_CAL 0x42B24210 411 #define ORIGINAL_REF_VALUE_AFTER_CAL 0x42C9C590 412 413 /****************************************************** 414 * * Structures 415 * ******************************************************/ 416 417 //! This structure contains format for retention_boot_status_word_0 418 typedef struct retention_boot_status_word_s { 419 #define SDIO_USB_WITH_TA 3 420 #define SDIO_WITH_TA_USB_WITH_M4 2 421 #define SDIO_WITH_M4_USB_WITH_TA 1 422 #define SDIO_USB_WITH_M4 0 423 unsigned int m4_present : 1; 424 unsigned int m4_flash_present : 1; 425 unsigned int m4_flash_pinset : 4; 426 unsigned int m4_flash_address_width_valid : 1; 427 unsigned int m4_flash_address_width : 2; 428 unsigned int select_host_inf_with_m4_valid : 1; 429 unsigned int select_host_inf_with_m4 : 2; 430 unsigned int m4_secure_boot_enable : 1; 431 unsigned int m4_encrypt_firmware : 1; 432 unsigned int host_if_with_ta : 1; 433 unsigned int mcu_wdt_hw_timer : 1; 434 #ifdef CHIP_9118 435 #define NONE_MODE 0 436 #define NLINK 1 437 #define WISECONNECT 2 438 #define WCPLUS 3 439 #define MCU 4 440 #define WISEMCU 5 441 #define ACCELARATOR 6 442 #define WC_SIMULATANEOUS 7 443 #endif 444 #if defined(SLI_SI917) || defined(SLI_SI915) 445 //! Product modes 446 #define WISEMCU 0 447 #define WCPLUS 3 448 #define ACCELARATOR 4 449 #define WISECONNECT 6 450 #define NLINK 7 451 #define MCU 0xF // not supported 452 #endif 453 unsigned int product_mode : 4; 454 unsigned int m4_flash_type : 4; 455 unsigned int m4_dual_flash : 1; 456 unsigned int m4_csum : 1; 457 unsigned int wise_aoc_mode : 1; 458 unsigned int wise_aoc_from_m4_rom : 1; 459 unsigned int m4_image_format : 1; 460 unsigned int clean_ulp_wakeup : 1; 461 #define M4_IMAGE_VALID_IND BIT(30) 462 unsigned int m4_image_valid : 1; 463 unsigned int reserved : 1; /* one bit is reserved for hardware */ 464 } retention_boot_status_word_t; 465 466 /* This structure contains format for efuse_dword0 */ 467 typedef struct npss_boot_status_word_0_s { 468 //! Data from EFUSE 469 unsigned int usb_fsel_valid : 1; 470 unsigned int mems_ref_clk_as_usb_phy_clk : 1; 471 unsigned int modem_pll_as_usb_phy_clk : 1; 472 unsigned int usb_phy_clk_fsel_external : 1; 473 unsigned int usb_fsel : 3; 474 unsigned int bypass_usb_detection : 1; 475 //! Data derived by bootloder 476 unsigned int host_sel_valid : 1; 477 unsigned int host_sel : 3; 478 unsigned int ta_flash_present : 1; 479 unsigned int ta_flash_pinset : 4; 480 unsigned int ta_flash_address_width_valid : 1; 481 unsigned int ta_flash_address_width : 2; 482 unsigned int ta_flash_type : 4; 483 unsigned int fips_enable : 1; 484 unsigned int usb_fclk_div_factor : 2; 485 #define BBFF_DATA_VALID BIT(27) 486 unsigned int bbff_data_valid : 1; 487 //! Bits configured by FW 488 #define NWP_SOFT_RESET BIT(28) 489 unsigned int soft_reset : 1; 490 #define FACTORY_RESET BIT(29) 491 unsigned int factory_reset : 1; 492 #define TAMPER_RECOVERY BIT(30) 493 unsigned int tamper_recovery : 1; 494 unsigned int reserved : 1; 495 } npss_boot_status_word0_t; 496 497 #ifdef CHIP_9118 498 typedef struct efuse_ipmu_s { 499 unsigned int trim_0p5na1 : 1; 500 unsigned int trim_0p5na2 : 1; 501 unsigned int bg_r_vdd_ulp : 4; 502 unsigned int bg_r_ptat_vdd_ulp : 3; 503 unsigned int resbank_trim : 2; 504 unsigned int trim_sel : 7; 505 unsigned int del_2x_sel : 6; 506 unsigned int freq_trim : 5; 507 unsigned int coarse_trim_16k : 2; 508 unsigned int fine_trim_16k : 7; 509 unsigned int coarse_trim_64k : 2; 510 unsigned int fine_trim_64k : 7; 511 unsigned int coarse_trim_32k : 2; 512 unsigned int fine_trim_32k : 7; 513 unsigned int xtal1_trim_32k : 4; 514 unsigned int xtal2_trim_32k : 4; 515 unsigned int trim_ring_osc : 7; 516 unsigned int vbatt_status_1 : 6; 517 unsigned int str_temp_slope : 10; 518 unsigned int f2_nominal : 10; 519 unsigned int str_nominal_temp : 7; 520 unsigned int str_bjt_temp_sense_off : 16; 521 unsigned int str_bjt_temp_sense_slope : 16; 522 #ifndef AT_EFUSE_DATA_1P19 523 unsigned int reserved1 : 20; 524 #endif 525 526 #ifdef AT_EFUSE_DATA_1P19 527 unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc 528 unsigned int ro_32khz_00_trim : 5; 529 unsigned int scdc_dcdc_trim : 3; 530 unsigned int scdc_hpldo_trim : 3; 531 unsigned int reserved1 : 2; 532 #endif 533 unsigned int ldo_ctrl : 4; 534 #ifndef AT_EFUSE_DATA_1P19 535 unsigned int reserved2 : 16; 536 #endif 537 #ifdef AT_EFUSE_DATA_1P19 538 unsigned int vbg_tsbjt_efuse : 12; 539 unsigned int retn_ldo_lptrim : 3; 540 unsigned int reserved2 : 1; 541 #endif 542 unsigned int auxadc_offset_diff : 12; 543 unsigned int auxadc_invgain_diff : 16; 544 unsigned int auxadc_offset_single : 12; 545 unsigned int auxadc_invgain_single : 16; 546 unsigned int set_vref1p3 : 4; 547 548 #ifndef AT_EFUSE_DATA_1P19 549 unsigned int set_vref_isense1p3 : 2; 550 unsigned int set_vref_adc : 2; 551 unsigned int vtrim_ldosoc : 2; 552 #endif 553 554 #ifdef AT_EFUSE_DATA_1P19 555 unsigned int reserved13 : 6; 556 #endif 557 558 unsigned int trim_r1_resistorladder : 4; 559 #ifndef AT_EFUSE_DATA_1P19 560 unsigned int enable_undershoot_reduction : 1; 561 unsigned int select_vref_comp : 2; 562 #endif 563 564 #ifdef AT_EFUSE_DATA_1P19 565 unsigned int retn_ldo_hptrim : 3; 566 #endif 567 568 #ifndef AT_EFUSE_DATA_1P19 569 unsigned int pwr_gd_threshold_sel : 1; 570 unsigned int sel_overshoot_control : 1; 571 unsigned int ptat_load_ctrl : 3; 572 unsigned int ctrl_soc : 4; 573 unsigned int pt_gate_ctrl : 3; 574 unsigned int default_mode_ctrl : 1; 575 unsigned int ptat_load_enable : 1; 576 unsigned int ldosoc_outputpulldown_sel : 1; 577 unsigned int ldosoc_outputpulldown : 1; 578 #endif 579 580 #ifdef AT_EFUSE_DATA_1P19 581 unsigned int reserved12 : 16; 582 #endif 583 584 unsigned int scale_soc_ldo_vref : 1; 585 586 #ifndef AT_EFUSE_DATA_1P19 587 unsigned int ctrl_rf : 4; 588 unsigned int default_mode : 1; 589 unsigned int test_ldopulldown_sel : 1; 590 unsigned int test_ldopulldown : 1; 591 unsigned int drive_n : 2; 592 unsigned int drive_p : 2; 593 unsigned int deadtime_ctrl_n2p : 4; 594 unsigned int deadtime_ctrl_p2n : 4; 595 unsigned int revi_offset_prog : 3; 596 unsigned int tran_lo_ctr : 2; 597 unsigned int tran_hi_ctr : 2; 598 unsigned int tran_und_shoot_ctr : 3; 599 #endif 600 601 #ifdef AT_EFUSE_DATA_1P19 602 unsigned int reserved11 : 7; 603 unsigned int reserved10 : 12; 604 unsigned int reserved9 : 10; 605 #endif 606 607 unsigned int dpwm_freq_trim : 4; 608 609 #ifndef AT_EFUSE_DATA_1P19 610 unsigned int pfmro_freq_trim : 3; 611 unsigned int test_revi_delay : 1; 612 unsigned int sel_sleep_nmos_ctrl : 1; 613 unsigned int p_1p3 : 13; 614 unsigned int i_steady_state1p3 : 13; 615 unsigned int d_1p3 : 15; 616 unsigned int i_soft_start1p3 : 13; 617 unsigned int dither_en1p3 : 1; 618 unsigned int auto_mode_tran_disable : 1; 619 #endif 620 621 #ifdef AT_EFUSE_DATA_1P19 622 unsigned int reserved73 : 1; 623 unsigned int reserved74 : 13; 624 unsigned int reserved75 : 13; 625 unsigned int reserved76 : 15; 626 unsigned int reserved77 : 13; 627 unsigned int reserved78 : 1; 628 unsigned int reserved79 : 1; 629 #endif 630 631 unsigned int pfm_pon_time_sel : 4; 632 633 #ifndef AT_EFUSE_DATA_1P19 634 unsigned int pfm_non_time_sel : 3; 635 unsigned int pwm_cont_prog : 3; 636 unsigned int pfm_clk_up_del_sel : 3; 637 unsigned int pwm_to_pfm_pulse_count_prog : 2; 638 unsigned int pfm_to_pwm_pulse_count_prog : 2; 639 unsigned int pfm_to_pwm_cur_prog : 3; 640 unsigned int pwm_to_pfm_cur_prog : 3; 641 unsigned int max_duty_cycle_threshold : 3; 642 unsigned int min_duty_cycle_threshold : 3; 643 unsigned int bypass_pfm_to_pwm_counter_1 : 1; 644 unsigned int no_of_pfm_clk : 4; 645 unsigned int adc_op_thresh_sel : 2; 646 #endif 647 648 #ifdef AT_EFUSE_DATA_1P19 649 unsigned int reserved6; 650 unsigned int reserved31 : 3; 651 unsigned int reserved32 : 3; 652 unsigned int reserved33 : 3; 653 unsigned int reserved34 : 2; 654 unsigned int reserved35 : 2; 655 unsigned int reserved36 : 3; 656 unsigned int reserved37 : 3; 657 unsigned int reserved38 : 3; 658 unsigned int reserved39 : 3; 659 unsigned int reserved40 : 1; 660 unsigned int reserved41 : 4; 661 unsigned int reserved42 : 2; 662 #endif 663 unsigned int reserved3 : 4; 664 unsigned int reserved4[2]; 665 uint16_t reserved5; 666 667 } __attribute__((__packed__)) efuse_ipmu_t; 668 #endif 669 670 #if defined(SLI_SI917) || defined(SLI_SI915) 671 typedef struct efuse_ipmu_s { 672 unsigned int trim_0p5na1 : 1; 673 unsigned int bg_r_vdd_ulp : 5; 674 unsigned int bg_r_ptat_vdd_ulp : 3; 675 unsigned int reserved20 : 2; //Removed in RS9117 676 unsigned int trim_sel : 7; 677 unsigned int del_2x_sel : 6; 678 unsigned int freq_trim : 5; 679 unsigned int coarse_trim_16k : 2; 680 unsigned int fine_trim_16k : 7; 681 unsigned int coarse_trim_64k : 2; 682 unsigned int fine_trim_64k : 7; 683 unsigned int coarse_trim_32k : 2; 684 unsigned int fine_trim_32k : 7; 685 unsigned int xtal1_trim_32k : 4; 686 unsigned int xtal2_trim_32k : 4; 687 unsigned int trim_ring_osc : 7; 688 unsigned int vbatt_status_1 : 6; 689 unsigned int str_temp_slope : 10; 690 unsigned int f2_nominal : 10; 691 unsigned int str_nominal_temp : 7; 692 unsigned int str_bjt_temp_sense_off : 16; 693 unsigned int str_bjt_temp_sense_slope : 16; 694 unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc 695 unsigned int ro_32khz_00_trim : 5; 696 unsigned int scdc_dcdc_trim : 3; 697 unsigned int scdc_hpldo_trim : 3; 698 unsigned int reserved1 : 2; 699 unsigned int ldo_ctrl : 4; 700 unsigned int vbg_tsbjt_efuse : 12; 701 unsigned int retn_ldo_lptrim : 3; 702 unsigned int reserved2 : 1; 703 unsigned int auxadc_offset_diff : 12; 704 unsigned int auxadc_invgain_diff : 16; 705 unsigned int auxadc_offset_single : 12; 706 unsigned int auxadc_invgain_single : 16; 707 unsigned int set_vref1p3 : 4; 708 unsigned int reserved13 : 6; 709 unsigned int trim_r1_resistorladder : 4; 710 unsigned int retn_ldo_hptrim : 3; 711 unsigned int reserved12 : 16; 712 unsigned int scale_soc_ldo_vref : 1; 713 unsigned int reserved11 : 7; 714 unsigned int reserved10 : 12; 715 unsigned int reserved9 : 10; 716 unsigned int dpwm_freq_trim : 4; 717 unsigned int reserved73 : 32; // 73 and 74 togther as 50 718 unsigned int reserved74 : 18; // 719 unsigned int scdc_clk_freq : 5; 720 unsigned int reserved7 : 6; 721 unsigned int buck_ind_efuse : 4; 722 unsigned int reserved31 : 32; // 31,32 and 33 togther as 80 723 unsigned int reserved32 : 32; 724 unsigned int reserved33 : 16; 725 } __attribute__((__packed__)) efuse_ipmu_t; 726 #endif 727 728 /* Clock trim APL structure */ 729 typedef enum INPUT_CLOCK { 730 ulp_ref_clk = 0, 731 ulp_20mhz_ringosc_clk = 2, 732 sleep_clk = 8, 733 soc_pll_clk = 6 734 735 } INPUT_CLOCK_T; 736 737 typedef enum SLEEP_CLOCK { khz_rc_clk = 0x0, khz_xtal_clk = 0x1, khz_ro_clk = 0x3, none = 0x233 } SLEEP_CLOCK_T; 738 739 /****************************************************** 740 * * Global Variables 741 * ******************************************************/ 742 743 /****************************************************** 744 * * Function Declarations 745 * ******************************************************/ 746 /** 747 * \ingroup RSI_SPECIFIC_DRIVERS 748 * \defgroup RSI_IPMU_DRIVERS RSI:RS1xxxx IPMU 749 * @{ 750 * 751 */ 752 rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void); 753 rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void); 754 uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void); 755 rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void); 756 rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void); 757 rsi_error_t RSI_IPMU_Buck_TrimEfuse(void); 758 rsi_error_t RSI_IPMU_POCbias_Efuse(void); 759 rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void); 760 rsi_error_t RSI_IPMU_Bg_TrimEfuse(void); 761 uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void); 762 uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void); 763 uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void); 764 uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void); 765 uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void); 766 uint32_t RSI_IPMU_RO_TsEfuse(void); 767 rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void); 768 rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void); 769 rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void); 770 rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void); 771 rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void); 772 rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void); 773 rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void); 774 rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void); 775 rsi_error_t RSI_IPMU_PMUCommonConfig(void); 776 rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void); 777 void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue); 778 void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue); 779 rsi_error_t RSI_IPMU_CommonConfig(void); 780 void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk); 781 uint32_t RSI_IPMU_32MHzClkClib(void); 782 rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config); 783 void RSI_IPMU_InitCalibData(void); 784 void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data); 785 uint32_t RSI_APB_ProgramConfigData(const uint32_t *config); 786 uint32_t RSI_IPMU_RO_TsConfig(void); 787 void RSI_Configure_DCDC_LowerVoltage(void); 788 void RSI_IPMU_32KHzRCClkClib(void); 789 void RSI_IPMU_32KHzROClkClib(void); 790 rsi_error_t RSI_IPMU_PocbiasCurrent11(void); 791 rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void); 792 rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void); 793 rsi_error_t RSI_IPMU_PocbiasCurrent(void); 794 void RSI_IPMU_RetnLdoHpmode(void); 795 void RSI_IPMU_RetnLdoLpmode(void); 796 void RSI_IPMU_Retn_Voltage_Reduction(void); 797 void RSI_IPMU_Retn_Voltage_To_Default(void); 798 void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void); 799 rsi_error_t RSI_IPMU_RetnLdo0p75(void); 800 rsi_error_t RSI_IPMU_RetnLdoVoltsel(void); 801 void RSI_IPMU_64KHZ_RCClktrim(void); 802 void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq); 803 uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type); 804 uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq); 805 void RSI_IPMU_SCDC_Enable(void); 806 void RSI_IPMU_HP_LDO_Enable(void); 807 void RSI_Ipmu_Init(void); 808 void RSI_Configure_Ipmu_Mode(void); 809 void ipmu_init(void); 810 void configure_ipmu_mode(uint32_t mode); 811 uint32_t init_ipmu_calib_data(uint32_t m4_present); 812 void update_ipmu_data(uint32_t reg_addr, uint32_t reg_type, uint32_t data, uint32_t mask); 813 void update_efuse_system_configs(int data, uint32_t config_ptr[]); 814 rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void); 815 rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void); 816 rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void); 817 rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void); 818 void RSI_IPMU_Reconfig_to_SCDCDC(void); 819 rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void); 820 rsi_error_t RSI_IPMU_BOD_Cmphyst(void); 821 /** 822 * @} end of RSI_IPMU_DRIVERS 823 */ 824 /* @} end of RSI_IPMU_DRIVERS */ 825 826 #ifdef __cplusplus 827 } 828 #endif 829 #endif // RSI_IPMU_H 830
