1 /*
2  * Copyright 2022-2024 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef FSL_VBAT_H_
9 #define FSL_VBAT_H_
10 
11 #include "fsl_common.h"
12 
13 /*!
14  * @addtogroup mcx_vbat
15  * @{
16  */
17 
18 /*******************************************************************************
19  * Definitions
20  ******************************************************************************/
21 
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief VBAT driver version 2.3.1. */
25 #define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
26 /*@}*/
27 
28 #if !defined(VBAT_LDORAMC_RET_MASK)
29 #define VBAT_LDORAMC_RET_MASK   (0xF00U)
30 #define VBAT_LDORAMC_RET_SHIFT  (8U)
31 #define VBAT_LDORAMC_RET(x)     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK)
32 #endif
33 
34 /*!
35  * @brief The enumeration of VBAT module status.
36  */
37 enum
38 {
39     kStatus_VBAT_Fro16kNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 0),      /*!< Internal 16kHz free running
40                                                                                  oscillator not enabled. */
41     kStatus_VBAT_BandgapNotEnabled     = MAKE_STATUS(kStatusGroup_VBAT, 1), /*!< Bandgap not enabled. */
42     kStatus_VBAT_WrongCapacitanceValue = MAKE_STATUS(kStatusGroup_VBAT, 2), /*!< Wrong capacitance for
43                                                                                 selected oscillator mode. */
44     kStatus_VBAT_ClockMonitorLocked = MAKE_STATUS(kStatusGroup_VBAT, 3),    /*!< Clock monitor locked. */
45     kStatus_VBAT_OSC32KNotReady     = MAKE_STATUS(kStatusGroup_VBAT, 4),    /*!< OSC32K not ready. */
46     kStatus_VBAT_LDONotReady        = MAKE_STATUS(kStatusGroup_VBAT, 5),    /*!< LDO not ready. */
47     kStatus_VBAT_TamperLocked       = MAKE_STATUS(kStatusGroup_VBAT, 6),    /*!< Tamper locked. */
48 };
49 
50 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG)
51 /*!
52  * @brief The enumeration of VBAT status flags.
53  *
54  * @anchor vbat_status_flag_t
55  */
56 enum _vbat_status_flag
57 {
58     kVBAT_StatusFlagPORDetect     = VBAT_STATUSA_POR_DET_MASK,     /*!< VBAT domain has been reset */
59     kVBAT_StatusFlagWakeupPin     = VBAT_STATUSA_WAKEUP_FLAG_MASK, /*!< A falling edge is detected on the wakeup pin. */
60     kVBAT_StatusFlagBandgapTimer0 = VBAT_STATUSA_TIMER0_FLAG_MASK, /*!< Bandgap Timer0 period reached. */
61     kVBAT_StatusFlagBandgapTimer1 = VBAT_STATUSA_TIMER1_FLAG_MASK, /*!< Bandgap Timer1 period reached. */
62     kVBAT_StatusFlagLdoReady      = VBAT_STATUSA_LDO_RDY_MASK,     /*!< LDO is enabled and ready. */
63     kVBAT_StatusFlagOsc32kReady   = VBAT_STATUSA_OSC_RDY_MASK,     /*!< OSC32k is enabled and clock is ready. */
64 #if defined(VBAT_STATUSA_CLOCK_DET_MASK)
65     kVBAT_StatusFlagClockDetect = VBAT_STATUSA_CLOCK_DET_MASK,   /*!< The clock monitor has detected an error. */
66 #endif                                                           /* VBAT_STATUSA_CLOCK_DET_MASK */
67     kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */
68 #if defined(VBAT_STATUSA_VOLT_DET_MASK)
69     kVBAT_StatusFlagVoltageDetect = VBAT_STATUSA_VOLT_DET_MASK, /*!< Voltage monitor has detected
70                                                                     an error with VBAT supply. */
71 #endif                                                          /* VBAT_STATUSA_VOLT_DET_MASK */
72 #if defined(VBAT_STATUSA_TEMP_DET_MASK)
73     kVBAT_StatusFlagTemperatureDetect = VBAT_STATUSA_TEMP_DET_MASK, /*!< Temperature monitor has detected an error. */
74 #endif                                                              /* VBAT_STATUSA_TEMP_DET_MASK */
75 #if defined(VBAT_STATUSA_SEC0_DET_MASK)
76     kVBAT_StatusFlagSec0Detect = VBAT_STATUSA_SEC0_DET_MASK,       /*!< Security input 0 has detected an error. */
77 #endif                                                             /* VBAT_STATUSA_SEC0_DET_MASK */
78     kVBAT_StatusFlagInterrupt0Detect = VBAT_STATUSA_IRQ0_DET_MASK, /*!< Interrupt 0 asserted. */
79     kVBAT_StatusFlagInterrupt1Detect = VBAT_STATUSA_IRQ1_DET_MASK, /*!< Interrupt 1 asserted. */
80     kVBAT_StatusFlagInterrupt2Detect = VBAT_STATUSA_IRQ2_DET_MASK, /*!< Interrupt 2 asserted. */
81     kVBAT_StatusFlagInterrupt3Detect = VBAT_STATUSA_IRQ3_DET_MASK, /*!< Interrupt 2 asserted. */
82 };
83 
84 /*!
85  * @brief The enumeration of VBAT interrupt enable.
86  *
87  * @anchor vbat_interrupt_enable_t
88  */
89 enum _vbat_interrupt_enable
90 {
91     kVBAT_InterruptEnablePORDetect = VBAT_IRQENA_POR_DET_MASK,         /*!< Enable POR detect interrupt. */
92     kVBAT_InterruptEnableWakeupPin = VBAT_IRQENA_WAKEUP_FLAG_MASK,     /*!< Enable the interrupt when a falling edge is
93                                                                            detected on the wakeup pin. */
94     kVBAT_InterruptEnableBandgapTimer0 = VBAT_IRQENA_TIMER0_FLAG_MASK, /*!< Enable the interrupt if Bandgap
95                                                                            Timer0 period reached. */
96     kVBAT_InterruptEnableBandgapTimer1 = VBAT_IRQENA_TIMER1_FLAG_MASK, /*!< Enable the interrupt if Bandgap
97                                                                            Timer1 period reached. */
98     kVBAT_InterruptEnableLdoReady    = VBAT_IRQENA_LDO_RDY_MASK,       /*!< Enable LDO ready interrupt. */
99     kVBAT_InterruptEnableOsc32kReady = VBAT_IRQENA_OSC_RDY_MASK,       /*!< Enable OSC32K ready interrupt. */
100 #if defined(VBAT_IRQENA_CLOCK_DET_MASK)
101     kVBAT_InterruptEnableClockDetect = VBAT_IRQENA_CLOCK_DET_MASK, /*!< Enable clock monitor detect interrupt. */
102 #endif                                                             /* VBAT_IRQENA_CLOCK_DET_MASK */
103     kVBAT_InterruptEnableConfigDetect =
104         VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */
105 #if defined(VBAT_IRQENA_VOLT_DET_MASK)
106     kVBAT_InterruptEnableVoltageDetect = VBAT_IRQENA_VOLT_DET_MASK, /*!< Enable voltage monitor detect interrupt. */
107 #endif                                                              /* VBAT_IRQENA_VOLT_DET_MASK */
108 #if defined(VBAT_IRQENA_TEMP_DET_MASK)
109     kVBAT_InterruptEnableTemperatureDetect = VBAT_IRQENA_TEMP_DET_MASK, /*!< Enable temperature monitor detect
110                                                                             interrupt. */
111 #endif                                                                  /* VBAT_IRQENA_TEMP_DET_MASK */
112 #if defined(VBAT_IRQENA_SEC0_DET_MASK)
113     kVBAT_InterruptEnableSec0Detect = VBAT_IRQENA_SEC0_DET_MASK, /*!< Enable security input 0 detect interrupt. */
114 #endif                                                           /* VBAT_IRQENA_SEC0_DET_MASK */
115     kVBAT_InterruptEnableInterrupt0 = VBAT_IRQENA_IRQ0_DET_MASK, /*!< Enable the interrupt0. */
116     kVBAT_InterruptEnableInterrupt1 = VBAT_IRQENA_IRQ1_DET_MASK, /*!< Enable the interrupt1. */
117     kVBAT_InterruptEnableInterrupt2 = VBAT_IRQENA_IRQ2_DET_MASK, /*!< Enable the interrupt2. */
118     kVBAT_InterruptEnableInterrupt3 = VBAT_IRQENA_IRQ3_DET_MASK, /*!< Enable the interrupt3. */
119 
120     kVBAT_AllInterruptsEnable =
121         (VBAT_IRQENA_POR_DET_MASK | VBAT_IRQENA_WAKEUP_FLAG_MASK | VBAT_IRQENA_TIMER0_FLAG_MASK |
122          VBAT_IRQENA_TIMER1_FLAG_MASK | VBAT_IRQENA_LDO_RDY_MASK | VBAT_IRQENA_OSC_RDY_MASK |
123          VBAT_IRQENA_CONFIG_DET_MASK | VBAT_IRQENA_IRQ0_DET_MASK | VBAT_IRQENA_IRQ1_DET_MASK |
124          VBAT_IRQENA_IRQ2_DET_MASK | VBAT_IRQENA_IRQ3_DET_MASK), /*!< Enable all interrupts. */
125 };
126 
127 /*!
128  * @brief The enumeration of VBAT wakeup enable.
129  *
130  * @anchor vbat_wakeup_enable_t
131  */
132 enum _vbat_wakeup_enable
133 {
134     kVBAT_WakeupEnablePORDetect = VBAT_WAKENA_POR_DET_MASK,         /*!< Enable POR detect wakeup. */
135     kVBAT_WakeupEnableWakeupPin = VBAT_WAKENA_WAKEUP_FLAG_MASK,     /*!< Enable wakeup feature when a falling edge is
136                                                                         detected on the wakeup pin. */
137     kVBAT_WakeupEnableBandgapTimer0 = VBAT_WAKENA_TIMER0_FLAG_MASK, /*!< Enable wakeup feature when bandgap
138                                                                         timer0 period reached. */
139     kVBAT_WakeupEnableBandgapTimer1 = VBAT_WAKENA_TIMER1_FLAG_MASK, /*!< Enable wakeup feature when bandgap
140                                                                         timer1 period reached. */
141     kVBAT_WakeupEnableLdoReady    = VBAT_WAKENA_LDO_RDY_MASK,       /*!< Enable wakeup when LDO ready. */
142     kVBAT_WakeupEnableOsc32kReady = VBAT_WAKENA_OSC_RDY_MASK,       /*!< Enable wakeup when OSC32k ready. */
143 #if defined(VBAT_WAKENA_CLOCK_DET_MASK)
144     kVBAT_WakeupEnableClockDetect =
145         VBAT_WAKENA_CLOCK_DET_MASK, /*!< Enable wakeup when clock monitor detect an error. */
146 #endif                              /* VBAT_WAKENA_CLOCK_DET_MASK */
147     kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when
148                                                                       configuration error detected. */
149 #if defined(VBAT_WAKENA_VOLT_DET_MASK)
150     kVBAT_WakeupEnableVoltageDetect = VBAT_WAKENA_VOLT_DET_MASK, /*!< Enable wakeup when voltage monitor detect an
151                                                                      error. */
152 #endif                                                           /* VBAT_WAKENA_VOLT_DET_MASK */
153 #if defined(VBAT_WAKENA_TEMP_DET_MASK)
154     kVBAT_WakeupEnableTemperatureDetect = VBAT_WAKENA_TEMP_DET_MASK, /*!< Enable wakeup when temperature monitor
155                                                                          detect an error. */
156 #endif                                                               /* VBAT_WAKENA_TEMP_DET_MASK */
157 #if defined(VBAT_WAKENA_SEC0_DET_MASK)
158     kVBAT_WakeupEnableSec0Detect = VBAT_WAKENA_SEC0_DET_MASK, /*!< Enable wakeup when security input 0 detect an
159                                                                   error. */
160 #endif                                                        /* VBAT_WAKENA_SEC0_DET_MASK */
161     kVBAT_WakeupEnableInterrupt0 = VBAT_WAKENA_IRQ0_DET_MASK, /*!< Enable wakeup when interrupt0 asserted. */
162     kVBAT_WakeupEnableInterrupt1 = VBAT_WAKENA_IRQ1_DET_MASK, /*!< Enable wakeup when interrupt1 asserted. */
163     kVBAT_WakeupEnableInterrupt2 = VBAT_WAKENA_IRQ2_DET_MASK, /*!< Enable wakeup when interrupt2 asserted. */
164     kVBAT_WakeupEnableInterrupt3 = VBAT_WAKENA_IRQ3_DET_MASK, /*!< Enable wakeup when interrupt3 asserted. */
165 
166     kVBAT_AllWakeupsEnable = (VBAT_WAKENA_POR_DET_MASK | VBAT_WAKENA_WAKEUP_FLAG_MASK | VBAT_WAKENA_TIMER0_FLAG_MASK |
167                               VBAT_WAKENA_TIMER1_FLAG_MASK | VBAT_WAKENA_LDO_RDY_MASK | VBAT_WAKENA_OSC_RDY_MASK |
168                               VBAT_WAKENA_CONFIG_DET_MASK | VBAT_WAKENA_IRQ0_DET_MASK | VBAT_WAKENA_IRQ1_DET_MASK |
169                               VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK
170 
171 #if defined(VBAT_WAKENA_CLOCK_DET_MASK)
172                               | VBAT_WAKENA_CLOCK_DET_MASK
173 
174 #endif /* VBAT_WAKENA_CLOCK_DET_MASK */
175 #if defined(VBAT_WAKENA_VOLT_DET_MASK)
176                               | VBAT_WAKENA_VOLT_DET_MASK
177 
178 #endif /* VBAT_WAKENA_VOLT_DET_MASK */
179 #if defined(VBAT_WAKENA_TEMP_DET_MASK)
180                               | VBAT_WAKENA_TEMP_DET_MASK
181 
182 #endif /* VBAT_WAKENA_TEMP_DET_MASK */
183 #if defined(VBAT_WAKENA_SEC0_DET_MASK)
184                               | VBAT_WAKENA_SEC0_DET_MASK
185 
186 #endif                           /* VBAT_WAKENA_SEC0_DET_MASK */
187                               ), /*!< Enable all wakeup. */
188 };
189 #endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */
190 
191 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG)
192 /*!
193  * @brief The enumeration of VBAT tamper enable.
194  */
195 enum _vbat_tamper_enable
196 {
197     kVBAT_TamperEnablePOR         = VBAT_TAMPERA_POR_DET_MASK, /*!< Enable tamper if POR asserted in STATUS register. */
198     kVBAT_TamperEnableClockDetect = VBAT_TAMPERA_CLOCK_DET_MASK, /*!< Enable tamper if clock monitor detect an error. */
199     kVBAT_TamperEnableConfigDetect =
200         VBAT_TAMPERA_CONFIG_DET_MASK,                             /*!< Enable tamper if configuration error detected. */
201     kVBAT_TamperEnableVoltageDetect = VBAT_TAMPERA_VOLT_DET_MASK, /*!< Enable tamper if voltage monitor detect an
202                                                                       error. */
203     kVBAT_TamperEnableTemperatureDetect = VBAT_TAMPERA_TEMP_DET_MASK, /*!< Enable tamper if temperature monitor
204                                                                           detect an error. */
205     kVBAT_TamperEnableSec0Detect = VBAT_TAMPERA_SEC0_DET_MASK,        /*!< Enable tamper if security input 0 detect an
206                                                                           error. */
207 };
208 #endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */
209 
210 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER)
211 /*!
212  * @brief The enumeration of bandgap timer id, VBAT support two bandgap timers.
213  *
214  * @anchor vbat_bandgap_timer_id_t
215  */
216 enum _vbat_bandgap_timer_id
217 {
218     kVBAT_BandgapTimer0 = 1U << 0U, /*!< Bandgap Timer0. */
219     kVBAT_BandgapTimer1 = 1U << 1U, /*!< Bandgap Timer1. */
220 };
221 #endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */
222 
223 /*!
224  * @brief The enumeration of connections for OSC32K/FRO32K output clock to other modules.
225  *
226  * @anchor vbat_clock_enable_t
227  */
228 enum _vbat_clock_enable
229 {
230     kVBAT_EnableClockToDomain0 = 1U << 0U, /*!< Enable clock to power domain0. */
231     kVBAT_EnableClockToDomain1 = 1U << 1U, /*!< Enable clock to power domain1. */
232     kVBAT_EnableClockToDomain2 = 1U << 2U, /*!< Enable clock to power domain2. */
233     kVBAT_EnableClockToDomain3 = 1U << 3U, /*!< Enable clock to power domain3. */
234 };
235 #define kVBAT_EnableClockToVddBat   kVBAT_EnableClockToDomain0
236 #define kVBAT_EnableClockToVddSys   kVBAT_EnableClockToDomain1
237 #define kVBAT_EnableClockToVddWake  kVBAT_EnableClockToDomain2
238 #define kVBAT_EnableClockToVddMain  kVBAT_EnableClockToDomain3
239 
240 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG)
241 /*!
242  * @brief The enumeration of SRAM arrays that controlled by VBAT.
243  * @anchor vbat_ram_array_t
244  */
245 enum _vbat_ram_array
246 {
247     kVBAT_SramArray0 = 1U << 0U, /*!< Specify SRAM array0 that controlled by VBAT. */
248     kVBAT_SramArray1 = 1U << 1U, /*!< Specify SRAM array1 that controlled by VBAT. */
249     kVBAT_SramArray2 = 1U << 2U, /*!< Specify SRAM array2 that controlled by VBAT. */
250     kVBAT_SramArray3 = 1U << 3U, /*!< Specify SRAM array3 that controlled by VBAT. */
251 };
252 #endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */
253 
254 /*!
255  * @brief The enumeration of bandgap refresh period.
256  */
257 typedef enum _vbat_bandgap_refresh_period
258 {
259     kVBAT_BandgapRefresh7P8125ms = 0U, /*!< Bandgap refresh every 7.8125ms. */
260     kVBAT_BandgapRefresh15P625ms = 1U, /*!< Bandgap refresh every 15.625ms. */
261     kVBAT_BandgapRefresh31P25ms  = 2U, /*!< Bandgap refresh every 31.25ms. */
262     kVBAT_BandgapRefresh62P5ms   = 3U, /*!< Bandgap refresh every 62.5ms. */
263 } vbat_bandgap_refresh_period_t;
264 
265 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER)
266 /*!
267  * @brief The enumeration of bandgap timer0 timeout period.
268  */
269 typedef enum _vbat_bandgap_timer0_timeout_period
270 {
271     kVBAT_BangapTimer0Timeout1s      = 0U, /*!< Bandgap timer0 timerout every 1s. */
272     kVBAT_BangapTimer0Timeout500ms   = 1U, /*!< Bandgap timer0 timerout every 500ms. */
273     kVBAT_BangapTimer0Timeout250ms   = 2U, /*!< Bandgap timer0 timerout every 250ms. */
274     kVBAT_BangapTimer0Timeout125ms   = 3U, /*!< Bandgap timer0 timerout every 125ms. */
275     kVBAT_BangapTimer0Timeout62P5ms  = 4U, /*!< Bandgap timer0 timerout every 62.5ms. */
276     kVBAT_BangapTimer0Timeout31P25ms = 5U, /*!< Bandgap timer0 timerout every 31.25ms. */
277 } vbat_bandgap_timer0_timeout_period_t;
278 #endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */
279 
280 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG)
281 /*!
282  * @brief The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on.
283  */
284 typedef enum _vbat_osc32k_operate_mode
285 {
286     kVBAT_Osc32kEnabledToTransconductanceMode = 0U, /*!< Set to transconductance mode. */
287     kVBAT_Osc32kEnabledToLowPowerBackupMode   = 1U, /*!< Set to low power backup mode. */
288     kVBAT_Osc32kEnabledToLowPowerSwitchedMode = 2U, /*!< Set to low power switched mode. */
289 } vbat_osc32k_operate_mode_t;
290 
291 /*!
292  * @brief The enumeration of OSC32K load capacitance.
293  */
294 typedef enum _vbat_osc32k_load_capacitance_select
295 {
296     kVBAT_Osc32kCrystalLoadCap0pF =
297         0U,                         /*!< Internal capacitance bank is enabled, set the internal capacitance to 0 pF. */
298     kVBAT_Osc32kCrystalLoadCap2pF,  /*!< Internal capacitance bank is enabled, set the internal capacitance to 2 pF. */
299     kVBAT_Osc32kCrystalLoadCap4pF,  /*!< Internal capacitance bank is enabled, set the internal capacitance to 4 pF. */
300     kVBAT_Osc32kCrystalLoadCap6pF,  /*!< Internal capacitance bank is enabled, set the internal capacitance to 6 pF. */
301     kVBAT_Osc32kCrystalLoadCap8pF,  /*!< Internal capacitance bank is enabled, set the internal capacitance to 8 pF. */
302     kVBAT_Osc32kCrystalLoadCap10pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 10 pF. */
303     kVBAT_Osc32kCrystalLoadCap12pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 12 pF. */
304     kVBAT_Osc32kCrystalLoadCap14pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 14 pF. */
305     kVBAT_Osc32kCrystalLoadCap16pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 16 pF. */
306     kVBAT_Osc32kCrystalLoadCap18pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 18 pF. */
307     kVBAT_Osc32kCrystalLoadCap20pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 20 pF. */
308     kVBAT_Osc32kCrystalLoadCap22pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 22 pF. */
309     kVBAT_Osc32kCrystalLoadCap24pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 24 pF. */
310     kVBAT_Osc32kCrystalLoadCap26pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 26 pF. */
311     kVBAT_Osc32kCrystalLoadCap28pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 28 pF. */
312     kVBAT_Osc32kCrystalLoadCap30pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 30 pF. */
313     kVBAT_Osc32kCrystalLoadCapBankDisabled = 0xF0U, /*!< Internal capacitance bank is disabled. */
314 } vbat_osc32k_load_capacitance_select_t;
315 
316 /*!
317  * @brief The enumeration of start-up time of the oscillator.
318  */
319 typedef enum _vbat_osc32k_start_up_time
320 {
321     kVBAT_Osc32kStartUpTime8Sec = 0U, /*!< Configure the start-up time as 8 seconds. */
322     kVBAT_Osc32kStartUpTime4Sec,      /*!< Configure the start-up time as 4 seconds. */
323     kVBAT_Osc32kStartUpTime2Sec,      /*!< Configure the start-up time as 2 seconds. */
324     kVBAT_Osc32kStartUpTime1Sec,      /*!< Configure the start-up time as 1 seconds. */
325     kVBAT_Osc32kStartUpTime0P5Sec,    /*!< Configure the start-up time as 0.5 seconds. */
326     kVBAT_Osc32kStartUpTime0P25Sec,   /*!< Configure the start-up time as 0.25 seconds. */
327     kVBAT_Osc32kStartUpTime0P125Sec,  /*!< Configure the start-up time as 0.125 seconds. */
328     kVBAT_Osc32kStartUpTime0P5MSec,   /*!< Configure the start-up time as 0.5 milliseconds. */
329 } vbat_osc32k_start_up_time_t;
330 #endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */
331 
332 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG)
333 /*!
334  * @brief The enumeration of VBAT module supplies.
335  */
336 typedef enum _vbat_internal_module_supply
337 {
338     kVBAT_ModuleSuppliedByVddBat = 0U, /*!< VDD_BAT supplies VBAT modules. */
339     kVBAT_ModuleSuppliedByVddSys = 1U, /*!< VDD_SYS supplies VBAT modules. */
340 } vbat_internal_module_supply_t;
341 #endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */
342 
343 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG)
344 /*!
345  * @brief The enumeration of VBAT clock monitor divide trim value
346  */
347 typedef enum _vbat_clock_monitor_divide_trim
348 {
349     kVBAT_ClockMonitorOperateAt1kHz = 0U, /*!< Clock monitor operates at 1 kHz. */
350     kVBAT_ClockMonitorOperateAt64Hz = 1U, /*!< Clock monitor operates at 64 Hz. */
351 } vbat_clock_monitor_divide_trim_t;
352 
353 /*!
354  * @brief The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert.
355  */
356 typedef enum _vbat_clock_monitor_freq_trim
357 {
358     kVBAT_ClockMonitorAssert2Cycle = 0U, /*!< Clock monitor assert 2 cycles after expected edge. */
359     kVBAT_ClockMonitorAssert4Cycle = 1U, /*!< Clock monitor assert 4 cycles after expected edge. */
360     kVBAT_ClockMonitorAssert6Cycle = 2U, /*!< Clock monitor assert 8 cycles after expected edge. */
361     kVBAT_ClockMonitorAssert8Cycle = 3U, /*!< Clock monitor assert 8 cycles after expected edge. */
362 } vbat_clock_monitor_freq_trim_t;
363 #endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */
364 
365 /*!
366  * @brief The structure of internal 16kHz free running oscillator attributes.
367  */
368 typedef struct _vbat_fro16k_config
369 {
370     bool enableFRO16k;              /*!< Enable/disable internal 16kHz free running oscillator. */
371     uint8_t enabledConnectionsMask; /*!< The mask of connected modules to enable FRO16k clock output.  */
372 } vbat_fro16k_config_t;
373 
374 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG)
375 /*!
376  * @brief The structure of internal clock monitor, including divide trim and frequency trim.
377  */
378 typedef struct _vbat_clock_monitor_config
379 {
380     vbat_clock_monitor_divide_trim_t divideTrim : 1U; /* !< Divide trim value, please
381                                                     refer to @ref vbat_clock_monitor_divide_trim_t */
382     vbat_clock_monitor_freq_trim_t freqTrim : 2U;     /*!< Frequency trim value used to adjust the clock monitor
383                                                      assert, please refer to @ref vbat_clock_monitor_freq_trim_t. */
384     bool lock : 1U;                                   /*!< Lock the clock monitor control after enabled. */
385 } vbat_clock_monitor_config_t;
386 #endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */
387 
388 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG)
389 /*!
390  * @brief The structure of Tamper configuration.
391  */
392 typedef struct _vbat_tamper_config
393 {
394     bool enableVoltageDetect : 1U;     /*!< Enable/disable voltage detection. */
395     bool enableTemperatureDetect : 1U; /*!< Enable/disable temperature detection. */
396     bool lock : 1U;                    /*!< Lock the tamper control after enabled. */
397 } vbat_tamper_config_t;
398 #endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */
399 
400 /*******************************************************************************
401  * API
402  ******************************************************************************/
403 
404 #if defined(__cplusplus)
405 extern "C" {
406 #endif
407 
408 /*!
409  * @name FRO16K Control Interfaces
410  * @{
411  */
412 
413 /*!
414  * @brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output.
415  *
416  * @param base VBAT peripheral base address.
417  * @param config Pointer to @ref vbat_fro16k_config_t structure.
418  */
419 void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config);
420 
421 /*!
422  * @brief Enable/disable internal 16kHz free running oscillator.
423  *
424  * @param base VBAT peripheral base address.
425  * @param enable Used to enable/disable 16kHz FRO.
426  *          - \b true Enable internal 16kHz free running oscillator.
427  *          - \b false Disable internal 16kHz free running oscillator.
428  */
VBAT_EnableFRO16k(VBAT_Type * base,bool enable)429 static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable)
430 {
431     if (enable)
432     {
433         base->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK;
434 #if (defined(VBAT_FROCTLB_INVERSE_MASK))
435         base->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK;
436 #endif /* VBAT_FROCTLB_INVERSE_MASK */
437     }
438     else
439     {
440         base->FROCTLA &= ~VBAT_FROCTLA_FRO_EN_MASK;
441 #if (defined(VBAT_FROCTLB_INVERSE_MASK))
442         base->FROCTLB |= VBAT_FROCTLB_INVERSE_MASK;
443 #endif /* VBAT_FROCTLB_INVERSE_MASK */
444     }
445 }
446 
447 /*!
448  * @brief Check if internal 16kHz free running oscillator is enabled.
449  *
450  * @param base VBAT peripheral base address.
451  *
452  * @retval true The internal 16kHz Free running oscillator is enabled.
453  * @retval false The internal 16kHz Free running oscillator is enabled.
454  */
VBAT_CheckFRO16kEnabled(VBAT_Type * base)455 static inline bool VBAT_CheckFRO16kEnabled(VBAT_Type *base)
456 {
457     return (bool)((base->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) == VBAT_FROCTLA_FRO_EN_MASK);
458 }
459 
460 /*!
461  * @brief Enable FRO16kHz output clock to selected modules.
462  *
463  * @param base VBAT peripheral base address.
464  * @param connectionsMask The mask of modules that FRO16k is connected, should be the OR'ed
465  *                        value of @ref vbat_clock_enable_t.
466  */
VBAT_UngateFRO16k(VBAT_Type * base,uint8_t connectionsMask)467 static inline void VBAT_UngateFRO16k(VBAT_Type *base, uint8_t connectionsMask)
468 {
469     base->FROCLKE |= VBAT_FROCLKE_CLKE(connectionsMask);
470 }
471 
472 /*!
473  * @brief Disable FRO16kHz output clock to selected modules.
474  *
475  * @param base VBAT peripheral base address.
476  * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t.
477  */
VBAT_GateFRO16k(VBAT_Type * base,uint8_t connectionsMask)478 static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask)
479 {
480     base->FROCLKE &= ~VBAT_FROCLKE_CLKE(connectionsMask);
481 }
482 
483 /*!
484  * @brief Lock settings of internal 16kHz free running oscillator, please note that if locked 16kHz FRO's settings can
485  * not be updated until the next POR.
486  *
487  * @note Please note that the operation to ungate/gate FRO 16kHz output clock can not be locked by this function.
488  *
489  * @param base VBAT peripheral base address.
490  */
VBAT_LockFRO16kSettings(VBAT_Type * base)491 static inline void VBAT_LockFRO16kSettings(VBAT_Type *base)
492 {
493     base->FROLCKA |= VBAT_FROLCKA_LOCK_MASK;
494 #if (defined(VBAT_FROLCKB_LOCK_MASK))
495     base->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK;
496 #endif /* VBAT_FROLCKB_LOCK_MASK */
497 }
498 
499 /*!
500  * @brief Check if FRO16K settings are locked.
501  *
502  * @param base VBAT peripheral base address.
503  *
504  * @return @c true in case of FRO16k settings are locked, @c false in case of FRO16k settings are not locked.
505  */
VBAT_CheckFRO16kSettingsLocked(VBAT_Type * base)506 static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base)
507 {
508     return ((base->FROLCKA & VBAT_FROLCKA_LOCK_MASK) != 0UL);
509 }
510 
511 /*! @} */
512 
513 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG)
514 /*!
515  * @name OSC32K Control Interfaces
516  * @{
517  */
518 
519 /*!
520  * @brief Enable/disable 32K Crystal Oscillator.
521  *
522  * @param base VBAT peripheral base address.
523  * @param enable Used to enable/disable 32k Crystal Oscillator:
524  *         - \b true Enable crystal oscillator and polling status register to check clock is ready.
525  *         - \b false Disable crystal oscillator.
526  */
VBAT_EnableCrystalOsc32k(VBAT_Type * base,bool enable)527 static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable)
528 {
529     if (enable)
530     {
531         base->OSCCTLA |= VBAT_OSCCTLA_OSC_EN_MASK;
532         base->OSCCTLB &= ~VBAT_OSCCTLA_OSC_EN_MASK;
533 
534         /* Polling status register to check clock is ready. */
535         while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL)
536         {}
537     }
538     else
539     {
540         base->OSCCTLA &= ~VBAT_OSCCTLA_OSC_EN_MASK;
541         base->OSCCTLB |= VBAT_OSCCTLA_OSC_EN_MASK;
542     }
543 }
544 
545 /*!
546  * @brief Bypass 32k crystal oscillator, the clock is still output by oscillator but this clock is the same as clock
547  * provided on EXTAL pin.
548  *
549  * @note In bypass mode, oscillator must be enabled; To exit bypass mode, oscillator must be disabled.
550  *
551  * @param base VBAT peripheral base address.
552  * @param enableBypass Used to enter/exit bypass mode:
553  *          - \b true Enter into bypass mode;
554  *          - \b false Exit bypass mode.
555  */
VBAT_BypassCrystalOsc32k(VBAT_Type * base,bool enableBypass)556 static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass)
557 {
558     if (enableBypass)
559     {
560         base->OSCCTLA |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK);
561         base->OSCCTLB &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK);
562     }
563     else
564     {
565         base->OSCCTLA &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK);
566         base->OSCCTLB |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK);
567     }
568 }
569 
570 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT)
571 /*!
572  * @brief Adjust 32k crystal oscillator amplifier gain.
573  *
574  * @param base VBAT peripheral base address.
575  * @param coarse Specify amplifier coarse trim value.
576  * @param fine Specify amplifier fine trim value.
577  */
VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type * base,uint8_t coarse,uint8_t fine)578 static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse, uint8_t fine)
579 {
580     base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) |
581                      (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(fine)));
582     base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) |
583                      (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine)));
584 }
585 #else
586 /*!
587  * @brief Adjust 32k crystal oscillator amplifier gain.
588  *
589  * @param base VBAT peripheral base address.
590  * @param coarse Specify amplifier coarse trim value.
591  */
VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type * base,uint8_t coarse)592 static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse)
593 {
594     base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse));
595     base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~(uint32_t)coarse));
596 }
597 
598 #endif /*  */
599 
600 /*!
601  * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin.
602  *
603  * @param base VBAT peripheral base address.
604  * @param operateMode Specify the crystal oscillator mode, please refer to @ref vbat_osc32k_operate_mode_t.
605  * @param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank.
606  * @param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank.
607  *
608  * @retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's
609  * requirements.
610  * @retval kStatus_Success Success to set operate mode and load capacitance.
611  */
612 status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
613                                                      vbat_osc32k_operate_mode_t operateMode,
614                                                      vbat_osc32k_load_capacitance_select_t xtalCap,
615                                                      vbat_osc32k_load_capacitance_select_t extalCap);
616 
617 /*!
618  * @brief Trim 32k crystal oscillator startup time.
619  *
620  * @param base VBAT peripheral base address.
621  * @param startupTime Specify the startup time of the oscillator.
622  */
VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type * base,vbat_osc32k_start_up_time_t startupTime)623 static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime)
624 {
625     base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime));
626     base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime)));
627 }
628 
629 /*!
630  * @brief Set crystal oscillator comparator trim value when oscillator is set as low power switch mode.
631  *
632  * @param base VBAT peripheral base address.
633  * @param comparatorTrimValue Comparator trim value, ranges from 0 to 7.
634  */
VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type * base,uint8_t comparatorTrimValue)635 static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue)
636 {
637     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue));
638     base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue)));
639 }
640 
641 /*!
642  * @brief Set crystal oscillator delay trim value when oscillator is set as low power switch mode.
643  *
644  * @param base VBAT peripheral base address.
645  * @param delayTrimValue Delay trim value, ranges from 0 to 15.
646  */
VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type * base,uint8_t delayTrimValue)647 static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue)
648 {
649     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue));
650     base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue)));
651 }
652 
653 /*!
654  * @brief Set crystal oscillator capacitor trim value when oscillator is set as low power switch mode.
655  *
656  * @param base VBAT peripheral base address.
657  * @param capacitorTrimValue Capacitor value to trim, ranges from 0 to 3.
658  */
VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type * base,uint8_t capacitorTrimValue)659 static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue)
660 {
661     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue));
662     base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue)));
663 }
664 
665 /*!
666  * @brief Lock Osc32k settings, after locked all writes to the Oscillator registers are blocked.
667  *
668  * @param base VBAT peripheral base address.
669  */
VBAT_LookOsc32kSettings(VBAT_Type * base)670 static inline void VBAT_LookOsc32kSettings(VBAT_Type *base)
671 {
672     base->OSCLCKA |= VBAT_OSCLCKA_LOCK_MASK;
673     base->OSCLCKB &= ~VBAT_OSCLCKB_LOCK_MASK;
674 }
675 
676 /*!
677  * @brief Unlock Osc32k settings.
678  *
679  * @param base VBAT peripheral base address.
680  */
VBAT_UnlockOsc32kSettings(VBAT_Type * base)681 static inline void VBAT_UnlockOsc32kSettings(VBAT_Type *base)
682 {
683     base->OSCLCKA &= ~VBAT_OSCLCKA_LOCK_MASK;
684     base->OSCLCKB |= VBAT_OSCLCKB_LOCK_MASK;
685 }
686 
687 /*!
688  * @brief Check if osc32k settings are locked.
689  *
690  * @param base VBAT peripheral base address.
691  * @return \c true in case of osc32k settings are locked, \c false in case of osc32k settings are not locked.
692  */
VBAT_CheckOsc32kSettingsLocked(VBAT_Type * base)693 static inline bool VBAT_CheckOsc32kSettingsLocked(VBAT_Type *base)
694 {
695     return ((base->OSCLCKA & VBAT_OSCLCKA_LOCK_MASK) != 0UL);
696 }
697 
698 /*!
699  * @brief Enable OSC32k output clock to selected modules.
700  *
701  * @param base VBAT peripheral base address.
702  * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t.
703  */
VBAT_UngateOsc32k(VBAT_Type * base,uint8_t connectionsMask)704 static inline void VBAT_UngateOsc32k(VBAT_Type *base, uint8_t connectionsMask)
705 {
706     base->OSCCLKE |= VBAT_OSCCLKE_CLKE(connectionsMask);
707 }
708 
709 /*!
710  * @brief Disable OSC32k output clock to selected modules.
711  *
712  * @param base VBAT peripheral base address.
713  * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t.
714  */
VBAT_GateOsc32k(VBAT_Type * base,uint8_t connectionsMask)715 static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask)
716 {
717     base->OSCCLKE &= ~VBAT_OSCCLKE_CLKE(connectionsMask);
718 }
719 
720 /*! @} */
721 #endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */
722 
723 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG)
724 /*!
725  * @name RAM_LDO Control Interfaces
726  * @{
727  */
728 
729 /*!
730  * @brief Enable/disable Bandgap.
731  *
732  * @note The FRO16K must be enabled before enabling the bandgap.
733  * @note This setting can be locked by VBAT_LockRamLdoSettings() function.
734  *
735  * @param base VBAT peripheral base address.
736  * @param enable Used to enable/disable bandgap.
737  *      - \b true Enable the bandgap.
738  *      - \b false Disable the bandgap.
739  *
740  * @retval kStatus_Success Success to enable/disable the bandgap.
741  * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously.
742  */
743 status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable);
744 
745 /*!
746  * @brief Check if bandgap is enabled.
747  *
748  * @param base VBAT peripheral base address.
749  *
750  * @retval true The bandgap is enabled.
751  * @retval false The bandgap is disabled.
752  */
VBAT_CheckBandgapEnabled(VBAT_Type * base)753 static inline bool VBAT_CheckBandgapEnabled(VBAT_Type *base)
754 {
755     return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK);
756 }
757 
758 /*!
759  * @brief Enable/disable bandgap low power refresh mode.
760  *
761  * @note For lowest power consumption, refresh mode must be enabled.
762  * @note This setting can be locked by VBAT_LockRamLdoSettings() function.
763  *
764  * @param base VBAT peripheral base address.
765  * @param enableRefreshMode Used to enable/disable bandgap low power refresh mode.
766  *          - \b true Enable bandgap low power refresh mode.
767  *          - \b false Disable bandgap low power refresh mode.
768  */
VBAT_EnableBandgapRefreshMode(VBAT_Type * base,bool enableRefreshMode)769 static inline void VBAT_EnableBandgapRefreshMode(VBAT_Type *base, bool enableRefreshMode)
770 {
771     if (enableRefreshMode)
772     {
773         base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK;
774         base->LDOCTLB &= ~VBAT_LDOCTLA_REFRESH_EN_MASK;
775     }
776     else
777     {
778         base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK;
779         base->LDOCTLB |= VBAT_LDOCTLA_REFRESH_EN_MASK;
780     }
781 }
782 
783 /*!
784  * @brief Enable/disable Backup RAM Regulator(RAM_LDO).
785  *
786  * @note This setting can be locked by VBAT_LockRamLdoSettings() function.
787  *
788  * @param base VBAT peripheral base address.
789  * @param enable Used to enable/disable RAM_LDO.
790  *          - \b true Enable backup SRAM regulator.
791  *          - \b false Disable backup SRAM regulator.
792  *
793  * @retval kStatusSuccess Success to enable/disable backup SRAM regulator.
794  * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously.
795  * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled
796  * previously.
797  */
798 status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable);
799 
800 /*!
801  * @brief Lock settings of RAM_LDO, please note that if locked then RAM_LDO's settings
802  * can not be updated until the next POR.
803  *
804  * @param base VBAT peripheral base address.
805  */
VBAT_LockRamLdoSettings(VBAT_Type * base)806 static inline void VBAT_LockRamLdoSettings(VBAT_Type *base)
807 {
808     base->LDOLCKA |= VBAT_LDOLCKA_LOCK_MASK;
809     base->LDOLCKB &= ~VBAT_LDOLCKA_LOCK_MASK;
810 }
811 
812 /*!
813  * @brief Check if RAM_LDO settings is locked.
814  *
815  * @param base VBAT peripheral base address.
816  * @return @c true in case of RAM_LDO settings are locked, @c false in case of RAM_LDO settings are unlocked.
817  */
VBAT_CheckRamLdoSettingsLocked(VBAT_Type * base)818 static inline bool VBAT_CheckRamLdoSettingsLocked(VBAT_Type *base)
819 {
820     return ((base->LDOLCKA & VBAT_LDOLCKA_LOCK_MASK) != 0UL);
821 }
822 
823 /*!
824  * @brief Switch the SRAM to be powered by LDO_RAM.
825  *
826  * @note This function can be used to switch the SRAM to the VBAT retention supply at any time, but please note that the
827  * SRAM must not be accessed during this time.
828  * @note Invoke this function to switch power supply before switching off external power.
829  * @note RAM_LDO must be enabled before invoking this function.
830  * @note To access the SRAM arrays retained by the LDO_RAM, please invoke VBAT_SwitchSRAMPowerBySocSupply(), after
831  * external power is switched back on.
832  *
833  * @param base VBAT peripheral base address.
834  *
835  * @retval kStatusSuccess Success to Switch SRAM powered by VBAT.
836  * @retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously.
837  */
838 status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base);
839 
840 /*!
841  * @brief Switch the RAM to be powered by Soc Supply in software mode.
842  *
843  * @param base VBAT peripheral base address.
844  */
VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type * base)845 static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base)
846 {
847     base->LDORAMC &= ~VBAT_LDORAMC_SWI_MASK;
848     base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK;
849 }
850 
851 /*!
852  * @brief Power off selected SRAM array in low power modes.
853  *
854  * @param base VBAT peripheral base address.
855  * @param sramMask The mask of SRAM array to power off, should be the OR'ed value of @ref vbat_ram_array_t.
856  */
VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type * base,uint8_t sramMask)857 static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
858 {
859     base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask);
860 }
861 
862 /*!
863  * @brief Retain selected SRAM array in low power modes.
864  *
865  * @param base VBAT peripheral base address.
866  * @param sramMask The mask of SRAM array to retain, should be the OR'ed value of @ref vbat_ram_array_t.
867  */
VBAT_RetainSRAMsInLowPowerModes(VBAT_Type * base,uint8_t sramMask)868 static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
869 {
870     base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask);
871 }
872 
873 /*!
874  * @brief Enable/disable SRAM isolation.
875  *
876  * @param base VBAT peripheral base address.
877  * @param enable Used to enable/disable SRAM violation.
878  *          - \b true SRAM will be isolated.
879  *          - \b false SRAM state follows the SoC power modes.
880  */
VBAT_EnableSRAMIsolation(VBAT_Type * base,bool enable)881 static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable)
882 {
883     if (enable)
884     {
885         base->LDORAMC |= VBAT_LDORAMC_ISO_MASK;
886     }
887     else
888     {
889         base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK;
890     }
891 }
892 
893 /*! @} */
894 #endif /* FSL_FEATURE_MCX_VBAT_HAS_RAM_LDO */
895 
896 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER)
897 /*! @name Bandgap Timer Control Interfaces
898  * @{
899  */
900 
901 /*!
902  * @brief Enable/disable Bandgap timer.
903  *
904  * @note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k.
905  *
906  * @param base VBAT peripheral base address.
907  * @param enable Used to enable/disable bandgap timer.
908  * @param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of @ref vbat_bandgap_timer_id_t.
909  *
910  * @retval kStatus_Success Success to enable/disable selected bandgap timer.
911  * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled
912  * previously.
913  * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not enabled
914  * previously.
915  */
916 status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask);
917 
918 /*!
919  * @brief Set bandgap timer0 timeout value.
920  *
921  * @note The timeout value can only be changed when the timer is disabled.
922  *
923  * @param base VBAT peripheral base address.
924  * @param timeoutPeriod Bandgap timer timeout value, please refer to @ref vbat_bandgap_timer0_timeout_period_t.
925  */
926 void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod);
927 
928 /*!
929  * @brief Set bandgap timer1 timeout value.
930  *
931  * @note The timeout value can only be changed when the timer is disabled.
932  *
933  * @param base VBAT peripheral base address.
934  * @param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s.
935  */
936 void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod);
937 
938 /*! @} */
939 #endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */
940 
941 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG)
942 /*! @name Switch Control Interfaces
943  * @{
944  */
945 
946 /*!
947  * @brief Control the VBAT internal switch in active mode, VBAT modules can be suppiled by VDD_BAT and VDD_SYS.
948  *
949  * @param base VBAT peripheral base address.
950  * @param supply Used to control the VBAT internal switch.
951  */
VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type * base,vbat_internal_module_supply_t supply)952 static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_internal_module_supply_t supply)
953 {
954     if (supply == kVBAT_ModuleSuppliedByVddBat)
955     {
956         base->SWICTLA &= ~VBAT_SWICTLA_SWI_EN_MASK;
957         base->SWICTLB |= VBAT_SWICTLA_SWI_EN_MASK;
958     }
959     else
960     {
961         base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK;
962         base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK;
963     }
964 }
965 
966 /*!
967  * @brief Get VBAT module supply in active mode.
968  *
969  * @param base VBAT peripheral base address.
970  * @return VDD_SYS supplies VBAT modules or VDD_BAT supplies VBAT modules, in type of @ref
971  * vbat_internal_module_supply_t.
972  */
VBAT_GetVBATModuleSupply(VBAT_Type * base)973 static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base)
974 {
975     return (vbat_internal_module_supply_t)(uint8_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK);
976 }
977 
978 /*!
979  * @brief Control the VBAT internal switch in low power modes.
980  *
981  * @note If VBAT modules are supplied by VDD_SYS in low power modes, VBAT module will also supplied by VDD_SYS in active
982  * mode.
983  *
984  * @param base VBAT peripheral base address.
985  * @param supply Used to specify which voltage input supply VBAT modules in low power mode.
986  */
VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type * base,vbat_internal_module_supply_t supply)987 static inline void VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type *base, vbat_internal_module_supply_t supply)
988 {
989     if (supply == kVBAT_ModuleSuppliedByVddBat)
990     {
991         base->SWICTLA &= ~VBAT_SWICTLA_LP_EN_MASK;
992         base->SWICTLB |= VBAT_SWICTLA_LP_EN_MASK;
993     }
994     else
995     {
996         base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK;
997         base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK;
998         base->SWICTLA |= VBAT_SWICTLA_LP_EN_MASK;
999         base->SWICTLB &= ~VBAT_SWICTLA_LP_EN_MASK;
1000     }
1001 }
1002 
1003 /*!
1004  * @brief Lock switch control, if locked all writes to the switch registers will be blocked.
1005  *
1006  * @param base VBAT peripheral base address.
1007  */
VBAT_LockSwitchControl(VBAT_Type * base)1008 static inline void VBAT_LockSwitchControl(VBAT_Type *base)
1009 {
1010     base->SWILCKA |= VBAT_SWILCKA_LOCK_MASK;
1011     base->SWILCKB &= ~VBAT_SWILCKB_LOCK_MASK;
1012 }
1013 
1014 /*!
1015  * @brief Unlock switch control.
1016  *
1017  * @param base VBAT peripheral base address.
1018  */
VBAT_UnlockSwitchControl(VBAT_Type * base)1019 static inline void VBAT_UnlockSwitchControl(VBAT_Type *base)
1020 {
1021     base->SWILCKA &= ~VBAT_SWILCKA_LOCK_MASK;
1022     base->SWILCKB |= VBAT_SWILCKB_LOCK_MASK;
1023 }
1024 
1025 /*!
1026  * @brief Check if switch control is locked.
1027  *
1028  * @param base VBAT peripheral base address.
1029  *
1030  * @retval false switch control is not locked.
1031  * @retval true  switch control is locked, any writes to related registers are blocked.
1032  */
VBAT_CheckSwitchControlLocked(VBAT_Type * base)1033 static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base)
1034 {
1035     return ((base->SWILCKA & VBAT_SWILCKA_LOCK_MASK) != 0UL);
1036 }
1037 
1038 /*! @} */
1039 #endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */
1040 
1041 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG)
1042 /*!
1043  * @name Clock Monitor Interfaces
1044  * @{
1045  */
1046 
1047 /*!
1048  * @brief Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration.
1049  *
1050  * @note Both FRO16K and OSC32K should be enabled and stable before invoking this function.
1051  *
1052  * @param base VBAT peripheral base address.
1053  * @param config Pointer to @ref vbat_clock_monitor_config_t structure.
1054  *
1055  * @retval kStatus_Success Clock monitor is initialized successfully.
1056  * @retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled.
1057  * @retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready.
1058  * @retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked.
1059  */
1060 status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config);
1061 
1062 /*!
1063  * @brief Deinitialize the VBAT clock monitor.
1064  *
1065  * @param base VBAT peripheral base address.
1066  *
1067  * @retval kStatus_Success Clock monitor is de-initialized successfully.
1068  * @retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked.
1069  */
1070 status_t VBAT_DeinitMonitor(VBAT_Type *base);
1071 
1072 /*!
1073  * @brief Enable/disable clock monitor.
1074  *
1075  * @param base VBAT peripheral base address.
1076  * @param enable Switcher to enable/disable clock monitor:
1077  *         - true: enable clock monitor;
1078  *        - false: disable clock monitor.
1079  */
VBAT_EnableClockMonitor(VBAT_Type * base,bool enable)1080 static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable)
1081 {
1082     if (enable)
1083     {
1084         base->MONCTLA |= VBAT_MONCTLA_MON_EN_MASK;
1085         base->MONCTLB &= ~VBAT_MONCTLA_MON_EN_MASK;
1086     }
1087     else
1088     {
1089         base->MONCTLA &= ~VBAT_MONCTLA_MON_EN_MASK;
1090         base->MONCTLB |= VBAT_MONCTLA_MON_EN_MASK;
1091     }
1092 }
1093 
1094 /*!
1095  * @brief Set clock monitor's divide trim, avaiable value is #kVBAT_ClockMonitorOperateAt1kHz and
1096  * #kVBAT_ClockMonitorOperateAt64Hz
1097  *
1098  * @param base VBAT peripheral base address.
1099  * @param divideTrim Specify divide trim value, please refer to @ref vbat_clock_monitor_divide_trim_t.
1100  */
VBAT_SetClockMonitorDivideTrim(VBAT_Type * base,vbat_clock_monitor_divide_trim_t divideTrim)1101 static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim)
1102 {
1103     base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(divideTrim);
1104     base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(~divideTrim);
1105 }
1106 
1107 /*!
1108  * @brief Set clock monitor's frequency trim, avaiable value is #kVBAT_ClockMonitorAssert2Cycle,
1109  * #kVBAT_ClockMonitorAssert4Cycle, #kVBAT_ClockMonitorAssert6Cycle and #kVBAT_ClockMonitorAssert8Cycle.
1110  *
1111  * @param base VBAT peripheral base address.
1112  * @param freqTrim Specify frequency trim value, please refer to @ref vbat_clock_monitor_freq_trim_t.
1113  */
VBAT_SetClockMonitorFrequencyTrim(VBAT_Type * base,vbat_clock_monitor_freq_trim_t freqTrim)1114 static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim)
1115 {
1116     base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(freqTrim);
1117     base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(~freqTrim);
1118 }
1119 
1120 /*!
1121  * @brief Lock clock monitor enable/disable control.
1122  *
1123  * @note If locked, it is not allowed to change clock monitor enable/disable control.
1124  *
1125  * @param base VBAT peripheral base address.
1126  */
VBAT_LockClockMonitorControl(VBAT_Type * base)1127 static inline void VBAT_LockClockMonitorControl(VBAT_Type *base)
1128 {
1129     base->MONLCKA |= VBAT_MONLCKA_LOCK_MASK;
1130     base->MONLCKB &= ~VBAT_MONLCKA_LOCK_MASK;
1131 }
1132 
1133 /*!
1134  * @brief Unlock clock monitor enable/disable control.
1135  *
1136  * @param base VBTA peripheral base address.
1137  */
VBAT_UnlockClockMonitorControl(VBAT_Type * base)1138 static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base)
1139 {
1140     base->MONLCKA &= ~VBAT_MONLCKA_LOCK_MASK;
1141     base->MONLCKB |= VBAT_MONLCKA_LOCK_MASK;
1142 }
1143 
1144 /*!
1145  * @brief Check if clock monitor enable/disable control is locked.
1146  *
1147  * @note If locked, it is not allowed to change clock monitor enable/disable control.
1148  *
1149  * @param base VBAT peripheral base address.
1150  *
1151  * @retval false clock monitor enable/disable control is not locked.
1152  * @retval true  clock monitor enable/disable control is locked, any writes to related registers are blocked.
1153  */
VBAT_CheckClockMonitorControlLocked(VBAT_Type * base)1154 static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base)
1155 {
1156     return ((base->MONLCKA & VBAT_MONLCKA_LOCK_MASK) != 0UL);
1157 }
1158 
1159 /*! @} */
1160 #endif /* FSL_FEATURE_VBAT_HAS_CLOCK_MONITOR */
1161 
1162 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG)
1163 /*! @name Tamper Control Interfaces
1164  *
1165  */
1166 
1167 /*!
1168  * @brief Initialize tamper control.
1169  *
1170  * @note Both FRO16K and bandgap should be enabled before calling this function.
1171  *
1172  * @param base VBAT peripheral base address.
1173  * @param config Pointer to @ref vbat_tamper_config_t structure.
1174  *
1175  * @retval kStatus_Success Tamper is initialized successfully.
1176  * @retval kStatus_VBAT_TamperLocked Tamper control is locked.
1177  * @retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled.
1178  * @retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled.
1179  */
1180 status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config);
1181 
1182 /*!
1183  * @brief De-initialize tamper control.
1184  *
1185  * @param base VBAT peripheral base address.
1186  *
1187  * @retval kStatus_Success Tamper is de-initialized successfully.
1188  * @retval kStatus_VBAT_TamperLocked Tamper control is locked.
1189  */
1190 status_t VBAT_DeinitTamper(VBAT_Type *base);
1191 
1192 /*!
1193  * @brief Enable tampers for VBAT.
1194  *
1195  * @param base VBAT peripheral base address.
1196  * @param tamperEnableMask Mask of tamper to be enabled, should be the OR'ed value of @ref _vbat_tamper_enable.
1197  */
VBAT_EnableTamper(VBAT_Type * base,uint32_t tamperEnableMask)1198 static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask)
1199 {
1200     base->TAMPERA |= tamperEnableMask;
1201     base->TAMPERB &= ~tamperEnableMask;
1202 }
1203 
1204 /*!
1205  * @brief Disable tampers for VBAT.
1206  *
1207  * @param base VBAT peripheral base address.
1208  * @param tamperEnableMask Mask of tamper to be disabled, should be the OR'ed value of @ref _vbat_tamper_enable.
1209  */
VBAT_DisableTamper(VBAT_Type * base,uint32_t tamperEnableMask)1210 static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask)
1211 {
1212     base->TAMPERA &= ~tamperEnableMask;
1213     base->TAMPERB |= tamperEnableMask;
1214 }
1215 
1216 /*!
1217  * @brief Get tamper enable information.
1218  *
1219  * @param base VBAT peripheral base address.
1220  *
1221  * @return Mask of tamper enable information, should be the OR'ed value of @ref _vbat_tamper_enable.
1222  */
VBAT_GetTamperEnableInfo(VBAT_Type * base)1223 static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base)
1224 {
1225     return base->TAMPERA;
1226 }
1227 
1228 /*!
1229  * @brief Lock tamper control, if locked, it is not allowed to change tamper control.
1230  *
1231  * @param base VBAT peripheral base address.
1232  */
VBAT_LockTamperControl(VBAT_Type * base)1233 static inline void VBAT_LockTamperControl(VBAT_Type *base)
1234 {
1235     base->TAMLCKA |= VBAT_TAMLCKA_LOCK_MASK;
1236     base->TAMLCKB &= ~VBAT_TAMLCKA_LOCK_MASK;
1237 }
1238 
1239 /*!
1240  * @brief Unlock tamper control.
1241  *
1242  * @param base VBAT peripheral base address.
1243  */
VBAT_UnlockTamperControl(VBAT_Type * base)1244 static inline void VBAT_UnlockTamperControl(VBAT_Type *base)
1245 {
1246     base->TAMLCKA &= ~VBAT_TAMLCKA_LOCK_MASK;
1247     base->TAMLCKB |= VBAT_TAMLCKA_LOCK_MASK;
1248 }
1249 
1250 /*!
1251  * @brief Check if tamper control is locked.
1252  *
1253  * @param base VBAT peripheral base address.
1254  *
1255  * @retval false Tamper control is not locked.
1256  * @retval true  Tamper control is locked, any writes to related registers are blocked.
1257  */
VBAT_CheckTamperControlLocked(VBAT_Type * base)1258 static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base)
1259 {
1260     return ((base->TAMLCKA & VBAT_TAMLCKA_LOCK_MASK) != 0UL);
1261 }
1262 
1263 /*! @} */
1264 #endif /* FSL_FEATURE_VBAT_HAS_TAMPER */
1265 
1266 #if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG)
1267 /*! @name Status, Interrupt, Wakeup Control Interfaces
1268  * @{
1269  */
1270 
1271 /*!
1272  * @brief Get VBAT status flags
1273  *
1274  * @param base VBAT peripheral base address.
1275  * @return The asserted status flags, should be the OR'ed value of @ref vbat_status_flag_t.
1276  */
VBAT_GetStatusFlags(VBAT_Type * base)1277 static inline uint32_t VBAT_GetStatusFlags(VBAT_Type *base)
1278 {
1279     return (uint32_t)(base->STATUSA);
1280 }
1281 
1282 /*!
1283  * @brief Clear VBAT status flags.
1284  *
1285  * @param base VBAT peripheral base address.
1286  * @param mask The mask of status flags to be cleared, should be the OR'ed value of @ref vbat_status_flag_t except
1287  *              @ref kVBAT_StatusFlagLdoReady, @ref kVBAT_StatusFlagOsc32kReady, @ref kVBAT_StatusFlagInterrupt0Detect,
1288  *              @ref kVBAT_StatusFlagInterrupt1Detect, @ref kVBAT_StatusFlagInterrupt2Detect,
1289  *              @ref kVBAT_StatusFlagInterrupt3Detect.
1290  */
VBAT_ClearStatusFlags(VBAT_Type * base,uint32_t mask)1291 static inline void VBAT_ClearStatusFlags(VBAT_Type *base, uint32_t mask)
1292 {
1293     base->STATUSA = mask;
1294     base->STATUSB = ~mask;
1295 }
1296 
1297 /*!
1298  * @brief Enable interrupts for the VBAT module, such as POR detect interrupt, Wakeup Pin interrupt and so on.
1299  *
1300  * @param base VBAT peripheral base address.
1301  * @param mask The mask of interrupts to be enabled, should be the OR'ed value of @ref vbat_interrupt_enable_t.
1302  */
VBAT_EnableInterrupts(VBAT_Type * base,uint32_t mask)1303 static inline void VBAT_EnableInterrupts(VBAT_Type *base, uint32_t mask)
1304 {
1305     base->IRQENA |= mask;
1306     base->IRQENB &= (uint32_t)~mask;
1307 }
1308 
1309 /*!
1310  * @brief Disable interrupts for the VBAT module, such as POR detect interrupt, wakeup pin interrupt and so on.
1311  *
1312  * @param base VBAT peripheral base address.
1313  * @param mask The mask of interrupts to be disabled, should be the OR'ed value of @ref vbat_interrupt_enable_t.
1314  */
VBAT_DisableInterrupts(VBAT_Type * base,uint32_t mask)1315 static inline void VBAT_DisableInterrupts(VBAT_Type *base, uint32_t mask)
1316 {
1317     base->IRQENA &= ~mask;
1318     base->IRQENB |= mask;
1319 }
1320 
1321 /*!
1322  * @brief Enable wakeup for the VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on.
1323  *
1324  * @param base VBAT peripheral base address.
1325  * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t.
1326  */
VBAT_EnableWakeup(VBAT_Type * base,uint32_t mask)1327 static inline void VBAT_EnableWakeup(VBAT_Type *base, uint32_t mask)
1328 {
1329     base->WAKENA |= mask;
1330     base->WAKENB &= ~mask;
1331 }
1332 
1333 /*!
1334  * @brief Disable wakeup for VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on.
1335  *
1336  * @param base VBAT peripheral base address.
1337  * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t.
1338  */
VBAT_DisableWakeup(VBAT_Type * base,uint32_t mask)1339 static inline void VBAT_DisableWakeup(VBAT_Type *base, uint32_t mask)
1340 {
1341     base->WAKENA &= ~mask;
1342     base->WAKENB |= mask;
1343 }
1344 
1345 /*!
1346  * @brief Lock VBAT interrupt and wakeup settings, please note that if locked the interrupt and wakeup settings can not
1347  * be updated until the next POR.
1348  *
1349  * @param base VBAT peripheral base address.
1350  */
VBAT_LockInterruptWakeupSettings(VBAT_Type * base)1351 static inline void VBAT_LockInterruptWakeupSettings(VBAT_Type *base)
1352 {
1353     base->LOCKA |= VBAT_LOCKA_LOCK_MASK;
1354 }
1355 
1356 /*!
1357  * @brief Set the default state of the WAKEUP_b pin output when no enabled wakeup source is asserted.
1358  *
1359  * @param base VBAT peripheral base address.
1360  * @param assert Used to set default state of the WAKEUP_b pin output:
1361  *          - \b true WAKEUP_b output state is logic one;
1362  *          - \b false WAKEUP_b output state is logic zero.
1363  */
VBAT_SetWakeupPinDefaultState(VBAT_Type * base,bool assert)1364 static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert)
1365 {
1366     if (assert)
1367     {
1368         base->WAKECFG |= VBAT_WAKECFG_OUT_MASK;
1369     }
1370     else
1371     {
1372         base->WAKECFG &= ~VBAT_WAKECFG_OUT_MASK;
1373     }
1374 }
1375 
1376 /*! @} */
1377 #endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */
1378 
1379 #if defined(__cplusplus)
1380 }
1381 #endif
1382 
1383 /*!
1384  * @}
1385  */
1386 #endif /* FSL_VBAT_H__ */
1387