1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_MMAU_H_
10 #define _FSL_MMAU_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup mmau
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 #define FSL_MMAU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
26 /*@}*/
27
28 /*******************************************************************************
29 * MMAU memory map *
30 ******************************************************************************/
31
32 /*!
33 * @name Registers decorated load/store addresses
34 * @{
35 */
36 #define MMAU__X0 0xF0004000UL /*!< Accumulator register X0 */
37 #define MMAU__X1 0xF0004004UL /*!< Accumulator register X1 */
38 #define MMAU__X2 0xF0004008UL /*!< Accumulator register X2 */
39 #define MMAU__X3 0xF000400CUL /*!< Accumulator register X3 */
40 #define MMAU__A0 0xF0004010UL /*!< Accumulator register A0 */
41 #define MMAU__A1 0xF0004014UL /*!< Accumulator register A1 */
42 #define MMAU__A10 0xF0004010UL /*!< Accumulator register pair A10 */
43
44 /*! @} */
45
46 /*!
47 * @name Unsigned integer instructions decorated load/store addresses
48 * @{
49 */
50 #define MMAU__REGRW 0xF0004000UL /*!< Registers RW */
51 #define MMAU__UMUL 0xF0004020UL /*!< A10=X2*X3 */
52 #define MMAU__UMULD 0xF0004040UL /*!< A10=X21*X3 */
53 #define MMAU__UMULDA 0xF0004060UL /*!< A10=A10*X3 */
54 #define MMAU__UMAC 0xF00040A0UL /*!< A10=X2*X3+A10 */
55 #define MMAU__UMACD 0xF00040C0UL /*!< A10=X21*X3+A10 */
56 #define MMAU__UMACDA 0xF00040E0UL /*!< A10=A10*X3+X21 */
57 #define MMAU__UDIV 0xF0004120UL /*!< X21/X3=A10 */
58 #define MMAU__UDIVD 0xF0004140UL /*!< A10=X2/X3 */
59 #define MMAU__UDIVDA 0xF0004160UL /*!< A10=X21/X3 */
60 #define MMAU__UDIVDD 0xF0004180UL /*!< A10=A10/X3 */
61 #define MMAU__UDIVDDA 0xF00041A0UL /*!< A10=A10/X32 */
62 #define MMAU__USQR 0xF0004220UL /*!< A10=SQR(X3) */
63 #define MMAU__USQRD 0xF0004240UL /*!< A10=SQR(X32) */
64 #define MMAU__USQRDA 0xF0004260UL /*!< A10=SQR(A10) */
65
66 /*! @} */
67
68 /*!
69 * @name Signed fractional instructions decorated load/store addresses
70 * @{
71 */
72 #define MMAU__QSQR 0xF00042A0UL /*!< A10=SQR(X3) */
73 #define MMAU__QSQRD 0xF00042C0UL /*!< A10=SQR(X32) */
74 #define MMAU__QSQRDA 0xF00042E0UL /*!< A10=SQR(A10) */
75 #define MMAU__QDIV 0xF0004320UL /*!< A10=X2/X3 */
76 #define MMAU__QDIVD 0xF0004340UL /*!< A10=X21/X3 */
77 #define MMAU__QDIVDA 0xF0004360UL /*!< A10=A10/X3 */
78 #define MMAU__QMUL 0xF0004420UL /*!< A10=X2*X3 */
79 #define MMAU__QMULD 0xF0004440UL /*!< A10=X21*X3 */
80 #define MMAU__QMULDA 0xF0004460UL /*!< A10=A10*X3 */
81 #define MMAU__QMAC 0xF00044A0UL /*!< A10=X2*X3+A10 */
82 #define MMAU__QMACD 0xF00044C0UL /*!< A10=X21*X3+A10 */
83 #define MMAU__QMACDA 0xF00044E0UL /*!< A10=A10*X3+X21 */
84
85 /*! @} */
86
87 /*!
88 * @name Signed integer instructions decorated load/store addresses
89 * @{
90 */
91 #define MMAU__SMUL 0xF0004620UL /*!< A10=X2*X3 */
92 #define MMAU__SMULD 0xF0004640UL /*!< A10=X21*X3 */
93 #define MMAU__SMULDA 0xF0004660UL /*!< A10=A10*X3 */
94 #define MMAU__SMAC 0xF00046A0UL /*!< A10=X2*X3+A10 */
95 #define MMAU__SMACD 0xF00046C0UL /*!< A10=X21*X3+A10 */
96 #define MMAU__SMACDA 0xF00046E0UL /*!< A10=A10*X3+X21 */
97 #define MMAU__SDIV 0xF0004720UL /*!< A10=X2/X3 */
98 #define MMAU__SDIVD 0xF0004740UL /*!< A10=X21/X3 */
99 #define MMAU__SDIVDA 0xF0004760UL /*!< A10=A10/X3 */
100 #define MMAU__SDIVDD 0xF0004780UL /*!< A10=X10/X32 */
101 #define MMAU__SDIVDDA 0xF00047A0UL /*!< A10=A10/X32 */
102
103 /*! @} */
104
105 /*!
106 * @name Auxiliary decorated load/store addresses
107 * @{
108 */
109 #define MMAU__SAT 0xF0004800UL /*!< Saturation */
110
111 /*! @} */
112
113 /*!
114 * @name Fractional Data Type
115 * @{
116 */
117 typedef short int frac16_t; /*!< Q0.15 fractional */
118 typedef long frac24_t; /*!< Q8.23 fractional */
119 typedef long frac32_t; /*!< Q0.31 fractional */
120 typedef long long frac48_t; /*!< Q16.47 fractional */
121 typedef long long frac64_t; /*!< Q0.63 fractional */
122
123 /*! @} */
124
125 /*!
126 * @brief MMAU interrupt configuration structure, default settings all disabled.
127 *
128 * This structure contains the settings for all of the MMAU interrupt configurations.
129 */
130 typedef enum _mmau_interrupt_enable
131 {
132 kMMAU_AccumOverflowInterruptEnable = (MMAU_CSR_QIE_MASK), /*!< Accumulation Overflow Enable */
133 kMMAU_OverflowInterruptEnable = (MMAU_CSR_VIE_MASK), /*!< Multiply or Divide overflow Enable */
134 kMMAU_DivideByZeroInterruptEnable = (MMAU_CSR_DZIE_MASK), /*!< Divide by Zero Enable */
135 } mmau_interrupt_enable_t;
136
137 /*! @brief MMAU interrupt and instruction flags */
138 typedef enum _mmau_interrupt_flag
139 {
140 kMMAU_AccumOverflowInterruptFlag = (MMAU_CSR_QIF_MASK), /*!< Accumulation Overflow Interrupt Flag */
141 kMMAU_OverflowInterruptFlag = (MMAU_CSR_VIF_MASK), /*!< Multiply or Divide overflow Interrupt Flag */
142 kMMAU_DivideByZeroInterruptFlag = (MMAU_CSR_DZIF_MASK), /*!< Divide by Zero Interrupt Flag */
143 } mmau_interrupt_flag_t;
144
145 /*! @brief MMAU interrupt and instruction flags */
146 typedef enum _mmau_instruction_flag
147 {
148 kMMAU_AccumOverflowInstructionFlag = (MMAU_CSR_Q_MASK), /*!< Accumulation Overflow */
149 kMMAU_OverflowInstructionFlag = (MMAU_CSR_V_MASK), /*!< Multiply or Divide overflow */
150 kMMAU_DivideByZeroInstructionFlag = (MMAU_CSR_DZ_MASK), /*!< Divide by Zero */
151 kMMAU_NegativeInstructionFlag = (MMAU_CSR_N_MASK), /*!< Signed calculation result is negative */
152 } mmau_instruction_flag_t;
153
154 /*******************************************************************************
155 * API
156 ******************************************************************************/
157 #if defined(__cplusplus)
158 extern "C" {
159 #endif
160
161 /*!
162 * @name MMAU Configure
163 * @{
164 */
165
166 /*!
167 * @brief Enable DMA for MMAU module.
168 *
169 * @param base MMAU peripheral address.
170 * @param enable Mode of DMA access
171 * - true Enable DMA access
172 * - false Disable DMA access
173 */
MMAU_EnableDMA(MMAU_Type * base,bool enable)174 static inline void MMAU_EnableDMA(MMAU_Type *base, bool enable)
175 {
176 if (enable)
177 {
178 base->CSR |= MMAU_CSR_DRE_MASK;
179 }
180 else
181 {
182 base->CSR &= ~(MMAU_CSR_DRE_MASK);
183 }
184 }
185 /*!
186 * @brief Enable supervisor only for MMAU module.
187 *
188 * @param base MMAU peripheral address.
189 * @param enable Mode of MMAU module can be access
190 * - true MMAU registers can only be access in Supervisor Mode.
191 * - false MMAU registers can be access in both User Mode or Supervisor Mode.
192 */
MMAU_EnableSupervisorOnly(MMAU_Type * base,bool enable)193 static inline void MMAU_EnableSupervisorOnly(MMAU_Type *base, bool enable)
194 {
195 if (enable)
196 {
197 base->CSR |= MMAU_CSR_SO_MASK;
198 }
199 else
200 {
201 base->CSR &= ~(MMAU_CSR_SO_MASK);
202 }
203 }
204
205 /*!
206 * @brief Set control/status register into reset state.
207 *
208 * This function sets control/status register to a known state. This state is
209 * defined in Reference Manual, which is power on reset value. This function must
210 * execute in a Supervisor Mode
211 * @param base MMAU peripheral address.
212 */
213 void MMAU_Reset(MMAU_Type *base);
214
215 /*! @} */
216
217 /*!
218 * @name MMAU Interrupt
219 * @{
220 */
221
222 /*!
223 * @brief Enable MMAU interrupts.
224 *
225 * This function enables the interrupts related to the mask.
226 * Example:
227 @code
228 MMAU_EnableInterrupts(MMAU, kMMAU_AccumOverflowInterruptEnable | kMMAU_DivideByZeroInterruptEnable);
229 @endcode
230 *
231 * @param base MMAU peripheral address.
232 * @param mask Mask of the interrupt enable to be written
233 * (kMMAU_AccumOverflowInterruptEnable|kMMAU_OverflowInterruptEnable|kMMAU_DivideByZeroInterruptEnable).
234 */
MMAU_EnableInterrupts(MMAU_Type * base,uint32_t mask)235 static inline void MMAU_EnableInterrupts(MMAU_Type *base, uint32_t mask)
236 {
237 base->CSR |= (mask & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInterruptEnable |
238 (uint32_t)kMMAU_DivideByZeroInterruptEnable));
239 }
240
241 /*!
242 * @brief Disable MMAU interrupts.
243 *
244 * This function disables the interrupt related to the mask.
245 * Example:
246 @code
247 MMAU_DisableInterrupts(MMAU, kMMAU_AccumOverflowInterruptEnable | kMMAU_DivideByZeroInterruptEnable);
248 @endcode
249 *
250 * @param base MMAU peripheral address.
251 * @param mask Mask of the interrupt enable to be written
252 * (kMMAU_AccumOverflowInterruptEnable|kMMAU_OverflowInterruptEnable|kMMAU_DivideByZeroInterruptEnable).
253 */
MMAU_DisableInterrupts(MMAU_Type * base,uint32_t mask)254 static inline void MMAU_DisableInterrupts(MMAU_Type *base, uint32_t mask)
255 {
256 base->CSR &= ~(mask & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInterruptEnable |
257 (uint32_t)kMMAU_DivideByZeroInterruptEnable));
258 }
259
260 /*!
261 * @brief Gets enabled interrupts.
262 *
263 * This function gets all interrupt values.
264 * Example:
265 @code
266 uint32_t flags = 0;
267 ...
268 flags = MMAU_GetEnabledInterrupts(MMAU);
269 if (flags & kMMAU_AccumOverflowInterruptEnable)
270 {
271 ...
272 }
273 @endcode
274 *
275 * @param base MMAU peripheral address.
276 *
277 * @return Combination of enabled interrupt
278 */
MMAU_GetEnabledInterrupts(MMAU_Type * base)279 static inline uint32_t MMAU_GetEnabledInterrupts(MMAU_Type *base)
280 {
281 return base->CSR & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInterruptEnable |
282 (uint32_t)kMMAU_DivideByZeroInterruptEnable);
283 }
284
285 /*!
286 * @brief Get interrupt flags.
287 *
288 * This function gets interrupt flags.
289 *
290 * @param base MMAU peripheral address.
291 *
292 * @return the mask of these interrupt flag bits.
293 */
MMAU_GetInterruptFlags(MMAU_Type * base)294 static inline uint32_t MMAU_GetInterruptFlags(MMAU_Type *base)
295 {
296 return base->CSR & ((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterruptFlag |
297 (uint32_t)kMMAU_DivideByZeroInterruptFlag);
298 }
299
300 /*!
301 * @brief Clears interrupt flags.
302 *
303 * This function clears the interrupt flags.
304 * Example, if you want to clear Overflow and DivideByZero interrupt flags:
305 @code
306 MMAU_ClearInterruptFlags(MMAU, kMMAU_OverflowInterruptFlag|kMMAU_DivideByZeroInterruptFlag);
307 @endcode
308 *
309 * @param base MMAU peripheral address.
310 * @param mask Mask of the asserted interrupt flags
311 * (kMMAU_AccumOverflowInterruptFlag|kMMAU_OverflowInterruptFlag|kMMAU_DivideByZeroInterruptFlag).
312 */
313 void MMAU_ClearInterruptFlags(MMAU_Type *base, uint32_t mask);
314
315 /*! @} */
316
317 /*!
318 * @name MMAU Instruction flag
319 * @{
320 */
321
322 /*!
323 * @brief Gets the instruction flags.
324 *
325 * This function gets the instruction flag. Instruction flags are
326 * updated by the MMAU after computation of each instruction.
327 * Example:
328 @code
329 uint32_t flags;
330 ...
331 flags = MMAU_GetInstructionFlags(MMAU);
332 if (flags & kMMAU_OverflowInstructionFlag)
333 {
334 ...
335 }
336 @endcode
337 *
338 * @param base MMAU peripheral address.
339 *
340 * @return Combination of all instruction flags.
341 */
MMAU_GetInstructionFlags(MMAU_Type * base)342 static inline uint32_t MMAU_GetInstructionFlags(MMAU_Type *base)
343 {
344 return base->CSR & ((uint32_t)kMMAU_AccumOverflowInstructionFlag | (uint32_t)kMMAU_OverflowInstructionFlag |
345 (uint32_t)kMMAU_DivideByZeroInstructionFlag | (uint32_t)kMMAU_NegativeInstructionFlag);
346 }
347
348 /*!
349 * @brief Sets the instruction flags.
350 *
351 * This function sets the instruction flags.
352 * Example:
353 @code
354 MMAU_SetInstructionFlags(MMAU, kMMAU_AccumOverflowInstructionFlag | kMMAU_NegativeInstructionFlag);
355 MMAU_SetInstructionFlags(MMAU, kMMAU_OverflowInstructionFlag | kMMAU_DivideByZeroInstructionFlag);
356 @endcode
357 *
358 * @param base MMAU peripheral address.
359 * @param mask Mask of the instruction flags to be written
360 *
361 (kMMAU_AccumOverflowInstructionFlag|kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag|kMMAU_NegativeInstructionFlag).
362 */
363 void MMAU_SetInstructionFlags(MMAU_Type *base, uint32_t mask);
364
365 /*!
366 * @brief Clears instruction flags.
367 *
368 * This function clears the instruction flags.
369 * Example, if you want to clear Overflow and DivideByZero instruction flags:
370 @code
371 MMAU_ClearInstructionFlags(MMAU, kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag);
372 @endcode
373 *
374 * @param base MMAU peripheral address.
375 * @param mask Mask of the asserted instruction flags
376 *
377 (kMMAU_AccumOverflowInstructionFlag|kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag|kMMAU_NegativeInstructionFlag).
378 */
379 void MMAU_ClearInstructionFlags(MMAU_Type *base, uint32_t mask);
380
381 /*! @} */
382
383 /*!
384 * @brief Gets hardware revision level.
385 *
386 * This function gets the hardware revision level of the MMAU. It returns HDR field
387 * of the control/status register.
388 *
389 * @param base MMAU peripheral address.
390 * @return uint32_t hardware revision level.
391 */
MMAU_GetHwRevCmd(MMAU_Type * base)392 static inline uint32_t MMAU_GetHwRevCmd(MMAU_Type *base)
393 {
394 return ((base->CSR & MMAU_CSR_HDR_MASK) >> MMAU_CSR_HDR_SHIFT);
395 }
396
397 /*!
398 * @name Unsigned Integer Operands
399 * @{
400 */
401
402 /*!
403 * @brief Load A10 accumulator register of the MMAU by 64-bit unsigned value.
404 *
405 * The ulda_d function loads A10 accumulator register of the MMAU
406 * by 64-bit unsigned value.
407 *
408 * @param dval uint64_t unsigned load value.
409 */
MMAU_ulda_d(register uint64_t dval)410 static inline void MMAU_ulda_d(register uint64_t dval)
411 {
412 *((uint64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;
413 }
414 /*!
415 * @brief Multiply two 32-bit unsigned values returning a 64-bit unsigned
416 * product.
417 *
418 * The @ref MMAU_d_umul_ll function multiplies two 32-bit unsigned values
419 * returning a 64-bit unsigned product.
420 * @param lval1 uint32_t unsigned value.
421 * @param lval2 uint32_t unsigned value.
422 * @return uint64_t unsigned value after multiply.
423 * @note Product is stored in A10 register of the MMAU for next computation.
424 */
MMAU_d_umul_ll(register uint32_t lval1,register uint32_t lval2)425 static inline uint64_t MMAU_d_umul_ll(register uint32_t lval1, register uint32_t lval2)
426 {
427 *((uint32_t volatile *)(MMAU__UMUL | MMAU__X2)) = lval1;
428 *((uint32_t volatile *)(MMAU__UMUL | MMAU__X3)) = lval2;
429 return *((uint64_t volatile *)(MMAU__UMUL | MMAU__A10));
430 }
431
432 /*!
433 * @brief Multiply 64-bit unsigned value with 32-bit unsigned value returning
434 * a 64-bit unsigned product.
435 *
436 * The @ref MMAU_d_umul_dl function multiplies 64-bit unsigned value with
437 * 32-bit unsigned value returning a 64-bit unsigned product.
438 * @param dval uint64_t unsigned value.
439 * @param lval uint32_t unsigned value.
440 * @return uint64_t unsigned value after multiply.
441 * @note Product is stored in A10 register of the MMAU for next computation.
442 */
MMAU_d_umul_dl(register uint64_t dval,register uint32_t lval)443 static inline uint64_t MMAU_d_umul_dl(register uint64_t dval, register uint32_t lval)
444 {
445 *((uint64_t volatile *)(MMAU__UMULD | MMAU__X1)) = dval;
446 *((uint32_t volatile *)(MMAU__UMULD | MMAU__X3)) = lval;
447 return *((uint64_t volatile *)(MMAU__UMULD | MMAU__A10));
448 }
449
450 /*!
451 * @brief Saturating multiply 64-bit unsigned value with 32-bit unsigned value
452 * returning saturated 64-bit unsigned product.
453 *
454 * The @ref MMAU_d_umuls_dl function multiplies 64-bit unsigned value with
455 * 32-bit unsigned value returning saturated 64-bit unsigned product.
456 * @param dval uint64_t unsigned value.
457 * @param lval uint32_t unsigned value.
458 * @return uint64_t unsigned value after multiply.
459 * @note Saturated product is stored in A10 register of the MMAU for next
460 * computation.
461 */
MMAU_d_umuls_dl(register uint64_t dval,register uint32_t lval)462 static inline uint64_t MMAU_d_umuls_dl(register uint64_t dval, register uint32_t lval)
463 {
464 *((uint64_t volatile *)(MMAU__UMULD | MMAU__X1 | MMAU__SAT)) = dval;
465 *((uint32_t volatile *)(MMAU__UMULD | MMAU__X3 | MMAU__SAT)) = lval;
466 return *((uint64_t volatile *)(MMAU__UMULD | MMAU__A10 | MMAU__SAT));
467 }
468
469 /*!
470 * @brief Multiply 32-bit unsigned value with 64-bit unsigned value stored in
471 * the A10 register of the MMAU returning a 64-bit unsigned product.
472 *
473 * The @ref MMAU_d_umula_l function multiplies 32-bit unsigned value with
474 * 64-bit unsigned value stored in the A10 register of the MMAU
475 * returning a 64-bit unsigned product.
476 * @param lval uint32_t unsigned value.
477 * @return uint64_t unsigned value after multiply.
478 * @note Product is stored in A10 register of the MMAU for next computation.
479 */
MMAU_d_umula_l(register uint32_t lval)480 static inline uint64_t MMAU_d_umula_l(register uint32_t lval)
481 {
482 *((uint32_t volatile *)(MMAU__UMULDA | MMAU__X3)) = lval;
483 return *((uint64_t volatile *)(MMAU__UMULDA | MMAU__A10));
484 }
485
486 /*!
487 * @brief Saturating multiply 32-bit unsigned value with 64-bit unsigned value
488 * stored in the A10 register of the MMAU returning saturated 64-bit unsigned
489 * product.
490 *
491 * The @ref MMAU_d_umulas_l function multiplies 32-bit unsigned value with
492 * 64-bit unsigned value stored in the A10 register of the MMAU
493 * returning saturated 64-bit unsigned product.
494 * @param lval uint32_t unsigned value.
495 * @return uint64_t unsigned value after multiply.
496 * @note Saturated product is stored in A10 register of the MMAU for next
497 * computation.
498 */
MMAU_d_umulas_l(register uint32_t lval)499 static inline uint64_t MMAU_d_umulas_l(register uint32_t lval)
500 {
501 *((uint32_t volatile *)(MMAU__UMULDA | MMAU__X3 | MMAU__SAT)) = lval;
502 return *((uint64_t volatile *)(MMAU__UMULDA | MMAU__A10 | MMAU__SAT));
503 }
504
505 /*!
506 * @brief Multiply two 32-bit unsigned values and add product with value
507 * stored in the A10 register of the MMAU returning a 64-bit unsigned
508 * A10 register value.
509 *
510 * The @ref MMAU_d_umac_ll function multiplies two 32-bit unsigned values
511 * and add product with value stored in the A10 register of the MMAU
512 * returning a 64-bit unsigned A10 register value.
513 * @param lval1 uint32_t unsigned value.
514 * @param lval2 uint32_t unsigned value.
515 * @return uint64_t unsigned value after multiply.
516 * @note Product is stored in A10 register of the MMAU for next computation.
517 */
MMAU_d_umac_ll(register uint32_t lval1,register uint32_t lval2)518 static inline uint64_t MMAU_d_umac_ll(register uint32_t lval1, register uint32_t lval2)
519 {
520 *((uint32_t volatile *)(MMAU__UMAC | MMAU__X2)) = lval1;
521 *((uint32_t volatile *)(MMAU__UMAC | MMAU__X3)) = lval2;
522 return *((uint64_t volatile *)(MMAU__UMAC | MMAU__A10));
523 }
524
525 /*!
526 * @brief Saturating multiply two 32-bit unsigned values and add product with
527 * value stored in the A10 register of the MMAU returning a 64-bit unsigned
528 * A10 register value.
529 *
530 * The @ref MMAU_d_umacs_ll function multiplies two 32-bit unsigned values
531 * and add product with value stored in the A10 register of the MMAU
532 * returning saturated 64-bit unsigned A10 register value.
533 * @param lval1 uint32_t unsigned value.
534 * @param lval2 uint32_t unsigned value.
535 * @return uint64_t unsigned value after multiply.
536 * @note Saturated product is stored in A10 register of the MMAU for next
537 * computation.
538 */
MMAU_d_umacs_ll(register uint32_t lval1,register uint32_t lval2)539 static inline uint64_t MMAU_d_umacs_ll(register uint32_t lval1, register uint32_t lval2)
540 {
541 *((uint32_t volatile *)(MMAU__UMAC | MMAU__X2 | MMAU__SAT)) = lval1;
542 *((uint32_t volatile *)(MMAU__UMAC | MMAU__X3 | MMAU__SAT)) = lval2;
543 return *((uint64_t volatile *)(MMAU__UMAC | MMAU__A10 | MMAU__SAT));
544 }
545
546 /*!
547 * @brief Multiply 64-bit unsigned value with 32-bit unsigned value and add
548 * product with value stored in the A10 register of the MMAU
549 * returning a 64-bit unsigned A10 register value.
550 *
551 * @details The @ref MMAU_d_umac_dl function multiplies 64-bit unsigned value with
552 * 32-bit unsigned value and add product with value stored in the
553 * A10 register of the MMAU returning a 64-bit unsigned A10 register
554 * value.
555 * @param dval uint64_t unsigned value.
556 * @param lval uint32_t unsigned value.
557 * @return uint64_t unsigned value after multiply.
558 * @note Product is stored in A10 register of the MMAU for next computation.
559 */
MMAU_d_umac_dl(register uint64_t dval,register uint32_t lval)560 static inline uint64_t MMAU_d_umac_dl(register uint64_t dval, register uint32_t lval)
561 {
562 *((uint64_t volatile *)(MMAU__UMACD | MMAU__X1)) = dval;
563 *((uint32_t volatile *)(MMAU__UMACD | MMAU__X3)) = lval;
564 return *((uint64_t volatile *)(MMAU__UMACD | MMAU__A10));
565 }
566
567 /*!
568 * @brief Saturating multiply 64-bit unsigned value with 32-bit unsigned value
569 * and add product with value stored in the A10 register of the MMAU
570 * returning saturated 64-bit unsigned A10 register value.
571 *
572 * @details The @ref MMAU_d_umacs_dl function multiplies 64-bit unsigned value with
573 * 32-bit unsigned value and add product with value stored in the
574 * A10 register of the MMAU returning saturated 64-bit unsigned A10
575 * register value.
576 * @param dval uint64_t unsigned value.
577 * @param lval uint32_t unsigned value.
578 * @return uint64_t unsigned value after multiply.
579 * @note Saturated product is stored in A10 register of the MMAU for next
580 * computation.
581 */
MMAU_d_umacs_dl(register uint64_t dval,register uint32_t lval)582 static inline uint64_t MMAU_d_umacs_dl(register uint64_t dval, register uint32_t lval)
583 {
584 *((uint64_t volatile *)(MMAU__UMACD | MMAU__X1 | MMAU__SAT)) = dval;
585 *((uint32_t volatile *)(MMAU__UMACD | MMAU__X3 | MMAU__SAT)) = lval;
586 return *((uint64_t volatile *)(MMAU__UMACD | MMAU__A10 | MMAU__SAT));
587 }
588
589 /*!
590 * @brief Multiply 32-bit unsigned value by value stored in the A10 register
591 * of the MMAU and add product with 64-bit unsigned value returning
592 * a 64-bit unsigned A10 register value.
593 *
594 * @details The @ref MMAU_d_umaca_dl function multiplies 32-bit unsigned value by
595 * value stored in the A10 register of the MMAU and add product with
596 * 64-bit unsigned value returning a 64-bit unsigned A10 register
597 * value.
598 * @param dval uint64_t unsigned value.
599 * @param lval uint32_t unsigned value.
600 * @return uint64_t unsigned value after multiply.
601 * @note Product is stored in A10 register of the MMAU for next computation.
602 */
MMAU_d_umaca_dl(register uint64_t dval,register uint32_t lval)603 static inline uint64_t MMAU_d_umaca_dl(register uint64_t dval, register uint32_t lval)
604 {
605 *((uint64_t volatile *)(MMAU__UMACDA | MMAU__X1)) = dval;
606 *((uint32_t volatile *)(MMAU__UMACDA | MMAU__X3)) = lval;
607 return *((uint64_t volatile *)(MMAU__UMACDA | MMAU__A10));
608 }
609
610 /*!
611 * @brief Saturating multiply 32-bit unsigned value by value stored in the A10
612 * register of the MMAU and add product with 64-bit unsigned value returning
613 * a saturated 64-bit unsigned A10 register value.
614 *
615 * @details The @ref MMAU_d_umacas_dl function multiplies 32-bit unsigned value by
616 * value stored in the A10 register of the MMAU and add product with
617 * 64-bit unsigned value returning saturated 64-bit unsigned A10
618 * register value.
619 * @param dval uint64_t unsigned value.
620 * @param lval uint32_t unsigned value.
621 * @return uint64_t unsigned value after multiply.
622 * @note Saturated product is stored in A10 register of the MMAU for next
623 * computation.
624 */
MMAU_d_umacas_dl(register uint64_t dval,register uint32_t lval)625 static inline uint64_t MMAU_d_umacas_dl(register uint64_t dval, register uint32_t lval)
626 {
627 *((uint64_t volatile *)(MMAU__UMACDA | MMAU__X1 | MMAU__SAT)) = dval;
628 *((uint32_t volatile *)(MMAU__UMACDA | MMAU__X3 | MMAU__SAT)) = lval;
629 return *((uint64_t volatile *)(MMAU__UMACDA | MMAU__A10 | MMAU__SAT));
630 }
631
632 /*!
633 * @brief Divide two 32-bit unsigned values returning a 32-bit unsigned
634 * quotient.
635 *
636 * @details The @ref MMAU_l_udiv_ll function divides two 32-bit unsigned values
637 * returning a 32-bit unsigned quotient.
638 * @param lnum uint32_t unsigned divisor value.
639 * @param lden uint32_t unsigned dividend value.
640 * @return uint32_t unsigned quotient value.
641 * @note Quotient is stored in A0 register of the MMAU for next computation.
642 */
MMAU_l_udiv_ll(register uint32_t lnum,register uint32_t lden)643 static inline uint32_t MMAU_l_udiv_ll(register uint32_t lnum, register uint32_t lden)
644 {
645 *((uint32_t volatile *)(MMAU__UDIV | MMAU__X2)) = lnum;
646 *((uint32_t volatile *)(MMAU__UDIV | MMAU__X3)) = lden;
647 return *((uint32_t volatile *)(MMAU__UDIV | MMAU__A0));
648 }
649
650 /*!
651 * @brief Divide 64-bit unsigned value by 32-bit unsigned value returning a
652 * 64-bit unsigned quotient.
653 *
654 * @details The @ref MMAU_d_udiv_dl function divides 64-bit unsigned value by 32-bit
655 * unsigned value returning a 64-bit unsigned quotient.
656 * @param dnum uint64_t unsigned divisor value.
657 * @param lden uint32_t unsigned dividend value.
658 * @return uint64_t unsigned quotient value.
659 * @note Quotient is stored in A10 register of the MMAU for next computation.
660 */
MMAU_d_udiv_dl(register uint64_t dnum,register uint32_t lden)661 static inline uint64_t MMAU_d_udiv_dl(register uint64_t dnum, register uint32_t lden)
662 {
663 *((uint64_t volatile *)(MMAU__UDIVD | MMAU__X1)) = dnum;
664 *((uint32_t volatile *)(MMAU__UDIVD | MMAU__X3)) = lden;
665 return *((uint64_t volatile *)(MMAU__UDIVD | MMAU__A10));
666 }
667
668 /*!
669 * @brief Divide two 64-bit unsigned values returning a 64-bit unsigned
670 * quotient.
671 *
672 * @details The @ref MMAU_d_udiv_dd function divides two 64-bit unsigned values
673 * returning a 64-bit unsigned quotient.
674 * @param dnum uint64_t unsigned divisor value.
675 * @param dden uint64_t unsigned dividend value.
676 * @return uint64_t unsigned quotient value.
677 * @note Quotient is stored in A10 register of the MMAU for next computation.
678 */
MMAU_d_udiv_dd(register uint64_t dnum,register uint64_t dden)679 static inline uint64_t MMAU_d_udiv_dd(register uint64_t dnum, register uint64_t dden)
680 {
681 *((uint64_t volatile *)(MMAU__UDIVDD | MMAU__X0)) = dnum;
682 *((uint64_t volatile *)(MMAU__UDIVDD | MMAU__X2)) = dden;
683 return *((uint64_t volatile *)(MMAU__UDIVDD | MMAU__A10));
684 }
685
686 /*!
687 * @brief Divide 32-bit unsigned value stored in the A10 register of the MMAU
688 * by 32-bit unsigned value returning a 64-bit unsigned quotient.
689 *
690 * @details The @ref MMAU_d_udiva_l function divides 64-bit unsigned value stored in
691 * the A10 register of the MMAU by 32-bit unsigned value returning
692 * a 64-bit unsigned quotient.
693 * @param lden1 uint32_t unsigned dividend value.
694 * @return uint64_t unsigned quotient value.
695 * @note Quotient is stored in A10 register of the MMAU for next computation.
696 */
MMAU_d_udiva_l(register uint32_t lden1)697 static inline uint64_t MMAU_d_udiva_l(register uint32_t lden1)
698 {
699 *((uint32_t volatile *)(MMAU__UDIVDA | MMAU__X3)) = lden1;
700 return *((uint64_t volatile *)(MMAU__UDIVDA | MMAU__A10));
701 }
702
703 /*!
704 * @brief Divide 64-bit unsigned value stored in the A10 register of the MMAU
705 * by 64-bit unsigned value returning a 64-bit unsigned quotient.
706 *
707 * @details The @ref MMAU_d_udiva_d function divides 64-bit unsigned value stored in
708 * the A10 register of the MMAU by 64-bit unsigned value returning
709 * a 64-bit unsigned quotient.
710 * @param dden1 uint64_t unsigned dividend value.
711 * @return uint64_t unsigned quotient value.
712 * @note Quotient is stored in A10 register of the MMAU for next computation.
713 */
MMAU_d_udiva_d(register uint64_t dden1)714 static inline uint64_t MMAU_d_udiva_d(register uint64_t dden1)
715 {
716 *((uint64_t volatile *)(MMAU__UDIVDDA | MMAU__X2)) = dden1;
717 return *((uint64_t volatile *)(MMAU__UDIVDDA | MMAU__A10));
718 }
719
720 /*!
721 * @brief Compute and return a 32-bit unsigned square root of the 32-bit
722 * unsigned radicand.
723 *
724 * @details The @ref MMAU_l_usqr_l function computes and returns a 32-bit unsigned
725 * square root of the 32-bit unsigned radicand.
726 * @param lrad uint32_t unsigned radicand.
727 * @return uint32_t unsigned square root.
728 * @note Quotient is stored in A0 register of the MMAU for next computation.
729 */
MMAU_l_usqr_l(register uint32_t lrad)730 static inline uint32_t MMAU_l_usqr_l(register uint32_t lrad)
731 {
732 *((uint32_t volatile *)(MMAU__USQR | MMAU__X3)) = lrad;
733 return *((uint32_t volatile *)(MMAU__USQR | MMAU__A0));
734 }
735
736 /*!
737 * @brief Compute and return a 32-bit unsigned square root of the 64-bit
738 * unsigned radicand.
739 *
740 * @details The @ref MMAU_l_usqr_d function computes and returns a 32-bit unsigned
741 * square root of the 64-bit unsigned radicand.
742 * @param drad uint64_t unsigned radicand.
743 * @return uint32_t unsigned square root.
744 * @note Quotient is stored in A0 register of the MMAU for next computation.
745 */
MMAU_l_usqr_d(register uint64_t drad)746 static inline uint32_t MMAU_l_usqr_d(register uint64_t drad)
747 {
748 *((uint64_t volatile *)(MMAU__USQRD | MMAU__X2)) = drad;
749 return *((uint32_t volatile *)(MMAU__USQRD | MMAU__A0));
750 }
751
752 /*!
753 * @brief Compute and return a 16-bit unsigned square root of the 32-bit
754 * unsigned radicand.
755 *
756 * @details The @ref MMAU_s_usqr_l function computes and returns a 16-bit unsigned
757 * square root of the 32-bit unsigned radicand.
758 * @param lrad uint32 unsigned radicand.
759 * @return uint16 unsigned square root.
760 * @note Square root is stored in A0 register of the MMAU for next
761 * computation.
762 */
MMAU_s_usqr_l(register uint32_t lrad)763 static inline uint16_t MMAU_s_usqr_l(register uint32_t lrad)
764 {
765 *((uint32_t volatile *)(MMAU__USQR | MMAU__X3)) = lrad;
766 return (uint16_t)(*((uint32_t volatile *)(MMAU__USQR | MMAU__A0)));
767 }
768
769 /*!
770 * @brief Compute and return a 32-bit unsigned square root of the radicand
771 * stored in the A10 register of the MMAU.
772 *
773 * @details The @ref MMAU_l_usqra function computes and returns a 32-bit unsigned
774 * square root of the radicand stored in the A10 register of the MMAU.
775 * @return uint32_t unsigned square root.
776 * @note Quotient is stored in A0 register of the MMAU for next computation.
777 */
MMAU_l_usqra(void)778 static inline uint32_t MMAU_l_usqra(void)
779 {
780 return *((uint32_t volatile *)(MMAU__USQRDA | MMAU__A0));
781 }
782 /*! @} */
783
784 /*!
785 * @name Signed Integer Operands
786 * @{
787 */
788
789 /*!
790 * @brief Load A10 accumulator register of the MMAU by 64-bit integer value.
791 *
792 * @details The @ref MMAU_slda_d function loads A10 accumulator register of the MMAU
793 * by 64-bit integer value.
794 * @param dval int64_t integer value.
795 */
MMAU_slda_d(register int64_t dval)796 static inline void MMAU_slda_d(register int64_t dval)
797 {
798 *((int64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;
799 }
800 /*!
801 * @brief Multiply two 32-bit integer values returning a 64-bit integer
802 * product.
803 *
804 * @details The @ref MMAU_d_smul_ll function multiplies two 32-bit integer values
805 * returning a 64-bit integer product.
806 * @param lval1 int32_t integer value.
807 * @param lval2 int32_t integer value.
808 * @return int64_t integer value after multiply.
809 * @note Product is stored in A10 register of the MMAU for next computation.
810 */
MMAU_d_smul_ll(register int32_t lval1,register int32_t lval2)811 static inline int64_t MMAU_d_smul_ll(register int32_t lval1, register int32_t lval2)
812 {
813 *((int32_t volatile *)(MMAU__SMUL | MMAU__X2)) = lval1;
814 *((int32_t volatile *)(MMAU__SMUL | MMAU__X3)) = lval2;
815 return *((int64_t volatile *)(MMAU__SMUL | MMAU__A10));
816 }
817
818 /*!
819 * @brief Multiply 64-bit integer value with 32-bit integer value returning a
820 * 64-bit integer product.
821 *
822 * @details The @ref MMAU_d_smul_dl function multiplies 64-bit integer value with
823 * 32-bit integer value returning a 64-bit integer product.
824 * @param dval int64_t integer value.
825 * @param lval int32_t integer value.
826 * @return int64_t integer value after multiply.
827 * @note Product is stored in A10 register of the MMAU for next computation.
828 */
MMAU_d_smul_dl(register int64_t dval,register int32_t lval)829 static inline int64_t MMAU_d_smul_dl(register int64_t dval, register int32_t lval)
830 {
831 *((int64_t volatile *)(MMAU__SMULD | MMAU__X1)) = dval;
832 *((int32_t volatile *)(MMAU__SMULD | MMAU__X3)) = lval;
833 return *((int64_t volatile *)(MMAU__SMULD | MMAU__A10));
834 }
835
836 /*!
837 * @brief Saturating multiply 64-bit integer value with 32-bit integer value
838 * returning saturated 64-bit integer product.
839 *
840 * @details The @ref MMAU_d_smuls_dl function multiplies 64-bit integer value with
841 * 32-bit integer value returning saturated 64-bit integer product.
842 * @param dval int64_t integer value.
843 * @param lval int32_t integer value.
844 * @return int64_t integer value after multiply.
845 * @note Saturated product is stored in A10 register of the MMAU for next
846 * computation.
847 */
MMAU_d_smuls_dl(register int64_t dval,register int32_t lval)848 static inline int64_t MMAU_d_smuls_dl(register int64_t dval, register int32_t lval)
849 {
850 *((int64_t volatile *)(MMAU__SMULD | MMAU__X1 | MMAU__SAT)) = dval;
851 *((int32_t volatile *)(MMAU__SMULD | MMAU__X3 | MMAU__SAT)) = lval;
852 return *((int64_t volatile *)(MMAU__SMULD | MMAU__A10 | MMAU__SAT));
853 }
854
855 /*!
856 * @brief Multiply 32-bit integer value with 64-bit integer value stored in
857 * the A10 register of the MMAU returning a 64-bit integer product.
858 *
859 * @details The @ref MMAU_d_smula_l function multiplies 32-bit integer value with
860 * 64-bit integer value stored in the A10 register of the MMAU
861 * returning a 64-bit integer product.
862 * @param lval int32_t integer value.
863 * @return int64_t integer value after multiply.
864 * @note Product is stored in A10 register of the MMAU for next computation.
865 */
MMAU_d_smula_l(register int32_t lval)866 static inline int64_t MMAU_d_smula_l(register int32_t lval)
867 {
868 *((int32_t volatile *)(MMAU__SMULDA | MMAU__X3)) = lval;
869 return *((int64_t volatile *)(MMAU__SMULDA | MMAU__A10));
870 }
871
872 /*!
873 * @brief Saturating multiply 32-bit integer value with 64-bit integer value
874 * stored in the A10 register of the MMAU returning saturated 64-bit integer
875 * product.
876 *
877 * @details The @ref MMAU_d_smulas_l function multiplies 32-bit integer value with
878 * 64-bit integer value stored in the A10 register of the MMAU
879 * returning saturated 64-bit integer product.
880 * @param lval int32_t integer value.
881 * @return int64_t integer value after multiply.
882 * @note Saturated product is stored in A10 register of the MMAU for next
883 * computation.
884 */
MMAU_d_smulas_l(register int32_t lval)885 static inline int64_t MMAU_d_smulas_l(register int32_t lval)
886 {
887 *((int32_t volatile *)(MMAU__SMULDA | MMAU__X3 | MMAU__SAT)) = lval;
888 return *((int64_t volatile *)(MMAU__SMULDA | MMAU__A10 | MMAU__SAT));
889 }
890
891 /*!
892 * @brief Multiply two 32-bit integer values and add product with value stored
893 * in the A10 register of the MMAU returning a 64-bit integer
894 * A10 register value.
895 *
896 * @details The @ref MMAU_d_smac_ll function multiplies two 32-bit integer values and
897 * add product with value stored in the A10 register of the MMAU
898 * returning a 64-bit integer A10 register value.
899 * @param lval1 int32_t integer value.
900 * @param lval2 int32_t integer value.
901 * @return int64_t integer value after multiply.
902 * @note Product is stored in A10 register of the MMAU for next computation.
903 */
MMAU_d_smac_ll(register int32_t lval1,register int32_t lval2)904 static inline int64_t MMAU_d_smac_ll(register int32_t lval1, register int32_t lval2)
905 {
906 *((int32_t volatile *)(MMAU__SMAC | MMAU__X2)) = lval1;
907 *((int32_t volatile *)(MMAU__SMAC | MMAU__X3)) = lval2;
908 return *((int64_t volatile *)(MMAU__SMAC | MMAU__A10));
909 }
910
911 /*!
912 * @brief Saturating multiply two 32-bit integer values and add product with
913 * value stored in the A10 register of the MMAU returning a 64-bit integer
914 * A10 register value.
915 *
916 * @details The @ref MMAU_d_smacs_ll function multiplies two 32-bit integer values
917 * and add product with value stored in the A10 register of the MMAU
918 * returning saturated 64-bit integer A10 register value.
919 * @param lval1 int32_t integer value.
920 * @param lval2 int32_t integer value.
921 * @return int64_t integer value after multiply.
922 * @note Saturated product is stored in A10 register of the MMAU for next
923 * computation.
924 */
MMAU_d_smacs_ll(register int32_t lval1,register int32_t lval2)925 static inline int64_t MMAU_d_smacs_ll(register int32_t lval1, register int32_t lval2)
926 {
927 *((int32_t volatile *)(MMAU__SMAC | MMAU__X2 | MMAU__SAT)) = lval1;
928 *((int32_t volatile *)(MMAU__SMAC | MMAU__X3 | MMAU__SAT)) = lval2;
929 return *((int64_t volatile *)(MMAU__SMAC | MMAU__A10 | MMAU__SAT));
930 }
931
932 /*!
933 * @brief Multiply 64-bit integer value with 32-bit integer value and add
934 * product with value stored in the A10 register of the MMAU
935 * returning a 64-bit integer A10 register value.
936 *
937 * @details The @ref MMAU_d_smac_dl function multiplies 64-bit integer value with
938 * 32-bit integer value and add product with value stored in the
939 * A10 register of the MMAU returning a 64-bit integer A10 register
940 * value.
941 * @param dval int64_t integer value.
942 * @param lval int32_t integer value.
943 * @return int64_t integer value after multiply.
944 * @note Product is stored in A10 register of the MMAU for next computation.
945 */
MMAU_d_smac_dl(register int64_t dval,register int32_t lval)946 static inline int64_t MMAU_d_smac_dl(register int64_t dval, register int32_t lval)
947 {
948 *((int64_t volatile *)(MMAU__SMACD | MMAU__X1)) = dval;
949 *((int32_t volatile *)(MMAU__SMACD | MMAU__X3)) = lval;
950 return *((int64_t volatile *)(MMAU__SMACD | MMAU__A10));
951 }
952
953 /*!
954 * @brief Saturating multiply 64-bit integer value with 32-bit integer value
955 * and add product with value stored in the A10 register of the MMAU
956 * returning saturated 64-bit integer A10 register value.
957 *
958 * @details The @ref MMAU_d_smacs_dl function multiplies 64-bit integer value with
959 * 32-bit integer value and add product with value stored in the
960 * A10 register of the MMAU returning saturated 64-bit integer A10
961 * register value.
962 * @param dval int64_t integer value.
963 * @param lval int32_t integer value.
964 * @return int64_t integer value after multiply.
965 * @note Saturated product is stored in A10 register of the MMAU for next
966 * computation. If saturation occurs, the instruction sets the
967 * accumulation overflow (Q) and multiply or divide overflow (V) flags
968 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
969 */
MMAU_d_smacs_dl(register int64_t dval,register int32_t lval)970 static inline int64_t MMAU_d_smacs_dl(register int64_t dval, register int32_t lval)
971 {
972 *((int64_t volatile *)(MMAU__SMACD | MMAU__X1 | MMAU__SAT)) = dval;
973 *((int32_t volatile *)(MMAU__SMACD | MMAU__X3 | MMAU__SAT)) = lval;
974 return *((int64_t volatile *)(MMAU__SMACD | MMAU__A10 | MMAU__SAT));
975 }
976
977 /*!
978 * @brief Multiply 32-bit integer value by value stored in the A10 register of
979 * the MMAU and add product with 64-bit integer value returning
980 * a 64-bit integer A10 register value.
981 *
982 * @details The @ref MMAU_d_smaca_dl function multiplies 32-bit integer value by
983 * value stored in the A10 register of the MMAU and add product with
984 * 64-bit integer value returning a 64-bit integer A10 register value.
985 * @param dval int64_t integer value.
986 * @param lval int32_t integer value.
987 * @return int64_t integer value after multiply.
988 * @note Product is stored in A10 register of the MMAU for next computation.
989 */
MMAU_d_smaca_dl(register int64_t dval,register int32_t lval)990 static inline int64_t MMAU_d_smaca_dl(register int64_t dval, register int32_t lval)
991 {
992 *((int64_t volatile *)(MMAU__SMACDA | MMAU__X1)) = dval;
993 *((int32_t volatile *)(MMAU__SMACDA | MMAU__X3)) = lval;
994 return *((int64_t volatile *)(MMAU__SMACDA | MMAU__A10));
995 }
996
997 /*!
998 * @brief Saturating multiply 32-bit integer value by value stored in the A10
999 * register of the MMAU and add product with 64-bit integer value returning
1000 * a saturated 64-bit integer A10 register value.
1001 *
1002 * @details The @ref MMAU_d_smacas_dl function multiplies 32-bit integer value by
1003 * value stored in the A10 register of the MMAU and add product with
1004 * 64-bit integer value returning saturated 64-bit integer A10 register
1005 * value.
1006 * @param dval int64_t integer value.
1007 * @param lval int32_t integer value.
1008 * @return int64_t integer value after multiply.
1009 * @note Saturated product is stored in A10 register of the MMAU for next
1010 * computation. If saturation occurs, the instruction sets the
1011 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1012 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1013 */
MMAU_d_smacas_dl(register int64_t dval,register int32_t lval)1014 static inline int64_t MMAU_d_smacas_dl(register int64_t dval, register int32_t lval)
1015 {
1016 *((int64_t volatile *)(MMAU__SMACDA | MMAU__X1 | MMAU__SAT)) = dval;
1017 *((int32_t volatile *)(MMAU__SMACDA | MMAU__X3 | MMAU__SAT)) = lval;
1018 return *((int64_t volatile *)(MMAU__SMACDA | MMAU__A10 | MMAU__SAT));
1019 }
1020
1021 /*!
1022 * @brief Divide two 32-bit integer values returning a 32-bit integer
1023 * quotient.
1024 *
1025 * @details The @ref MMAU_l_sdiv_ll function divides two 32-bit integer values
1026 * returning a 32-bit integer quotient.
1027 * @param lnum int32_t integer divisor value.
1028 * @param lden int32_t integer dividend value.
1029 * @return int32_t integer quotient value.
1030 * @note Quotient is stored in A0 register of the MMAU for next computation.
1031 */
MMAU_l_sdiv_ll(register int32_t lnum,register int32_t lden)1032 static inline int32_t MMAU_l_sdiv_ll(register int32_t lnum, register int32_t lden)
1033 {
1034 *((int32_t volatile *)(MMAU__SDIV | MMAU__X2)) = lnum;
1035 *((int32_t volatile *)(MMAU__SDIV | MMAU__X3)) = lden;
1036 return *((int32_t volatile *)(MMAU__SDIV | MMAU__A0));
1037 }
1038
1039 /*!
1040 * @brief Divide two 32-bit integer values returning a 32-bit integer
1041 * quotient.
1042 *
1043 * @details The @ref MMAU_l_sdivs_ll function divides two 32-bit integer values
1044 * returning a 32-bit integer quotient.
1045 * @param lnum int32_t integer divisor value.
1046 * @param lden int32_t integer dividend value.
1047 * @return int32_t integer quotient value.
1048 * @note Saturated quotient is stored in A0 register of the MMAU for
1049 * next computation.
1050 */
MMAU_l_sdivs_ll(register int32_t lnum,register int32_t lden)1051 static inline int32_t MMAU_l_sdivs_ll(register int32_t lnum, register int32_t lden)
1052 {
1053 *((int32_t volatile *)(MMAU__SDIV | MMAU__X2 | MMAU__SAT)) = lnum;
1054 *((int32_t volatile *)(MMAU__SDIV | MMAU__X3 | MMAU__SAT)) = lden;
1055 return *((int32_t volatile *)(MMAU__SDIV | MMAU__A0 | MMAU__SAT));
1056 }
1057
1058 /*!
1059 * @brief Divide 64-bit integer value by 32-bit integer value returning a
1060 * 64-bit integer quotient.
1061 *
1062 * @details The @ref MMAU_d_sdiv_dl function divides 64-bit integer value by 32-bit
1063 * integer value returning a 64-bit integer quotient.
1064 * @param dnum int64_t integer divisor value.
1065 * @param lden int32_t integer dividend value.
1066 * @return int64_t integer quotient value.
1067 * @note Quotient is stored in A10 register of the MMAU for next computation.
1068 */
MMAU_d_sdiv_dl(register int64_t dnum,register int32_t lden)1069 static inline int64_t MMAU_d_sdiv_dl(register int64_t dnum, register int32_t lden)
1070 {
1071 *((int64_t volatile *)(MMAU__SDIVD | MMAU__X1)) = dnum;
1072 *((int32_t volatile *)(MMAU__SDIVD | MMAU__X3)) = lden;
1073 return *((int64_t volatile *)(MMAU__SDIVD | MMAU__A10));
1074 }
1075
1076 /*!
1077 * @brief Divide 64-bit integer value by 32-bit integer value returning a
1078 * 64-bit integer quotient.
1079 *
1080 * @details The @ref MMAU_d_sdivs_dl function divides 64-bit integer value by 32-bit
1081 * integer value returning a 64-bit integer quotient.
1082 * @param dnum int64_t integer divisor value.
1083 * @param lden int32_t integer dividend value.
1084 * @return int64_t integer quotient value.
1085 * @note Saturated quotient is stored in A10 register of the MMAU for
1086 * next computation.
1087 */
MMAU_d_sdivs_dl(register int64_t dnum,register int32_t lden)1088 static inline int64_t MMAU_d_sdivs_dl(register int64_t dnum, register int32_t lden)
1089 {
1090 *((int64_t volatile *)(MMAU__SDIVD | MMAU__X1 | MMAU__SAT)) = dnum;
1091 *((int32_t volatile *)(MMAU__SDIVD | MMAU__X3 | MMAU__SAT)) = lden;
1092 return *((int64_t volatile *)(MMAU__SDIVD | MMAU__A10 | MMAU__SAT));
1093 }
1094
1095 /*!
1096 * @brief Divide two 64-bit integer values returning a 64-bit integer
1097 * quotient.
1098 *
1099 * @details The @ref MMAU_d_sdiv_dd function divides two 64-bit integer values
1100 * returning a 64-bit integer quotient.
1101 * @param dnum int64_t integer divisor value.
1102 * @param dden int64_t integer dividend value.
1103 * @return int64_t integer quotient value.
1104 * @note Quotient is stored in A10 register of the MMAU for next computation.
1105 */
MMAU_d_sdiv_dd(register int64_t dnum,register int64_t dden)1106 static inline int64_t MMAU_d_sdiv_dd(register int64_t dnum, register int64_t dden)
1107 {
1108 *((int64_t volatile *)(MMAU__SDIVDD | MMAU__X0)) = dnum;
1109 *((int64_t volatile *)(MMAU__SDIVDD | MMAU__X2)) = dden;
1110 return *((int64_t volatile *)(MMAU__SDIVDD | MMAU__A10));
1111 }
1112
1113 /*!
1114 * @brief Divide two 64-bit integer values returning a 64-bit integer
1115 * quotient.
1116 *
1117 * @details The @ref MMAU_d_sdivs_dd function divides two 64-bit integer values
1118 * returning a 64-bit integer quotient.
1119 * @param dnum int64_t integer divisor value.
1120 * @param dden int64_t integer dividend value.
1121 * @return int64_t integer quotient value.
1122 * @note Saturated quotient is stored in A10 register of the MMAU for
1123 * next computation.
1124 */
MMAU_d_sdivs_dd(register int64_t dnum,register int64_t dden)1125 static inline int64_t MMAU_d_sdivs_dd(register int64_t dnum, register int64_t dden)
1126 {
1127 *((int64_t volatile *)(MMAU__SDIVDD | MMAU__X0 | MMAU__SAT)) = dnum;
1128 *((int64_t volatile *)(MMAU__SDIVDD | MMAU__X2 | MMAU__SAT)) = dden;
1129 return *((int64_t volatile *)(MMAU__SDIVDD | MMAU__A10 | MMAU__SAT));
1130 }
1131
1132 /*!
1133 * @brief Divide 32-bit integer value stored in the A10 register of the MMAU
1134 * by 32-bit integer value returning a 64-bit integer quotient.
1135 *
1136 * @details The @ref MMAU_d_sdiva_l function divides 32-bit integer value stored in
1137 * the A10 register of the MMAU by 32-bit integer value returning
1138 * a 64-bit integer quotient.
1139 * @param lden1 int32_t integer dividend value.
1140 * @return int64_t integer quotient value.
1141 * @note Quotient is stored in A10 register of the MMAU for next computation.
1142 */
MMAU_d_sdiva_l(register int32_t lden1)1143 static inline int64_t MMAU_d_sdiva_l(register int32_t lden1)
1144 {
1145 *((int32_t volatile *)(MMAU__SDIVDA | MMAU__X3)) = lden1;
1146 return *((int64_t volatile *)(MMAU__SDIVDA | MMAU__A10));
1147 }
1148
1149 /*!
1150 * @brief Divide 32-bit integer value stored in the A10 register of the MMAU
1151 * by 32-bit integer value returning saturated 64-bit integer quotient.
1152 *
1153 * @details The @ref MMAU_d_sdivas_l function divides 32-bit integer value stored in
1154 * the A10 register of the MMAU by 32-bit integer value returning
1155 * a saturated 64-bit integer quotient.
1156 * @param lden1 int32_t integer dividend value.
1157 * @return int64_t integer quotient value.
1158 * @note Saturated quotient is stored in A10 register of the MMAU for
1159 * next computation.
1160 */
MMAU_d_sdivas_l(register int32_t lden1)1161 static inline int64_t MMAU_d_sdivas_l(register int32_t lden1)
1162 {
1163 *((int32_t volatile *)(MMAU__SDIVDA | MMAU__X3 | MMAU__SAT)) = lden1;
1164 return *((int64_t volatile *)(MMAU__SDIVDA | MMAU__A10 | MMAU__SAT));
1165 }
1166
1167 /*!
1168 * @brief Divide 64-bit integer value stored in the A10 register of the MMAU
1169 * by 64-bit integer value returning a 64-bit integer quotient.
1170 *
1171 * @details The @ref MMAU_d_sdiva_d function divides 64-bit integer value stored in
1172 * the A10 register of the MMAU by 64-bit integer value returning
1173 * a 64-bit integer quotient.
1174 * @param dden1 int64_t integer dividend value.
1175 * @return int64_t integer quotient value.
1176 * @note Quotient is stored in A10 register of the MMAU for next computation.
1177 */
MMAU_d_sdiva_d(register int64_t dden1)1178 static inline int64_t MMAU_d_sdiva_d(register int64_t dden1)
1179 {
1180 *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__X2)) = dden1;
1181 return *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__A10));
1182 }
1183
1184 /*!
1185 * @brief Divide 64-bit integer value stored in the A10 register of the MMAU
1186 * by 64-bit integer value returning saturated 64-bit integer quotient.
1187 *
1188 * @details The @ref MMAU_d_sdivas_d function divides 64-bit integer value stored in
1189 * the A10 register of the MMAU by 64-bit integer value returning
1190 * a saturated 64-bit integer quotient.
1191 * @param dden1 int64_t integer dividend value.
1192 * @return int64_t integer quotient value.
1193 * @note Saturated quotient is stored in A10 register of the MMAU for
1194 * next computation.
1195 */
MMAU_d_sdivas_d(register int64_t dden1)1196 static inline int64_t MMAU_d_sdivas_d(register int64_t dden1)
1197 {
1198 *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__X2 | MMAU__SAT)) = dden1;
1199 return *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__A10 | MMAU__SAT));
1200 }
1201
1202 /*! @} */
1203
1204 /*!
1205 * @name Fractional Operands
1206 * @{
1207 */
1208
1209 /*!
1210 * @brief Load A10 accumulator register of the MMAU by 64-bit fractional
1211 * value.
1212 *
1213 * @details The @ref MMAU_lda_d function loads A10 accumulator register of the MMAU
1214 * by 64-bit fractional value.
1215 * @param dval @ref frac64_t fractional value.
1216 */
MMAU_lda_d(register frac64_t dval)1217 static inline void MMAU_lda_d(register frac64_t dval)
1218 {
1219 *((frac64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;
1220 }
1221 /*!
1222 * @brief Multiply two 32-bit fractional values returning a 32-bit fractional
1223 * product.
1224 *
1225 * @details The @ref MMAU_l_mul_ll function multiplies two 32-bit fractional values
1226 * returning a 32-bit fractional product.
1227 * @param lval1 @ref frac32_t fractional value.
1228 * @param lval2 @ref frac32_t fractional value.
1229 * @return @ref frac32_t fractional value after multiply.
1230 * @note Product is stored in A10 register of the MMAU for next computation.
1231 */
MMAU_l_mul_ll(register frac32_t lval1,register frac32_t lval2)1232 static inline frac32_t MMAU_l_mul_ll(register frac32_t lval1, register frac32_t lval2)
1233 {
1234 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X2)) = lval1;
1235 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X3)) = lval2;
1236 return *((frac32_t volatile *)(MMAU__QMUL | MMAU__A1));
1237 }
1238
1239 /*!
1240 * @brief Saturating multiply two 32-bit fractional values returning saturated
1241 * 32-bit fractional product.
1242 *
1243 * @details The @ref MMAU_l_muls_ll function multiplies two 32-bit fractional values
1244 * returning saturated 32-bit fractional product.
1245 * @param lval1 @ref frac32_t fractional value.
1246 * @param lval2 @ref frac32_t fractional value.
1247 * @return @ref frac32_t fractional value after multiply.
1248 * @note Saturated product is stored in A10 register of the MMAU for next
1249 * computation.
1250 */
MMAU_l_muls_ll(register frac32_t lval1,register frac32_t lval2)1251 static inline frac32_t MMAU_l_muls_ll(register frac32_t lval1, register frac32_t lval2)
1252 {
1253 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X2 | MMAU__SAT)) = lval1;
1254 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X3 | MMAU__SAT)) = lval2;
1255 return *((frac32_t volatile *)(MMAU__QMUL | MMAU__A1 | MMAU__SAT));
1256 }
1257
1258 /*!
1259 * @brief Multiply two 32-bit fractional values returning a 64-bit fractional
1260 * product.
1261 *
1262 * @details The @ref MMAU_d_mul_ll function multiplies two 32-bit fractional values
1263 * returning a 64-bit fractional product.
1264 * @param lval1 @ref frac32_t fractional value.
1265 * @param lval2 @ref frac32_t fractional value.
1266 * @return @ref frac64_t fractional value after multiply.
1267 * @note Product is stored in A10 register of the MMAU for next computation.
1268 */
MMAU_d_mul_ll(register frac32_t lval1,register frac32_t lval2)1269 static inline frac64_t MMAU_d_mul_ll(register frac32_t lval1, register frac32_t lval2)
1270 {
1271 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X2)) = lval1;
1272 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X3)) = lval2;
1273 return *((frac64_t volatile *)(MMAU__QMUL | MMAU__A10));
1274 }
1275
1276 /*!
1277 * @brief Saturating multiply two 32-bit fractional values returning saturated
1278 * 64-bit fractional product.
1279 *
1280 * @details The @ref MMAU_d_muls_ll function multiplies two 32-bit fractional values
1281 * returning saturated 64-bit fractional product.
1282 * @param lval1 @ref frac32_t fractional value.
1283 * @param lval2 @ref frac32_t fractional value.
1284 * @return @ref frac64_t fractional value after multiply.
1285 * @note Saturated product is stored in A10 register of the MMAU for next
1286 * computation. If saturation occurs, the instruction sets the
1287 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1288 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1289 */
MMAU_d_muls_ll(register frac32_t lval1,register frac32_t lval2)1290 static inline frac64_t MMAU_d_muls_ll(register frac32_t lval1, register frac32_t lval2)
1291 {
1292 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X2 | MMAU__SAT)) = lval1;
1293 *((frac32_t volatile *)(MMAU__QMUL | MMAU__X3 | MMAU__SAT)) = lval2;
1294 return *((frac64_t volatile *)(MMAU__QMUL | MMAU__A10 | MMAU__SAT));
1295 }
1296
1297 /*!
1298 * @brief Multiply 64-bit fractional value with 32-bit fractional value
1299 * returning a 64-bit fractional product.
1300 *
1301 * @details The @ref MMAU_d_mul_dl function multiplies 64-bit fractional value with
1302 * 32-bit fractional value returning a 64-bit fractional product.
1303 * @param dval @ref frac64_t fractional value.
1304 * @param lval @ref frac32_t fractional value.
1305 * @return @ref frac64_t fractional value after multiply.
1306 * @note Product is stored in A10 register of the MMAU for next computation.
1307 */
MMAU_d_mul_dl(register frac64_t dval,register frac32_t lval)1308 static inline frac64_t MMAU_d_mul_dl(register frac64_t dval, register frac32_t lval)
1309 {
1310 *((frac64_t volatile *)(MMAU__QMULD | MMAU__X1)) = dval;
1311 *((frac32_t volatile *)(MMAU__QMULD | MMAU__X3)) = lval;
1312 return *((frac64_t volatile *)(MMAU__QMULD | MMAU__A10));
1313 }
1314
1315 /*!
1316 * @brief Saturating multiply 64-bit fractional value with 32-bit fractional
1317 * value returning saturated 64-bit fractional product.
1318 *
1319 * @details The @ref MMAU_d_muls_dl function multiplies 64-bit fractional value with
1320 * 32-bit fractional value returning saturated 64-bit fractional product.
1321 * @param dval @ref frac64_t fractional value.
1322 * @param lval @ref frac32_t fractional value.
1323 * @return @ref frac64_t fractional value after multiply.
1324 * @note Saturated product is stored in A10 register of the MMAU for next
1325 * computation. If saturation occurs, the instruction sets the
1326 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1327 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1328 */
MMAU_d_muls_dl(register frac64_t dval,register frac32_t lval)1329 static inline frac64_t MMAU_d_muls_dl(register frac64_t dval, register frac32_t lval)
1330 {
1331 *((frac64_t volatile *)(MMAU__QMULD | MMAU__X1 | MMAU__SAT)) = dval;
1332 *((frac32_t volatile *)(MMAU__QMULD | MMAU__X3 | MMAU__SAT)) = lval;
1333 return *((frac64_t volatile *)(MMAU__QMULD | MMAU__A10 | MMAU__SAT));
1334 }
1335
1336 /*!
1337 * @brief Multiply 32-bit fractional value with 64-bit fractional value stored
1338 * in the A10 register of the MMAU returning a 64-bit fractional product.
1339 *
1340 * @details The @ref MMAU_d_mula_l function multiplies 32-bit fractional value with
1341 * 64-bit fractional value stored in the A10 register of the MMAU
1342 * returning a 64-bit fractional product.
1343 * @param lval @ref frac32_t fractional value.
1344 * @return @ref frac64_t fractional value after multiply.
1345 * @note Product is stored in A10 register of the MMAU for next computation.
1346 */
MMAU_d_mula_l(register frac32_t lval)1347 static inline frac64_t MMAU_d_mula_l(register frac32_t lval)
1348 {
1349 *((frac32_t volatile *)(MMAU__QMULDA | MMAU__X3)) = lval;
1350 return *((frac64_t volatile *)(MMAU__QMULDA | MMAU__A10));
1351 }
1352
1353 /*!
1354 * @brief Saturating multiply 32-bit fractional value with 64-bit fractional
1355 * value stored in the A10 register of the MMAU returning saturated 64-bit
1356 * fractional product.
1357 *
1358 * @details The @ref MMAU_d_mulas_l function multiplies 32-bit fractional value with
1359 * 64-bit fractional value stored in the A10 register of the MMAU
1360 * returning saturated 64-bit fractional product.
1361 * @param lval @ref frac32_t fractional value.
1362 * @return @ref frac64_t fractional value after multiply.
1363 * @note Saturated product is stored in A10 register of the MMAU for next
1364 * computation. If saturation occurs, the instruction sets the
1365 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1366 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1367 */
MMAU_d_mulas_l(register frac32_t lval)1368 static inline frac64_t MMAU_d_mulas_l(register frac32_t lval)
1369 {
1370 *((frac32_t volatile *)(MMAU__QMULDA | MMAU__X3 | MMAU__SAT)) = lval;
1371 return *((frac64_t volatile *)(MMAU__QMULDA | MMAU__A10 | MMAU__SAT));
1372 }
1373
1374 /*!
1375 * @brief Multiply 64-bit fractional value with 32-bit fractional value
1376 * returning a 32-bit fractional product.
1377 *
1378 * @details The @ref MMAU_l_mul_dl function multiplies 64-bit fractional value with
1379 * 32-bit fractional value returning a 32-bit fractional product.
1380 * @param dval @ref frac64_t fractional value.
1381 * @param lval @ref frac32_t fractional value.
1382 * @return @ref frac32_t fractional value after multiply.
1383 * @note Product is stored in A10 register of the MMAU for next computation.
1384 */
MMAU_l_mul_dl(register frac64_t dval,register frac32_t lval)1385 static inline frac32_t MMAU_l_mul_dl(register frac64_t dval, register frac32_t lval)
1386 {
1387 *((frac64_t volatile *)(MMAU__QMULD | MMAU__X1)) = dval;
1388 *((frac32_t volatile *)(MMAU__QMULD | MMAU__X3)) = lval;
1389 return *((frac32_t volatile *)(MMAU__QMULD | MMAU__A1));
1390 }
1391
1392 /*!
1393 * @brief Saturating multiply 64-bit fractional value with 32-bit fractional
1394 * value returning saturated 32-bit fractional product.
1395 *
1396 * @details The @ref MMAU_l_muls_dl function multiplies 64-bit fractional value with
1397 * 32-bit fractional value returning saturated 32-bit fractional
1398 * product.
1399 * @param dval @ref frac64_t fractional value.
1400 * @param lval @ref frac32_t fractional value.
1401 * @return @ref frac32_t fractional value after multiply.
1402 * @note Saturated product is stored in A10 register of the MMAU for next
1403 * computation.
1404 */
MMAU_l_muls_dl(register frac64_t dval,register frac32_t lval)1405 static inline frac32_t MMAU_l_muls_dl(register frac64_t dval, register frac32_t lval)
1406 {
1407 *((frac64_t volatile *)(MMAU__QMULD | MMAU__X1 | MMAU__SAT)) = dval;
1408 *((frac32_t volatile *)(MMAU__QMULD | MMAU__X3 | MMAU__SAT)) = lval;
1409 return *((frac32_t volatile *)(MMAU__QMULD | MMAU__A1 | MMAU__SAT));
1410 }
1411
1412 /*!
1413 * @brief Multiply 32-bit fractional value with 64-bit fractional value stored
1414 * in the A10 register of the MMAU returning a 32-bit fractional
1415 * product.
1416 *
1417 * @details The @ref MMAU_l_mula_l function multiplies 32-bit fractional value with
1418 * 64-bit fractional value stored in the A10 register of the MMAU
1419 * returning a 32-bit fractional product.
1420 * @param lval @ref frac32_t fractional value.
1421 * @return @ref frac32_t fractional value after multiply.
1422 * @note Product is stored in A10 register of the MMAU for next computation.
1423 */
MMAU_l_mula_l(register frac32_t lval)1424 static inline frac32_t MMAU_l_mula_l(register frac32_t lval)
1425 {
1426 *((frac32_t volatile *)(MMAU__QMULDA | MMAU__X3)) = lval;
1427 return *((frac32_t volatile *)(MMAU__QMULDA | MMAU__A1));
1428 }
1429
1430 /*!
1431 * @brief Saturating multiply 32-bit fractional value with 64-bit fractional
1432 * value stored in the A10 register of the MMAU returning saturated
1433 * 32-bit fractional product.
1434 *
1435 * @details The @ref MMAU_l_mulas_l function multiplies 32-bit fractional value with
1436 * 64-bit fractional value stored in the A10 register of the MMAU
1437 * returning saturated 32-bit fractional product.
1438 * @param lval @ref frac32_t fractional value.
1439 * @return @ref frac32_t fractional value after multiply.
1440 * @note Saturated product is stored in A10 register of the MMAU for next
1441 * computation.
1442 */
MMAU_l_mulas_l(register frac32_t lval)1443 static inline frac32_t MMAU_l_mulas_l(register frac32_t lval)
1444 {
1445 *((frac32_t volatile *)(MMAU__QMULDA | MMAU__X3 | MMAU__SAT)) = lval;
1446 return *((frac32_t volatile *)(MMAU__QMULDA | MMAU__A1 | MMAU__SAT));
1447 }
1448
1449 /*!
1450 * @brief Multiply two 32-bit fractional values and add product with value
1451 * stored in the A10 register of the MMAU returning a 64-bit fractional
1452 * A10 register value.
1453 *
1454 * @details The @ref MMAU_d_mac_ll function multiplies two 32-bit fractional values
1455 * and add product with value stored in the A10 register of the MMAU
1456 * returning a 64-bit fractional A10 register value.
1457 * @param lval1 @ref frac32_t fractional value.
1458 * @param lval2 @ref frac32_t fractional value.
1459 * @return @ref frac64_t fractional value after multiply.
1460 * @note Product is stored in A10 register of the MMAU for next computation.
1461 */
MMAU_d_mac_ll(register frac32_t lval1,register frac32_t lval2)1462 static inline frac64_t MMAU_d_mac_ll(register frac32_t lval1, register frac32_t lval2)
1463 {
1464 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X2)) = lval1;
1465 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X3)) = lval2;
1466 return *((frac64_t volatile *)(MMAU__QMAC | MMAU__A10));
1467 }
1468
1469 /*!
1470 * @brief Saturating multiply two 32-bit fractional values and add product
1471 * with value stored in the A10 register of the MMAU returning a 64-bit fractional
1472 * A10 register value.
1473 *
1474 * @details The @ref MMAU_d_macs_ll function multiplies two 32-bit fractional values
1475 * and add product with value stored in the A10 register of the MMAU
1476 * returning saturated 64-bit fractional A10 register value.
1477 * @param lval1 @ref frac32_t fractional value.
1478 * @param lval2 @ref frac32_t fractional value.
1479 * @return @ref frac64_t fractional value after multiply.
1480 * @note Saturated product is stored in A10 register of the MMAU for next
1481 * computation. If saturation occurs, the instruction sets the
1482 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1483 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1484 */
MMAU_d_macs_ll(register frac32_t lval1,register frac32_t lval2)1485 static inline frac64_t MMAU_d_macs_ll(register frac32_t lval1, register frac32_t lval2)
1486 {
1487 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X2 | MMAU__SAT)) = lval1;
1488 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X3 | MMAU__SAT)) = lval2;
1489 return *((frac64_t volatile *)(MMAU__QMAC | MMAU__A10 | MMAU__SAT));
1490 }
1491
1492 /*!
1493 * @brief Multiply 64-bit fractional value with 32-bit fractional value and
1494 * add product with value stored in the A10 register of the MMAU
1495 * returning a 64-bit fractional A10 register value.
1496 *
1497 * @details The @ref MMAU_d_mac_dl function multiplies 64-bit fractional value with
1498 * 32-bit fractional value and add product with value stored in the
1499 * A10 register of the MMAU returning a 64-bit fractional A10 register
1500 * value.
1501 * @param dval @ref frac64_t fractional value.
1502 * @param lval @ref frac32_t fractional value.
1503 * @return @ref frac64_t fractional value after multiply.
1504 * @note Product is stored in A10 register of the MMAU for next computation.
1505 */
MMAU_d_mac_dl(register frac64_t dval,register frac32_t lval)1506 static inline frac64_t MMAU_d_mac_dl(register frac64_t dval, register frac32_t lval)
1507 {
1508 *((frac64_t volatile *)(MMAU__QMACD | MMAU__X1)) = dval;
1509 *((frac32_t volatile *)(MMAU__QMACD | MMAU__X3)) = lval;
1510 return *((frac64_t volatile *)(MMAU__QMACD | MMAU__A10));
1511 }
1512
1513 /*!
1514 * @brief Saturating multiply 64-bit fractional value with 32-bit fractional
1515 * value and add product with value stored in the A10 register of the MMAU
1516 * returning saturated 64-bit fractional A10 register value.
1517 *
1518 * @details The @ref MMAU_d_macs_dl function multiplies 64-bit fractional value with
1519 * 32-bit fractional value and add product with value stored in the
1520 * A10 register of the MMAU returning saturated 64-bit fractional A10
1521 * register value.
1522 * @param dval @ref frac64_t fractional value.
1523 * @param lval @ref frac32_t fractional value.
1524 * @return @ref frac64_t fractional value after multiply.
1525 * @note Saturated product is stored in A10 register of the MMAU for next
1526 * computation. If saturation occurs, the instruction sets the
1527 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1528 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1529 */
MMAU_d_macs_dl(register frac64_t dval,register frac32_t lval)1530 static inline frac64_t MMAU_d_macs_dl(register frac64_t dval, register frac32_t lval)
1531 {
1532 *((frac64_t volatile *)(MMAU__QMACD | MMAU__X1 | MMAU__SAT)) = dval;
1533 *((frac32_t volatile *)(MMAU__QMACD | MMAU__X3 | MMAU__SAT)) = lval;
1534 return *((frac64_t volatile *)(MMAU__QMACD | MMAU__A10 | MMAU__SAT));
1535 }
1536
1537 /*!
1538 * @brief Multiply 32-bit fractional value by value stored in the A10 register
1539 * of the MMAU and add product with 64-bit fractional value returning
1540 * a 64-bit fractional A10 register value.
1541 *
1542 * @details The @ref MMAU_d_maca_dl function multiplies 32-bit fractional value by
1543 * value stored in the A10 register of the MMAU and add product with
1544 * 64-bit fractional value returning a 64-bit fractional A10 register
1545 * value.
1546 * @param dval @ref frac64_t fractional value.
1547 * @param lval @ref frac32_t fractional value.
1548 * @return @ref frac64_t fractional value after multiply.
1549 * @note Product is stored in A10 register of the MMAU for next computation.
1550 */
MMAU_d_maca_dl(register frac64_t dval,register frac32_t lval)1551 static inline frac64_t MMAU_d_maca_dl(register frac64_t dval, register frac32_t lval)
1552 {
1553 *((frac64_t volatile *)(MMAU__QMACDA | MMAU__X1)) = dval;
1554 *((frac32_t volatile *)(MMAU__QMACDA | MMAU__X3)) = lval;
1555 return *((frac64_t volatile *)(MMAU__QMACDA | MMAU__A10));
1556 }
1557
1558 /*!
1559 * @brief Saturating multiply 32-bit fractional value by value stored in the
1560 * A10 register of the MMAU and add product with 64-bit fractional value returning
1561 * a saturated 64-bit fractional A10 register value.
1562 *
1563 * @details The @ref MMAU_d_macas_dl function multiplies 32-bit fractional value by
1564 * value stored in the A10 register of the MMAU and add product with
1565 * 64-bit fractional value returning saturated 64-bit fractional A10
1566 * register value.
1567 * @param dval @ref frac64_t fractional value.
1568 * @param lval @ref frac32_t fractional value.
1569 * @return @ref frac64_t fractional value after multiply.
1570 * @note Saturated product is stored in A10 register of the MMAU for next
1571 * computation. If saturation occurs, the instruction sets the
1572 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1573 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1574 */
MMAU_d_macas_dl(register frac64_t dval,register frac32_t lval)1575 static inline frac64_t MMAU_d_macas_dl(register frac64_t dval, register frac32_t lval)
1576 {
1577 *((frac64_t volatile *)(MMAU__QMACDA | MMAU__X1 | MMAU__SAT)) = dval;
1578 *((frac32_t volatile *)(MMAU__QMACDA | MMAU__X3 | MMAU__SAT)) = lval;
1579 return *((frac64_t volatile *)(MMAU__QMACDA | MMAU__A10 | MMAU__SAT));
1580 }
1581
1582 /*!
1583 * @brief Multiply two 32-bit fractional values and add product with value
1584 * stored in the A10 register of the MMAU returning a 32-bit fractional
1585 * A10 register value.
1586 *
1587 * @details The @ref MMAU_l_mac_ll function multiplies two 32-bit fractional values
1588 * and add product with value stored in the A10 register of the MMAU
1589 * returning a 32-bit fractional A1 register value.
1590 * @param lval1 @ref frac32_t fractional value.
1591 * @param lval2 @ref frac32_t fractional value.
1592 * @return @ref frac32_t fractional value after multiply.
1593 * @note Product is stored in A10 register of the MMAU for next computation.
1594 */
MMAU_l_mac_ll(register frac32_t lval1,register frac32_t lval2)1595 static inline frac32_t MMAU_l_mac_ll(register frac32_t lval1, register frac32_t lval2)
1596 {
1597 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X2)) = lval1;
1598 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X3)) = lval2;
1599 return *((frac32_t volatile *)(MMAU__QMAC | MMAU__A1));
1600 }
1601
1602 /*!
1603 * @brief Saturating multiply two 32-bit fractional values and add product
1604 * with value stored in the A10 register of the MMAU returning a 32-bit
1605 * fractional A10 register value.
1606 *
1607 * @details The @ref MMAU_l_macs_ll function multiplies two 32-bit fractional values
1608 * and add product with value stored in the A10 register of the MMAU
1609 * returning saturated 32-bit fractional A1 register value.
1610 * @param lval1 @ref frac32_t fractional value.
1611 * @param lval2 @ref frac32_t fractional value.
1612 * @return @ref frac32_t fractional value after multiply.
1613 * @note Saturated product is stored in A10 register of the MMAU for next
1614 * computation.
1615 */
MMAU_l_macs_ll(register frac32_t lval1,register frac32_t lval2)1616 static inline frac32_t MMAU_l_macs_ll(register frac32_t lval1, register frac32_t lval2)
1617 {
1618 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X2 | MMAU__SAT)) = lval1;
1619 *((frac32_t volatile *)(MMAU__QMAC | MMAU__X3 | MMAU__SAT)) = lval2;
1620 return *((frac32_t volatile *)(MMAU__QMAC | MMAU__A1 | MMAU__SAT));
1621 }
1622
1623 /*!
1624 * @brief Multiply 64-bit fractional value with 32-bit fractional value and
1625 * add product with value stored in the A10 register of the MMAU
1626 * returning a 32-bit fractional A10 register value.
1627 *
1628 * @details The @ref MMAU_l_mac_dl function multiplies 64-bit fractional value with
1629 * 32-bit fractional value and add product with value stored in the A10
1630 * register of the MMAU returning a 32-bit fractional A1 register
1631 * value.
1632 * @param dval @ref frac64_t fractional value.
1633 * @param lval @ref frac32_t fractional value.
1634 * @return @ref frac32_t fractional value after multiply.
1635 * @note Product is stored in A10 register of the MMAU for next computation.
1636 */
MMAU_l_mac_dl(register frac64_t dval,register frac32_t lval)1637 static inline frac32_t MMAU_l_mac_dl(register frac64_t dval, register frac32_t lval)
1638 {
1639 *((frac64_t volatile *)(MMAU__QMACD | MMAU__X1)) = dval;
1640 *((frac32_t volatile *)(MMAU__QMACD | MMAU__X3)) = lval;
1641 return *((frac32_t volatile *)(MMAU__QMACD | MMAU__A1));
1642 }
1643
1644 /*!
1645 * @brief Saturating multiply 64-bit fractional value with 32-bit fractional
1646 * value and add product with value stored in the A10 register of the
1647 * MMAU returning saturated 32-bit fractional A10 register value.
1648 *
1649 * @details The @ref MMAU_l_macs_dl function multiplies 64-bit fractional value with
1650 * 32-bit fractional value and add product with value stored in the A10
1651 * register of the MMAU returning saturated 32-bit fractional A1
1652 * register value.
1653 * @param dval @ref frac64_t fractional value.
1654 * @param lval @ref frac32_t fractional value.
1655 * @return @ref frac32_t fractional value after multiply.
1656 * @note Saturated product is stored in A10 register of the MMAU for next
1657 * computation.
1658 */
MMAU_l_macs_dl(register frac64_t dval,register frac32_t lval)1659 static inline frac32_t MMAU_l_macs_dl(register frac64_t dval, register frac32_t lval)
1660 {
1661 *((frac64_t volatile *)(MMAU__QMACD | MMAU__X1 | MMAU__SAT)) = dval;
1662 *((frac32_t volatile *)(MMAU__QMACD | MMAU__X3 | MMAU__SAT)) = lval;
1663 return *((frac32_t volatile *)(MMAU__QMACD | MMAU__A1 | MMAU__SAT));
1664 }
1665
1666 /*!
1667 * @brief Multiply 32-bit fractional value by value stored in the A10 register
1668 * of the MMAU and add product with 64-bit fractional value returning a
1669 * 32-bit fractional A10 register value.
1670 *
1671 * @details The @ref MMAU_l_maca_dl function multiplies 32-bit fractional value by
1672 * value stored in the A10 register of the MMAU and add product with
1673 * 64-bit fractional value returning a 32-bit fractional A1 register
1674 * value.
1675 * @param dval @ref frac64_t fractional value.
1676 * @param lval @ref frac32_t fractional value.
1677 * @return @ref frac32_t fractional value after multiply.
1678 * @note Product is stored in A10 register of the MMAU for next computation.
1679 */
MMAU_l_maca_dl(register frac64_t dval,register frac32_t lval)1680 static inline frac32_t MMAU_l_maca_dl(register frac64_t dval, register frac32_t lval)
1681 {
1682 *((frac64_t volatile *)(MMAU__QMACDA | MMAU__X1)) = dval;
1683 *((frac32_t volatile *)(MMAU__QMACDA | MMAU__X3)) = lval;
1684 return *((frac32_t volatile *)(MMAU__QMACDA | MMAU__A1));
1685 }
1686
1687 /*!
1688 * @brief Saturating multiply 32-bit fractional value by value stored in the
1689 * A10 register of the MMAU and add product with 64-bit fractional
1690 * value returning a saturated 32-bit fractional A10 register value.
1691 *
1692 * @details The @ref MMAU_l_macas_dl function multiplies 32-bit fractional value by
1693 * value stored in the A10 register of the MMAU and add product with
1694 * 64-bit fractional value returning saturated 32-bit fractional A1
1695 * register value.
1696 * @param dval @ref frac64_t fractional value.
1697 * @param lval @ref frac32_t fractional value.
1698 * @return @ref frac32_t fractional value after multiply.
1699 * @note Saturated product is stored in A10 register of the MMAU for next
1700 * computation.
1701 */
MMAU_l_macas_dl(register frac64_t dval,register frac32_t lval)1702 static inline frac32_t MMAU_l_macas_dl(register frac64_t dval, register frac32_t lval)
1703 {
1704 *((frac64_t volatile *)(MMAU__QMACDA | MMAU__X1 | MMAU__SAT)) = dval;
1705 *((frac32_t volatile *)(MMAU__QMACDA | MMAU__X3 | MMAU__SAT)) = lval;
1706 return *((frac32_t volatile *)(MMAU__QMACDA | MMAU__A1 | MMAU__SAT));
1707 }
1708
1709 /*!
1710 * @brief Divide two 32-bit fractional values returning a 32-bit fractional
1711 * quotient.
1712 *
1713 * @details The @ref MMAU_l_div_ll function divides two 32-bit fractional values
1714 * returning a 32-bit fractional quotient.
1715 * @param lnum @ref frac32_t fractional divisor value.
1716 * @param lden @ref frac32_t fractional dividend value.
1717 * @return @ref frac32_t fractional quotient value.
1718 * @note Quotient is stored in A1 register of the MMAU for next computation.
1719 */
MMAU_l_div_ll(register frac32_t lnum,register frac32_t lden)1720 static inline frac32_t MMAU_l_div_ll(register frac32_t lnum, register frac32_t lden)
1721 {
1722 *((frac32_t volatile *)(MMAU__QDIV | MMAU__X2)) = lnum;
1723 *((frac32_t volatile *)(MMAU__QDIV | MMAU__X3)) = lden;
1724 return *((frac32_t volatile *)(MMAU__QDIV | MMAU__A1));
1725 }
1726
1727 /*!
1728 * @brief Divide two 32-bit fractional values returning a 32-bit fractional
1729 * quotient.
1730 *
1731 * @details The @ref MMAU_l_divs_ll function divides two 32-bit fractional values
1732 * returning a 32-bit fractional quotient.
1733 * @param lnum @ref frac32_t fractional divisor value.
1734 * @param lden @ref frac32_t fractional dividend value.
1735 * @return @ref frac32_t fractional quotient value.
1736 * @note Saturated quotient is stored in A1 register of the MMAU for
1737 * next computation. If saturation occurs, the instruction sets the
1738 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1739 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1740 */
MMAU_l_divs_ll(register frac32_t lnum,register frac32_t lden)1741 static inline frac32_t MMAU_l_divs_ll(register frac32_t lnum, register frac32_t lden)
1742 {
1743 *((frac32_t volatile *)(MMAU__QDIV | MMAU__X2 | MMAU__SAT)) = lnum;
1744 *((frac32_t volatile *)(MMAU__QDIV | MMAU__X3 | MMAU__SAT)) = lden;
1745 return *((frac32_t volatile *)(MMAU__QDIV | MMAU__A1 | MMAU__SAT));
1746 }
1747
1748 /*!
1749 * @brief Divide 64-bit fractional value stored in the A10 register of the
1750 * MMAU by 32-bit fractional value returning saturated 32-bit
1751 * fractional quotient.
1752 *
1753 * @details The @ref MMAU_l_divas_l function divides 64-bit fractional value stored
1754 * in the A10 register of the MMAU by 32-bit fractional value returning
1755 * a saturated 32-bit fractional quotient.
1756 * @param lden @ref frac32_t fractional dividend value.
1757 * @return @ref frac32_t fractional quotient value.
1758 * @note Saturated quotient is stored in A1 register of the MMAU for next
1759 * computation.
1760 */
MMAU_l_divas_l(register frac32_t lden)1761 static inline frac32_t MMAU_l_divas_l(register frac32_t lden)
1762 {
1763 *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__X3 | MMAU__SAT)) = lden;
1764 return *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__A1 | MMAU__SAT));
1765 }
1766
1767 /*!
1768 * @brief Divide 64-bit fractional value by 32-bit fractional value returning
1769 * a 64-bit fractional quotient.
1770 *
1771 * @details The @ref MMAU_d_div_dl function divides 64-bit fractional value by 32-bit
1772 * fractional value returning a 64-bit fractional quotient.
1773 * @param dnum @ref frac64_t fractional divisor value.
1774 * @param lden @ref frac32_t fractional dividend value.
1775 * @return @ref frac64_t fractional quotient value.
1776 * @note Quotient is stored in A10 register of the MMAU for next computation.
1777 */
MMAU_d_div_dl(register frac64_t dnum,register frac32_t lden)1778 static inline frac64_t MMAU_d_div_dl(register frac64_t dnum, register frac32_t lden)
1779 {
1780 *((frac64_t volatile *)(MMAU__QDIVD | MMAU__X1)) = dnum;
1781 *((frac32_t volatile *)(MMAU__QDIVD | MMAU__X3)) = lden;
1782 return *((frac64_t volatile *)(MMAU__QDIVD | MMAU__A10));
1783 }
1784
1785 /*!
1786 * @brief Divide 64-bit fractional value by 32-bit fractional value returning
1787 * a 64-bit fractional quotient.
1788 *
1789 * @details The @ref MMAU_d_divs_dl function divides 64-bit fractional value by
1790 * 32-bit fractional value returning a 64-bit fractional quotient.
1791 * @param dnum @ref frac64_t fractional divisor value.
1792 * @param lden @ref frac32_t fractional dividend value.
1793 * @return @ref frac64_t fractional quotient value.
1794 * @note Saturated quotient is stored in A10 register of the MMAU for
1795 * next computation. If saturation occurs, the instruction sets the
1796 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1797 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1798 */
MMAU_d_divs_dl(register frac64_t dnum,register frac32_t lden)1799 static inline frac64_t MMAU_d_divs_dl(register frac64_t dnum, register frac32_t lden)
1800 {
1801 *((frac64_t volatile *)(MMAU__QDIVD | MMAU__X1 | MMAU__SAT)) = dnum;
1802 *((frac32_t volatile *)(MMAU__QDIVD | MMAU__X3 | MMAU__SAT)) = lden;
1803 return *((frac64_t volatile *)(MMAU__QDIVD | MMAU__A10 | MMAU__SAT));
1804 }
1805
1806 /*!
1807 * @brief Divide 32-bit fractional value stored in the A10 register of the
1808 * MMAU by 32-bit fractional value returning a 64-bit fractional quotient.
1809 *
1810 * @details The @ref MMAU_d_diva_l function divides 32-bit fractional value stored in
1811 * the A10 register of the MMAU by 32-bit fractional value returning
1812 * a 64-bit fractional quotient.
1813 * @param lden1 @ref frac32_t fractional dividend value.
1814 * @return @ref frac64_t fractional quotient value.
1815 * @note Quotient is stored in A10 register of the MMAU for next computation.
1816 */
MMAU_d_diva_l(register frac32_t lden1)1817 static inline frac64_t MMAU_d_diva_l(register frac32_t lden1)
1818 {
1819 *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__X3)) = lden1;
1820 return *((frac64_t volatile *)(MMAU__QDIVDA | MMAU__A10));
1821 }
1822
1823 /*!
1824 * @brief Divide 32-bit fractional value stored in the A10 register of the
1825 * MMAU by 32-bit fractional value returning saturated 64-bit fractional quotient.
1826 *
1827 * @details The @ref MMAU_d_divas_l function divides 32-bit fractional value stored
1828 * in the A10 register of the MMAU by 32-bit fractional value returning
1829 * a saturated 64-bit fractional quotient.
1830 * @param lden1 @ref frac32_t fractional dividend value.
1831 * @return @ref frac64_t fractional quotient value.
1832 * @note Saturated quotient is stored in A10 register of the MMAU for
1833 * next computation. If saturation occurs, the instruction sets the
1834 * accumulation overflow (Q) and multiply or divide overflow (V) flags
1835 * to 1 in the CSR. Otherwise, it clears the Q and V flags.
1836 */
MMAU_d_divas_l(register frac32_t lden1)1837 static inline frac64_t MMAU_d_divas_l(register frac32_t lden1)
1838 {
1839 *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__X3 | MMAU__SAT)) = lden1;
1840 return *((frac64_t volatile *)(MMAU__QDIVDA | MMAU__A0 | MMAU__SAT));
1841 }
1842
1843 /*!
1844 * @brief Divide 64-bit fractional value stored in the A10 register of the
1845 * MMAU by 32-bit fractional value returning a 32-bit fractional
1846 * quotient.
1847 *
1848 * @details The @ref MMAU_l_diva_l function divides 64-bit fractional value stored in
1849 * the A10 register of the MMAU by 32-bit fractional value returning a
1850 * 32-bit fractional quotient.
1851 * @param lden @ref frac32_t fractional dividend value.
1852 * @return @ref frac32_t fractional quotient value.
1853 * @note Quotient is stored in A1 register of the MMAU for next computation.
1854 */
MMAU_l_diva_l(register frac32_t lden)1855 static inline frac32_t MMAU_l_diva_l(register frac32_t lden)
1856 {
1857 *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__X3)) = lden;
1858 return *((frac32_t volatile *)(MMAU__QDIVDA | MMAU__A1));
1859 }
1860
1861 /*!
1862 * @brief Compute and return a 32-bit fractional square root of the 32-bit
1863 * fractional radicand.
1864 *
1865 * @details The @ref MMAU_l_sqr_l function computes and returns a 32-bit fractional
1866 * square root of the 32-bit fractional radicand.
1867 * @param lrad @ref frac32_t fractional radicand.
1868 * @return @ref frac32_t fractional square root.
1869 * @note Square root is stored in A1 register of the MMAU for next
1870 * computation.
1871 */
MMAU_l_sqr_l(register frac32_t lrad)1872 static inline frac32_t MMAU_l_sqr_l(register frac32_t lrad)
1873 {
1874 *((frac32_t volatile *)(MMAU__QSQRD | MMAU__X2)) = 0L;
1875 *((frac32_t volatile *)(MMAU__QSQRD | MMAU__X3)) = lrad;
1876 return *((frac32_t volatile *)(MMAU__QSQRD | MMAU__A1));
1877 }
1878
1879 /*!
1880 * @brief Compute and return a 32-bit fractional square root of the 64-bit
1881 * fractional radicand.
1882 *
1883 * @details The @ref MMAU_l_sqr_d function computes and returns a 32-bit fractional
1884 * square root of the 64-bit fractional radicand.
1885 * @param drad @ref frac64_t fractional radicand.
1886 * @return @ref frac32_t fractional square root.
1887 * @note Quotient is stored in A1 register of the MMAU for next computation.
1888 */
MMAU_l_sqr_d(register frac64_t drad)1889 static inline frac32_t MMAU_l_sqr_d(register frac64_t drad)
1890 {
1891 *((frac64_t volatile *)(MMAU__QSQRD | MMAU__X2)) = drad;
1892 return *((frac32_t volatile *)(MMAU__QSQRD | MMAU__A1));
1893 }
1894
1895 /*!
1896 * @brief Compute and return a 32-bit fractional square root of the radicand
1897 * stored in the A10 register of the MMAU.
1898 *
1899 * @details The @ref MMAU_l_sqra function computes and returns a 32-bit fractional
1900 * square root of the radicand stored in the A10 register of the MMAU.
1901 * @return @ref frac32_t fractional square root.
1902 * @note Quotient is stored in A1 register of the MMAU for next computation.
1903 */
MMAU_l_sqra(void)1904 static inline frac32_t MMAU_l_sqra(void)
1905 {
1906 return *((frac32_t volatile *)(MMAU__QSQRDA | MMAU__A1));
1907 }
1908 /*! @} */
1909
1910 #if defined(__cplusplus)
1911 }
1912 #endif
1913
1914 /*! @} */
1915
1916 #endif /* _FSL_MMAU_H_ */
1917
