1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_IRQSTEER_H_
10 #define _FSL_IRQSTEER_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup irqsteer
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*!< Version 2.0.2. */
26 #define FSL_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
27 /*@}*/
28
29 /*! @brief IRQSTEER interrupt source register width. */
30 #define IRQSTEER_INT_SRC_REG_WIDTH 32U
31
32 /*! @brief IRQSTEER interrupt source mapping register index. */
33 #define IRQSTEER_INT_SRC_REG_INDEX(irq) \
34 (((uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT - 1U) - \
35 ((irq - (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / IRQSTEER_INT_SRC_REG_WIDTH))
36
37 /*! @brief IRQSTEER interrupt source mapping bit offset. */
38 #define IRQSTEER_INT_SRC_BIT_OFFSET(irq) \
39 ((irq - (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) % IRQSTEER_INT_SRC_REG_WIDTH)
40
41 /*! @brief IRQSTEER interrupt source number. */
42 #define IRQSTEER_INT_SRC_NUM(regIndex, bitOffset) \
43 ((((uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT - 1U - (regIndex)) * (IRQSTEER_INT_SRC_REG_WIDTH)) + (bitOffset))
44
45 /*! @brief IRQSTEER interrupt groups. */
46 typedef enum _irqsteer_int_group
47 {
48 kIRQSTEER_InterruptGroup0, /*!< Interrupt Group 0: interrupt source 31 - 0 */
49 kIRQSTEER_InterruptGroup1, /*!< Interrupt Group 1: interrupt source 63 - 32 */
50 kIRQSTEER_InterruptGroup2, /*!< Interrupt Group 2: interrupt source 95 - 64 */
51 kIRQSTEER_InterruptGroup3, /*!< Interrupt Group 3: interrupt source 127 - 96 */
52 kIRQSTEER_InterruptGroup4, /*!< Interrupt Group 4: interrupt source 159 - 128 */
53 kIRQSTEER_InterruptGroup5, /*!< Interrupt Group 5: interrupt source 191 - 160 */
54 kIRQSTEER_InterruptGroup6, /*!< Interrupt Group 6: interrupt source 223 - 192 */
55 kIRQSTEER_InterruptGroup7, /*!< Interrupt Group 7: interrupt source 255 - 224 */
56 kIRQSTEER_InterruptGroup8, /*!< Interrupt Group 8: interrupt source 287 - 256 */
57 kIRQSTEER_InterruptGroup9, /*!< Interrupt Group 9: interrupt source 319 - 288 */
58 kIRQSTEER_InterruptGroup10, /*!< Interrupt Group 10: interrupt source 351 - 320 */
59 kIRQSTEER_InterruptGroup11, /*!< Interrupt Group 11: interrupt source 383 - 352 */
60 kIRQSTEER_InterruptGroup12, /*!< Interrupt Group 12: interrupt source 415 - 384 */
61 kIRQSTEER_InterruptGroup13, /*!< Interrupt Group 13: interrupt source 447 - 416 */
62 kIRQSTEER_InterruptGroup14, /*!< Interrupt Group 14: interrupt source 479 - 448 */
63 kIRQSTEER_InterruptGroup15 /*!< Interrupt Group 15: interrupt source 511 - 480 */
64 } irqsteer_int_group_t;
65
66 /*! @brief IRQSTEER master interrupts mapping. */
67 typedef enum _irqsteer_int_master
68 {
69 kIRQSTEER_InterruptMaster0, /*!< Interrupt Master 0: interrupt source 63 - 0 */
70 kIRQSTEER_InterruptMaster1, /*!< Interrupt Master 1: interrupt source 127 - 64 */
71 kIRQSTEER_InterruptMaster2, /*!< Interrupt Master 2: interrupt source 191 - 128 */
72 kIRQSTEER_InterruptMaster3, /*!< Interrupt Master 3: interrupt source 255 - 192 */
73 kIRQSTEER_InterruptMaster4, /*!< Interrupt Master 4: interrupt source 319 - 256 */
74 kIRQSTEER_InterruptMaster5, /*!< Interrupt Master 5: interrupt source 383 - 320 */
75 kIRQSTEER_InterruptMaster6, /*!< Interrupt Master 6: interrupt source 447 - 384 */
76 kIRQSTEER_InterruptMaster7, /*!< Interrupt Master 7: interrupt source 511 - 448 */
77 } irqsteer_int_master_t;
78
79 /*******************************************************************************
80 * API
81 ******************************************************************************/
82
83 #if defined(__cplusplus)
84 extern "C" {
85 #endif
86
87 /*! @name Initialization and deinitialization */
88 /*@{*/
89
90 /*!
91 * @brief Initializes the IRQSTEER module.
92 *
93 * This function enables the clock gate for the specified IRQSTEER.
94 *
95 * @param base IRQSTEER peripheral base address.
96 */
97 void IRQSTEER_Init(IRQSTEER_Type *base);
98
99 /*!
100 * @brief Deinitializes an IRQSTEER instance for operation.
101 *
102 * The clock gate for the specified IRQSTEER is disabled.
103 *
104 * @param base IRQSTEER peripheral base address.
105 */
106 void IRQSTEER_Deinit(IRQSTEER_Type *base);
107
108 /*@}*/
109
110 /*! @name Sources */
111 /*@{*/
112
113 /*!
114 * @brief Enables an interrupt source.
115 *
116 * @param base IRQSTEER peripheral base address.
117 * @param irq Interrupt to be routed. The interrupt must be an IRQSTEER source.
118 */
IRQSTEER_EnableInterrupt(IRQSTEER_Type * base,IRQn_Type irq)119 static inline void IRQSTEER_EnableInterrupt(IRQSTEER_Type *base, IRQn_Type irq)
120 {
121 assert((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX);
122
123 base->CHn_MASK[((uint32_t)IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] |=
124 (1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq))));
125 }
126
127 /*!
128 * @brief Disables an interrupt source.
129 *
130 * @param base IRQSTEER peripheral base address.
131 * @param irq Interrupt source number. The interrupt must be an IRQSTEER source.
132 */
IRQSTEER_DisableInterrupt(IRQSTEER_Type * base,IRQn_Type irq)133 static inline void IRQSTEER_DisableInterrupt(IRQSTEER_Type *base, IRQn_Type irq)
134 {
135 assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX));
136
137 base->CHn_MASK[(IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] &=
138 ~(1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq))));
139 }
140
141 /*!
142 * @brief Sets/Forces an interrupt.
143 *
144 * @param base IRQSTEER peripheral base address.
145 * @param irq Interrupt to be set/forced. The interrupt must be an IRQSTEER source.
146 * @param set Switcher of the interrupt set/force function. "true" means to set. "false" means not (normal operation).
147 * @note This function is not affected by the function @ref IRQSTEER_DisableInterrupt
148 * and @ref IRQSTEER_EnableInterrupt.
149 */
IRQSTEER_SetInterrupt(IRQSTEER_Type * base,IRQn_Type irq,bool set)150 static inline void IRQSTEER_SetInterrupt(IRQSTEER_Type *base, IRQn_Type irq, bool set)
151 {
152 assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX));
153
154 if (set)
155 {
156 base->CHn_SET[((uint32_t)IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] |=
157 (1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq))));
158 }
159 else
160 {
161 base->CHn_SET[((uint32_t)IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] &=
162 ~(1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq))));
163 }
164 }
165
166 /*!
167 * @brief Enables a master interrupt. By default, all the master interrupts are enabled.
168 *
169 * @param base IRQSTEER peripheral base address.
170 * @param intMasterIndex Master index of interrupt sources to be routed, options available in enumeration
171 * ::irqsteer_int_master_t.
172 *
173 * For example, to enable the interrupt sources of master 1:
174 * @code
175 * IRQSTEER_EnableMasterInterrupt(IRQSTEER_M4_0, kIRQSTEER_InterruptMaster1);
176 * @endcode
177 */
IRQSTEER_EnableMasterInterrupt(IRQSTEER_Type * base,irqsteer_int_master_t intMasterIndex)178 static inline void IRQSTEER_EnableMasterInterrupt(IRQSTEER_Type *base, irqsteer_int_master_t intMasterIndex)
179 {
180 base->CHn_MINTDIS &= ~(1UL << ((uint32_t)intMasterIndex));
181 }
182
183 /*!
184 * @brief Disables a master interrupt.
185 *
186 * @param base IRQSTEER peripheral base address.
187 * @param intMasterIndex Master index of interrupt sources to be disabled, options available in enumeration
188 * ::irqsteer_int_master_t.
189 *
190 * For example, to disable the interrupt sources of master 1:
191 * @code
192 * IRQSTEER_DisableMasterInterrupt(IRQSTEER_M4_0, kIRQSTEER_InterruptMaster1);
193 * @endcode
194 */
IRQSTEER_DisableMasterInterrupt(IRQSTEER_Type * base,irqsteer_int_master_t intMasterIndex)195 static inline void IRQSTEER_DisableMasterInterrupt(IRQSTEER_Type *base, irqsteer_int_master_t intMasterIndex)
196 {
197 base->CHn_MINTDIS |= (1UL << ((uint32_t)intMasterIndex));
198 }
199
200 /*@}*/
201
202 /*! @name Status */
203 /*@{*/
204
205 /*!
206 * @brief Checks the status of one specific IRQSTEER interrupt.
207 *
208 * @param base IRQSTEER peripheral base address.
209 * @param irq Interrupt source status to be checked. The interrupt must be an IRQSTEER source.
210 * @return The interrupt status. "true" means interrupt set. "false" means not.
211 *
212 * For example, to check whether interrupt from output 0 of Display 1 is set:
213 * @code
214 * if (IRQSTEER_IsInterruptSet(IRQSTEER_DISPLAY1_INT_OUT0)
215 * {
216 * ...
217 * }
218 * @endcode
219 */
IRQSTEER_IsInterruptSet(IRQSTEER_Type * base,IRQn_Type irq)220 static inline bool IRQSTEER_IsInterruptSet(IRQSTEER_Type *base, IRQn_Type irq)
221 {
222 assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX));
223
224 return (bool)(base->CHn_STATUS[((uint32_t)(IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq))))] &
225 (1UL << ((uint32_t)(IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq))))));
226 }
227
228 /*!
229 * @brief Checks the status of IRQSTEER master interrupt.
230 * The master interrupt status represents at least one interrupt is asserted or not among ALL interrupts.
231 *
232 * @param base IRQSTEER peripheral base address.
233 * @return The master interrupt status. "true" means at least one interrupt set. "false" means not.
234 * @note The master interrupt status is not affected by the function @ref IRQSTEER_DisableMasterInterrupt.
235 */
IRQSTEER_IsMasterInterruptSet(IRQSTEER_Type * base)236 static inline bool IRQSTEER_IsMasterInterruptSet(IRQSTEER_Type *base)
237 {
238 return (bool)(base->CHn_MSTRSTAT & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK);
239 }
240
241 /*!
242 * @brief Gets the status of IRQSTEER group interrupt.
243 * The group interrupt status represents all the interrupt status within the group specified.
244 * This API aims for facilitating the status return of one set of interrupts.
245 *
246 * @param base IRQSTEER peripheral base address.
247 * @param intGroupIndex Index of the interrupt group status to get.
248 * @return The mask of the group interrupt status.
249 * Bit[n] set means the source with bit offset n in group intGroupIndex of IRQSTEER is asserted.
250 */
IRQSTEER_GetGroupInterruptStatus(IRQSTEER_Type * base,irqsteer_int_group_t intGroupIndex)251 static inline uint32_t IRQSTEER_GetGroupInterruptStatus(IRQSTEER_Type *base, irqsteer_int_group_t intGroupIndex)
252 {
253 return (base->CHn_STATUS[intGroupIndex]);
254 }
255
256 /*!
257 * @brief Gets the next interrupt source (currently set) of one specific master.
258 *
259 * @param base IRQSTEER peripheral base address.
260 * @param intMasterIndex Master index of interrupt sources, options available in enumeration ::irqsteer_int_master_t.
261 * @return The current set next interrupt source number of one specific master.
262 * Return IRQSTEER_INT_Invalid if no interrupt set.
263 */
264 IRQn_Type IRQSTEER_GetMasterNextInterrupt(IRQSTEER_Type *base, irqsteer_int_master_t intMasterIndex);
265
266 /*@}*/
267
268 #if defined(__cplusplus)
269 }
270 #endif
271
272 /*! @} */
273
274 #endif /* _FSL_INTMUX_H_ */
275
