1 /*
2 * Copyright 2018-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef FSL_I3C_H_
7 #define FSL_I3C_H_
8
9 #include "fsl_common.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /*!
16 * @addtogroup i3c
17 * @{
18 */
19
20 /*! @name Driver version */
21 /*@{*/
22 /*! @brief I3C driver version */
23 #define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 10, 6))
24 /*@}*/
25
26 /*! @brief Timeout times for waiting flag. */
27 #ifndef I3C_RETRY_TIMES
28 #define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
29 #endif
30
31 #define I3C_MAX_DEVCNT 10U
32
33 #ifndef I3C_IBI_BUFF_SIZE
34 #define I3C_IBI_BUFF_SIZE 10U
35 #endif
36
37 /*! @brief I3C status return codes. */
38 enum
39 {
40 kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */
41 kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */
42 kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */
43 kStatus_I3C_WriteAbort =
44 MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */
45 kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */
46 kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */
47 kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */
48 kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */
49 kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */
50 kStatus_I3C_MsgError =
51 MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */
52 kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */
53 kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */
54 kStatus_I3C_SlaveCountExceed =
55 MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */
56 kStatus_I3C_IBIWon = MAKE_STATUS(
57 kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */
58 kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */
59 kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */
60 kStatus_I3C_UnderrunNak =
61 MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */
62 kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */
63 kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */
64 kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */
65 };
66
67 /*! @brief I3C HDR modes. */
68 typedef enum _i3c_hdr_mode
69 {
70 kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */
71 kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */
72 kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */
73 kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */
74 } i3c_hdr_mode_t;
75
76 /*! @brief I3C device information. */
77 typedef struct _i3c_device_info
78 {
79 uint8_t dynamicAddr; /*!< Device dynamic address. */
80 uint8_t staticAddr; /*!< Static address. */
81 uint8_t dcr; /*!< Device characteristics register information. */
82 uint8_t bcr; /*!< Bus characteristics register information. */
83 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
84 uint32_t partNumber; /*!< Device part number info */
85 uint16_t maxReadLength; /*!< Maximum read length. */
86 uint16_t maxWriteLength; /*!< Maximum write length. */
87 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */
88 } i3c_device_info_t;
89
90 /*! @} */
91
92 /*!
93 * @addtogroup i3c_master_driver
94 * @{
95 */
96
97 /*!
98 * @brief I3C master peripheral flags.
99 *
100 * The following status register flags can be cleared:
101 * - #kI3C_MasterSlaveStartFlag
102 * - #kI3C_MasterControlDoneFlag
103 * - #kI3C_MasterCompleteFlag
104 * - #kI3C_MasterArbitrationWonFlag
105 * - #kI3C_MasterSlave2MasterFlag
106 *
107 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
108 * interrupts.
109 *
110 * @note These enums are meant to be OR'd together to form a bit mask.
111 */
112 enum _i3c_master_flags
113 {
114 kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */
115 kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */
116 kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */
117 kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */
118 kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */
119 kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */
120 kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */
121 kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */
122 kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */
123 kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */
124 kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag |
125 kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag,
126 };
127
128 /*!
129 * @brief I3C master error flags to indicate the causes.
130 *
131 * @note These enums are meant to be OR'd together to form a bit mask.
132 */
133 enum _i3c_master_error_flags
134 {
135 kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */
136 kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */
137 #if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM)
138 kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */
139 #endif
140 kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */
141 kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */
142 kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */
143 kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */
144 kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or
145 read/write message in wrong state */
146 kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */
147 kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */
148 kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag |
149 #if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM)
150 kI3C_MasterErrorTermFlag |
151 #endif
152 kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag |
153 kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag |
154 kI3C_MasterErrorTimeoutFlag, /*!< All error flags */
155 };
156
157 /*! @brief I3C working master state. */
158 typedef enum _i3c_master_state
159 {
160 kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */
161 kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */
162 kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */
163 kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */
164 kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */
165 kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */
166 kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */
167 kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */
168 } i3c_master_state_t;
169
170 /*! @brief I3C master enable configuration. */
171 typedef enum _i3c_master_enable
172 {
173 kI3C_MasterOff = 0U, /*!< Master off. */
174 kI3C_MasterOn = 1U, /*!< Master on. */
175 kI3C_MasterCapable = 2U /*!< Master capable. */
176 } i3c_master_enable_t;
177
178 /*! @brief I3C high keeper configuration. */
179 typedef enum _i3c_master_hkeep
180 {
181 kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */
182 kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */
183 kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */
184 kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */
185 } i3c_master_hkeep_t;
186
187 /*! @brief Emits the requested operation when doing in pieces vs. by message. */
188 typedef enum _i3c_bus_request
189 {
190 kI3C_RequestNone = 0U, /*!< No request. */
191 kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */
192 kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */
193 kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */
194 kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */
195 kI3C_RequestForceExit = 6U, /*!< Request to force exit. */
196 kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */
197 } i3c_bus_request_t;
198
199 /*! @brief Bus type with EmitStartAddr. */
200 typedef enum _i3c_bus_type
201 {
202 kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */
203 kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */
204 kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */
205 } i3c_bus_type_t;
206
207 /*! @brief IBI response. */
208 typedef enum _i3c_ibi_response
209 {
210 kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */
211 kI3C_IbiRespNack = 1U, /*!< NACK. */
212 kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */
213 kI3C_IbiRespManual = 3U, /*!< Reserved. */
214 } i3c_ibi_response_t;
215
216 /*! @brief IBI type. */
217 typedef enum _i3c_ibi_type
218 {
219 kI3C_IbiNormal = 0U, /*!< In-band interrupt. */
220 kI3C_IbiHotJoin = 1U, /*!< slave hot join. */
221 kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */
222 } i3c_ibi_type_t;
223
224 /*! @brief IBI state. */
225 typedef enum _i3c_ibi_state
226 {
227 kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */
228 kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */
229 kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */
230 } i3c_ibi_state_t;
231
232 /*! @brief Direction of master and slave transfers. */
233 typedef enum _i3c_direction
234 {
235 kI3C_Write = 0U, /*!< Master transmit. */
236 kI3C_Read = 1U /*!< Master receive. */
237 } i3c_direction_t;
238
239 /*! @brief Watermark of TX int/dma trigger level. */
240 typedef enum _i3c_tx_trigger_level
241 {
242 kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */
243 kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */
244 kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */
245 kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */
246 } i3c_tx_trigger_level_t;
247
248 /*! @brief Watermark of RX int/dma trigger level. */
249 typedef enum _i3c_rx_trigger_level
250 {
251 kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */
252 kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */
253 kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */
254 kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */
255 } i3c_rx_trigger_level_t;
256
257 /*! @brief I3C master read termination operations. */
258 typedef enum _i3c_rx_term_ops
259 {
260 kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */
261 kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */
262 kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */
263 } i3c_rx_term_ops_t;
264
265 /*! @brief Structure with setting master IBI rules and slave registry. */
266 typedef struct _i3c_register_ibi_addr
267 {
268 uint8_t address[5]; /*!< Address array for registry. */
269 bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */
270 } i3c_register_ibi_addr_t;
271
272 /*! @brief Structure with I3C baudrate settings. */
273 typedef struct _i3c_baudrate
274 {
275 uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */
276 uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */
277 uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */
278 } i3c_baudrate_hz_t;
279
280 /*! @brief I3C DAA baud rate configuration. */
281 typedef struct _i3c_master_daa_baudrate
282 {
283 uint32_t sourceClock_Hz; /*!< FCLK, function clock in Hertz. */
284 uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */
285 uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */
286 } i3c_master_daa_baudrate_t;
287
288 /*!
289 * @brief Structure with settings to initialize the I3C master module.
290 *
291 * This structure holds configuration settings for the I3C peripheral. To initialize this
292 * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and
293 * pass a pointer to your configuration structure instance.
294 *
295 * The configuration structure can be made constant so it resides in flash.
296 */
297 typedef struct _i3c_master_config
298 {
299 i3c_master_enable_t enableMaster; /*!< Enable master mode. */
300 bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */
301 i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */
302 bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */
303 bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
304 i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */
305 } i3c_master_config_t;
306
307 /* Forward declaration of the transfer descriptor and handle typedefs. */
308 typedef struct _i3c_master_transfer i3c_master_transfer_t;
309 typedef struct _i3c_master_handle i3c_master_handle_t;
310
311 /*! @brief i3c master callback functions. */
312 typedef struct _i3c_master_transfer_callback
313 {
314 void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */
315 void (*ibiCallback)(I3C_Type *base,
316 i3c_master_handle_t *handle,
317 i3c_ibi_type_t ibiType,
318 i3c_ibi_state_t ibiState); /*!< IBI event callback */
319 void (*transferComplete)(I3C_Type *base,
320 i3c_master_handle_t *handle,
321 status_t completionStatus,
322 void *userData); /*!< Transfer complete callback */
323 } i3c_master_transfer_callback_t;
324 /*!
325 * @brief Transfer option flags.
326 *
327 * @note These enumerations are intended to be OR'd together to form a bit mask of options for
328 * the #_i3c_master_transfer::flags field.
329 */
330 enum _i3c_master_transfer_flags
331 {
332 kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */
333 kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */
334 kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
335 kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */
336 kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */
337 kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */
338 kI3C_TransferRxAutoTermFlag =
339 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */
340 kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */
341 };
342
343 /*!
344 * @brief Non-blocking transfer descriptor structure.
345 *
346 * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API.
347 */
348 struct _i3c_master_transfer
349 {
350 uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available
351 options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */
352 uint8_t slaveAddress; /*!< The 7-bit slave address. */
353 i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */
354 uint32_t subaddress; /*!< Sub address. Transferred MSB first. */
355 size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
356 void *data; /*!< Pointer to data to transfer. */
357 size_t dataSize; /*!< Number of bytes to transfer. */
358 i3c_bus_type_t busType; /*!< bus type. */
359 i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */
360 };
361
362 /*!
363 * @brief Driver handle for master non-blocking APIs.
364 * @note The contents of this structure are private and subject to change.
365 */
366 struct _i3c_master_handle
367 {
368 uint8_t state; /*!< Transfer state machine current state. */
369 uint32_t remainingBytes; /*!< Remaining byte count in current state. */
370 i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */
371 i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
372 uint8_t ibiAddress; /*!< Slave address which request IBI. */
373 uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */
374 size_t ibiPayloadSize; /*!< IBI payload size. */
375 i3c_ibi_type_t ibiType; /*!< IBI type. */
376 i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */
377 void *userData; /*!< Application data passed to callback. */
378 };
379
380 /*! @brief Typedef for master interrupt handler. */
381 typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle);
382
383 /*! @} */
384
385 /*!
386 * @addtogroup i3c_slave_driver
387 * @{
388 */
389
390 /*!
391 * @brief I3C slave peripheral flags.
392 *
393 * The following status register flags can be cleared:
394 * - #kI3C_SlaveBusStartFlag
395 * - #kI3C_SlaveMatchedFlag
396 * - #kI3C_SlaveBusStopFlag
397 *
398 * Only below flags can be enabled as interrupts.
399 * - #kI3C_SlaveBusStartFlag
400 * - #kI3C_SlaveMatchedFlag
401 * - #kI3C_SlaveBusStopFlag
402 * - #kI3C_SlaveRxReadyFlag
403 * - #kI3C_SlaveTxReadyFlag
404 * - #kI3C_SlaveDynamicAddrChangedFlag
405 * - #kI3C_SlaveReceivedCCCFlag
406 * - #kI3C_SlaveErrorFlag
407 * - #kI3C_SlaveHDRCommandMatchFlag
408 * - #kI3C_SlaveCCCHandledFlag
409 * - #kI3C_SlaveEventSentFlag
410
411 * @note These enums are meant to be OR'd together to form a bit mask.
412 */
413 enum _i3c_slave_flags
414 {
415 kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */
416 kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is
417 listening to the bus traffic or responding */
418 kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR
419 read from slave, or is IBI pushing out. */
420 kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR
421 write to slave, except slave in ENTDAA mode */
422 kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */
423 kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */
424 kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */
425 kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */
426 kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!<Stop event is seen since the bus was last cleared */
427 kI3C_SlaveRxReadyFlag = I3C_SSTATUS_RX_PEND_MASK, /*!< Rx data ready in rx buffer flag */
428 kI3C_SlaveTxReadyFlag = I3C_SSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */
429 kI3C_SlaveDynamicAddrChangedFlag =
430 I3C_SSTATUS_DACHG_MASK, /*!< Slave dynamic address has been assigned, re-assigned, or lost */
431 kI3C_SlaveReceivedCCCFlag = I3C_SSTATUS_CCC_MASK, /*!< Slave received Common command code */
432 kI3C_SlaveErrorFlag = I3C_SSTATUS_ERRWARN_MASK, /*!< Error occurred flag */
433 kI3C_SlaveHDRCommandMatchFlag = I3C_SSTATUS_HDRMATCH_MASK, /*!< High data rate command match */
434 kI3C_SlaveCCCHandledFlag =
435 I3C_SSTATUS_CHANDLED_MASK, /*!< Slave received Common command code is handled by I3C module */
436 kI3C_SlaveEventSentFlag = I3C_SSTATUS_EVENT_MASK, /*!< Slave IBI/P2P/MR/HJ event has been sent */
437 kI3C_SlaveIbiDisableFlag = I3C_SSTATUS_IBIDIS_MASK, /*!< Slave in band interrupt is disabled. */
438 kI3C_SlaveMasterRequestDisabledFlag = I3C_SSTATUS_MRDIS_MASK, /*!< Slave master request is disabled. */
439 kI3C_SlaveHotJoinDisabledFlag = I3C_SSTATUS_HJDIS_MASK, /*!< Slave Hot-Join is disabled. */
440 /*! All flags which are cleared by the driver upon starting a transfer. */
441 kI3C_SlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag,
442
443 kI3C_SlaveAllIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag |
444 kI3C_SlaveRxReadyFlag | kI3C_SlaveTxReadyFlag | kI3C_SlaveDynamicAddrChangedFlag |
445 kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | kI3C_SlaveHDRCommandMatchFlag |
446 kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag,
447
448 };
449
450 /*!
451 * @brief I3C slave error flags to indicate the causes.
452 *
453 * @note These enums are meant to be OR'd together to form a bit mask.
454 */
455 enum _i3c_slave_error_flags
456 {
457 kI3C_SlaveErrorOverrunFlag = I3C_SERRWARN_ORUN_MASK, /*!< Slave internal from-bus buffer/FIFO overrun. */
458 kI3C_SlaveErrorUnderrunFlag = I3C_SERRWARN_URUN_MASK, /*!< Slave internal to-bus buffer/FIFO underrun */
459 kI3C_SlaveErrorUnderrunNakFlag =
460 I3C_SERRWARN_URUNNACK_MASK, /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */
461 kI3C_SlaveErrorTermFlag = I3C_SERRWARN_TERM_MASK, /*!< Terminate error from master */
462 kI3C_SlaveErrorInvalidStartFlag = I3C_SERRWARN_INVSTART_MASK, /*!< Slave invalid start flag */
463 kI3C_SlaveErrorSdrParityFlag = I3C_SERRWARN_SPAR_MASK, /*!< SDR parity error */
464 kI3C_SlaveErrorHdrParityFlag = I3C_SERRWARN_HPAR_MASK, /*!< HDR parity error */
465 kI3C_SlaveErrorHdrCRCFlag = I3C_SERRWARN_HCRC_MASK, /*!< HDR-DDR CRC error */
466 kI3C_SlaveErrorS0S1Flag = I3C_SERRWARN_S0S1_MASK, /*!< S0 or S1 error */
467 kI3C_SlaveErrorOverreadFlag = I3C_SERRWARN_OREAD_MASK, /*!< Over-read error */
468 kI3C_SlaveErrorOverwriteFlag = I3C_SERRWARN_OWRITE_MASK, /*!< Over-write error */
469 };
470
471 /*! @brief I3C slave.event */
472 typedef enum _i3c_slave_event
473 {
474 kI3C_SlaveEventNormal = 0U, /*!< Normal mode. */
475 kI3C_SlaveEventIBI = 1U, /*!< In band interrupt event. */
476 kI3C_SlaveEventMasterReq = 2U, /*!< Master request event. */
477 kI3C_SlaveEventHotJoinReq = 3U, /*!< Hot-join event. */
478 } i3c_slave_event_t;
479
480 /*! @brief I3C slave.activity state */
481 typedef enum _i3c_slave_activity_state
482 {
483 kI3C_SlaveNoLatency = 0U, /*!< Normal bus operation */
484 kI3C_SlaveLatency1Ms = 1U, /*!< 1ms of latency. */
485 kI3C_SlaveLatency100Ms = 2U, /*!< 100ms of latency. */
486 kI3C_SlaveLatency10S = 3U, /*!< 10s latency. */
487 } i3c_slave_activity_state_t;
488
489 /*!
490 * @brief Structure with settings to initialize the I3C slave module.
491 *
492 * This structure holds configuration settings for the I3C peripheral. To initialize this
493 * structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and
494 * pass a pointer to your configuration structure instance.
495 *
496 * The configuration structure can be made constant so it resides in flash.
497 */
498 typedef struct _i3c_slave_config
499 {
500 bool enableSlave; /*!< Whether to enable slave. */
501 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
502 bool isHotJoin; /*!< Whether to enable slave hotjoin before enable slave. */
503 #endif
504 uint8_t staticAddr; /*!< Static address. */
505 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
506 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
507 bool enableRandomPart; /*!< Whether to generate random part number, if using random part number,
508 the partNumber variable setting is meaningless. */
509 #endif
510 uint32_t partNumber; /*!< Device part number info */
511 uint8_t dcr; /*!< Device characteristics register information. */
512 uint8_t bcr; /*!< Bus characteristics register information. */
513 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. */
514 bool nakAllRequest; /*!< Whether to reply NAK to all requests except broadcast CCC. */
515 bool ignoreS0S1Error; /*!< Whether to ignore S0/S1 error in SDR mode. */
516 bool offline; /*!< Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. */
517 bool matchSlaveStartStop; /*!< Whether to assert start/stop status only the time slave is addressed. */
518 uint32_t maxWriteLength; /*!< Maximum write length. */
519 uint32_t maxReadLength; /*!< Maximum read length. */
520 } i3c_slave_config_t;
521
522 /*!
523 * @brief Set of events sent to the callback for non blocking slave transfers.
524 *
525 * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
526 * events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable.
527 * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
528 * parameter.
529 *
530 * @note These enumerations are meant to be OR'd together to form a bit mask of events.
531 */
532 typedef enum _i3c_slave_transfer_event
533 {
534 kI3C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
535 kI3C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit
536 (slave-transmitter role). */
537 kI3C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received
538 data (slave-receiver role). */
539 kI3C_SlaveRequiredTransmitEvent = 0x08U, /*!< Callback is requested to provide a buffer in which to place received
540 data (slave-receiver role). */
541 kI3C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
542 kI3C_SlaveHDRCommandMatchEvent = 0x20U, /*!< Slave Match HDR Command. */
543 kI3C_SlaveCompletionEvent = 0x40U, /*!< A stop was detected, completing the transfer. */
544 kI3C_SlaveRequestSentEvent = 0x80U, /*!< Slave request event sent. */
545 kI3C_SlaveReceivedCCCEvent = 0x100L, /*!< Slave received CCC event, need to handle by application. */
546
547 /*! Bit mask of all available events. */
548 kI3C_SlaveAllEvents = kI3C_SlaveAddressMatchEvent | kI3C_SlaveTransmitEvent | kI3C_SlaveReceiveEvent |
549 kI3C_SlaveStartEvent | kI3C_SlaveHDRCommandMatchEvent | kI3C_SlaveCompletionEvent |
550 kI3C_SlaveRequestSentEvent | kI3C_SlaveReceivedCCCEvent,
551 } i3c_slave_transfer_event_t;
552
553 /*! @brief I3C slave transfer structure */
554 typedef struct _i3c_slave_transfer
555 {
556 uint32_t event; /*!< Reason the callback is being invoked. */
557 uint8_t *txData; /*!< Transfer buffer */
558 size_t txDataSize; /*!< Transfer size */
559 uint8_t *rxData; /*!< Transfer buffer */
560 size_t rxDataSize; /*!< Transfer size */
561 status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for
562 #kI3C_SlaveCompletionEvent. */
563 size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */
564 } i3c_slave_transfer_t;
565
566 /* Forward declaration. */
567 typedef struct _i3c_slave_handle i3c_slave_handle_t;
568
569 /*!
570 * @brief Slave event callback function pointer type.
571 *
572 * This callback is used only for the slave non-blocking transfer API. To install a callback,
573 * use the I3C_SlaveSetCallback() function after you have created a handle.
574 *
575 * @param base Base address for the I3C instance on which the event occurred.
576 * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
577 * @param userData Arbitrary pointer-sized value passed from the application.
578 */
579 typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData);
580
581 /*!
582 * @brief I3C slave handle structure.
583 * @note The contents of this structure are private and subject to change.
584 */
585 struct _i3c_slave_handle
586 {
587 i3c_slave_transfer_t transfer; /*!< I3C slave transfer copy. */
588 bool isBusy; /*!< Whether transfer is busy. */
589 bool wasTransmit; /*!< Whether the last transfer was a transmit. */
590 uint32_t eventMask; /*!< Mask of enabled events. */
591 uint32_t transferredCount; /*!< Count of bytes transferred. */
592 i3c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
593 void *userData; /*!< Callback parameter passed to callback. */
594 uint8_t txFifoSize; /*!< Tx Fifo size */
595 };
596
597 /*! @brief Typedef for slave interrupt handler. */
598 typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle);
599 /*! @} */
600
601 /*!
602 * @addtogroup i3c_common_driver
603 * @{
604 */
605
606 /*!
607 * @brief Structure with settings to initialize the I3C module, could both initialize master and slave functionality.
608 *
609 * This structure holds configuration settings for the I3C peripheral. To initialize this
610 * structure to reasonable defaults, call the I3C_GetDefaultConfig() function and
611 * pass a pointer to your configuration structure instance.
612 *
613 * The configuration structure can be made constant so it resides in flash.
614 */
615 typedef struct _i3c_config
616 {
617 i3c_master_enable_t enableMaster; /*!< Enable master mode. */
618 bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */
619 i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */
620 bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */
621 bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
622 i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */
623 uint8_t masterDynamicAddress; /*!< Main master dynamic address configuration. */
624 uint32_t slowClock_Hz; /*!< Slow clock frequency for time control. */
625 uint32_t maxWriteLength; /*!< Maximum write length. */
626 uint32_t maxReadLength; /*!< Maximum read length. */
627 bool enableSlave; /*!< Whether to enable slave. */
628 uint8_t staticAddr; /*!< Static address. */
629 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
630 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
631 bool enableRandomPart; /*!< Whether to generate random part number, if using random part number,
632 the partNumber variable setting is meaningless. */
633 #endif
634 uint32_t partNumber; /*!< Device part number info */
635 uint8_t dcr; /*!< Device characteristics register information. */
636 uint8_t bcr; /*!< Bus characteristics register information. */
637 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. */
638 bool nakAllRequest; /*!< Whether to reply NAK to all requests except broadcast CCC. */
639 bool ignoreS0S1Error; /*!< Whether to ignore S0/S1 error in SDR mode. */
640 bool offline; /*!< Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. */
641 bool matchSlaveStartStop; /*!< Whether to assert start/stop status only the time slave is addressed. */
642 } i3c_config_t;
643
644 /*! @} */
645
646 /*******************************************************************************
647 * Variables
648 ******************************************************************************/
649 /*! Array to map I3C instance number to IRQ number. */
650 extern IRQn_Type const kI3cIrqs[];
651
652 /*! Pointer to master IRQ handler for each instance. */
653 extern i3c_master_isr_t s_i3cMasterIsr;
654
655 /*! Pointers to master handles for each instance. */
656 extern void *s_i3cMasterHandle[];
657
658 /*! Pointers to slave handles for each instance. */
659 extern void *s_i3cSlaveHandle[];
660
661 /*! @brief Pointers to slave IRQ handler. */
662 extern i3c_slave_isr_t s_i3cSlaveIsr;
663 /*******************************************************************************
664 * API
665 ******************************************************************************/
666 #
667 #if defined(__cplusplus)
668 extern "C" {
669 #endif
670
671 /*!
672 * @addtogroup i3c_common_driver
673 * @{
674 */
675 /*!
676 * @brief Get which instance current I3C is used.
677 * @param base The I3C peripheral base address.
678 */
679 uint32_t I3C_GetInstance(I3C_Type *base);
680 /*!
681 * @brief Provides a default configuration for the I3C peripheral, the configuration covers both master
682 * functionality and slave functionality.
683 *
684 * This function provides the following default configuration for I3C:
685 * @code
686 * config->enableMaster = kI3C_MasterCapable;
687 * config->disableTimeout = false;
688 * config->hKeep = kI3C_MasterHighKeeperNone;
689 * config->enableOpenDrainStop = true;
690 * config->enableOpenDrainHigh = true;
691 * config->baudRate_Hz.i2cBaud = 400000U;
692 * config->baudRate_Hz.i3cPushPullBaud = 12500000U;
693 * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U;
694 * config->masterDynamicAddress = 0x0AU;
695 * config->slowClock_Hz = 1000000U;
696 * config->enableSlave = true;
697 * config->vendorID = 0x11BU;
698 * config->enableRandomPart = false;
699 * config->partNumber = 0;
700 * config->dcr = 0;
701 * config->bcr = 0;
702 * config->hdrMode = (uint8_t)kI3C_HDRModeDDR;
703 * config->nakAllRequest = false;
704 * config->ignoreS0S1Error = false;
705 * config->offline = false;
706 * config->matchSlaveStartStop = false;
707 * @endcode
708 *
709 * After calling this function, you can override any settings in order to customize the configuration,
710 * prior to initializing the common I3C driver with I3C_Init().
711 *
712 * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t.
713 */
714 void I3C_GetDefaultConfig(i3c_config_t *config);
715
716 /*!
717 * @brief Initializes the I3C peripheral.
718 * This function enables the peripheral clock and initializes the I3C peripheral as described by the user
719 * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C
720 * module could work as pure master, pure slave or secondary master, etc.
721 * A software reset is performed prior to configuration.
722 *
723 * @param base The I3C peripheral base address.
724 * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of
725 * defaults that you can override.
726 * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors,
727 * filter widths, and timeout periods.
728 */
729 void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz);
730
731 /*! @} */
732
733 /*!
734 * @addtogroup i3c_master_driver
735 * @{
736 */
737
738 /*! @name Initialization and deinitialization */
739 /*@{*/
740
741 /*!
742 * @brief Provides a default configuration for the I3C master peripheral.
743 *
744 * This function provides the following default configuration for the I3C master peripheral:
745 * @code
746 * masterConfig->enableMaster = kI3C_MasterOn;
747 * masterConfig->disableTimeout = false;
748 * masterConfig->hKeep = kI3C_MasterHighKeeperNone;
749 * masterConfig->enableOpenDrainStop = true;
750 * masterConfig->enableOpenDrainHigh = true;
751 * masterConfig->baudRate_Hz = 100000U;
752 * masterConfig->busType = kI3C_TypeI2C;
753 * @endcode
754 *
755 * After calling this function, you can override any settings in order to customize the configuration,
756 * prior to initializing the master driver with I3C_MasterInit().
757 *
758 * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t.
759 */
760 void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig);
761
762 /*!
763 * @brief Initializes the I3C master peripheral.
764 *
765 * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user
766 * provided configuration. A software reset is performed prior to configuration.
767 *
768 * @param base The I3C peripheral base address.
769 * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of
770 * defaults that you can override.
771 * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors,
772 * filter widths, and timeout periods.
773 */
774 void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz);
775
776 /*!
777 * @brief Deinitializes the I3C master peripheral.
778 *
779 * This function disables the I3C master peripheral and gates the clock. It also performs a software
780 * reset to restore the peripheral to reset conditions.
781 *
782 * @param base The I3C peripheral base address.
783 */
784 void I3C_MasterDeinit(I3C_Type *base);
785
786 /* Not static so it can be used from fsl_i3c_dma.c. */
787 status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status);
788
789 /* Not static so it can be used from fsl_i3c_dma.c. */
790 status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle);
791
792 /* Not static so it can be used from fsl_i3c_dma.c. */
793 status_t I3C_CheckForBusyBus(I3C_Type *base);
794
795 /*!
796 * @brief Set I3C module master mode.
797 *
798 * @param base The I3C peripheral base address.
799 * @param enable Enable master mode.
800 */
I3C_MasterEnable(I3C_Type * base,i3c_master_enable_t enable)801 static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)
802 {
803 base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable);
804 }
805
806 /*@}*/
807
808 /*! @name Status */
809 /*@{*/
810
811 /*!
812 * @brief Gets the I3C master status flags.
813 *
814 * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit
815 * in the return value is set if the flag is asserted.
816 *
817 * @param base The I3C peripheral base address.
818 * @return State of the status flags:
819 * - 1: related status flag is set.
820 * - 0: related status flag is not set.
821 * @see _i3c_master_flags
822 */
I3C_MasterGetStatusFlags(I3C_Type * base)823 static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)
824 {
825 return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK);
826 }
827
828 /*!
829 * @brief Clears the I3C master status flag state.
830 *
831 * The following status register flags can be cleared:
832 * - #kI3C_MasterSlaveStartFlag
833 * - #kI3C_MasterControlDoneFlag
834 * - #kI3C_MasterCompleteFlag
835 * - #kI3C_MasterArbitrationWonFlag
836 * - #kI3C_MasterSlave2MasterFlag
837 *
838 * Attempts to clear other flags has no effect.
839 *
840 * @param base The I3C peripheral base address.
841 * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
842 * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to
843 * I3C_MasterGetStatusFlags().
844 * @see _i3c_master_flags.
845 */
I3C_MasterClearStatusFlags(I3C_Type * base,uint32_t statusMask)846 static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)
847 {
848 base->MSTATUS = statusMask;
849 }
850
851 /*!
852 * @brief Gets the I3C master error status flags.
853 *
854 * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit
855 * in the return value is set if the flag is asserted.
856 *
857 * @param base The I3C peripheral base address.
858 * @return State of the error status flags:
859 * - 1: related status flag is set.
860 * - 0: related status flag is not set.
861 * @see _i3c_master_error_flags
862 */
I3C_MasterGetErrorStatusFlags(I3C_Type * base)863 static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)
864 {
865 return base->MERRWARN;
866 }
867
868 /*!
869 * @brief Clears the I3C master error status flag state.
870 *
871 * @param base The I3C peripheral base address.
872 * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of
873 * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to
874 * I3C_MasterGetStatusFlags().
875 * @see _i3c_master_error_flags.
876 */
I3C_MasterClearErrorStatusFlags(I3C_Type * base,uint32_t statusMask)877 static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
878 {
879 while ((base->MERRWARN & statusMask) != 0U)
880 {
881 base->MERRWARN = statusMask;
882 }
883 }
884
885 /*!
886 * @brief Gets the I3C master state.
887 *
888 * @param base The I3C peripheral base address.
889 * @return I3C master state.
890 */
891 i3c_master_state_t I3C_MasterGetState(I3C_Type *base);
892
893 /*@}*/
894
895 /*! @name Interrupts */
896 /*@{*/
897
898 /*!
899 * @brief Enables the I3C master interrupt requests.
900 *
901 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
902 * interrupts.
903 *
904 * @param base The I3C peripheral base address.
905 * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set
906 * of constants that should be OR'd together to form the bit mask.
907 */
I3C_MasterEnableInterrupts(I3C_Type * base,uint32_t interruptMask)908 static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
909 {
910 base->MINTSET |= interruptMask;
911 }
912
913 /*!
914 * @brief Disables the I3C master interrupt requests.
915 *
916 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
917 * interrupts.
918 *
919 * @param base The I3C peripheral base address.
920 * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set
921 * of constants that should be OR'd together to form the bit mask.
922 */
I3C_MasterDisableInterrupts(I3C_Type * base,uint32_t interruptMask)923 static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
924 {
925 base->MINTCLR = interruptMask;
926 }
927
928 /*!
929 * @brief Returns the set of currently enabled I3C master interrupt requests.
930 *
931 * @param base The I3C peripheral base address.
932 * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the
933 * set of enabled interrupts.
934 */
I3C_MasterGetEnabledInterrupts(I3C_Type * base)935 static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)
936 {
937 return base->MINTSET;
938 }
939
940 /*!
941 * @brief Returns the set of pending I3C master interrupt requests.
942 *
943 * @param base The I3C peripheral base address.
944 * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the
945 * set of pending interrupts.
946 */
I3C_MasterGetPendingInterrupts(I3C_Type * base)947 static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)
948 {
949 return base->MINTMASKED;
950 }
951
952 /*@}*/
953
954 /*! @name DMA control */
955 /*@{*/
956
957 /*!
958 * @brief Enables or disables I3C master DMA requests.
959 *
960 * @param base The I3C peripheral base address.
961 * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable.
962 * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable.
963 * @param width DMA read/write unit in bytes.
964 */
I3C_MasterEnableDMA(I3C_Type * base,bool enableTx,bool enableRx,uint32_t width)965 static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
966 {
967 assert(width <= 2U);
968 base->MDMACTRL =
969 I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width);
970 }
971
972 /*!
973 * @brief Gets I3C master transmit data register address for DMA transfer.
974 *
975 * @param base The I3C peripheral base address.
976 * @param width DMA read/write unit in bytes.
977 * @return The I3C Master Transmit Data Register address.
978 */
I3C_MasterGetTxFifoAddress(I3C_Type * base,uint32_t width)979 static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)
980 {
981 assert(width <= 2U);
982 return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB);
983 }
984
985 /*!
986 * @brief Gets I3C master receive data register address for DMA transfer.
987 *
988 * @param base The I3C peripheral base address.
989 * @param width DMA read/write unit in bytes.
990 * @return The I3C Master Receive Data Register address.
991 */
I3C_MasterGetRxFifoAddress(I3C_Type * base,uint32_t width)992 static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)
993 {
994 assert(width <= 2U);
995 return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB);
996 }
997
998 /*@}*/
999
1000 /*! @name FIFO control */
1001 /*@{*/
1002
1003 /*!
1004 * @brief Sets the watermarks for I3C master FIFOs.
1005 *
1006 * @param base The I3C peripheral base address.
1007 * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever
1008 * the number of words in the transmit FIFO reaches @a txLvl.
1009 * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever
1010 * the number of words in the receive FIFO reaches @a rxLvl.
1011 * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
1012 * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
1013 */
I3C_MasterSetWatermarks(I3C_Type * base,i3c_tx_trigger_level_t txLvl,i3c_rx_trigger_level_t rxLvl,bool flushTx,bool flushRx)1014 static inline void I3C_MasterSetWatermarks(
1015 I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
1016 {
1017 base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) |
1018 (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U);
1019 }
1020
1021 /*!
1022 * @brief Gets the current number of bytes in the I3C master FIFOs.
1023 *
1024 * @param base The I3C peripheral base address.
1025 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
1026 * Pass NULL if this value is not required.
1027 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
1028 * Pass NULL if this value is not required.
1029 */
I3C_MasterGetFifoCounts(I3C_Type * base,size_t * rxCount,size_t * txCount)1030 static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
1031 {
1032 if (NULL != txCount)
1033 {
1034 *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT;
1035 }
1036 if (NULL != rxCount)
1037 {
1038 *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT;
1039 }
1040 }
1041
1042 /*@}*/
1043
1044 /*! @name Bus operations */
1045 /*@{*/
1046
1047 /*!
1048 * @brief Sets the I3C bus frequency for master transactions.
1049 *
1050 * The I3C master is automatically disabled and re-enabled as necessary to configure the baud
1051 * rate. Do not call this function during a transfer, or the transfer is aborted.
1052 *
1053 * @param base The I3C peripheral base address.
1054 * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz.
1055 * @param sourceClock_Hz I3C functional clock frequency in Hertz.
1056 */
1057 void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz);
1058
1059 /*!
1060 * @brief Returns whether the bus is idle.
1061 *
1062 * Requires the master mode to be enabled.
1063 *
1064 * @param base The I3C peripheral base address.
1065 * @retval true Bus is busy.
1066 * @retval false Bus is idle.
1067 */
I3C_MasterGetBusIdleState(I3C_Type * base)1068 static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)
1069 {
1070 return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false);
1071 }
1072
1073 /*!
1074 * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified
1075 * in the call.
1076 *
1077 * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
1078 * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
1079 * 7-bit address specified in the a address parameter. Note that this function does not actually wait
1080 * until the START and address are successfully sent on the bus before returning.
1081 *
1082 * @param base The I3C peripheral base address.
1083 * @param type The bus type to use in this transaction.
1084 * @param address 7-bit slave device address, in bits [6:0].
1085 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1086 * the R/w bit (bit 0) in the transmitted slave address.
1087 * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
1088 * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
1089 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1090 */
1091 status_t I3C_MasterStartWithRxSize(
1092 I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
1093
1094 /*!
1095 * @brief Sends a START signal and slave address on the I2C/I3C bus.
1096 *
1097 * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
1098 * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
1099 * 7-bit address specified in the @a address parameter. Note that this function does not actually wait
1100 * until the START and address are successfully sent on the bus before returning.
1101 *
1102 * @param base The I3C peripheral base address.
1103 * @param type The bus type to use in this transaction.
1104 * @param address 7-bit slave device address, in bits [6:0].
1105 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1106 * the R/w bit (bit 0) in the transmitted slave address.
1107 * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
1108 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1109 */
1110 status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir);
1111
1112 /*!
1113 * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified
1114 * in the call.
1115 *
1116 * This function is used to send a Repeated START signal when a transfer is already in progress. Like
1117 * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read
1118 * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer
1119 * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize
1120 * configuration.
1121 *
1122 * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
1123 * as well as to better document the intent of code that uses these APIs.
1124 *
1125 * @param base The I3C peripheral base address.
1126 * @param type The bus type to use in this transaction.
1127 * @param address 7-bit slave device address, in bits [6:0].
1128 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1129 * the R/w bit (bit 0) in the transmitted slave address.
1130 * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
1131 * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
1132 */
1133 status_t I3C_MasterRepeatedStartWithRxSize(
1134 I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
1135
1136 /*!
1137 * @brief Sends a repeated START signal and slave address on the I2C/I3C bus.
1138 *
1139 * This function is used to send a Repeated START signal when a transfer is already in progress. Like
1140 * I3C_MasterStart(), it also sends the specified 7-bit address.
1141 *
1142 * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
1143 * as well as to better document the intent of code that uses these APIs.
1144 *
1145 * @param base The I3C peripheral base address.
1146 * @param type The bus type to use in this transaction.
1147 * @param address 7-bit slave device address, in bits [6:0].
1148 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1149 * the R/w bit (bit 0) in the transmitted slave address.
1150 * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
1151 */
I3C_MasterRepeatedStart(I3C_Type * base,i3c_bus_type_t type,uint8_t address,i3c_direction_t dir)1152 static inline status_t I3C_MasterRepeatedStart(I3C_Type *base,
1153 i3c_bus_type_t type,
1154 uint8_t address,
1155 i3c_direction_t dir)
1156 {
1157 return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0);
1158 }
1159
1160 /*!
1161 * @brief Performs a polling send transfer on the I2C/I3C bus.
1162 *
1163 * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
1164 * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
1165 * function returns #kStatus_I3C_Nak.
1166 *
1167 * @param base The I3C peripheral base address.
1168 * @param txBuff The pointer to the data to be transferred.
1169 * @param txSize The length in bytes of the data to be transferred.
1170 * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options.
1171 * @retval #kStatus_Success Data was sent successfully.
1172 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1173 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1174 * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address.
1175 * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write.
1176 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1177 * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full.
1178 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1179 */
1180 status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
1181
1182 /*!
1183 * @brief Performs a polling receive transfer on the I2C/I3C bus.
1184 *
1185 * @param base The I3C peripheral base address.
1186 * @param rxBuff The pointer to the data to be transferred.
1187 * @param rxSize The length in bytes of the data to be transferred.
1188 * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options.
1189 * @retval #kStatus_Success Data was received successfully.
1190 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1191 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1192 * @retval #kStatus_I3C_Term The master terminates slave read.
1193 * @retval #kStatus_I3C_HdrParityError Parity error from DDR read.
1194 * @retval #kStatus_I3C_CrcError CRC error from DDR read.
1195 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1196 * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty.
1197 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1198 */
1199 status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
1200
1201 /*!
1202 * @brief Sends a STOP signal on the I2C/I3C bus.
1203 *
1204 * This function does not return until the STOP signal is seen on the bus, or an error occurs.
1205 *
1206 * @param base The I3C peripheral base address.
1207 * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated.
1208 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1209 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1210 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1211 */
1212 status_t I3C_MasterStop(I3C_Type *base);
1213
1214 /*!
1215 * @brief I3C master emit request.
1216 *
1217 * @param base The I3C peripheral base address.
1218 * @param masterReq I3C master request of type #i3c_bus_request_t
1219 */
1220 void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq);
1221
1222 /*!
1223 * @brief I3C master emit request.
1224 *
1225 * @param base The I3C peripheral base address.
1226 * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t
1227 */
I3C_MasterEmitIBIResponse(I3C_Type * base,i3c_ibi_response_t ibiResponse)1228 static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)
1229 {
1230 uint32_t ctrlVal = base->MCTRL;
1231 ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK);
1232 ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack);
1233 base->MCTRL = ctrlVal;
1234 }
1235
1236 /*!
1237 * @brief I3C master register IBI rule.
1238 *
1239 * @param base The I3C peripheral base address.
1240 * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t
1241 */
1242 void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule);
1243
1244 /*!
1245 * @brief I3C master get IBI rule.
1246 *
1247 * @param base The I3C peripheral base address.
1248 * @param ibiRule Pointer to store the read out ibi rule description.
1249 */
1250 void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule);
1251
1252 /*!
1253 * @brief I3C master get IBI Type.
1254 *
1255 * @param base The I3C peripheral base address.
1256 * @retval i3c_ibi_type_t Type of #i3c_ibi_type_t.
1257 */
1258 i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base);
1259
1260 /*!
1261 * @brief I3C master get IBI Address.
1262 *
1263 * @param base The I3C peripheral base address.
1264 * @retval The 8-bit IBI address.
1265 */
I3C_GetIBIAddress(I3C_Type * base)1266 static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)
1267 {
1268 return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT);
1269 }
1270
1271 /*!
1272 * @brief Performs a DAA in the i3c bus with specified temporary baud rate.
1273 *
1274 * @param base The I3C peripheral base address.
1275 * @param addressList The pointer for address list which is used to do DAA.
1276 * @param count The address count in the address list.
1277 * @param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting.
1278 * The initial setting is set back between the completion of the DAA and the return of this function.
1279 * @retval #kStatus_Success The transaction was started successfully.
1280 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1281 * transaction is already in progress.
1282 * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
1283 */
1284 status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base,
1285 uint8_t *addressList,
1286 uint32_t count,
1287 i3c_master_daa_baudrate_t *daaBaudRate);
1288
1289 /*!
1290 * @brief Performs a DAA in the i3c bus.
1291 *
1292 * @param base The I3C peripheral base address.
1293 * @param addressList The pointer for address list which is used to do DAA.
1294 * @param count The address count in the address list.
1295 * The initial setting is set back between the completion of the DAA and the return of this function.
1296 * @retval #kStatus_Success The transaction was started successfully.
1297 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1298 * transaction is already in progress.
1299 * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
1300 */
I3C_MasterProcessDAA(I3C_Type * base,uint8_t * addressList,uint32_t count)1301 static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)
1302 {
1303 return I3C_MasterProcessDAASpecifiedBaudrate(base, addressList, count, NULL);
1304 }
1305
1306 /*!
1307 * @brief Get device information list after DAA process is done.
1308 *
1309 * @param base The I3C peripheral base address.
1310 * @param[out] count The pointer to store the available device count.
1311 * @return Pointer to the i3c_device_info_t array.
1312 */
1313 i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count);
1314 /*!
1315 * @brief Performs a master polling transfer on the I2C/I3C bus.
1316 *
1317 * @note The API does not return until the transfer succeeds or fails due
1318 * to error happens during transfer.
1319 *
1320 * @param base The I3C peripheral base address.
1321 * @param transfer Pointer to the transfer structure.
1322 * @retval #kStatus_Success Data was received successfully.
1323 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1324 * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address.
1325 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1326 * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address.
1327 * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write.
1328 * @retval #kStatus_I3C_Term The master terminates slave read.
1329 * @retval #kStatus_I3C_HdrParityError Parity error from DDR read.
1330 * @retval #kStatus_I3C_CrcError CRC error from DDR read.
1331 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1332 * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty.
1333 * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full.
1334 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1335 */
1336 status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer);
1337
1338 /*@}*/
1339
1340 /*! @name Non-blocking */
1341 /*@{*/
1342
1343 /*!
1344 * @brief Creates a new handle for the I3C master non-blocking APIs.
1345 *
1346 * The creation of a handle is for use with the non-blocking APIs. Once a handle
1347 * is created, there is not a corresponding destroy handle. If the user wants to
1348 * terminate a transfer, the I3C_MasterTransferAbort() API shall be called.
1349 *
1350 *
1351 * @note The function also enables the NVIC IRQ for the input I3C. Need to notice
1352 * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to
1353 * enable the associated INTMUX IRQ in application.
1354 *
1355 * @param base The I3C peripheral base address.
1356 * @param[out] handle Pointer to the I3C master driver handle.
1357 * @param callback User provided pointer to the asynchronous callback function.
1358 * @param userData User provided pointer to the application callback data.
1359 */
1360 void I3C_MasterTransferCreateHandle(I3C_Type *base,
1361 i3c_master_handle_t *handle,
1362 const i3c_master_transfer_callback_t *callback,
1363 void *userData);
1364
1365 /*!
1366 * @brief Performs a non-blocking transaction on the I2C/I3C bus.
1367 *
1368 * @param base The I3C peripheral base address.
1369 * @param handle Pointer to the I3C master driver handle.
1370 * @param transfer The pointer to the transfer descriptor.
1371 * @retval #kStatus_Success The transaction was started successfully.
1372 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1373 * transaction is already in progress.
1374 */
1375 status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer);
1376
1377 /*!
1378 * @brief Returns number of bytes transferred so far.
1379 * @param base The I3C peripheral base address.
1380 * @param handle Pointer to the I3C master driver handle.
1381 * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
1382 * @retval #kStatus_Success
1383 * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
1384 */
1385 status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count);
1386
1387 /*!
1388 * @brief Terminates a non-blocking I3C master transmission early.
1389 *
1390 * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
1391 * I3C peripheral's IRQ priority.
1392 *
1393 * @param base The I3C peripheral base address.
1394 * @param handle Pointer to the I3C master driver handle.
1395 * @retval #kStatus_Success A transaction was successfully aborted.
1396 * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress.
1397 */
1398 void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle);
1399
1400 /*@}*/
1401
1402 /*! @name IRQ handler */
1403 /*@{*/
1404
1405 /*!
1406 * @brief Reusable routine to handle master interrupts.
1407 * @note This function does not need to be called unless you are reimplementing the
1408 * nonblocking API's interrupt handler routines to add special functionality.
1409 * @param base The I3C peripheral base address.
1410 * @param handle Pointer to the I3C master driver handle.
1411 */
1412 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
1413
1414 /*@}*/
1415
1416 /*! @} */
1417
1418 /*!
1419 * @addtogroup i3c_slave_driver
1420 * @{
1421 */
1422
1423 /*! @name Initialization and deinitialization */
1424 /*@{*/
1425
1426 /*!
1427 * @brief Provides a default configuration for the I3C slave peripheral.
1428 *
1429 * This function provides the following default configuration for the I3C slave peripheral:
1430 * @code
1431 * slaveConfig->enableslave = true;
1432 * @endcode
1433 *
1434 * After calling this function, you can override any settings in order to customize the configuration,
1435 * prior to initializing the slave driver with I3C_SlaveInit().
1436 *
1437 * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t.
1438 */
1439 void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig);
1440
1441 /*!
1442 * @brief Initializes the I3C slave peripheral.
1443 *
1444 * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user
1445 * provided configuration.
1446 *
1447 * @param base The I3C peripheral base address.
1448 * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
1449 * defaults that you can override.
1450 * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
1451 */
1452 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz);
1453
1454 /*!
1455 * @brief Deinitializes the I3C slave peripheral.
1456 *
1457 * This function disables the I3C slave peripheral and gates the clock.
1458 *
1459 * @param base The I3C peripheral base address.
1460 */
1461 void I3C_SlaveDeinit(I3C_Type *base);
1462
1463 /*!
1464 * @brief Enable/Disable Slave.
1465 *
1466 * @param base The I3C peripheral base address.
1467 * @param isEnable Enable or disable.
1468 */
I3C_SlaveEnable(I3C_Type * base,bool isEnable)1469 static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
1470 {
1471 base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable);
1472 }
1473
1474 /*@}*/
1475
1476 /*! @name Status */
1477 /*@{*/
1478
1479 /*!
1480 * @brief Gets the I3C slave status flags.
1481 *
1482 * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit
1483 * in the return value is set if the flag is asserted.
1484 *
1485 * @param base The I3C peripheral base address.
1486 * @return State of the status flags:
1487 * - 1: related status flag is set.
1488 * - 0: related status flag is not set.
1489 * @see _i3c_slave_flags
1490 */
I3C_SlaveGetStatusFlags(I3C_Type * base)1491 static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)
1492 {
1493 return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK);
1494 }
1495
1496 /*!
1497 * @brief Clears the I3C slave status flag state.
1498 *
1499 * The following status register flags can be cleared:
1500 * - #kI3C_SlaveBusStartFlag
1501 * - #kI3C_SlaveMatchedFlag
1502 * - #kI3C_SlaveBusStopFlag
1503 *
1504 * Attempts to clear other flags has no effect.
1505 *
1506 * @param base The I3C peripheral base address.
1507 * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
1508 * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
1509 * I3C_SlaveGetStatusFlags().
1510 * @see _i3c_slave_flags.
1511 */
I3C_SlaveClearStatusFlags(I3C_Type * base,uint32_t statusMask)1512 static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)
1513 {
1514 base->SSTATUS = statusMask;
1515 }
1516
1517 /*!
1518 * @brief Gets the I3C slave error status flags.
1519 *
1520 * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit
1521 * in the return value is set if the flag is asserted.
1522 *
1523 * @param base The I3C peripheral base address.
1524 * @return State of the error status flags:
1525 * - 1: related status flag is set.
1526 * - 0: related status flag is not set.
1527 * @see _i3c_slave_error_flags
1528 */
I3C_SlaveGetErrorStatusFlags(I3C_Type * base)1529 static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)
1530 {
1531 return base->SERRWARN;
1532 }
1533
1534 /*!
1535 * @brief Clears the I3C slave error status flag state.
1536 *
1537 * @param base The I3C peripheral base address.
1538 * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of
1539 * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to
1540 * I3C_SlaveGetErrorStatusFlags().
1541 * @see _i3c_slave_error_flags.
1542 */
I3C_SlaveClearErrorStatusFlags(I3C_Type * base,uint32_t statusMask)1543 static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
1544 {
1545 base->SERRWARN = statusMask;
1546 }
1547
1548 /*!
1549 * @brief Gets the I3C slave state.
1550 *
1551 * @param base The I3C peripheral base address.
1552 * @return I3C slave activity state, refer #i3c_slave_activity_state_t.
1553 */
1554 i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base);
1555
1556 /* Not static so it can be used from fsl_i3c_dma.c. */
1557 status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status);
1558 /*@}*/
1559
1560 /*! @name Interrupts */
1561 /*@{*/
1562
1563 /*!
1564 * @brief Enables the I3C slave interrupt requests.
1565 *
1566 * Only below flags can be enabled as interrupts.
1567 * - #kI3C_SlaveBusStartFlag
1568 * - #kI3C_SlaveMatchedFlag
1569 * - #kI3C_SlaveBusStopFlag
1570 * - #kI3C_SlaveRxReadyFlag
1571 * - #kI3C_SlaveTxReadyFlag
1572 * - #kI3C_SlaveDynamicAddrChangedFlag
1573 * - #kI3C_SlaveReceivedCCCFlag
1574 * - #kI3C_SlaveErrorFlag
1575 * - #kI3C_SlaveHDRCommandMatchFlag
1576 * - #kI3C_SlaveCCCHandledFlag
1577 * - #kI3C_SlaveEventSentFlag
1578 *
1579 * @param base The I3C peripheral base address.
1580 * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set
1581 * of constants that should be OR'd together to form the bit mask.
1582 */
I3C_SlaveEnableInterrupts(I3C_Type * base,uint32_t interruptMask)1583 static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
1584 {
1585 base->SINTSET |= interruptMask;
1586 }
1587
1588 /*!
1589 * @brief Disables the I3C slave interrupt requests.
1590 *
1591 * Only below flags can be disabled as interrupts.
1592 * - #kI3C_SlaveBusStartFlag
1593 * - #kI3C_SlaveMatchedFlag
1594 * - #kI3C_SlaveBusStopFlag
1595 * - #kI3C_SlaveRxReadyFlag
1596 * - #kI3C_SlaveTxReadyFlag
1597 * - #kI3C_SlaveDynamicAddrChangedFlag
1598 * - #kI3C_SlaveReceivedCCCFlag
1599 * - #kI3C_SlaveErrorFlag
1600 * - #kI3C_SlaveHDRCommandMatchFlag
1601 * - #kI3C_SlaveCCCHandledFlag
1602 * - #kI3C_SlaveEventSentFlag
1603 *
1604 * @param base The I3C peripheral base address.
1605 * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set
1606 * of constants that should be OR'd together to form the bit mask.
1607 */
I3C_SlaveDisableInterrupts(I3C_Type * base,uint32_t interruptMask)1608 static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
1609 {
1610 base->SINTCLR = interruptMask;
1611 }
1612
1613 /*!
1614 * @brief Returns the set of currently enabled I3C slave interrupt requests.
1615 *
1616 * @param base The I3C peripheral base address.
1617 * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the
1618 * set of enabled interrupts.
1619 */
I3C_SlaveGetEnabledInterrupts(I3C_Type * base)1620 static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)
1621 {
1622 return base->SINTSET;
1623 }
1624
1625 /*!
1626 * @brief Returns the set of pending I3C slave interrupt requests.
1627 *
1628 * @param base The I3C peripheral base address.
1629 * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the
1630 * set of pending interrupts.
1631 */
I3C_SlaveGetPendingInterrupts(I3C_Type * base)1632 static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
1633 {
1634 return base->SINTMASKED;
1635 }
1636
1637 /*@}*/
1638
1639 /*! @name DMA control */
1640 /*@{*/
1641
1642 /*!
1643 * @brief Enables or disables I3C slave DMA requests.
1644 *
1645 * @param base The I3C peripheral base address.
1646 * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable.
1647 * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable.
1648 * @param width DMA read/write unit in bytes.
1649 */
I3C_SlaveEnableDMA(I3C_Type * base,bool enableTx,bool enableRx,uint32_t width)1650 static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
1651 {
1652 assert(width <= 2U);
1653 base->SDMACTRL =
1654 I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width);
1655 }
1656
1657 /*!
1658 * @brief Gets I3C slave transmit data register address for DMA transfer.
1659 *
1660 * @param base The I3C peripheral base address.
1661 * @param width DMA read/write unit in bytes.
1662 * @return The I3C Slave Transmit Data Register address.
1663 */
I3C_SlaveGetTxFifoAddress(I3C_Type * base,uint32_t width)1664 static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)
1665 {
1666 assert(width <= 2U);
1667 return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB);
1668 }
1669
1670 /*!
1671 * @brief Gets I3C slave receive data register address for DMA transfer.
1672 *
1673 * @param base The I3C peripheral base address.
1674 * @param width DMA read/write unit in bytes.
1675 * @return The I3C Slave Receive Data Register address.
1676 */
I3C_SlaveGetRxFifoAddress(I3C_Type * base,uint32_t width)1677 static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
1678 {
1679 assert(width <= 2U);
1680 return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB);
1681 }
1682
1683 /*@}*/
1684
1685 /*! @name FIFO control */
1686 /*@{*/
1687
1688 /*!
1689 * @brief Sets the watermarks for I3C slave FIFOs.
1690 *
1691 * @param base The I3C peripheral base address.
1692 * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever
1693 * the number of words in the transmit FIFO reaches @a txLvl.
1694 * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever
1695 * the number of words in the receive FIFO reaches @a rxLvl.
1696 * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
1697 * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
1698 */
I3C_SlaveSetWatermarks(I3C_Type * base,i3c_tx_trigger_level_t txLvl,i3c_rx_trigger_level_t rxLvl,bool flushTx,bool flushRx)1699 static inline void I3C_SlaveSetWatermarks(
1700 I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
1701 {
1702 base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) |
1703 (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U);
1704 }
1705
1706 /*!
1707 * @brief Gets the current number of bytes in the I3C slave FIFOs.
1708 *
1709 * @param base The I3C peripheral base address.
1710 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
1711 * Pass NULL if this value is not required.
1712 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
1713 * Pass NULL if this value is not required.
1714 */
I3C_SlaveGetFifoCounts(I3C_Type * base,size_t * rxCount,size_t * txCount)1715 static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
1716 {
1717 if (NULL != txCount)
1718 {
1719 *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT;
1720 }
1721 if (NULL != rxCount)
1722 {
1723 *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT;
1724 }
1725 }
1726
1727 /*@}*/
1728
1729 /*! @name Bus operations */
1730 /*@{*/
1731
1732 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
1733 /*!
1734 * @brief I3C slave request event.
1735 *
1736 * @param base The I3C peripheral base address.
1737 * @param event I3C slave event of type #i3c_slave_event_t
1738 */
1739 void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event);
1740 #endif
1741
1742 /*!
1743 * @brief Performs a polling send transfer on the I3C bus.
1744 *
1745 * @param base The I3C peripheral base address.
1746 * @param txBuff The pointer to the data to be transferred.
1747 * @param txSize The length in bytes of the data to be transferred.
1748 * @return Error or success status returned by API.
1749 */
1750 status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize);
1751
1752 /*!
1753 * @brief Performs a polling receive transfer on the I3C bus.
1754 *
1755 * @param base The I3C peripheral base address.
1756 * @param rxBuff The pointer to the data to be transferred.
1757 * @param rxSize The length in bytes of the data to be transferred.
1758 * @return Error or success status returned by API.
1759 */
1760 status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize);
1761
1762 /*@}*/
1763
1764 /*! @name Slave non-blocking */
1765 /*@{*/
1766
1767 /*!
1768 * @brief Creates a new handle for the I3C slave non-blocking APIs.
1769 *
1770 * The creation of a handle is for use with the non-blocking APIs. Once a handle
1771 * is created, there is not a corresponding destroy handle. If the user wants to
1772 * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.
1773 *
1774 * @note The function also enables the NVIC IRQ for the input I3C. Need to notice
1775 * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to
1776 * enable the associated INTMUX IRQ in application.
1777
1778 * @param base The I3C peripheral base address.
1779 * @param[out] handle Pointer to the I3C slave driver handle.
1780 * @param callback User provided pointer to the asynchronous callback function.
1781 * @param userData User provided pointer to the application callback data.
1782 */
1783 void I3C_SlaveTransferCreateHandle(I3C_Type *base,
1784 i3c_slave_handle_t *handle,
1785 i3c_slave_transfer_callback_t callback,
1786 void *userData);
1787
1788 /*!
1789 * @brief Starts accepting slave transfers.
1790 *
1791 * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing
1792 * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
1793 * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked
1794 * from the interrupt context.
1795 *
1796 * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
1797 * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive.
1798 * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need
1799 * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
1800 * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as
1801 * a convenient way to enable all events.
1802 *
1803 * @param base The I3C peripheral base address.
1804 * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1805 * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify
1806 * which events to send to the callback. Other accepted values are 0 to get a default set of
1807 * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events.
1808 *
1809 * @retval #kStatus_Success Slave transfers were successfully started.
1810 * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle.
1811 */
1812 status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask);
1813
1814 /*!
1815 * @brief Gets the slave transfer status during a non-blocking transfer.
1816 * @param base The I3C peripheral base address.
1817 * @param handle Pointer to i2c_slave_handle_t structure.
1818 * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not
1819 * required.
1820 * @retval #kStatus_Success
1821 * @retval #kStatus_NoTransferInProgress
1822 */
1823 status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count);
1824
1825 /*!
1826 * @brief Aborts the slave non-blocking transfers.
1827 * @note This API could be called at any time to stop slave for handling the bus events.
1828 * @param base The I3C peripheral base address.
1829 * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1830 * @retval #kStatus_Success
1831 * @retval #kStatus_I3C_Idle
1832 */
1833 void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle);
1834
1835 /*@}*/
1836
1837 /*! @name Slave IRQ handler */
1838 /*@{*/
1839
1840 /*!
1841 * @brief Reusable routine to handle slave interrupts.
1842 * @note This function does not need to be called unless you are reimplementing the
1843 * non blocking API's interrupt handler routines to add special functionality.
1844 * @param base The I3C peripheral base address.
1845 * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1846 */
1847 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle);
1848
1849 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
1850 /*!
1851 * @brief I3C slave request IBI event with data payload(mandatory and extended).
1852 *
1853 * @param base The I3C peripheral base address.
1854 * @param data Pointer to IBI data to be sent in the request.
1855 * @param dataSize IBI data size.
1856 */
1857 void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize);
1858
1859 /*!
1860 * @brief I3C slave request IBI event with single data.
1861 * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData.
1862 *
1863 * @param base The I3C peripheral base address.
1864 * @param data IBI data to be sent in the request.
1865 * @param dataSize IBI data size.
1866 */
1867 void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize);
1868 #endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */
1869
1870 /*@}*/
1871 /*! @} */
1872 #if defined(__cplusplus)
1873 }
1874 #endif
1875
1876 #endif /* FSL_I3C_H_ */
1877
