1 /*
2 * Copyright 2017 - 2021 , NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.6. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40 #endif
41
42 /*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51 #endif
52
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
56 #endif
57
58 /*! @brief Clock ip name array for ROM. */
59 #define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63 /*! @brief Clock ip name array for SRAM. */
64 #define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
67 }
68 /*! @brief Clock ip name array for FLASH. */
69 #define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73 /*! @brief Clock ip name array for FMC. */
74 #define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78 /*! @brief Clock ip name array for INPUTMUX. */
79 #define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83 /*! @brief Clock ip name array for IOCON. */
84 #define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88 /*! @brief Clock ip name array for GPIO. */
89 #define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \
92 }
93 /*! @brief Clock ip name array for PINT. */
94 #define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98 /*! @brief Clock ip name array for GINT. */
99 #define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103 /*! @brief Clock ip name array for DMA. */
104 #define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108 /*! @brief Clock ip name array for CRC. */
109 #define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113 /*! @brief Clock ip name array for WWDT. */
114 #define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118 /*! @brief Clock ip name array for RTC. */
119 #define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123 /*! @brief Clock ip name array for Mailbox. */
124 #define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128 /*! @brief Clock ip name array for LPADC. */
129 #define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133 /*! @brief Clock ip name array for MRT. */
134 #define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138 /*! @brief Clock ip name array for OSTIMER. */
139 #define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143 /*! @brief Clock ip name array for SCT0. */
144 #define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148 /*! @brief Clock ip name array for UTICK. */
149 #define UTICK_CLOCKS \
150 { \
151 kCLOCK_Utick0 \
152 }
153 /*! @brief Clock ip name array for FLEXCOMM. */
154 #define FLEXCOMM_CLOCKS \
155 { \
156 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
157 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
158 }
159 /*! @brief Clock ip name array for LPUART. */
160 #define LPUART_CLOCKS \
161 { \
162 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
163 kCLOCK_MinUart6, kCLOCK_MinUart7 \
164 }
165
166 /*! @brief Clock ip name array for BI2C. */
167 #define BI2C_CLOCKS \
168 { \
169 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
170 }
171 /*! @brief Clock ip name array for LSPI. */
172 #define LPSPI_CLOCKS \
173 { \
174 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
175 }
176 /*! @brief Clock ip name array for FLEXI2S. */
177 #define FLEXI2S_CLOCKS \
178 { \
179 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
180 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
181 }
182 /*! @brief Clock ip name array for CTIMER. */
183 #define CTIMER_CLOCKS \
184 { \
185 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
186 }
187 /*! @brief Clock ip name array for COMP */
188 #define COMP_CLOCKS \
189 { \
190 kCLOCK_Comp \
191 }
192 /*! @brief Clock ip name array for SDIO. */
193 #define SDIO_CLOCKS \
194 { \
195 kCLOCK_Sdio \
196 }
197 /*! @brief Clock ip name array for USB1CLK. */
198 #define USB1CLK_CLOCKS \
199 { \
200 kCLOCK_Usb1Clk \
201 }
202 /*! @brief Clock ip name array for FREQME. */
203 #define FREQME_CLOCKS \
204 { \
205 kCLOCK_Freqme \
206 }
207 /*! @brief Clock ip name array for USBRAM. */
208 #define USBRAM_CLOCKS \
209 { \
210 kCLOCK_UsbRam1 \
211 }
212 /*! @brief Clock ip name array for RNG. */
213 #define RNG_CLOCKS \
214 { \
215 kCLOCK_Rng \
216 }
217 /*! @brief Clock ip name array for USBHMR0. */
218 #define USBHMR0_CLOCKS \
219 { \
220 kCLOCK_Usbhmr0 \
221 }
222 /*! @brief Clock ip name array for USBHSL0. */
223 #define USBHSL0_CLOCKS \
224 { \
225 kCLOCK_Usbhsl0 \
226 }
227 /*! @brief Clock ip name array for HashCrypt. */
228 #define HASHCRYPT_CLOCKS \
229 { \
230 kCLOCK_HashCrypt \
231 }
232 /*! @brief Clock ip name array for PowerQuad. */
233 #define POWERQUAD_CLOCKS \
234 { \
235 kCLOCK_PowerQuad \
236 }
237 /*! @brief Clock ip name array for PLULUT. */
238 #define PLULUT_CLOCKS \
239 { \
240 kCLOCK_PluLut \
241 }
242 /*! @brief Clock ip name array for PUF. */
243 #define PUF_CLOCKS \
244 { \
245 kCLOCK_Puf \
246 }
247 /*! @brief Clock ip name array for CASPER. */
248 #define CASPER_CLOCKS \
249 { \
250 kCLOCK_Casper \
251 }
252 /*! @brief Clock ip name array for ANALOGCTRL. */
253 #define ANALOGCTRL_CLOCKS \
254 { \
255 kCLOCK_AnalogCtrl \
256 }
257 /*! @brief Clock ip name array for HS_LSPI. */
258 #define HS_LSPI_CLOCKS \
259 { \
260 kCLOCK_Hs_Lspi \
261 }
262 /*! @brief Clock ip name array for GPIO_SEC. */
263 #define GPIO_SEC_CLOCKS \
264 { \
265 kCLOCK_Gpio_Sec \
266 }
267 /*! @brief Clock ip name array for GPIO_SEC_INT. */
268 #define GPIO_SEC_INT_CLOCKS \
269 { \
270 kCLOCK_Gpio_Sec_Int \
271 }
272 /*! @brief Clock ip name array for USBD. */
273 #define USBD_CLOCKS \
274 { \
275 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
276 }
277 /*! @brief Clock ip name array for USBH. */
278 #define USBH_CLOCKS \
279 { \
280 kCLOCK_Usbh1 \
281 }
282 #define PLU_CLOCKS \
283 { \
284 kCLOCK_PluLut \
285 }
286 #define SYSCTL_CLOCKS \
287 { \
288 kCLOCK_Sysctl \
289 }
290 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
291 /*------------------------------------------------------------------------------
292 clock_ip_name_t definition:
293 ------------------------------------------------------------------------------*/
294
295 #define CLK_GATE_REG_OFFSET_SHIFT 8U
296 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
297 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
298 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
299
300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
301 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
302 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
303
304 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
305 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
306
307 #define AHB_CLK_CTRL0 0
308 #define AHB_CLK_CTRL1 1
309 #define AHB_CLK_CTRL2 2
310
311 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
312 typedef enum _clock_ip_name
313 {
314 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
316
317 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
318
319 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
320
321 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */
322
323 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */
324
325 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
326
327 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
328
329 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
330
331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
332
333 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
334
335 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
336
337 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */
338
339 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */
340
341 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
342
343 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
344
345 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */
346
347 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
348
349 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
350
351 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
352
353 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */
354
355 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
356
357 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
358
359 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */
360
361 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
362
363 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */
364
365 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
366
367 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
368
369 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
370
371 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
372
373 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
374
375 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
376
377 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
378
379 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
380
381 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
382
383 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
384
385 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
386
387 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
388
389 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
390
391 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
392
393 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
394
395 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
396
397 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
398
399 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
400
401 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
402
403 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
404
405 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
406
407 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
408
409 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
410
411 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
412
413 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
414
415 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
416
417 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
418
419 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
420
421 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
422
423 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
424
425 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
426
427 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
428
429 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
430
431 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
432
433 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
434
435 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
436
437 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
438
439 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
440
441 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
442
443 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
444
445 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */
446
447 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */
448
449 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */
450
451 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */
452
453 kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */
454
455 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */
456
457 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */
458
459 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */
460
461 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */
462
463 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */
464
465 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */
466
467 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */
468
469 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */
470
471 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */
472
473 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */
474
475 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
476
477 kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */
478
479 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */
480
481 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */
482
483 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */
484
485 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */
486
487 kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */
488
489 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */
490
491 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */
492
493 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */
494
495 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */
496
497 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */
498
499 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */
500
501 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */
502
503 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */
504
505 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */
506 } clock_ip_name_t;
507
508 /*! @brief Peripherals clock source definition. */
509 #define BUS_CLK kCLOCK_BusClk
510
511 #define I2C0_CLK_SRC BUS_CLK
512
513 /*! @brief Clock name used to get clock frequency. */
514 typedef enum _clock_name
515 {
516 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
517 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
518 kCLOCK_ClockOut, /*!< CLOCKOUT */
519 kCLOCK_FroHf, /*!< FRO48/96 */
520 kCLOCK_Pll1Out, /*!< PLL1 Output */
521 kCLOCK_Mclk, /*!< MCLK */
522 kCLOCK_Fro12M, /*!< FRO12M */
523 kCLOCK_ExtClk, /*!< External Clock */
524 kCLOCK_Pll0Out, /*!< PLL0 Output */
525 kCLOCK_FlexI2S, /*!< FlexI2S clock */
526
527 } clock_name_t;
528
529 /*! @brief Clock Mux Switches
530 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
531 * starting from LSB upwards
532 *
533 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
534 *
535 */
536
537 #define CLK_ATTACH_ID(mux, sel, pos) \
538 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
539 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
540 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
541
542 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
543 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
544 #define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
545 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
546 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
547
548 #define CM_SYSTICKCLKSEL0 0U
549 #define CM_SYSTICKCLKSEL1 1U
550 #define CM_TRACECLKSEL 2U
551 #define CM_CTIMERCLKSEL0 3U
552 #define CM_CTIMERCLKSEL1 4U
553 #define CM_CTIMERCLKSEL2 5U
554 #define CM_CTIMERCLKSEL3 6U
555 #define CM_CTIMERCLKSEL4 7U
556 #define CM_MAINCLKSELA 8U
557 #define CM_MAINCLKSELB 9U
558 #define CM_CLKOUTCLKSEL 10U
559 #define CM_PLL0CLKSEL 12U
560 #define CM_PLL1CLKSEL 13U
561 #define CM_ADCASYNCCLKSEL 17U
562 #define CM_USB0CLKSEL 18U
563 #define CM_FXCOMCLKSEL0 20U
564 #define CM_FXCOMCLKSEL1 21U
565 #define CM_FXCOMCLKSEL2 22U
566 #define CM_FXCOMCLKSEL3 23U
567 #define CM_FXCOMCLKSEL4 24U
568 #define CM_FXCOMCLKSEL5 25U
569 #define CM_FXCOMCLKSEL6 26U
570 #define CM_FXCOMCLKSEL7 27U
571 #define CM_HSLSPICLKSEL 28U
572 #define CM_MCLKCLKSEL 32U
573 #define CM_SCTCLKSEL 36U
574 #define CM_SDIOCLKSEL 38U
575
576 #define CM_RTCOSC32KCLKSEL 63U
577
578 /*!
579 * @brief The enumerator of clock attach Id.
580 */
581 typedef enum _clock_attach_id
582 {
583
584 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
585
586 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
587
588 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */
589
590 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
591
592 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */
593
594 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */
595
596 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
597
598 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
599
600 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
601
602 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */
603
604 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
605
606 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */
607
608 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */
609
610 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */
611
612 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */
613
614 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */
615
616 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */
617
618 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */
619
620 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */
621
622 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */
623
624 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */
625
626 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */
627
628 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */
629
630 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
631
632 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */
633
634 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */
635
636 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */
637
638 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */
639
640 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */
641
642 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */
643
644 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */
645
646 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
647
648 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
649
650 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */
651
652 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */
653
654 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */
655
656 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
657
658 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */
659
660 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */
661
662 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
663
664 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
665
666 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */
667
668 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */
669
670 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */
671
672 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
673
674 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */
675
676 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */
677
678 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
679
680 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
681
682 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */
683
684 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */
685
686 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */
687
688 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
689
690 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */
691
692 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */
693
694 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
695
696 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
697
698 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */
699
700 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */
701
702 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */
703
704 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
705
706 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */
707
708 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */
709
710 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
711
712 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
713
714 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */
715
716 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */
717
718 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */
719
720 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
721
722 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */
723
724 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */
725
726 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
727
728 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
729
730 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */
731
732 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */
733
734 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */
735
736 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
737
738 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */
739
740 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */
741
742 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
743
744 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
745
746 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */
747
748 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */
749
750 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */
751
752 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
753
754 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */
755
756 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */
757
758 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */
759
760 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */
761
762 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */
763
764 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */
765
766 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */
767
768 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
769
770 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */
771
772 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */
773
774 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */
775
776 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */
777
778 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */
779
780 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */
781
782 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */
783
784 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
785
786 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */
787
788 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
789
790 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
791
792 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */
793
794 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */
795
796 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */
797
798 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */
799
800 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
801
802 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */
803
804 kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */
805
806 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */
807
808 kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */
809
810 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */
811
812 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */
813
814 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */
815
816 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
817
818 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */
819
820 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */
821
822 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
823
824 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */
825
826 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */
827
828 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */
829
830 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
831
832 kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */
833
834 kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */
835
836 kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */
837
838 kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */
839
840 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */
841
842 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */
843
844 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */
845
846 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */
847
848 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */
849
850 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */
851
852 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
853
854 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
855
856 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */
857
858 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */
859
860 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */
861
862 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */
863
864 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */
865
866 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
867
868 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
869
870 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */
871
872 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */
873
874 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */
875
876 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */
877
878 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */
879
880 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
881
882 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
883
884 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */
885
886 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */
887
888 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */
889
890 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */
891
892 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */
893
894 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
895
896 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
897
898 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */
899
900 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */
901
902 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */
903
904 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */
905
906 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */
907
908 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
909
910 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
911
912 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */
913
914 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */
915
916 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */
917
918 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */
919
920 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
921
922 } clock_attach_id_t;
923
924 /*! @brief Clock dividers */
925 typedef enum _clock_div_name
926 {
927 kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */
928
929 kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */
930
931 kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */
932
933 kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */
934
935 kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */
936
937 kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */
938
939 kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */
940
941 kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */
942
943 kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */
944
945 kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */
946
947 kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */
948
949 kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
950
951 kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
952
953 kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
954
955 kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */
956
957 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
958
959 kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */
960
961 kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
962
963 kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
964
965 kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */
966
967 kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */
968 } clock_div_name_t;
969
970 /*******************************************************************************
971 * API
972 ******************************************************************************/
973
974 #if defined(__cplusplus)
975 extern "C" {
976 #endif /* __cplusplus */
977
978 /**
979 * @brief Enable the clock for specific IP.
980 * @param clk : Clock to be enabled.
981 * @return Nothing
982 */
CLOCK_EnableClock(clock_ip_name_t clk)983 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
984 {
985 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
986 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
987 }
988 /**
989 * @brief Disable the clock for specific IP.
990 * @param clk : Clock to be Disabled.
991 * @return Nothing
992 */
CLOCK_DisableClock(clock_ip_name_t clk)993 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
994 {
995 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
996 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
997 }
998 /**
999 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
1000 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
1001 * enabled.
1002 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
1003 * @return returns success or fail status.
1004 */
1005 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
1006 /**
1007 * @brief Set the flash wait states for the input freuqency.
1008 * @param iFreq : Input frequency
1009 * @return Nothing
1010 */
1011 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
1012 /**
1013 * @brief Initialize the external osc clock to given frequency.
1014 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1015 * @return returns success or fail status.
1016 */
1017 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
1018 /**
1019 * @brief Initialize the I2S MCLK clock to given frequency.
1020 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1021 * @return returns success or fail status.
1022 */
1023 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
1024 /**
1025 * @brief Initialize the PLU CLKIN clock to given frequency.
1026 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1027 * @return returns success or fail status.
1028 */
1029 status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
1030 /**
1031 * @brief Configure the clock selection muxes.
1032 * @param connection : Clock to be configured.
1033 * @return Nothing
1034 */
1035 void CLOCK_AttachClk(clock_attach_id_t connection);
1036 /**
1037 * @brief Get the actual clock attach id.
1038 * This fuction uses the offset in input attach id, then it reads the actual source value in
1039 * the register and combine the offset to obtain an actual attach id.
1040 * @param attachId : Clock attach id to get.
1041 * @return Clock source value.
1042 */
1043 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
1044 /**
1045 * @brief Setup peripheral clock dividers.
1046 * @param div_name : Clock divider name
1047 * @param divided_by_value: Value to be divided
1048 * @param reset : Whether to reset the divider counter.
1049 * @return Nothing
1050 */
1051 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
1052 /**
1053 * @brief Setup rtc 1khz clock divider.
1054 * @param divided_by_value: Value to be divided
1055 * @return Nothing
1056 */
1057 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
1058 /**
1059 * @brief Setup rtc 1hz clock divider.
1060 * @param divided_by_value: Value to be divided
1061 * @return Nothing
1062 */
1063 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
1064
1065 /**
1066 * @brief Set the flexcomm output frequency.
1067 * @param id : flexcomm instance id
1068 * @param freq : output frequency
1069 * @return 0 : the frequency range is out of range.
1070 * 1 : switch successfully.
1071 */
1072 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
1073
1074 /*! @brief Return Frequency of flexcomm input clock
1075 * @param id : flexcomm instance id
1076 * @return Frequency value
1077 */
1078 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
1079
1080 /*! @brief Return Frequency of selected clock
1081 * @return Frequency of selected clock
1082 */
1083 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1084 /*! @brief Return Frequency of FRO 12MHz
1085 * @return Frequency of FRO 12MHz
1086 */
1087 uint32_t CLOCK_GetFro12MFreq(void);
1088 /*! @brief Return Frequency of FRO 1MHz
1089 * @return Frequency of FRO 1MHz
1090 */
1091 uint32_t CLOCK_GetFro1MFreq(void);
1092 /*! @brief Return Frequency of ClockOut
1093 * @return Frequency of ClockOut
1094 */
1095 uint32_t CLOCK_GetClockOutClkFreq(void);
1096 /*! @brief Return Frequency of Adc Clock
1097 * @return Frequency of Adc.
1098 */
1099 uint32_t CLOCK_GetAdcClkFreq(void);
1100 /*! @brief Return Frequency of Usb0 Clock
1101 * @return Frequency of Usb0 Clock.
1102 */
1103 uint32_t CLOCK_GetUsb0ClkFreq(void);
1104 /*! @brief Return Frequency of Usb1 Clock
1105 * @return Frequency of Usb1 Clock.
1106 */
1107 uint32_t CLOCK_GetUsb1ClkFreq(void);
1108 /*! @brief Return Frequency of MClk Clock
1109 * @return Frequency of MClk Clock.
1110 */
1111 uint32_t CLOCK_GetMclkClkFreq(void);
1112 /*! @brief Return Frequency of SCTimer Clock
1113 * @return Frequency of SCTimer Clock.
1114 */
1115 uint32_t CLOCK_GetSctClkFreq(void);
1116 /*! @brief Return Frequency of SDIO Clock
1117 * @return Frequency of SDIO Clock.
1118 */
1119 uint32_t CLOCK_GetSdioClkFreq(void);
1120 /*! @brief Return Frequency of External Clock
1121 * @return Frequency of External Clock. If no external clock is used returns 0.
1122 */
1123 uint32_t CLOCK_GetExtClkFreq(void);
1124 /*! @brief Return Frequency of Watchdog
1125 * @return Frequency of Watchdog
1126 */
1127 uint32_t CLOCK_GetWdtClkFreq(void);
1128 /*! @brief Return Frequency of High-Freq output of FRO
1129 * @return Frequency of High-Freq output of FRO
1130 */
1131 uint32_t CLOCK_GetFroHfFreq(void);
1132 /*! @brief Return Frequency of PLL
1133 * @return Frequency of PLL
1134 */
1135 uint32_t CLOCK_GetPll0OutFreq(void);
1136 /*! @brief Return Frequency of USB PLL
1137 * @return Frequency of PLL
1138 */
1139 uint32_t CLOCK_GetPll1OutFreq(void);
1140 /*! @brief Return Frequency of 32kHz osc
1141 * @return Frequency of 32kHz osc
1142 */
1143 uint32_t CLOCK_GetOsc32KFreq(void);
1144 /*! @brief Return Frequency of Core System
1145 * @return Frequency of Core System
1146 */
1147 uint32_t CLOCK_GetCoreSysClkFreq(void);
1148 /*! @brief Return Frequency of I2S MCLK Clock
1149 * @return Frequency of I2S MCLK Clock
1150 */
1151 uint32_t CLOCK_GetI2SMClkFreq(void);
1152 /*! @brief Return Frequency of PLU CLKIN Clock
1153 * @return Frequency of PLU CLKIN Clock
1154 */
1155 uint32_t CLOCK_GetPLUClkInFreq(void);
1156 /*! @brief Return Frequency of FlexComm Clock
1157 * @return Frequency of FlexComm Clock
1158 */
1159 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1160 /*! @brief Return Frequency of High speed SPI Clock
1161 * @return Frequency of High speed SPI Clock
1162 */
1163 uint32_t CLOCK_GetHsLspiClkFreq(void);
1164 /*! @brief Return Frequency of CTimer functional Clock
1165 * @return Frequency of CTimer functional Clock
1166 */
1167 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
1168 /*! @brief Return Frequency of SystickClock
1169 * @return Frequency of Systick Clock
1170 */
1171 uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
1172
1173 /*! @brief Return PLL0 input clock rate
1174 * @return PLL0 input clock rate
1175 */
1176 uint32_t CLOCK_GetPLL0InClockRate(void);
1177
1178 /*! @brief Return PLL1 input clock rate
1179 * @return PLL1 input clock rate
1180 */
1181 uint32_t CLOCK_GetPLL1InClockRate(void);
1182
1183 /*! @brief Return PLL0 output clock rate
1184 * @param recompute : Forces a PLL rate recomputation if true
1185 * @return PLL0 output clock rate
1186 * @note The PLL rate is cached in the driver in a variable as
1187 * the rate computation function can take some time to perform. It
1188 * is recommended to use 'false' with the 'recompute' parameter.
1189 */
1190 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
1191
1192 /*! @brief Enables and disables PLL0 bypass mode
1193 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
1194 * @return PLL0 output clock rate
1195 */
CLOCK_SetBypassPLL0(bool bypass)1196 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
1197 {
1198 if (bypass)
1199 {
1200 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1201 }
1202 else
1203 {
1204 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1205 }
1206 }
1207
1208 /*! @brief Enables and disables PLL1 bypass mode
1209 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
1210 * @return PLL1 output clock rate
1211 */
CLOCK_SetBypassPLL1(bool bypass)1212 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
1213 {
1214 if (bypass)
1215 {
1216 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1217 }
1218 else
1219 {
1220 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1221 }
1222 }
1223
1224 /*! @brief Check if PLL is locked or not
1225 * @return true if the PLL is locked, false if not locked
1226 */
CLOCK_IsPLL0Locked(void)1227 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
1228 {
1229 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
1230 }
1231
1232 /*! @brief Check if PLL1 is locked or not
1233 * @return true if the PLL1 is locked, false if not locked
1234 */
CLOCK_IsPLL1Locked(void)1235 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
1236 {
1237 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
1238 }
1239
1240 /*! @brief Store the current PLL0 rate
1241 * @param rate: Current rate of the PLL0
1242 * @return Nothing
1243 **/
1244 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1245
1246 /*! @brief PLL configuration structure flags for 'flags' field
1247 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1248 *
1249 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1250 * configuration structure must be assigned with the expected PLL frequency. If the
1251 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1252 * function and the driver will determine the PLL rate from the currently selected
1253 * PLL source. This flag might be used to configure the PLL input clock more accurately
1254 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1255 *
1256 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1257 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1258 * are not used.<br>
1259 */
1260 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1261 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1262 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1263
1264 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1265 * See (MF) field in the PLL0SSCG1 register in the UM.
1266 */
1267 typedef enum _ss_progmodfm
1268 {
1269 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1270 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1271 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1272 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1273 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1274 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1275 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1276 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1277 } ss_progmodfm_t;
1278
1279 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1280 * See (MR) field in the PLL0SSCG1 register in the UM.
1281 */
1282 typedef enum _ss_progmoddp
1283 {
1284 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
1285 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
1286 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
1287 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
1288 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
1289 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
1290 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
1291 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
1292 } ss_progmoddp_t;
1293
1294 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1295 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1296 * Compensation for low pass filtering of the PLL to get a triangular
1297 * modulation at the output of the PLL, giving a flat frequency spectrum.
1298 */
1299 typedef enum _ss_modwvctrl
1300 {
1301 kSS_MC_NOC = (0 << 26), /*!< no compensation */
1302 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
1303 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
1304 } ss_modwvctrl_t;
1305
1306 /*! @brief PLL configuration structure
1307 *
1308 * This structure can be used to configure the settings for a PLL
1309 * setup structure. Fill in the desired configuration for the PLL
1310 * and call the PLL setup function to fill in a PLL setup structure.
1311 */
1312 typedef struct _pll_config
1313 {
1314 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1315 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1316 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1317 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1318 PLL_CONFIGFLAG_FORCENOFRACT flag */
1319 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1320 PLL_CONFIGFLAG_FORCENOFRACT flag */
1321 ss_modwvctrl_t
1322 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1323 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1324 PLL_CONFIGFLAG_FORCENOFRACT flag */
1325
1326 } pll_config_t;
1327
1328 /*! @brief PLL setup structure flags for 'flags' field
1329 * These flags control how the PLL setup function sets up the PLL
1330 */
1331 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1332 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1333 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1334 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1335
1336 /*! @brief PLL0 setup structure
1337 * This structure can be used to pre-build a PLL setup configuration
1338 * at run-time and quickly set the PLL to the configuration. It can be
1339 * populated with the PLL setup function. If powering up or waiting
1340 * for PLL lock, the PLL input clock source should be configured prior
1341 * to PLL setup.
1342 */
1343 typedef struct _pll_setup
1344 {
1345 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1346 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1347 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1348 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1349 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1350 uint32_t pllRate; /*!< Acutal PLL rate */
1351 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1352 } pll_setup_t;
1353
1354 /*! @brief PLL status definitions
1355 */
1356 typedef enum _pll_error
1357 {
1358 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1359 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1360 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1361 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1362 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1363 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1364 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1365 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1366 } pll_error_t;
1367
1368 /*! @brief USB FS clock source definition. */
1369 typedef enum _clock_usbfs_src
1370 {
1371 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
1372 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
1373 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1374 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
1375
1376 kCLOCK_UsbfsSrcNone =
1377 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
1378 } clock_usbfs_src_t;
1379
1380 /*! @brief USBhs clock source definition. */
1381 typedef enum _clock_usbhs_src
1382 {
1383 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
1384 care the clock source. */
1385 } clock_usbhs_src_t;
1386
1387 /*! @brief Source of the USB HS PHY. */
1388 typedef enum _clock_usb_phy_src
1389 {
1390 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
1391 } clock_usb_phy_src_t;
1392
1393 /*! @brief Return PLL0 output clock rate from setup structure
1394 * @param pSetup : Pointer to a PLL setup structure
1395 * @return System PLL output clock rate the setup structure will generate
1396 */
1397 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1398
1399 /*! @brief Set PLL0 output based on the passed PLL setup data
1400 * @param pControl : Pointer to populated PLL control structure to generate setup with
1401 * @param pSetup : Pointer to PLL setup structure to be filled
1402 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1403 * @note Actual frequency for setup may vary from the desired frequency based on the
1404 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1405 */
1406 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1407
1408 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1409 * @param pSetup : Pointer to populated PLL setup structure
1410 * @param flagcfg : Flag configuration for PLL config structure
1411 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1412 * @note This function will power off the PLL, setup the PLL with the
1413 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1414 * and adjust system voltages to the new PLL rate. The function will not
1415 * alter any source clocks (ie, main systen clock) that may use the PLL,
1416 * so these should be setup prior to and after exiting the function.
1417 */
1418 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1419
1420 /**
1421 * @brief Set PLL output from PLL setup structure (precise frequency)
1422 * @param pSetup : Pointer to populated PLL setup structure
1423 * @return kStatus_PLL_Success on success, or PLL setup error code
1424 * @note This function will power off the PLL, setup the PLL with the
1425 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1426 * and adjust system voltages to the new PLL rate. The function will not
1427 * alter any source clocks (ie, main systen clock) that may use the PLL,
1428 * so these should be setup prior to and after exiting the function.
1429 */
1430 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1431
1432 /**
1433 * @brief Set PLL output from PLL setup structure (precise frequency)
1434 * @param pSetup : Pointer to populated PLL setup structure
1435 * @return kStatus_PLL_Success on success, or PLL setup error code
1436 * @note This function will power off the PLL, setup the PLL with the
1437 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1438 * and adjust system voltages to the new PLL rate. The function will not
1439 * alter any source clocks (ie, main systen clock) that may use the PLL,
1440 * so these should be setup prior to and after exiting the function.
1441 */
1442 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1443
1444 /*! @brief Set PLL0 output based on the multiplier and input frequency
1445 * @param multiply_by : multiplier
1446 * @param input_freq : Clock input frequency of the PLL
1447 * @return Nothing
1448 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1449 * function does not disable or enable PLL power, wait for PLL lock,
1450 * or adjust system voltages. These must be done in the application.
1451 * The function will not alter any source clocks (ie, main systen clock)
1452 * that may use the PLL, so these should be setup prior to and after
1453 * exiting the function.
1454 */
1455 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1456
1457 /*! @brief Disable USB clock.
1458 *
1459 * Disable USB clock.
1460 */
CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)1461 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1462 {
1463 CLOCK_DisableClock(clk);
1464 }
1465
1466 /*! @brief Enable USB Device FS clock.
1467 * @param src : clock source
1468 * @param freq: clock frequency
1469 * Enable USB Device Full Speed clock.
1470 */
1471 bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
1472
1473 /*! @brief Enable USB HOST FS clock.
1474 * @param src : clock source
1475 * @param freq: clock frequency
1476 * Enable USB HOST Full Speed clock.
1477 */
1478 bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
1479
1480 /*! @brief Enable USB phy clock.
1481 * Enable USB phy clock.
1482 */
1483 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1484
1485 /*! @brief Enable USB Device HS clock.
1486 * Enable USB Device High Speed clock.
1487 */
1488 bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
1489
1490 /*! @brief Enable USB HOST HS clock.
1491 * Enable USB HOST High Speed clock.
1492 */
1493 bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);
1494
1495 #if defined(__cplusplus)
1496 }
1497 #endif /* __cplusplus */
1498
1499 /*! @} */
1500
1501 #endif /* _FSL_CLOCK_H_ */
1502
