1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020, 2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_FLEXIO_SPI_H_
10 #define FSL_FLEXIO_SPI_H_
11
12 #include "fsl_common.h"
13 #include "fsl_flexio.h"
14
15 /*!
16 * @addtogroup flexio_spi
17 * @{
18 */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*! @{ */
26 /*! @brief FlexIO SPI driver version. */
27 #define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
28 /*! @} */
29
30 #ifndef FLEXIO_SPI_DUMMYDATA
31 /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
32 #define FLEXIO_SPI_DUMMYDATA (0x00U)
33 #endif
34
35 /*! @brief Retry times for waiting flag. */
36 #ifndef SPI_RETRY_TIMES
37 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
38 #endif
39
40 /*! @brief Get the transfer data format of width and bit order. */
41 #define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
42
43 /*! @brief Error codes for the FlexIO SPI driver. */
44 enum
45 {
46 kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
47 kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
48 kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
49 kStatus_FLEXIO_SPI_Timeout =
50 MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 4), /*!< FlexIO SPI timeout polling status flags. */
51 };
52
53 /*! @brief FlexIO SPI clock phase configuration. */
54 typedef enum _flexio_spi_clock_phase
55 {
56 kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
57 * cycle of a data transfer. */
58 kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
59 * first cycle of a data transfer. */
60 } flexio_spi_clock_phase_t;
61
62 /*! @brief FlexIO SPI data shifter direction options. */
63 typedef enum _flexio_spi_shift_direction
64 {
65 kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */
66 kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */
67 } flexio_spi_shift_direction_t;
68
69 /*! @brief FlexIO SPI data length mode options. */
70 typedef enum _flexio_spi_data_bitcount_mode
71 {
72 kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
73 kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
74 kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
75 } flexio_spi_data_bitcount_mode_t;
76
77 /*! @brief Define FlexIO SPI interrupt mask. */
78 enum _flexio_spi_interrupt_enable
79 {
80 kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
81 kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
82 };
83
84 /*! @brief Define FlexIO SPI status mask. */
85 enum _flexio_spi_status_flags
86 {
87 kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
88 kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */
89 };
90
91 /*! @brief Define FlexIO SPI DMA mask. */
92 enum _flexio_spi_dma_enable
93 {
94 kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
95 kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
96 kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
97 };
98
99 /*! @brief Define FlexIO SPI transfer flags.
100 * @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
101 enum _flexio_spi_transfer_flags
102 {
103 kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
104 kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
105 kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
106 kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
107 kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
108 kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
109 kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
110 };
111
112 /*! @brief Define FlexIO SPI access structure typedef. */
113 typedef struct _flexio_spi_type
114 {
115 FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
116 uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
117 GPIO input and disable all pull up/down in application. */
118 uint8_t SDIPinIndex; /*!< Pin select for data input. */
119 uint8_t SCKPinIndex; /*!< Pin select for clock. */
120 uint8_t CSnPinIndex; /*!< Pin select for enable. */
121 uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */
122 uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */
123 } FLEXIO_SPI_Type;
124
125 /*! @brief Define FlexIO SPI master configuration structure. */
126 typedef struct _flexio_spi_master_config
127 {
128 bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */
129 bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */
130 bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */
131 bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
132 fast access requires the FlexIO clock to be at least
133 twice the frequency of the bus clock. */
134 uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
135 flexio_spi_clock_phase_t phase; /*!< Clock phase. */
136 flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
137 } flexio_spi_master_config_t;
138
139 /*! @brief Define FlexIO SPI slave configuration structure. */
140 typedef struct _flexio_spi_slave_config
141 {
142 bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */
143 bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */
144 bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */
145 bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
146 fast access requires the FlexIO clock to be at least
147 twice the frequency of the bus clock. */
148 flexio_spi_clock_phase_t phase; /*!< Clock phase. */
149 flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
150 } flexio_spi_slave_config_t;
151
152 /*! @brief Define FlexIO SPI transfer structure. */
153 typedef struct _flexio_spi_transfer
154 {
155 const uint8_t *txData; /*!< Send buffer. */
156 uint8_t *rxData; /*!< Receive buffer. */
157 size_t dataSize; /*!< Transfer bytes. */
158 uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */
159 } flexio_spi_transfer_t;
160
161 /*! @brief typedef for flexio_spi_master_handle_t in advance. */
162 typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t;
163
164 /*! @brief Slave handle is the same with master handle. */
165 typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t;
166
167 /*! @brief FlexIO SPI master callback for finished transmit */
168 typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base,
169 flexio_spi_master_handle_t *handle,
170 status_t status,
171 void *userData);
172
173 /*! @brief FlexIO SPI slave callback for finished transmit */
174 typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
175 flexio_spi_slave_handle_t *handle,
176 status_t status,
177 void *userData);
178
179 /*! @brief Define FlexIO SPI handle structure. */
180 struct _flexio_spi_master_handle
181 {
182 const uint8_t *txData; /*!< Transfer buffer. */
183 uint8_t *rxData; /*!< Receive buffer. */
184 size_t transferSize; /*!< Total bytes to be transferred. */
185 volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */
186 volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */
187 volatile uint32_t state; /*!< FlexIO SPI internal state. */
188 uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */
189 flexio_spi_shift_direction_t direction; /*!< Shift direction. */
190 flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */
191 void *userData; /*!< Callback parameter. */
192 };
193
194 /*******************************************************************************
195 * API
196 ******************************************************************************/
197
198 #if defined(__cplusplus)
199 extern "C" {
200 #endif /*_cplusplus*/
201
202 /*!
203 * @name FlexIO SPI Configuration
204 * @{
205 */
206
207 /*!
208 * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
209 * and configures the FlexIO SPI with FlexIO SPI master configuration. The
210 * configuration structure can be filled by the user, or be set with default values
211 * by the FLEXIO_SPI_MasterGetDefaultConfig().
212 *
213 * @note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low.
214 * 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
215 * is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud
216 * rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO
217 * SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
218 *
219 * Example
220 @code
221 FLEXIO_SPI_Type spiDev = {
222 .flexioBase = FLEXIO,
223 .SDOPinIndex = 0,
224 .SDIPinIndex = 1,
225 .SCKPinIndex = 2,
226 .CSnPinIndex = 3,
227 .shifterIndex = {0,1},
228 .timerIndex = {0,1}
229 };
230 flexio_spi_master_config_t config = {
231 .enableMaster = true,
232 .enableInDoze = false,
233 .enableInDebug = true,
234 .enableFastAccess = false,
235 .baudRate_Bps = 500000,
236 .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
237 .direction = kFLEXIO_SPI_MsbFirst,
238 .dataMode = kFLEXIO_SPI_8BitMode
239 };
240 FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
241 @endcode
242 *
243 * @param base Pointer to the FLEXIO_SPI_Type structure.
244 * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
245 * @param srcClock_Hz FlexIO source clock in Hz.
246 */
247 void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz);
248
249 /*!
250 * @brief Resets the FlexIO SPI timer and shifter config.
251 *
252 * @param base Pointer to the FLEXIO_SPI_Type.
253 */
254 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
255
256 /*!
257 * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration
258 * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
259 * Example:
260 @code
261 flexio_spi_master_config_t masterConfig;
262 FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
263 @endcode
264 * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
265 */
266 void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig);
267
268 /*!
269 * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
270 * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
271 * configuration structure can be filled by the user, or be set with default values
272 * by the FLEXIO_SPI_SlaveGetDefaultConfig().
273 *
274 * @note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
275 * 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
276 * 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
277 * is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud
278 * rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO
279 * SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
280 * Example
281 @code
282 FLEXIO_SPI_Type spiDev = {
283 .flexioBase = FLEXIO,
284 .SDOPinIndex = 0,
285 .SDIPinIndex = 1,
286 .SCKPinIndex = 2,
287 .CSnPinIndex = 3,
288 .shifterIndex = {0,1},
289 .timerIndex = {0}
290 };
291 flexio_spi_slave_config_t config = {
292 .enableSlave = true,
293 .enableInDoze = false,
294 .enableInDebug = true,
295 .enableFastAccess = false,
296 .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
297 .direction = kFLEXIO_SPI_MsbFirst,
298 .dataMode = kFLEXIO_SPI_8BitMode
299 };
300 FLEXIO_SPI_SlaveInit(&spiDev, &config);
301 @endcode
302 * @param base Pointer to the FLEXIO_SPI_Type structure.
303 * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
304 */
305 void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig);
306
307 /*!
308 * @brief Gates the FlexIO clock.
309 *
310 * @param base Pointer to the FLEXIO_SPI_Type.
311 */
312 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
313
314 /*!
315 * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
316 * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
317 * Example:
318 @code
319 flexio_spi_slave_config_t slaveConfig;
320 FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
321 @endcode
322 * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
323 */
324 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
325
326 /*! @} */
327
328 /*!
329 * @name Status
330 * @{
331 */
332
333 /*!
334 * @brief Gets FlexIO SPI status flags.
335 *
336 * @param base Pointer to the FLEXIO_SPI_Type structure.
337 * @return status flag; Use the status flag to AND the following flag mask and get the status.
338 * @arg kFLEXIO_SPI_TxEmptyFlag
339 * @arg kFLEXIO_SPI_RxEmptyFlag
340 */
341
342 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
343
344 /*!
345 * @brief Clears FlexIO SPI status flags.
346 *
347 * @param base Pointer to the FLEXIO_SPI_Type structure.
348 * @param mask status flag
349 * The parameter can be any combination of the following values:
350 * @arg kFLEXIO_SPI_TxEmptyFlag
351 * @arg kFLEXIO_SPI_RxEmptyFlag
352 */
353
354 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
355
356 /*! @} */
357
358 /*!
359 * @name Interrupts
360 * @{
361 */
362
363 /*!
364 * @brief Enables the FlexIO SPI interrupt.
365 *
366 * This function enables the FlexIO SPI interrupt.
367 *
368 * @param base Pointer to the FLEXIO_SPI_Type structure.
369 * @param mask interrupt source. The parameter can be any combination of the following values:
370 * @arg kFLEXIO_SPI_RxFullInterruptEnable
371 * @arg kFLEXIO_SPI_TxEmptyInterruptEnable
372 */
373 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
374
375 /*!
376 * @brief Disables the FlexIO SPI interrupt.
377 *
378 * This function disables the FlexIO SPI interrupt.
379 *
380 * @param base Pointer to the FLEXIO_SPI_Type structure.
381 * @param mask interrupt source The parameter can be any combination of the following values:
382 * @arg kFLEXIO_SPI_RxFullInterruptEnable
383 * @arg kFLEXIO_SPI_TxEmptyInterruptEnable
384 */
385 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
386
387 /*! @} */
388
389 /*!
390 * @name DMA Control
391 * @{
392 */
393
394 /*!
395 * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
396 * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
397 *
398 * @param base Pointer to the FLEXIO_SPI_Type structure.
399 * @param mask SPI DMA source.
400 * @param enable True means enable DMA, false means disable DMA.
401 */
402 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable);
403
404 /*!
405 * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer.
406 *
407 * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
408 *
409 * @param base Pointer to the FLEXIO_SPI_Type structure.
410 * @param direction Shift direction of MSB first or LSB first.
411 * @return FlexIO SPI transmit data register address.
412 */
FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type * base,flexio_spi_shift_direction_t direction)413 static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base,
414 flexio_spi_shift_direction_t direction)
415 {
416 if (direction == kFLEXIO_SPI_MsbFirst)
417 {
418 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped,
419 base->shifterIndex[0]) +
420 3U;
421 }
422 else
423 {
424 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
425 }
426 }
427
428 /*!
429 * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer.
430 *
431 * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
432 *
433 * @param base Pointer to the FLEXIO_SPI_Type structure.
434 * @param direction Shift direction of MSB first or LSB first.
435 * @return FlexIO SPI receive data register address.
436 */
FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type * base,flexio_spi_shift_direction_t direction)437 static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base,
438 flexio_spi_shift_direction_t direction)
439 {
440 if (direction == kFLEXIO_SPI_MsbFirst)
441 {
442 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]);
443 }
444 else
445 {
446 return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U;
447 }
448 }
449
450 /*! @} */
451
452 /*!
453 * @name Bus Operations
454 * @{
455 */
456
457 /*!
458 * @brief Enables/disables the FlexIO SPI module operation.
459 *
460 * @param base Pointer to the FLEXIO_SPI_Type.
461 * @param enable True to enable, false does not have any effect.
462 */
FLEXIO_SPI_Enable(FLEXIO_SPI_Type * base,bool enable)463 static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
464 {
465 if (enable)
466 {
467 base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
468 }
469 }
470
471 /*!
472 * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
473 *
474 * @param base Pointer to the FLEXIO_SPI_Type structure.
475 * @param baudRate_Bps Baud Rate needed in Hz.
476 * @param srcClockHz SPI source clock frequency in Hz.
477 */
478 void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz);
479
480 /*!
481 * @brief Writes one byte of data, which is sent using the MSB method.
482 *
483 * @note This is a non-blocking API, which returns directly after the data is put into the
484 * data register but the data transfer is not finished on the bus. Ensure that
485 * the TxEmptyFlag is asserted before calling this API.
486 *
487 * @param base Pointer to the FLEXIO_SPI_Type structure.
488 * @param direction Shift direction of MSB first or LSB first.
489 * @param data 8/16/32 bit data.
490 */
FLEXIO_SPI_WriteData(FLEXIO_SPI_Type * base,flexio_spi_shift_direction_t direction,uint32_t data)491 static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
492 {
493 if (direction == kFLEXIO_SPI_MsbFirst)
494 {
495 base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
496 }
497 else
498 {
499 base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data;
500 }
501 }
502
503 /*!
504 * @brief Reads 8 bit/16 bit data.
505 *
506 * @note This is a non-blocking API, which returns directly after the data is read from the
507 * data register. Ensure that the RxFullFlag is asserted before calling this API.
508 *
509 * @param base Pointer to the FLEXIO_SPI_Type structure.
510 * @param direction Shift direction of MSB first or LSB first.
511 * @return 8 bit/16 bit data received.
512 */
FLEXIO_SPI_ReadData(FLEXIO_SPI_Type * base,flexio_spi_shift_direction_t direction)513 static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
514 {
515 if (direction == kFLEXIO_SPI_MsbFirst)
516 {
517 return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
518 }
519 else
520 {
521 return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
522 }
523 }
524
525 /*!
526 * @brief Sends a buffer of data bytes.
527 *
528 * @note This function blocks using the polling method until all bytes have been sent.
529 *
530 * @param base Pointer to the FLEXIO_SPI_Type structure.
531 * @param direction Shift direction of MSB first or LSB first.
532 * @param buffer The data bytes to send.
533 * @param size The number of data bytes to send.
534 * @retval kStatus_Success Successfully create the handle.
535 * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
536 */
537 status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
538 flexio_spi_shift_direction_t direction,
539 const uint8_t *buffer,
540 size_t size);
541
542 /*!
543 * @brief Receives a buffer of bytes.
544 *
545 * @note This function blocks using the polling method until all bytes have been received.
546 *
547 * @param base Pointer to the FLEXIO_SPI_Type structure.
548 * @param direction Shift direction of MSB first or LSB first.
549 * @param buffer The buffer to store the received bytes.
550 * @param size The number of data bytes to be received.
551 * @retval kStatus_Success Successfully create the handle.
552 * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
553 */
554 status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
555 flexio_spi_shift_direction_t direction,
556 uint8_t *buffer,
557 size_t size);
558
559 /*!
560 * @brief Receives a buffer of bytes.
561 *
562 * @note This function blocks via polling until all bytes have been received.
563 *
564 * @param base pointer to FLEXIO_SPI_Type structure
565 * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
566 * @retval kStatus_Success Successfully create the handle.
567 * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
568 */
569 status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
570
571 /*!
572 * @brief Flush tx/rx shifters.
573 *
574 * @param base Pointer to the FLEXIO_SPI_Type structure.
575 */
576 void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
577 /*! @} */
578
579 /*Transactional APIs*/
580
581 /*!
582 * @name Transactional
583 * @{
584 */
585
586 /*!
587 * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
588 *
589 * @param base Pointer to the FLEXIO_SPI_Type structure.
590 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
591 * @param callback The callback function.
592 * @param userData The parameter of the callback function.
593 * @retval kStatus_Success Successfully create the handle.
594 * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
595 */
596 status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
597 flexio_spi_master_handle_t *handle,
598 flexio_spi_master_transfer_callback_t callback,
599 void *userData);
600
601 /*!
602 * @brief Master transfer data using IRQ.
603 *
604 * This function sends data using IRQ. This is a non-blocking function, which returns
605 * right away. When all data is sent out/received, the callback function is called.
606 *
607 * @param base Pointer to the FLEXIO_SPI_Type structure.
608 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
609 * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
610 * @retval kStatus_Success Successfully start a transfer.
611 * @retval kStatus_InvalidArgument Input argument is invalid.
612 * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
613 */
614 status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
615 flexio_spi_master_handle_t *handle,
616 flexio_spi_transfer_t *xfer);
617
618 /*!
619 * @brief Aborts the master data transfer, which used IRQ.
620 *
621 * @param base Pointer to the FLEXIO_SPI_Type structure.
622 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
623 */
624 void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
625
626 /*!
627 * @brief Gets the data transfer status which used IRQ.
628 *
629 * @param base Pointer to the FLEXIO_SPI_Type structure.
630 * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
631 * @param count Number of bytes transferred so far by the non-blocking transaction.
632 * @retval kStatus_InvalidArgument count is Invalid.
633 * @retval kStatus_Success Successfully return the count.
634 */
635 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count);
636
637 /*!
638 * @brief FlexIO SPI master IRQ handler function.
639 *
640 * @param spiType Pointer to the FLEXIO_SPI_Type structure.
641 * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
642 */
643 void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle);
644
645 /*!
646 * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
647 *
648 * @param base Pointer to the FLEXIO_SPI_Type structure.
649 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
650 * @param callback The callback function.
651 * @param userData The parameter of the callback function.
652 * @retval kStatus_Success Successfully create the handle.
653 * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
654 */
655 status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
656 flexio_spi_slave_handle_t *handle,
657 flexio_spi_slave_transfer_callback_t callback,
658 void *userData);
659
660 /*!
661 * @brief Slave transfer data using IRQ.
662 *
663 * This function sends data using IRQ. This is a non-blocking function, which returns
664 * right away. When all data is sent out/received, the callback function is called.
665 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
666 *
667 * @param base Pointer to the FLEXIO_SPI_Type structure.
668 * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
669 * @retval kStatus_Success Successfully start a transfer.
670 * @retval kStatus_InvalidArgument Input argument is invalid.
671 * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
672 */
673 status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
674 flexio_spi_slave_handle_t *handle,
675 flexio_spi_transfer_t *xfer);
676
677 /*!
678 * @brief Aborts the slave data transfer which used IRQ, share same API with master.
679 *
680 * @param base Pointer to the FLEXIO_SPI_Type structure.
681 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
682 */
FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type * base,flexio_spi_slave_handle_t * handle)683 static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
684 {
685 FLEXIO_SPI_MasterTransferAbort(base, handle);
686 }
687 /*!
688 * @brief Gets the data transfer status which used IRQ, share same API with master.
689 *
690 * @param base Pointer to the FLEXIO_SPI_Type structure.
691 * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
692 * @param count Number of bytes transferred so far by the non-blocking transaction.
693 * @retval kStatus_InvalidArgument count is Invalid.
694 * @retval kStatus_Success Successfully return the count.
695 */
FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type * base,flexio_spi_slave_handle_t * handle,size_t * count)696 static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
697 flexio_spi_slave_handle_t *handle,
698 size_t *count)
699 {
700 return FLEXIO_SPI_MasterTransferGetCount(base, handle, count);
701 }
702
703 /*!
704 * @brief FlexIO SPI slave IRQ handler function.
705 *
706 * @param spiType Pointer to the FLEXIO_SPI_Type structure.
707 * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
708 */
709 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
710
711 /*! @} */
712
713 #if defined(__cplusplus)
714 }
715 #endif /*_cplusplus*/
716 /*! @} */
717
718 #endif /*FSL_FLEXIO_SPI_H_*/
719
