1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2019 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_FLEXBUS_H_ 10 #define _FSL_FLEXBUS_H_ 11 12 #include "fsl_common.h" 13 14 /*! 15 * @addtogroup flexbus 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 23 /*! @name Driver version */ 24 /*@{*/ 25 #define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ 26 /*@}*/ 27 28 /*! 29 * @brief Defines port size for FlexBus peripheral. 30 */ 31 typedef enum _flexbus_port_size 32 { 33 kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */ 34 kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */ 35 kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */ 36 } flexbus_port_size_t; 37 38 /*! 39 * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. 40 */ 41 typedef enum _flexbus_write_address_hold 42 { 43 kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */ 44 kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */ 45 kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */ 46 kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */ 47 } flexbus_write_address_hold_t; 48 49 /*! 50 * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. 51 */ 52 typedef enum _flexbus_read_address_hold 53 { 54 kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */ 55 kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */ 56 kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */ 57 kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */ 58 } flexbus_read_address_hold_t; 59 60 /*! 61 * @brief Address setup for FlexBus peripheral. 62 */ 63 typedef enum _flexbus_address_setup 64 { 65 kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */ 66 kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */ 67 kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */ 68 kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */ 69 } flexbus_address_setup_t; 70 71 /*! 72 * @brief Defines byte-lane shift for FlexBus peripheral. 73 */ 74 typedef enum _flexbus_bytelane_shift 75 { 76 kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */ 77 kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */ 78 } flexbus_bytelane_shift_t; 79 80 /*! 81 * @brief Defines multiplex group1 valid signals. 82 */ 83 typedef enum _flexbus_multiplex_group1_signal 84 { 85 kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ 86 kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ 87 kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ 88 } flexbus_multiplex_group1_t; 89 90 /*! 91 * @brief Defines multiplex group2 valid signals. 92 */ 93 typedef enum _flexbus_multiplex_group2_signal 94 { 95 kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ 96 kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ 97 kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ 98 } flexbus_multiplex_group2_t; 99 100 /*! 101 * @brief Defines multiplex group3 valid signals. 102 */ 103 typedef enum _flexbus_multiplex_group3_signal 104 { 105 kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ 106 kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ 107 kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ 108 } flexbus_multiplex_group3_t; 109 110 /*! 111 * @brief Defines multiplex group4 valid signals. 112 */ 113 typedef enum _flexbus_multiplex_group4_signal 114 { 115 kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ 116 kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ 117 kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ 118 } flexbus_multiplex_group4_t; 119 120 /*! 121 * @brief Defines multiplex group5 valid signals. 122 */ 123 typedef enum _flexbus_multiplex_group5_signal 124 { 125 kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ 126 kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ 127 kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ 128 } flexbus_multiplex_group5_t; 129 130 /*! 131 * @brief Configuration structure that the user needs to set. 132 */ 133 typedef struct _flexbus_config 134 { 135 uint8_t chip; /*!< Chip FlexBus for validation */ 136 uint8_t waitStates; /*!< Value of wait states */ 137 uint8_t secondaryWaitStates; /*!< Value of secondary wait states */ 138 uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */ 139 uint32_t chipBaseAddressMask; /*!< Chip base address mask */ 140 bool writeProtect; /*!< Write protected */ 141 bool burstWrite; /*!< Burst-Write enable */ 142 bool burstRead; /*!< Burst-Read enable */ 143 bool byteEnableMode; /*!< Byte-enable mode support */ 144 bool autoAcknowledge; /*!< Auto acknowledge setting */ 145 bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */ 146 bool secondaryWaitStatesEnable; /*!< Enable secondary wait states */ 147 flexbus_port_size_t portSize; /*!< Port size of transfer */ 148 flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */ 149 flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */ 150 flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */ 151 flexbus_address_setup_t addressSetup; /*!< Address setup setting */ 152 flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */ 153 flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */ 154 flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */ 155 flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */ 156 flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */ 157 } flexbus_config_t; 158 159 /******************************************************************************* 160 * API 161 ******************************************************************************/ 162 163 #if defined(__cplusplus) 164 extern "C" { 165 #endif /* __cplusplus */ 166 167 /*! 168 * @name FlexBus functional operation 169 * @{ 170 */ 171 172 /*! 173 * @brief Initializes and configures the FlexBus module. 174 * 175 * This function enables the clock gate for FlexBus module. 176 * Only chip 0 is validated and set to known values. Other chips are disabled. 177 * Note that in this function, certain parameters, depending on external memories, must 178 * be set before using the FLEXBUS_Init() function. 179 * This example shows how to set up the uart_state_t and the 180 * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing 181 * in these parameters. 182 @code 183 flexbus_config_t flexbusConfig; 184 FLEXBUS_GetDefaultConfig(&flexbusConfig); 185 flexbusConfig.waitStates = 2U; 186 flexbusConfig.chipBaseAddress = 0x60000000U; 187 flexbusConfig.chipBaseAddressMask = 7U; 188 FLEXBUS_Init(FB, &flexbusConfig); 189 @endcode 190 * 191 * @param base FlexBus peripheral address. 192 * @param config Pointer to the configuration structure 193 */ 194 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config); 195 196 /*! 197 * @brief De-initializes a FlexBus instance. 198 * 199 * This function disables the clock gate of the FlexBus module clock. 200 * 201 * @param base FlexBus peripheral address. 202 */ 203 void FLEXBUS_Deinit(FB_Type *base); 204 205 /*! 206 * @brief Initializes the FlexBus configuration structure. 207 * 208 * This function initializes the FlexBus configuration structure to default value. The default 209 * values are. 210 @code 211 fbConfig->chip = 0; 212 fbConfig->writeProtect = 0; 213 fbConfig->burstWrite = 0; 214 fbConfig->burstRead = 0; 215 fbConfig->byteEnableMode = 0; 216 fbConfig->autoAcknowledge = true; 217 fbConfig->extendTransferAddress = 0; 218 fbConfig->secondaryWaitStates = 0; 219 fbConfig->byteLaneShift = kFLEXBUS_NotShifted; 220 fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle; 221 fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles; 222 fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge; 223 fbConfig->portSize = kFLEXBUS_1Byte; 224 fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; 225 fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ; 226 fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; 227 fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; 228 fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; 229 @endcode 230 * @param config Pointer to the initialization structure. 231 * @see FLEXBUS_Init 232 */ 233 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config); 234 235 /*! @}*/ 236 237 #if defined(__cplusplus) 238 } 239 #endif /* __cplusplus */ 240 241 /*! @}*/ 242 243 #endif /* _FSL_FLEXBUS_H_ */ 244
