1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef FSL_ENET_QOS_H_
7 #define FSL_ENET_QOS_H_
8
9 #include "fsl_common.h"
10 #if defined(FSL_ETH_ENABLE_CACHE_CONTROL)
11 #include "fsl_cache.h"
12 #endif
13 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
14 #include "fsl_memory.h"
15 #endif
16
17 #if !defined(ENET_QOS)
18 /* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */
19 #if defined(ENET_QOS_TSN)
20 #define ENET_QOS ENET_QOS_TSN
21 #endif
22 #endif
23 /*!
24 * @addtogroup enet_qos_qos
25 * @{
26 */
27
28 /*******************************************************************************
29 * Definitions
30 ******************************************************************************/
31
32 /*! @name Driver version */
33 /*! @{ */
34 /*! @brief Defines the driver version. */
35 #define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 2))
36 /*! @} */
37
38 /*! @name Control and status region bit masks of the receive buffer descriptor. */
39 /*! @{ */
40 /*! @brief Defines for read format. */
41 #define ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK (1UL << 24U) /*!< Buffer1 address valid. */
42 #define ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK (1UL << 25U) /*!< Buffer2 address valid. */
43 #define ENET_QOS_RXDESCRIP_RD_IOC_MASK (1UL << 30U) /*!< Interrupt enable on complete. */
44 #define ENET_QOS_RXDESCRIP_RD_OWN_MASK (1UL << 31U) /*!< Own bit. */
45
46 /*! @brief Defines for write back format. */
47 #define ENET_QOS_RXDESCRIP_WR_ERR_MASK ((1UL << 3U) | (1UL << 7U))
48 #define ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK (0x7UL)
49 #define ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00UL)
50 #define ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK (1UL << 12U)
51 #define ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK (1UL << 13U)
52 #define ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK (1UL << 14U)
53 #define ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFUL)
54 #define ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK (1UL << 15U)
55 #define ENET_QOS_RXDESCRIP_WR_TYPE_MASK (0x30000UL)
56 #define ENET_QOS_RXDESCRIP_WR_DE_MASK (1UL << 19U)
57 #define ENET_QOS_RXDESCRIP_WR_RE_MASK (1UL << 20U)
58 #define ENET_QOS_RXDESCRIP_WR_OE_MASK (1UL << 21U)
59 #define ENET_QOS_RXDESCRIP_WR_RWT_MASK (1UL << 22U)
60 #define ENET_QOS_RXDESCRIP_WR_GP_MASK (1UL << 22U)
61 #define ENET_QOS_RXDESCRIP_WR_CRC_MASK (1UL << 23U)
62 #define ENET_QOS_RXDESCRIP_WR_RS0V_MASK (1UL << 25U)
63 #define ENET_QOS_RXDESCRIP_WR_RS1V_MASK (1UL << 26U)
64 #define ENET_QOS_RXDESCRIP_WR_RS2V_MASK (1UL << 27U)
65 #define ENET_QOS_RXDESCRIP_WR_LD_MASK (1UL << 28U)
66 #define ENET_QOS_RXDESCRIP_WR_FD_MASK (1UL << 29U)
67 #define ENET_QOS_RXDESCRIP_WR_CTXT_MASK (1UL << 30U)
68 #define ENET_QOS_RXDESCRIP_WR_OWN_MASK (1UL << 31U)
69
70 #define ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK (1UL << 16U)
71 #define ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK (1UL << 17U)
72 /*! @} */
73
74 /*! @name Control and status bit masks of the transmit buffer descriptor. */
75 /*! @{ */
76 /*! @brief Defines for read format. */
77 #define ENET_QOS_TXDESCRIP_RD_BL1_MASK (0x3fffUL)
78 #define ENET_QOS_TXDESCRIP_RD_BL2_MASK (ENET_QOS_TXDESCRIP_RD_BL1_MASK << 16U)
79 #define ENET_QOS_TXDESCRIP_RD_BL1(n) ((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_BL1_MASK)
80 #define ENET_QOS_TXDESCRIP_RD_BL2(n) (((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_BL1_MASK) << 16)
81 #define ENET_QOS_TXDESCRIP_RD_TTSE_MASK (1UL << 30UL)
82 #define ENET_QOS_TXDESCRIP_RD_IOC_MASK (1UL << 31UL)
83
84 #define ENET_QOS_TXDESCRIP_RD_FL_MASK (0x7FFFUL)
85 #define ENET_QOS_TXDESCRIP_RD_FL(n) ((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_FL_MASK)
86 #define ENET_QOS_TXDESCRIP_RD_CIC(n) (((uint32_t)(n)&0x3U) << 16U)
87 #define ENET_QOS_TXDESCRIP_RD_TSE_MASK (1UL << 18U)
88 #define ENET_QOS_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n)&0x0fU) << 19U)
89 #define ENET_QOS_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n)&0x07U) << 23U)
90 #define ENET_QOS_TXDESCRIP_RD_CPC(n) (((uint32_t)(n)&0x03U) << 26U)
91 #define ENET_QOS_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n)&0x03U) << 28U)
92 #define ENET_QOS_TXDESCRIP_RD_LD_MASK (1UL << 28U)
93 #define ENET_QOS_TXDESCRIP_RD_FD_MASK (1UL << 29U)
94 #define ENET_QOS_TXDESCRIP_RD_CTXT_MASK (1UL << 30U)
95 #define ENET_QOS_TXDESCRIP_RD_OWN_MASK (1UL << 31U)
96
97 /*! @brief Defines for write back format. */
98 #define ENET_QOS_TXDESCRIP_WB_TTSS_MASK (1UL << 17U)
99 /*! @} */
100
101 /*! @name Bit mask for interrupt enable type. */
102 /*! @{ */
103 #define ENET_QOS_ABNORM_INT_MASK \
104 (ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK | ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RSE_MASK | \
105 ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK | ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK | ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
106 #define ENET_QOS_NORM_INT_MASK \
107 (ENET_QOS_DMA_CHX_INT_EN_TIE_MASK | ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RIE_MASK | \
108 ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
109 /*! @} */
110
111 /*! @name Defines some Ethernet parameters. */
112 /*! @{ */
113 #ifndef ENET_QOS_RING_NUM_MAX
114 #define ENET_QOS_RING_NUM_MAX (5U) /*!< The Maximum number of tx/rx descriptor rings. */
115 #endif
116 #define ENET_QOS_FRAME_MAX_FRAMELEN (1518U) /*!< Default maximum Ethernet frame size. */
117 #define ENET_QOS_FCS_LEN (4U) /*!< Ethernet FCS length. */
118 #define ENET_QOS_ADDR_ALIGNMENT (0x3U) /*!< Recommended Ethernet buffer alignment. */
119 #define ENET_QOS_BUFF_ALIGNMENT (8U) /*!< Receive buffer alignment shall be 4bytes-aligned. */
120 #define ENET_QOS_MTL_RXFIFOSIZE (8192U) /*!< The rx fifo size. */
121 #define ENET_QOS_MTL_TXFIFOSIZE (8192U) /*!< The tx fifo size. */
122 #define ENET_QOS_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */
123 #define ENET_QOS_RXP_ENTRY_COUNT (256U) /*!< RXP table entry count, implied by FRPES in MAC_HW_FEATURE3 */
124 #define ENET_QOS_RXP_BUFFER_SIZE (256U) /*!< RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3 */
125 #define ENET_QOS_EST_WID (24U) /*!< Width of the time interval in Gate Control List */
126 #define ENET_QOS_EST_DEP (512U) /*!< Maxmimum depth of Gate Control List */
127 /*! @} */
128
129 /*! @brief Defines the status return codes for transaction. */
130 enum
131 {
132 kStatus_ENET_QOS_InitMemoryFail =
133 MAKE_STATUS(kStatusGroup_ENET_QOS, 0U), /*!< Init fails since buffer memory is not enough. */
134 kStatus_ENET_QOS_RxFrameError =
135 MAKE_STATUS(kStatusGroup_ENET_QOS, 1U), /*!< A frame received but data error happen. */
136 kStatus_ENET_QOS_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 2U), /*!< Failed to receive a frame. */
137 kStatus_ENET_QOS_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET_QOS, 3U), /*!< No frame arrive. */
138 kStatus_ENET_QOS_RxFrameDrop =
139 MAKE_STATUS(kStatusGroup_ENET_QOS, 4U), /*!< Rx frame is dropped since no buffer memory. */
140 kStatus_ENET_QOS_TxFrameBusy =
141 MAKE_STATUS(kStatusGroup_ENET_QOS, 5U), /*!< Transmit descriptors are under process. */
142 kStatus_ENET_QOS_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 6U), /*!< Transmit frame fail. */
143 kStatus_ENET_QOS_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET_QOS, 7U), /*!< Transmit oversize. */
144 kStatus_ENET_QOS_Est_SwListBusy =
145 MAKE_STATUS(kStatusGroup_ENET_QOS, 8U), /*!< SW Gcl List not yet processed by HW. */
146 kStatus_ENET_QOS_Est_SwListWriteAbort = MAKE_STATUS(kStatusGroup_ENET_QOS, 9U), /*!< SW Gcl List write aborted .*/
147 kStatus_ENET_QOS_Est_InvalidParameter =
148 MAKE_STATUS(kStatusGroup_ENET_QOS, 10U), /*!< Invalid parameter in Gcl List .*/
149 kStatus_ENET_QOS_Est_BtrError = MAKE_STATUS(kStatusGroup_ENET_QOS, 11U), /*!< Base Time Error when loading list.*/
150 kStatus_ENET_QOS_TrgtBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 12U), /*!< Target time register busy.*/
151 kStatus_ENET_QOS_Timeout = MAKE_STATUS(kStatusGroup_ENET_QOS, 13U), /*!< Target time register busy.*/
152 kStatus_ENET_QOS_PpsBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 14U) /*!< Pps command busy.*/
153 };
154
155 /*! @brief Defines the MII/RGMII mode for data interface between the MAC and the PHY. */
156 typedef enum _enet_qos_mii_mode
157 {
158 kENET_QOS_MiiMode = 0U, /*!< MII mode for data interface. */
159 kENET_QOS_RgmiiMode = 1U, /*!< RGMII mode for data interface. */
160 kENET_QOS_RmiiMode = 4U /*!< RMII mode for data interface. */
161 } enet_qos_mii_mode_t;
162
163 /*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. */
164 typedef enum _enet_qos_mii_speed
165 {
166 kENET_QOS_MiiSpeed10M =
167 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 10 Mbps. */
168 kENET_QOS_MiiSpeed100M =
169 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(1U), /*!< Speed 100 Mbps. */
170 kENET_QOS_MiiSpeed1000M =
171 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 1000 Mbps. */
172 kENET_QOS_MiiSpeed2500M =
173 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(1U) /*!< Speed 2500 Mbps. */
174 } enet_qos_mii_speed_t;
175
176 /*! @brief Defines the half or full duplex for the MII data interface. */
177 typedef enum _enet_qos_mii_duplex
178 {
179 kENET_QOS_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
180 kENET_QOS_MiiFullDuplex /*!< Full duplex mode. */
181 } enet_qos_mii_duplex_t;
182
183 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
184 typedef enum _enet_qos_mii_normal_opcode
185 {
186 kENET_QOS_MiiWriteFrame =
187 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(0U) |
188 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U), /*!< Write frame operation for a valid MII management frame. */
189 kENET_QOS_MiiReadFrame =
190 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(1U) |
191 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U) /*!< Read frame operation for a valid MII management frame. */
192 } enet_qos_mii_normal_opcode;
193
194 /*! @brief Define the DMA maximum transmit burst length. */
195 typedef enum _enet_qos_dma_burstlen
196 {
197 kENET_QOS_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */
198 kENET_QOS_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */
199 kENET_QOS_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */
200 kENET_QOS_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */
201 kENET_QOS_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */
202 kENET_QOS_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */
203 kENET_QOS_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */
204 kENET_QOS_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
205 kENET_QOS_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
206 } enet_qos_dma_burstlen;
207
208 /*! @brief Define the flag for the descriptor. */
209 typedef enum _enet_qos_desc_flag
210 {
211 kENET_QOS_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
212 kENET_QOS_LastFlagOnly, /*!< It's the last descriptor of the frame. */
213 kENET_QOS_FirstFlagOnly, /*!< It's the first descriptor of the frame. */
214 kENET_QOS_FirstLastFlag /*!< It's the first and last descriptor of the frame. */
215 } enet_qos_desc_flag;
216
217 /*! @brief Define the system time adjust operation control. */
218 typedef enum _enet_qos_systime_op
219 {
220 kENET_QOS_SystimeAdd = 0U, /*!< System time add to. */
221 kENET_QOS_SystimeSubtract = 1U /*!< System time subtract. */
222 } enet_qos_systime_op;
223
224 /*! @brief Define the system time rollover control. */
225 typedef enum _enet_qos_ts_rollover_type
226 {
227 kENET_QOS_BinaryRollover = 0, /*!< System time binary rollover.*/
228 kENET_QOS_DigitalRollover = 1 /*!< System time digital rollover.*/
229 } enet_qos_ts_rollover_type;
230
231 /*! @brief Defines some special configuration for ENET.
232 *
233 * These control flags are provided for special user requirements.
234 * Normally, these is no need to set this control flags for ENET initialization.
235 * But if you have some special requirements, set the flags to specialControl
236 * in the enet_qos_config_t.
237 * @note "kENET_QOS_StoreAndForward" is recommended to be set.
238 */
239 typedef enum _enet_qos_special_config
240 {
241 /***********************DMA CONFIG**********************************************/
242 kENET_QOS_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
243 /**************************MTL************************************/
244 kENET_QOS_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
245 /***********************MAC****************************************/
246 kENET_QOS_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
247 kENET_QOS_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
248 kENET_QOS_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
249 kENET_QOS_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
250 kENET_QOS_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */
251 kENET_QOS_HashMulticastEnable = 0x0080U, /*!< The multicast packets are filtered through hash table. */
252 kENET_QOS_RxChecksumOffloadEnable = 0x0100U, /*!< The Rx checksum offload enabled. */
253 } enet_qos_special_config_t;
254
255 /*! @brief List of DMA interrupts supported by the ENET interrupt. This
256 * enumeration uses one-bot encoding to allow a logical OR of multiple
257 * members.
258 */
259 typedef enum _enet_qos_dma_interrupt_enable
260 {
261 kENET_QOS_DmaTx = ENET_QOS_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */
262 kENET_QOS_DmaTxStop = ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK, /*!< Tx stop interrupt. */
263 kENET_QOS_DmaTxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */
264 kENET_QOS_DmaRx = ENET_QOS_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */
265 kENET_QOS_DmaRxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */
266 kENET_QOS_DmaRxStop = ENET_QOS_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */
267 kENET_QOS_DmaRxWatchdogTimeout = ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
268 kENET_QOS_DmaEarlyTx = ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */
269 kENET_QOS_DmaEarlyRx = ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */
270 kENET_QOS_DmaBusErr = ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */
271 } enet_qos_dma_interrupt_enable_t;
272
273 /*! @brief List of mac interrupts supported by the ENET interrupt. This
274 * enumeration uses one-bot encoding to allow a logical OR of multiple
275 * members.
276 */
277 typedef enum _enet_qos_mac_interrupt_enable
278 {
279 kENET_QOS_MacPmt = (ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
280 kENET_QOS_MacTimestamp = (ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
281 } enet_qos_mac_interrupt_enable_t;
282
283 /*! @brief Defines the common interrupt event for callback use. */
284 typedef enum _enet_qos_event
285 {
286 kENET_QOS_RxIntEvent, /*!< Receive interrupt event. */
287 kENET_QOS_TxIntEvent, /*!< Transmit interrupt event. */
288 kENET_QOS_WakeUpIntEvent, /*!< Wake up interrupt event. */
289 kENET_QOS_TimeStampIntEvent, /*!< Time stamp interrupt event. */
290 } enet_qos_event_t;
291
292 /*! @brief Define the MTL mode for multiple queues/rings. */
293 typedef enum _enet_qos_queue_mode
294 {
295 kENET_QOS_AVB_Mode = 1U, /*!< Enable queue in AVB mode. */
296 kENET_QOS_DCB_Mode = 2U, /*!< Enable queue in DCB mode. */
297 } enet_qos_queue_mode_t;
298
299 /*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
300 typedef enum _enet_qos_mtl_multiqueue_txsche
301 {
302 kENET_QOS_txWeightRR = 0U, /*!< Tx weight round-robin. */
303 kENET_QOS_txWeightFQ = 1U, /*!< Tx weight fair queuing. */
304 kENET_QOS_txDefictWeightRR = 2U, /*!< Tx deficit weighted round-robin. */
305 kENET_QOS_txStrPrio = 3U, /*!< Tx strict priority. */
306 } enet_qos_mtl_multiqueue_txsche;
307
308 /*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
309 typedef enum _enet_qos_mtl_multiqueue_rxsche
310 {
311 kENET_QOS_rxStrPrio = 0U, /*!< Rx strict priority, Queue 0 has the lowest priority. */
312 kENET_QOS_rxWeightStrPrio, /*!< Weighted Strict Priority. */
313 } enet_qos_mtl_multiqueue_rxsche;
314
315 /*! @brief Define the MTL rx queue and DMA channel mapping. */
316 typedef enum _enet_qos_mtl_rxqueuemap
317 {
318 kENET_QOS_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) directly map to dma channel n. */
319 kENET_QOS_DynamicMap =
320 0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
321 */
322 } enet_qos_mtl_rxqueuemap_t;
323
324 /*! @brief Defines the package type for receive queue routing. */
325 typedef enum _enet_qos_rx_queue_route
326 {
327 kENET_QOS_PacketNoQ = 0x0, /* Not specific queue */
328 kENET_QOS_PacketAVCPQ = (1U << 0U), /* AV Untagged Control Packets Queue */
329 kENET_QOS_PacketPTPQ = (1U << 1U), /* PTP Packets Queue */
330 kENET_QOS_PacketDCBCPQ = (1U << 2U), /* DCB Control Packets Queue */
331 kENET_QOS_PacketUPQ = (1U << 3U), /* Untagged Packets Queue */
332 kENET_QOS_PacketMCBCQ = (1U << 4U), /* Multicast & Broadcast Packets Queue */
333 } enet_qos_rx_queue_route_t;
334
335 /*! @brief Defines the ENET PTP message related constant. */
336 typedef enum _enet_qos_ptp_event_type
337 {
338 kENET_QOS_PtpEventMsgType = 3U, /*!< PTP event message type. */
339 kENET_QOS_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
340 kENET_QOS_PtpEventPort = 319U, /*!< PTP event port number. */
341 kENET_QOS_PtpGnrlPort = 320U /*!< PTP general port number. */
342 } enet_qos_ptp_event_type_t;
343
344 /*! @brief Defines the PPS instance numbers. */
345 typedef enum _enet_qos_ptp_pps_instance
346 {
347 kENET_QOS_PtpPpsIstance0 = 0U, /*!< PPS instance 0. */
348 kENET_QOS_PtpPpsIstance1, /*!< PPS instance 1. */
349 kENET_QOS_PtpPpsIstance2, /*!< PPS instance 2. */
350 kENET_QOS_PtpPpsIstance3 /*!< PPS instance 3. */
351 } enet_qos_ptp_pps_instance_t;
352
353 /*! @brief Defines the Target Time register mode. */
354 typedef enum _enet_qos_ptp_pps_trgt_mode
355 {
356 kENET_QOS_PtpPpsTrgtModeOnlyInt = 0U, /*!< Only interrupts. */
357 kENET_QOS_PtpPpsTrgtModeIntSt = 2, /*!< Both interrupt and output signal. */
358 kENET_QOS_PtpPpsTrgtModeOnlySt = 3, /*!< Only output signal. */
359 } enet_qos_ptp_pps_trgt_mode_t;
360
361 /*! @brief Defines commands for ppscmd register. */
362 typedef enum _enet_qos_ptp_pps_cmd
363 {
364 kENET_QOS_PtpPpsCmdNC = 0U, /*!< No Command. */
365 kENET_QOS_PtpPpsCmdSSP = 1U, /*!< Start Single Pulse. */
366 kENET_QOS_PtpPpsCmdSPT = 2U, /*!< Start Pulse Train. */
367 kENET_QOS_PtpPpsCmdCS = 3U, /*!< Cancel Start. */
368 kENET_QOS_PtpPpsCmdSPTAT = 4U, /*!< Stop Pulse Train At Time. */
369 kENET_QOS_PtpPpsCmdSPTI = 5U, /*!< Stop Pulse Train Immediately. */
370 kENET_QOS_PtpPpsCmdCSPT = 6U, /*!< Cancel Stop Pulse Train. */
371 } enet_qos_ptp_pps_cmd_t;
372
373 /*! @brief Defines the enmueration of ETS list length.
374 */
375 typedef enum _enet_qos_ets_list_length
376 {
377 kENET_QOS_Ets_List_64 = 7U, /*!< List length of 64 */
378 kENET_QOS_Ets_List_128 = 8U, /*!< List length of 128 */
379 kENET_QOS_Ets_List_256 = 9U, /*!< List length of 256 */
380 kENET_QOS_Ets_List_512 = 10U, /*!< List length of 512 */
381 kENET_QOS_Ets_List_1024 = 11U, /*!< List length of 1024 */
382 } enet_qos_ets_list_length_t;
383
384 /*! @brief Defines the enmueration of ETS gate control address.
385 */
386 typedef enum _enet_qos_ets_gccr_addr
387 {
388 kENET_QOS_Ets_btr_low = 0U, /*!< BTR Low */
389 kENET_QOS_Ets_btr_high = 1U, /*!< BTR High */
390 kENET_QOS_Ets_ctr_low = 2U, /*!< CTR Low */
391 kENET_QOS_Ets_ctr_high = 3U, /*!< CTR High */
392 kENET_QOS_Ets_ter = 4U, /*!< TER */
393 kENET_QOS_Ets_llr = 5U, /*!< LLR */
394 } enet_qos_ets_gccr_addr_t;
395
396 /*! @brief Defines the enmueration of DMA channel used
397 * for rx parser entry.
398 */
399 typedef enum _enet_qos_rxp_dma_chn
400 {
401 kENET_QOS_Rxp_DMAChn0 = 1U, /*!< DMA Channel 0 used for RXP entry match */
402 kENET_QOS_Rxp_DMAChn1 = 2U, /*!< DMA Channel 1 used for RXP entry match */
403 kENET_QOS_Rxp_DMAChn2 = 4U, /*!< DMA Channel 2 used for RXP entry match */
404 kENET_QOS_Rxp_DMAChn3 = 8U, /*!< DMA Channel 3 used for RXP entry match */
405 kENET_QOS_Rxp_DMAChn4 = 16U, /*!< DMA Channel 4 used for RXP entry match */
406 } enet_qos_rxp_dma_chn_t;
407
408 /*! @brief Define the Tx checksum offload options. */
409 typedef enum _enet_qos_tx_offload
410 {
411 kENET_QOS_TxOffloadDisable = 0U, /*!< Disable Tx checksum offload. */
412 kENET_QOS_TxOffloadIPHeader = 1U, /*!< Enable IP header checksum calculation and insertion. */
413 kENET_QOS_TxOffloadIPHeaderPlusPayload = 2U, /*!< Enable IP header and payload checksum calculation and insertion. */
414 kENET_QOS_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */
415 } enet_qos_tx_offload_t;
416
417 /*! @brief Defines the receive descriptor structure
418 * has the read-format and write-back format structure. They both
419 * has the same size with different region definition. so
420 * we define the read-format region as the receive descriptor structure
421 * Use the read-format region mask bits in the descriptor initialization
422 * Use the write-back format region mask bits in the receive data process.
423 */
424 typedef struct _enet_qos_rx_bd_struct
425 {
426 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
427 __IO uint32_t reserved; /*!< Reserved */
428 __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
429 __IO uint32_t control; /*!< Buffer 1/2 byte counts and control */
430 } enet_qos_rx_bd_struct_t;
431
432 /*! @brief Defines the transmit descriptor structure
433 * has the read-format and write-back format structure. They both
434 * has the same size with different region definition. so
435 * we define the read-format region as the transmit descriptor structure
436 * Use the read-format region mask bits in the descriptor initialization
437 * Use the write-back format region mask bits in the transmit data process.
438 */
439 typedef struct _enet_qos_tx_bd_struct
440 {
441 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
442 __IO uint32_t buff2Addr; /*!< Buffer 2 address */
443 __IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */
444 __IO uint32_t controlStat; /*!< TDES control and status word */
445 } enet_qos_tx_bd_struct_t;
446
447 /*! @brief Defines the Tx BD configuration structure. */
448 typedef struct _enet_qos_tx_bd_config_struct
449 {
450 void *buffer1; /*!< The first buffer address in the descriptor. */
451 uint32_t bytes1; /*!< The bytes in the fist buffer. */
452 void *buffer2; /*!< The second buffer address in the descriptor. */
453 uint32_t bytes2; /*!< The bytes in the second buffer. */
454 uint32_t framelen; /*!< The length of the frame to be transmitted. */
455 bool intEnable; /*!< Interrupt enable flag. */
456 bool tsEnable; /*!< The timestamp enable. */
457 enet_qos_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option. */
458 enet_qos_desc_flag flag; /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */
459 } enet_qos_tx_bd_config_struct_t;
460
461 /*! @brief Defines the ENET PTP time stamp structure. */
462 typedef struct _enet_qos_ptp_time
463 {
464 uint64_t second; /*!< Second. */
465 uint32_t nanosecond; /*!< Nanosecond. */
466 } enet_qos_ptp_time_t;
467
468 /*! @brief Defines the frame info structure. */
469 typedef struct enet_qos_frame_info
470 {
471 void *context; /*!< User specified data, could be buffer address for free */
472 bool isTsAvail; /*!< Flag indicates timestamp available status */
473 enet_qos_ptp_time_t timeStamp; /*!< Timestamp of frame */
474 } enet_qos_frame_info_t;
475
476 /*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */
477 typedef struct _enet_qos_tx_dirty_ring
478 {
479 enet_qos_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */
480 uint16_t txGenIdx; /*!< tx generate index. */
481 uint16_t txConsumIdx; /*!< tx consume index. */
482 uint16_t txRingLen; /*!< tx ring length. */
483 bool isFull; /*!< tx ring is full flag, add this parameter to avoid waste one element. */
484 } enet_qos_tx_dirty_ring_t;
485
486 /*! @brief Defines the ENET PTP configuration structure. */
487 typedef struct _enet_qos_ptp_config
488 {
489 bool fineUpdateEnable; /*!< Use the fine update. */
490 uint32_t defaultAddend; /*!< Default addend value when fine update is enable, could be 2^32 / (refClk_Hz /
491 ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ). */
492 uint32_t systemTimeClock_Hz; /*! The desired system time frequency. Must be lower than reference clock. (Only used
493 with fine correction method). */
494 bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */
495 enet_qos_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
496 } enet_qos_ptp_config_t;
497
498 /*! @brief Defines the EST gate operation structure. */
499 typedef struct _enet_qos_est_gate_op
500 {
501 uint32_t gate;
502 uint32_t interval;
503 } enet_qos_est_gate_op_t;
504
505 /*! @brief Defines the EST gate control list structure. */
506 typedef struct _enet_qos_est_gcl
507 {
508 bool enable; /*!< Enable or disable EST */
509 uint64_t baseTime; /*! Base Time 32 bits seconds 32 bits nanoseconds */
510 uint64_t cycleTime; /*! Cycle Time 32 bits seconds 32 bits nanoseconds */
511 uint32_t extTime; /*! Time Extension 32 bits seconds 32 bits nanoseconds */
512 uint32_t numEntries; /*! Number of entries */
513 enet_qos_est_gate_op_t *opList; /*! Pointer to GCL list size */
514 } enet_qos_est_gcl_t;
515
516 /*! @brief Defines the ENET_QOS Rx parser configuration structure.*/
517 typedef struct _enet_qos_rxp_config
518 {
519 uint32_t matchData; /*! 4-byte match data used for comparing with incoming packet */
520 uint32_t matchEnable; /*! When matchEnable is set to 1, the matchData is used for comparing */
521 uint8_t acceptFrame : 1; /*! When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel */
522 uint8_t rejectFrame : 1; /*! When rejectFrame = 1 and data is matched, the frame will be dropped */
523 uint8_t inverseMatch : 1; /*! Inverse match */
524 uint8_t nextControl : 1; /*! Next instruction indexing control */
525 uint8_t reserved : 4; /*! Reserved control fields */
526 uint8_t frameOffset; /*! Frame offset in the packet data to be compared for match, in terms of 4 bytes. */
527 uint8_t okIndex; /*! Memory Index to be used next. */
528 uint8_t dmaChannel; /*! The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and
529 acceptFrame = 1 */
530 uint32_t reserved2; /*! Reserved for future enhancements */
531 } enet_qos_rxp_config_t;
532
533 /*! @brief Defines the buffer descriptor configure structure.
534 *
535 * @note
536 * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
537 * 2. The recommended minimum tx/rx ring length is 4.
538 * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
539 * of the last last descriptor. because only the descriptors between the start address and the
540 * tail address will be used by DMA.
541 * 4. The descriptor address is the start address of all used contiguous memory.
542 * for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories
543 * for rx descriptor ring 0.
544 * 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers)
545 * rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
546 * the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
547 * the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
548 * address of a rxRingLen or 2*rxRingLen array.
549 */
550 typedef struct _enet_qos_buffer_config
551 {
552 uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */
553 uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */
554 enet_qos_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
555 enet_qos_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */
556 enet_qos_frame_info_t *txDirtyStartAddr; /*!< Start address of the dirty tx frame information. */
557 enet_qos_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
558 enet_qos_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */
559 uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */
560 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
561 bool rxBuffNeedMaintain; /*!< Whether receive data buffer need cache maintain. */
562 } enet_qos_buffer_config_t;
563
564 /*! @brief Defines the CBS configuration for queue. */
565 typedef struct _enet_qos_cbs_config
566 {
567 uint16_t sendSlope; /*!< Send slope configuration. */
568 uint16_t idleSlope; /*!< Idle slope configuration. */
569 uint32_t highCredit; /*!< High credit. */
570 uint32_t lowCredit; /*!< Low credit. */
571 } enet_qos_cbs_config_t;
572
573 /*! @brief Defines the queue configuration structure. */
574 typedef struct enet_qos_tx_queue_config
575 {
576 enet_qos_queue_mode_t mode; /*!< tx queue mode configuration. */
577 uint32_t weight; /*!< Refer to the MTL TxQ Quantum Weight register. */
578 uint32_t priority; /*!< Refer to Transmit Queue Priority Mapping register. */
579 enet_qos_cbs_config_t *cbsConfig; /*!< CBS configuration if queue use AVB mode. */
580 } enet_qos_queue_tx_config_t;
581
582 /*! @brief Defines the queue configuration structure. */
583 typedef struct enet_qos_rx_queue_config
584 {
585 enet_qos_queue_mode_t mode; /*!< rx queue mode configuration. */
586 uint8_t mapChannel; /*!< tx queue map dma channel. */
587 uint32_t priority; /*!< Rx queue priority. */
588 enet_qos_rx_queue_route_t packetRoute; /*!< Receive packet routing. */
589 } enet_qos_queue_rx_config_t;
590
591 /*! @brief Defines the configuration when multi-queue is used. */
592 typedef struct enet_qos_multiqueue_config
593 {
594 enet_qos_dma_burstlen burstLen; /*!< Burst len for the multi-queue. */
595 uint8_t txQueueUse; /*!< Used Tx queue count. */
596 enet_qos_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */
597 enet_qos_queue_tx_config_t txQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Tx Queue configuration. */
598 uint8_t rxQueueUse; /*!< Used Rx queue count. */
599 enet_qos_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */
600 enet_qos_queue_rx_config_t rxQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Rx Queue configuration. */
601 } enet_qos_multiqueue_config_t;
602
603 /*! @brief Defines the Rx memory buffer alloc function pointer. */
604 typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel);
605
606 /*! @brief Defines the Rx memory buffer free function pointer. */
607 typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel);
608
609 /*! @brief Defines the basic configuration structure for the ENET device.
610 *
611 * @note Default the signal queue is used so the "*multiqueueCfg" is set default
612 * with NULL. Set the pointer with a valid configuration pointer if the multiple
613 * queues are required. If multiple queue is enabled, please make sure the
614 * buffer configuration for all are prepared also.
615 */
616 typedef struct _enet_qos_config
617 {
618 uint16_t specialControl; /*!< The logic or of enet_qos_special_config_t */
619 enet_qos_multiqueue_config_t *multiqueueCfg; /*!< Use multi-queue. */
620 /* -----------------MAC block-------------------------------*/
621 enet_qos_mii_mode_t miiMode; /*!< MII mode. */
622 enet_qos_mii_speed_t miiSpeed; /*!< MII Speed. */
623 enet_qos_mii_duplex_t miiDuplex; /*!< MII duplex. */
624 uint16_t
625 pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set. */
626 /* -----------------Timestamp -------------------------------*/
627 enet_qos_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
628 uint32_t csrClock_Hz; /*!< CSR clock frequency in HZ. */
629 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
630 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
631 } enet_qos_config_t;
632
633 /* Forward declaration of the handle typedef. */
634 typedef struct _enet_qos_handle enet_qos_handle_t;
635
636 /*! @brief ENET callback function. */
637 typedef void (*enet_qos_callback_t)(
638 ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData);
639
640 /*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
641 typedef struct _enet_qos_tx_bd_ring
642 {
643 enet_qos_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
644 uint16_t txGenIdx; /*!< tx generate index. */
645 uint16_t txConsumIdx; /*!< tx consume index. */
646 volatile uint16_t txDescUsed; /*!< tx descriptor used number. */
647 uint16_t txRingLen; /*!< tx ring length. */
648 } enet_qos_tx_bd_ring_t;
649
650 /*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
651 typedef struct _enet_qos_rx_bd_ring
652 {
653 enet_qos_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
654 uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */
655 uint16_t rxRingLen; /*!< Receive ring length. */
656 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */
657 } enet_qos_rx_bd_ring_t;
658
659 /*! @brief Defines the ENET handler structure. */
660 struct _enet_qos_handle
661 {
662 uint8_t txQueueUse; /*!< Used tx queue count. */
663 uint8_t rxQueueUse; /*!< Used rx queue count. */
664 bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */
665 bool rxintEnable; /*!< Rx interrupt enabled. */
666 bool rxMaintainEnable[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer cache maintain enabled. */
667 enet_qos_rx_bd_ring_t rxBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Receive buffer descriptor. */
668 enet_qos_tx_bd_ring_t txBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */
669 enet_qos_tx_dirty_ring_t txDirtyRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */
670 uint32_t *rxBufferStartAddr[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer start address for reInitialize. */
671 enet_qos_callback_t callback; /*!< Callback function. */
672 void *userData; /*!< Callback function parameter.*/
673 uint8_t multicastCount[64]; /*!< Multicast collisions counter */
674 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
675 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
676 };
677
678 /*! @brief Defines the frame buffer structure. */
679 typedef struct _enet_qos_buffer_struct
680 {
681 void *buffer; /*!< The buffer store the whole or partial frame. */
682 uint16_t length; /*!< The byte length of this buffer. */
683 } enet_qos_buffer_struct_t;
684
685 /*! @brief Defines the Rx frame error structure. */
686 typedef struct _enet_qos_rx_frame_error
687 {
688 bool rxDstAddrFilterErr : 1; /*!< Destination Address Filter Fail. */
689 bool rxSrcAddrFilterErr : 1; /*!< SA Address Filter Fail. */
690 bool rxDribbleErr : 1; /*!< Dribble error. */
691 bool rxReceiveErr : 1; /*!< Receive error. */
692 bool rxOverFlowErr : 1; /*!< Receive over flow. */
693 bool rxWatchDogErr : 1; /*!< Watch dog timeout. */
694 bool rxGaintPacketErr : 1; /*!< Receive gaint packet. */
695 bool rxCrcErr : 1; /*!< Receive CRC error. */
696 } enet_qos_rx_frame_error_t;
697
698 typedef struct _enet_qos_rx_frame_attribute_struct
699 {
700 bool isTsAvail; /*!< Rx frame timestamp is available or not. */
701 enet_qos_ptp_time_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */
702 } enet_qos_rx_frame_attribute_t;
703
704 /*! @brief Defines the Rx frame data structure. */
705 typedef struct _enet_qos_rx_frame_struct
706 {
707 enet_qos_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */
708 uint16_t totLen; /*!< Rx frame total length. */
709 enet_qos_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */
710 enet_qos_rx_frame_error_t rxFrameError; /*!< Rx frame error. */
711 } enet_qos_rx_frame_struct_t;
712
713 /*! @brief Defines the ENET QOS transfer statistics structure. */
714 typedef struct _enet_qos_transfer_stats
715 {
716 uint32_t statsRxFrameCount; /*!< Rx frame number. */
717 uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */
718 uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */
719 uint32_t statsRxLengthErr; /*!< Rx frame length field doesn't equal to packet size. */
720 uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */
721 uint32_t statsTxFrameCount; /*!< Tx frame number. */
722 uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */
723 } enet_qos_transfer_stats_t;
724
725 /* Typedef for interrupt handler. */
726 typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle);
727
728 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
729 /*! @brief Pointers to enet clocks for each instance. */
730 extern const clock_ip_name_t s_enetqosClock[];
731 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
732
733 /*!
734 * @brief Set ENET system configuration.
735 * @note User needs to provide the implementation because the implementation is SoC specific.
736 * This function set the phy selection and enable clock.
737 * It should be called before any other ethernet operation.
738 *
739 * @param miiMode The MII/RGMII/RMII mode for interface between the phy and Ethernet.
740 */
741 extern void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode);
742
743 /*!
744 * @brief Enable/Disable ENET qos clock.
745 * @note User needs to provide the implementation because the implementation is SoC specific.
746 * This function should be called before config RMII mode.
747 *
748 */
749 extern void ENET_QOS_EnableClock(bool enable);
750
751 /*******************************************************************************
752 * API
753 ******************************************************************************/
754
755 #if defined(__cplusplus)
756 extern "C" {
757 #endif
758
759 /*!
760 * @name Initialization and De-initialization
761 * @{
762 */
763
764 /*!
765 * @brief Gets the ENET default configuration structure.
766 *
767 * The purpose of this API is to get the default ENET configure
768 * structure for @ref ENET_QOS_Init(). User may use the initialized
769 * structure unchanged in @ref ENET_QOS_Init(), or modify some fields of the
770 * structure before calling @ref ENET_QOS_Init().
771 * Example:
772 @code
773 enet_qos_config_t config;
774 ENET_QOS_GetDefaultConfig(&config);
775 @endcode
776 * @param config The ENET mac controller configuration structure pointer.
777 */
778 void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config);
779
780 /*!
781 * @brief Initializes the ENET module.
782 *
783 * This function initializes it with the ENET basic
784 * configuration.
785 *
786 * @param base ENET peripheral base address.
787 * @param config ENET mac configuration structure pointer.
788 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
789 * can be used directly. It is also possible to verify the Mac configuration using other methods.
790 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
791 * provided.
792 * @param macCount Count of macAddr in the ENET mac address array
793 * @param refclkSrc_Hz ENET input reference clock.
794 */
795 status_t ENET_QOS_Up(
796 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
797
798 /*!
799 * @brief Initializes the ENET module.
800 *
801 * This function ungates the module clock and initializes it with the ENET basic
802 * configuration.
803 *
804 * @param base ENET peripheral base address.
805 * @param config ENET mac configuration structure pointer.
806 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
807 * can be used directly. It is also possible to verify the Mac configuration using other methods.
808 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
809 * provided.
810 * @param macCount Count of macAddr in the ENET mac address array
811 * @param refclkSrc_Hz ENET input reference clock.
812 */
813 status_t ENET_QOS_Init(
814 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
815
816 /*!
817 * @brief Stops the ENET module.
818
819 * This function disables the ENET module.
820 *
821 * @param base ENET peripheral base address.
822 */
823 void ENET_QOS_Down(ENET_QOS_Type *base);
824
825 /*!
826 * @brief Deinitializes the ENET module.
827
828 * This function gates the module clock and disables the ENET module.
829 *
830 * @param base ENET peripheral base address.
831 */
832 void ENET_QOS_Deinit(ENET_QOS_Type *base);
833
834 /*!
835 * @brief Get the ENET instance from peripheral base address.
836 *
837 * @param base ENET peripheral base address.
838 * @return ENET instance.
839 */
840 uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base);
841
842 /*!
843 * @brief Initialize for all ENET descriptors.
844 *
845 * @note This function is do all tx/rx descriptors initialization. Because this API
846 * read all interrupt registers first and then set the interrupt flag for all descriptors,
847 * if the interrupt register is set. so the descriptor initialization should be called
848 * after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs
849 * are used).
850 *
851 * @param base ENET peripheral base address.
852 * @param config The configuration for ENET.
853 * @param bufferConfig All buffers configuration.
854 */
855 status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base,
856 enet_qos_config_t *config,
857 enet_qos_buffer_config_t *bufferConfig);
858
859 /*!
860 * @brief Allocates Rx buffers for all BDs.
861 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
862 * will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used
863 * to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken
864 * by application application should free those buffers after they're used.
865 *
866 * @note This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback
867 * function should be ready.
868 *
869 * @param base ENET_QOS peripheral base address.
870 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
871 */
872 status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
873
874 /*!
875 * @brief Frees Rx buffers in all BDs.
876 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
877 * will free left buffers in all BDs.
878 *
879 * @param base ENET_QOS peripheral base address.
880 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
881 */
882 void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
883
884 /*!
885 * @brief Starts the ENET rx/tx.
886 * This function enable the tx/rx and starts the rx/tx DMA.
887 * This shall be set after ENET initialization and before
888 * starting to receive the data.
889 *
890 * @param base ENET peripheral base address.
891 * @param rxRingNum The number of the used rx rings. It shall not be
892 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
893 * 1, the ring 0 will be used.
894 * @param txRingNum The number of the used tx rings. It shall not be
895 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
896 * 1, the ring 0 will be used.
897 *
898 * @note This must be called after all the ENET initialization.
899 * And should be called when the ENET receive/transmit is required.
900 */
901 void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
902
903 /*! @} */
904
905 /*!
906 * @name MII interface operation
907 * @{
908 */
909
910 /*!
911 * @brief Sets the ENET MII speed and duplex.
912 *
913 * This API is provided to dynamically change the speed and duplex for MAC.
914 *
915 * @param base ENET peripheral base address.
916 * @param speed The speed of the RMII mode.
917 * @param duplex The duplex of the RMII mode.
918 */
ENET_QOS_SetMII(ENET_QOS_Type * base,enet_qos_mii_speed_t speed,enet_qos_mii_duplex_t duplex)919 static inline void ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex)
920 {
921 uint32_t reg = base->MAC_CONFIGURATION & ~(ENET_QOS_MAC_CONFIGURATION_DM_MASK | ENET_QOS_MAC_CONFIGURATION_PS_MASK |
922 ENET_QOS_MAC_CONFIGURATION_FES_MASK);
923 reg |= ENET_QOS_MAC_CONFIGURATION_DM(duplex) | (uint32_t)speed;
924
925 base->MAC_CONFIGURATION = reg;
926 }
927
928 /*!
929 * @brief Sets the ENET SMI(serial management interface)- MII management interface.
930 *
931 * @param base ENET peripheral base address.
932 * @param csrClock_Hz CSR clock frequency in HZ
933 */
934 void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz);
935
936 /*!
937 * @brief Checks if the SMI is busy.
938 *
939 * @param base ENET peripheral base address.
940 * @return The status of MII Busy status.
941 */
ENET_QOS_IsSMIBusy(ENET_QOS_Type * base)942 static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)
943 {
944 return ((base->MAC_MDIO_ADDRESS & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) != 0U) ? true : false;
945 }
946
947 /*!
948 * @brief Reads data from the PHY register through SMI interface.
949 *
950 * @param base ENET peripheral base address.
951 * @return The data read from PHY
952 */
ENET_QOS_ReadSMIData(ENET_QOS_Type * base)953 static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)
954 {
955 return (uint16_t)(base->MAC_MDIO_DATA & ENET_QOS_MAC_MDIO_DATA_GD_MASK);
956 }
957
958 /*!
959 * @brief Sends the MDIO IEEE802.3 Clause 22 format write command.
960 * After send command, user needs to check whether the transmission is over
961 * with ENET_QOS_IsSMIBusy().
962 *
963 * @param base ENET peripheral base address.
964 * @param phyAddr The PHY address.
965 * @param regAddr The PHY register address.
966 * @param data The data written to PHY.
967 */
968 void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
969
970 /*!
971 * @brief Sends the MDIO IEEE802.3 Clause 22 format read command.
972 * After send command, user needs to check whether the transmission is over
973 * with ENET_QOS_IsSMIBusy().
974 *
975 * @param base ENET peripheral base address.
976 * @param phyAddr The PHY address.
977 * @param regAddr The PHY register address.
978 */
979 void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr);
980
981 /*!
982 * @brief Sends the MDIO IEEE802.3 Clause 45 format write command.
983 * After send command, user needs to check whether the transmission is over
984 * with ENET_QOS_IsSMIBusy().
985 *
986 * @param base ENET peripheral base address.
987 * @param portAddr The MDIO port address(PHY address).
988 * @param devAddr The device address.
989 * @param regAddr The PHY register address.
990 * @param data The data written to PHY.
991 */
992 void ENET_QOS_StartExtC45SMIWrite(
993 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
994
995 /*!
996 * @brief Sends the MDIO IEEE802.3 Clause 45 format read command.
997 * After send command, user needs to check whether the transmission is over
998 * with ENET_QOS_IsSMIBusy().
999 *
1000 * @param base ENET peripheral base address.
1001 * @param portAddr The MDIO port address(PHY address).
1002 * @param devAddr The device address.
1003 * @param regAddr The PHY register address.
1004 */
1005 void ENET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr);
1006
1007 /*!
1008 * @brief MDIO write with IEEE802.3 MDIO Clause 22 format.
1009 *
1010 * @param base ENET peripheral base address.
1011 * @param phyAddr The PHY address.
1012 * @param regAddr The PHY register.
1013 * @param data The data written to PHY.
1014 * @return kStatus_Success MDIO access succeeds.
1015 * @return kStatus_Timeout MDIO access timeout.
1016 */
1017 status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
1018
1019 /*!
1020 * @brief MDIO read with IEEE802.3 MDIO Clause 22 format.
1021 *
1022 * @param base ENET peripheral base address.
1023 * @param phyAddr The PHY address.
1024 * @param regAddr The PHY register.
1025 * @param pData The data read from PHY.
1026 * @return kStatus_Success MDIO access succeeds.
1027 * @return kStatus_Timeout MDIO access timeout.
1028 */
1029 status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
1030
1031 /*!
1032 * @brief MDIO write with IEEE802.3 Clause 45 format.
1033 *
1034 * @param base ENET peripheral base address.
1035 * @param portAddr The MDIO port address(PHY address).
1036 * @param devAddr The device address.
1037 * @param regAddr The PHY register address.
1038 * @param data The data written to PHY.
1039 * @return kStatus_Success MDIO access succeeds.
1040 * @return kStatus_Timeout MDIO access timeout.
1041 */
1042 status_t ENET_QOS_MDIOC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1043
1044 /*!
1045 * @brief MDIO read with IEEE802.3 Clause 45 format.
1046 *
1047 * @param base ENET peripheral base address.
1048 * @param portAddr The MDIO port address(PHY address).
1049 * @param devAddr The device address.
1050 * @param regAddr The PHY register address.
1051 * @param pData The data read from PHY.
1052 * @return kStatus_Success MDIO access succeeds.
1053 * @return kStatus_Timeout MDIO access timeout.
1054 */
1055 status_t ENET_QOS_MDIOC45Read(
1056 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
1057
1058 /*! @} */
1059
1060 /*!
1061 * @name Other basic operation
1062 * @{
1063 */
1064
1065 /*!
1066 * @brief Sets the ENET module Mac address.
1067 *
1068 * @param base ENET peripheral base address.
1069 * @param macAddr The six-byte Mac address pointer.
1070 * The pointer is allocated by application and input into the API.
1071 * @param index Configure macAddr to MAC_ADDRESS[index] register.
1072 */
ENET_QOS_SetMacAddr(ENET_QOS_Type * base,uint8_t * macAddr,uint8_t index)1073 static inline void ENET_QOS_SetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)
1074 {
1075 uint32_t lowAddress;
1076 uint32_t highAddress;
1077
1078 assert(macAddr != NULL);
1079
1080 lowAddress = ((uint32_t)macAddr[3] << 24U) | ((uint32_t)macAddr[2] << 16U) | ((uint32_t)macAddr[1] << 8U) |
1081 ((uint32_t)macAddr[0]);
1082 highAddress = ((uint32_t)macAddr[5] << 8U) | ((uint32_t)macAddr[4]);
1083 /* Set Macaddr, the MAC address registers are configured to be double-synchronized to the MII clock
1084 domains, then the synchronization is triggered only when bits 31:24 (in little-endian mode)
1085 or bits 7:0 (in Big-Endian mode) of the MAC address low register are written to.*/
1086 base->MAC_ADDRESS[index].HIGH = highAddress | ENET_QOS_HIGH_AE_MASK;
1087 base->MAC_ADDRESS[index].LOW = lowAddress;
1088 }
1089
1090 /*!
1091 * @brief Gets the ENET module Mac address.
1092 *
1093 * @param base ENET peripheral base address.
1094 * @param macAddr The six-byte Mac address pointer.
1095 * The pointer is allocated by application and input into the API.
1096 * @param index Get macAddr from MAC_ADDRESS[index] register.
1097 */
1098 void ENET_QOS_GetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index);
1099
1100 /*!
1101 * @brief Adds the ENET_QOS device to a multicast group.
1102 *
1103 * @param base ENET_QOS peripheral base address.
1104 * @param address The six-byte multicast group address which is provided by application.
1105 */
1106 void ENET_QOS_AddMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1107
1108 /*!
1109 * @brief Moves the ENET_QOS device from a multicast group.
1110 *
1111 * @param base ENET_QOS peripheral base address.
1112 * @param address The six-byte multicast group address which is provided by application.
1113 */
1114 void ENET_QOS_LeaveMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1115
1116 /*!
1117 * @brief Enable ENET device to accept all multicast frames.
1118 *
1119 * @param base ENET peripheral base address.
1120 */
ENET_QOS_AcceptAllMulticast(ENET_QOS_Type * base)1121 static inline void ENET_QOS_AcceptAllMulticast(ENET_QOS_Type *base)
1122 {
1123 uint32_t reg = base->MAC_PACKET_FILTER;
1124
1125 base->MAC_PACKET_FILTER = reg | ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1126 }
1127
1128 /*!
1129 * @brief ENET device reject to accept all multicast frames.
1130 *
1131 * @param base ENET peripheral base address.
1132 */
ENET_QOS_RejectAllMulticast(ENET_QOS_Type * base)1133 static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base)
1134 {
1135 uint32_t reg = base->MAC_PACKET_FILTER;
1136
1137 base->MAC_PACKET_FILTER = reg & ~ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1138 }
1139
1140 /*!
1141 * @brief Set the MAC to enter into power down mode.
1142 * the remote power wake up frame and magic frame can wake up
1143 * the ENET from the power down mode.
1144 *
1145 * @param base ENET peripheral base address.
1146 * @param wakeFilter The wakeFilter provided to configure the wake up frame filter.
1147 * Set the wakeFilter to NULL is not required. But if you have the filter requirement,
1148 * please make sure the wakeFilter pointer shall be eight continuous
1149 * 32-bits configuration.
1150 */
1151 void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter);
1152
1153 /*!
1154 * @brief Set the MAC to exit power down mode.
1155 * Exit from the power down mode and recover to normal work mode.
1156 *
1157 * @param base ENET peripheral base address.
1158 */
ENET_QOS_ExitPowerDown(ENET_QOS_Type * base)1159 static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base)
1160 {
1161 /* Clear and status ans reset the power down. */
1162 base->MAC_PMT_CONTROL_STATUS &= ~ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
1163
1164 /* Restore the tx which is disabled when enter power down mode. */
1165 base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1166 base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1167 base->MAC_CONFIGURATION |= ENET_QOS_MAC_CONFIGURATION_TE_MASK;
1168 }
1169
1170 /*!
1171 * @brief Enable/Disable Rx parser,please notice that for enable/disable Rx Parser,
1172 * should better disable Receive first.
1173 *
1174 * @param base ENET_QOS peripheral base address.
1175 * @param enable Enable/Disable Rx parser function
1176 * @retval kStatus_Success Configure rx parser success.
1177 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1178 */
1179 status_t ENET_QOS_EnableRxParser(ENET_QOS_Type *base, bool enable);
1180 /*! @} */
1181
1182 /*!
1183 * @name Interrupts.
1184 * @{
1185 */
1186
1187 /*!
1188 * @brief Enables the ENET DMA and MAC interrupts.
1189 *
1190 * This function enables the ENET interrupt according to the provided mask. The mask
1191 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1192 * For example, to enable the dma and mac interrupt, do the following.
1193 * @code
1194 * ENET_QOS_EnableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1195 * @endcode
1196 *
1197 * @param base ENET peripheral base address.
1198 * @param mask ENET interrupts to enable. This is a logical OR of both
1199 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1200 */
1201 void ENET_QOS_EnableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1202
1203 /*!
1204 * @brief Disables the ENET DMA and MAC interrupts.
1205 *
1206 * This function disables the ENET interrupt according to the provided mask. The mask
1207 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1208 * For example, to disable the dma and mac interrupt, do the following.
1209 * @code
1210 * ENET_QOS_DisableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1211 * @endcode
1212 *
1213 * @param base ENET peripheral base address.
1214 * @param mask ENET interrupts to disables. This is a logical OR of both
1215 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1216 */
1217 void ENET_QOS_DisableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1218
1219 /*!
1220 * @brief Gets the ENET DMA interrupt status flag.
1221 *
1222 * @param base ENET peripheral base address.
1223 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1224 * @return The event status of the interrupt source. This is the logical OR of members
1225 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1226 */
ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel)1227 static inline uint32_t ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel)
1228 {
1229 return base->DMA_CH[channel].DMA_CHX_STAT;
1230 }
1231
1232 /*!
1233 * @brief Clear the ENET DMA interrupt status flag.
1234 *
1235 * @param base ENET peripheral base address.
1236 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1237 * @param mask The interrupt status to be cleared. This is the logical OR of members
1238 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1239 */
ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel,uint32_t mask)1240 static inline void ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel, uint32_t mask)
1241 {
1242 /* Clear the dam interrupt status bit in dma channel interrupt status register. */
1243 base->DMA_CH[channel].DMA_CHX_STAT = mask;
1244 }
1245
1246 /*!
1247 * @brief Gets the ENET MAC interrupt status flag.
1248 *
1249 * @param base ENET peripheral base address.
1250 * @return The event status of the interrupt source.
1251 * Use the enum in enet_qos_mac_interrupt_enable_t and right shift
1252 * ENET_QOS_MACINT_ENUM_OFFSET to mask the returned value to get the
1253 * exact interrupt status.
1254 */
ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type * base)1255 static inline uint32_t ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type *base)
1256 {
1257 return base->MAC_INTERRUPT_STATUS;
1258 }
1259
1260 /*!
1261 * @brief Clears the ENET mac interrupt events status flag.
1262 *
1263 * This function clears enabled ENET interrupts according to the provided mask. The mask
1264 * is a logical OR of enumeration members. See the @ref enet_qos_mac_interrupt_enable_t.
1265 * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
1266 * @code
1267 * ENET_QOS_ClearMacInterruptStatus(ENET, kENET_QOS_MacPmt);
1268 * @endcode
1269 *
1270 * @param base ENET peripheral base address.
1271 * @param mask ENET interrupt source to be cleared.
1272 * This is the logical OR of members of the enumeration :: enet_qos_mac_interrupt_enable_t.
1273 */
1274 void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask);
1275
1276 /*! @} */
1277
1278 /*!
1279 * @name Functional operation.
1280 * @{
1281 */
1282
1283 /*!
1284 * @brief Get the tx descriptor DMA Own flag.
1285 *
1286 * @param txDesc The given tx descriptor.
1287 * @retval True the dma own tx descriptor, false application own tx descriptor.
1288 *
1289 */
ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t * txDesc)1290 static inline bool ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t *txDesc)
1291 {
1292 return ((txDesc->controlStat & ENET_QOS_TXDESCRIP_RD_OWN_MASK) != 0U) ? true : false;
1293 }
1294
1295 /*!
1296 * @brief Setup a given tx descriptor.
1297 * This function is a low level functional API to setup or prepare
1298 * a given tx descriptor.
1299 *
1300 * @param txDesc The given tx descriptor.
1301 * @param buffer1 The first buffer address in the descriptor.
1302 * @param bytes1 The bytes in the fist buffer.
1303 * @param buffer2 The second buffer address in the descriptor.
1304 * @param bytes2 The bytes in the second buffer.
1305 * @param framelen The length of the frame to be transmitted.
1306 * @param intEnable Interrupt enable flag.
1307 * @param tsEnable The timestamp enable.
1308 * @param flag The flag of this tx descriptor, @ref enet_qos_desc_flag .
1309 * @param slotNum The slot num used for AV only.
1310 *
1311 * @note This must be called after all the ENET initialization.
1312 * And should be called when the ENET receive/transmit is required.
1313 * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
1314 * memory until the packet has been fully transmitted. The buffers
1315 * should be free or requeued in the transmit interrupt irq handler.
1316 */
1317 void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc,
1318 void *buffer1,
1319 uint32_t bytes1,
1320 void *buffer2,
1321 uint32_t bytes2,
1322 uint32_t framelen,
1323 bool intEnable,
1324 bool tsEnable,
1325 enet_qos_desc_flag flag,
1326 uint8_t slotNum);
1327
1328 /*!
1329 * @brief Update the tx descriptor tail pointer.
1330 * This function is a low level functional API to update the
1331 * the tx descriptor tail.
1332 * This is called after you setup a new tx descriptor to update
1333 * the tail pointer to make the new descriptor accessible by DMA.
1334 *
1335 * @param base ENET peripheral base address.
1336 * @param channel The tx DMA channel.
1337 * @param txDescTailAddrAlign The new tx tail pointer address.
1338 *
1339 */
ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t txDescTailAddrAlign)1340 static inline void ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
1341 {
1342 base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1343 }
1344
1345 /*!
1346 * @brief Update the rx descriptor tail pointer.
1347 * This function is a low level functional API to update the
1348 * the rx descriptor tail.
1349 * This is called after you setup a new rx descriptor to update
1350 * the tail pointer to make the new descriptor accessible by DMA
1351 * and to anouse the rx poll command for DMA.
1352 *
1353 * @param base ENET peripheral base address.
1354 * @param channel The rx DMA channel.
1355 * @param rxDescTailAddrAlign The new rx tail pointer address.
1356 *
1357 */
ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t rxDescTailAddrAlign)1358 static inline void ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
1359 {
1360 base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1361 }
1362
1363 /*!
1364 * @brief Gets the context in the ENET rx descriptor.
1365 * This function is a low level functional API to get the
1366 * the status flag from a given rx descriptor.
1367 *
1368 * @param rxDesc The given rx descriptor.
1369 * @retval The RDES3 regions for write-back format rx buffer descriptor.
1370 *
1371 * @note This must be called after all the ENET initialization.
1372 * And should be called when the ENET receive/transmit is required.
1373 */
ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t * rxDesc)1374 static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc)
1375 {
1376 assert(rxDesc != NULL);
1377
1378 return rxDesc->control;
1379 }
1380 /*!
1381 * @brief Updates the buffers and the own status for a given rx descriptor.
1382 * This function is a low level functional API to Updates the
1383 * buffers and the own status for a given rx descriptor.
1384 *
1385 * @param rxDesc The given rx descriptor.
1386 * @param buffer1 The first buffer address in the descriptor.
1387 * @param buffer2 The second buffer address in the descriptor.
1388 * @param intEnable Interrupt enable flag.
1389 * @param doubleBuffEnable The double buffer enable flag.
1390 *
1391 * @note This must be called after all the ENET initialization.
1392 * And should be called when the ENET receive/transmit is required.
1393 */
1394 void ENET_QOS_UpdateRxDescriptor(
1395 enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
1396
1397 /*!
1398 * @brief Configure flexible rx parser.
1399 *
1400 * This function is used to configure the flexible rx parser table.
1401 *
1402 * @param base ENET peripheral base address..
1403 * @param rxpConfig The rx parser configuration pointer.
1404 * @param entryCount The rx parser entry count.
1405 * @retval kStatus_Success Configure rx parser success.
1406 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1407 */
1408 status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount);
1409
1410 /*!
1411 * @brief Read flexible rx parser configuration at specified index.
1412 *
1413 * This function is used to read flexible rx parser configuration at specified index.
1414 *
1415 * @param base ENET peripheral base address..
1416 * @param rxpConfig The rx parser configuration pointer.
1417 * @param entryIndex The rx parser entry index to read, start from 0.
1418 * @retval kStatus_Success Configure rx parser success.
1419 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1420 */
1421 status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryIndex);
1422
1423 /*!
1424 * @brief Program Gate Control List.
1425 *
1426 * This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
1427 *
1428 * @param base ENET peripheral base address..
1429 * @param gcl Pointer to the Gate Control List structure.
1430 * @param ptpClk_Hz frequency of the PTP clock.
1431 */
1432 status_t ENET_QOS_EstProgramGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t ptpClk_Hz);
1433
1434 /*!
1435 * @brief Read Gate Control List.
1436 *
1437 * This function is used to read the Enhanced Scheduled Transmisson list. (IEEE802.1Qbv)
1438 *
1439 * @param base ENET peripheral base address..
1440 * @param gcl Pointer to the Gate Control List structure.
1441 * @param listLen length of the provided opList array in gcl structure.
1442 * @param hwList Boolean if True read HW list, false read SW list.
1443 */
1444 status_t ENET_QOS_EstReadGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t listLen, bool hwList);
1445
1446 /*!
1447 * @brief Enable Frame Preemption.
1448 *
1449 * This function is used to enable frame preemption. (IEEE802.1Qbu)
1450 *
1451 * @param base ENET peripheral base address..
1452 */
ENET_QOS_FpeEnable(ENET_QOS_Type * base)1453 static inline void ENET_QOS_FpeEnable(ENET_QOS_Type *base)
1454 {
1455 base->MAC_FPE_CTRL_STS |= ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1456 }
1457
1458 /*!
1459 * @brief Disable Frame Preemption.
1460 *
1461 * This function is used to disable frame preemption. (IEEE802.1Qbu)
1462 *
1463 * @param base ENET peripheral base address..
1464 */
ENET_QOS_FpeDisable(ENET_QOS_Type * base)1465 static inline void ENET_QOS_FpeDisable(ENET_QOS_Type *base)
1466 {
1467 base->MAC_FPE_CTRL_STS &= ~ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1468 }
1469
1470 /*!
1471 * @brief Configure preemptable transmit queues.
1472 *
1473 * This function is used to configure the preemptable queues. (IEEE802.1Qbu)
1474 *
1475 * @param base ENET peripheral base address..
1476 * @param queueMask bitmask representing queues to set in preemptable mode.
1477 * The N-th bit represents the queue N.
1478 */
ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type * base,uint8_t queueMask)1479 static inline void ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type *base, uint8_t queueMask)
1480 {
1481 uint32_t control;
1482
1483 control = base->MTL_FPE_CTRL_STS & ~ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK;
1484 control |= ENET_QOS_MTL_FPE_CTRL_STS_PEC(queueMask);
1485 base->MTL_FPE_CTRL_STS = control;
1486 }
1487
1488 /*!
1489 * @brief Sets the ENET AVB feature.
1490 *
1491 * ENET_QOS AVB feature configuration, set transmit bandwidth.
1492 * This API is called when the AVB feature is required.
1493 *
1494 * @param base ENET_QOS peripheral base address.
1495 * @param config The ENET_QOS AVB feature configuration structure.
1496 * @param queueIndex ENET_QOS queue index.
1497 */
1498 void ENET_QOS_AVBConfigure(ENET_QOS_Type *base, const enet_qos_cbs_config_t *config, uint8_t queueIndex);
1499
1500 /*!
1501 * @brief Gets statistical data in transfer.
1502 *
1503 * @param base ENET_QOS peripheral base address.
1504 * @param statistics The statistics structure pointer.
1505 */
1506 void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *statistics);
1507
1508 /*! @} */
1509
1510 /*!
1511 * @name Transactional operation
1512 * @{
1513 */
1514
1515 /*!
1516 * @brief Create ENET Handler
1517 *
1518 * This is a transactional API and it's provided to store all data which are needed
1519 * during the whole transactional process. This API should not be used when you use
1520 * functional APIs to do data tx/rx. This is function will store many data/flag for
1521 * transactional use, so all configure API such as ENET_QOS_Init(), ENET_QOS_DescriptorInit(),
1522 * ENET_QOS_EnableInterrupts() etc.
1523 *
1524 * @note as our transactional transmit API use the zero-copy transmit buffer.
1525 * so there are two thing we emphasize here:
1526 * 1. tx buffer free/requeue for application should be done in the tx
1527 * interrupt handler. Please set callback: kENET_QOS_TxIntEvent with tx buffer free/requeue
1528 * process APIs.
1529 * 2. the tx interrupt is forced to open.
1530 *
1531 * @param base ENET peripheral base address.
1532 * @param handle ENET handler.
1533 * @param config ENET configuration.
1534 * @param bufferConfig ENET buffer configuration.
1535 * @param callback The callback function.
1536 * @param userData The application data.
1537 */
1538 void ENET_QOS_CreateHandler(ENET_QOS_Type *base,
1539 enet_qos_handle_t *handle,
1540 enet_qos_config_t *config,
1541 enet_qos_buffer_config_t *bufferConfig,
1542 enet_qos_callback_t callback,
1543 void *userData);
1544
1545 /*!
1546 * @brief Gets the size of the read frame.
1547 * This function gets a received frame size from the ENET buffer descriptors.
1548 * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
1549 * After calling @ref ENET_QOS_GetRxFrameSize, @ref ENET_QOS_ReadFrame() should be called to update the
1550 * receive buffers If the result is not "kStatus_ENET_QOS_RxFrameEmpty".
1551 *
1552 * @param base ENET peripheral base address.
1553 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1554 * @param length The length of the valid frame received.
1555 * @param channel The DMAC channel for the rx.
1556 * @retval kStatus_ENET_QOS_RxFrameEmpty No frame received. Should not call ENET_QOS_ReadFrame to read frame.
1557 * @retval kStatus_ENET_QOS_RxFrameError Data error happens. @ref ENET_QOS_ReadFrame should be called with NULL data
1558 * and NULL length to update the receive buffers.
1559 * @retval kStatus_Success Receive a frame Successfully then the @ref ENET_QOS_ReadFrame
1560 * should be called with the right data buffer and the captured data length input.
1561 */
1562 status_t ENET_QOS_GetRxFrameSize(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint32_t *length, uint8_t channel);
1563
1564 /*!
1565 * @brief Reads a frame from the ENET device.
1566 * This function reads a frame from the ENET DMA descriptors.
1567 * The ENET_QOS_GetRxFrameSize should be used to get the size of the prepared data buffer.
1568 * For example use rx dma channel 0:
1569 * @code
1570 * uint32_t length;
1571 * enet_qos_handle_t g_handle;
1572 * status = ENET_QOS_GetRxFrameSize(&g_handle, &length, 0);
1573 * if (length != 0)
1574 * {
1575 * uint8_t *data = memory allocate interface;
1576 * if (!data)
1577 * {
1578 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1579 * }
1580 * else
1581 * {
1582 * status = ENET_QOS_ReadFrame(ENET, &g_handle, data, length, 0);
1583 * }
1584 * }
1585 * else if (status == kStatus_ENET_QOS_RxFrameError)
1586 * {
1587 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1588 * }
1589 * @endcode
1590 * @param base ENET peripheral base address.
1591 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1592 * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
1593 * @param length The size of the data buffer which is still the length of the received frame.
1594 * @param channel The rx DMA channel. shall not be larger than 2.
1595 * @param ts Pointer to the structure @ref enet_qos_ptp_time_t to save frame timestamp.
1596 * @return The execute status, successful or failure.
1597 */
1598 status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
1599 enet_qos_handle_t *handle,
1600 uint8_t *data,
1601 uint32_t length,
1602 uint8_t channel,
1603 enet_qos_ptp_time_t *ts);
1604
1605 /*!
1606 * @brief Transmits an ENET frame.
1607 * @note The CRC is automatically appended to the data. Input the data
1608 * to send without the CRC.
1609 *
1610 * @param base ENET peripheral base address.
1611 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1612 * @param data The data buffer provided by user to be send.
1613 * @param length The length of the data to be send.
1614 * @param channel Channel to send the frame, same with queue index.
1615 * @param isNeedTs True to enable timestamp save for the frame
1616 * @param context pointer to user context to be kept in the tx dirty frame information.
1617 * @param txOffloadOps The Tx frame checksum offload option.
1618 * @retval kStatus_Success Send frame succeed.
1619 * @retval kStatus_ENET_QOS_TxFrameBusy Transmit buffer descriptor is busy under transmission.
1620 * The transmit busy happens when the data send rate is over the MAC capacity.
1621 * The waiting mechanism is recommended to be added after each call return with
1622 * kStatus_ENET_QOS_TxFrameBusy.
1623 */
1624 status_t ENET_QOS_SendFrame(ENET_QOS_Type *base,
1625 enet_qos_handle_t *handle,
1626 uint8_t *data,
1627 uint32_t length,
1628 uint8_t channel,
1629 bool isNeedTs,
1630 void *context,
1631 enet_qos_tx_offload_t txOffloadOps);
1632
1633 /*!
1634 * @brief Reclaim tx descriptors.
1635 * This function is used to update the tx descriptor status and
1636 * store the tx timestamp when the 1588 feature is enabled.
1637 * This is called by the transmit interrupt IRQ handler after the
1638 * complete of a frame transmission.
1639 *
1640 * @param base ENET peripheral base address.
1641 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1642 * @param channel The tx DMA channel.
1643 *
1644 */
1645 void ENET_QOS_ReclaimTxDescriptor(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t channel);
1646
1647 /*!
1648 * @brief The ENET IRQ handler.
1649 *
1650 * @param base ENET peripheral base address.
1651 * @param handle The ENET handler pointer.
1652 */
1653 void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle);
1654
1655 /*!
1656 * @brief Set the second level IRQ handler, allow user to overwrite the default
1657 * second level weak IRQ handler.
1658 *
1659 * @param base ENET peripheral base address.
1660 * @param ISRHandler The handler to install.
1661 */
1662 void ENET_QOS_SetISRHandler(ENET_QOS_Type *base, enet_qos_isr_t ISRHandler);
1663
1664 /*! @} */
1665 /*!
1666 * @name ENET Enhanced function operation
1667 * @{
1668 */
1669
1670 /*!
1671 * @brief Correct the ENET PTP 1588 timer in coarse method.
1672 *
1673 * @param base ENET peripheral base address.
1674 * @param operation The system time operation, refer to "enet_qos_systime_op"
1675 * @param second The correction second.
1676 * @param nanosecond The correction nanosecond.
1677 */
1678 status_t ENET_QOS_Ptp1588CorrectTimerInCoarse(ENET_QOS_Type *base,
1679 enet_qos_systime_op operation,
1680 uint32_t second,
1681 uint32_t nanosecond);
1682
1683 /*!
1684 * @brief Correct the ENET PTP 1588 timer in fine method.
1685 *
1686 *
1687 * @param base ENET peripheral base address.
1688 * @param addend The addend value to be set in the fine method
1689 * @note Should take refer to the chapter "System time correction" and
1690 * see the description for the "fine correction method".
1691 */
1692 status_t ENET_QOS_Ptp1588CorrectTimerInFine(ENET_QOS_Type *base, uint32_t addend);
1693
1694 /*!
1695 * @brief Get the ENET Time stamp current addend value.
1696 *
1697 * @param base ENET peripheral base address.
1698 * @return The addend value.
1699 */
ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type * base)1700 static inline uint32_t ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type *base)
1701 {
1702 return base->MAC_TIMESTAMP_ADDEND;
1703 }
1704
1705 /*!
1706 * @brief Gets the current ENET time from the PTP 1588 timer without IRQ disable.
1707 *
1708 * @param base ENET peripheral base address.
1709 * @param second The PTP 1588 system timer second.
1710 * @param nanosecond The PTP 1588 system timer nanosecond.
1711 * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
1712 */
1713 void ENET_QOS_Ptp1588GetTimerNoIRQDisable(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1714
1715 /*!
1716 * @brief Sets the ENET PTP 1588 PPS control.
1717 * All channels operate in flexible PPS output mode.
1718 *
1719 * @param base ENET peripheral base address.
1720 * @param instance The ENET QOS PTP PPS instance.
1721 * @param trgtMode The target time register mode.
1722 * @param cmd The target flexible PPS output control command.
1723 */
ENET_Ptp1588PpsControl(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,enet_qos_ptp_pps_trgt_mode_t trgtMode,enet_qos_ptp_pps_cmd_t cmd)1724 static inline status_t ENET_Ptp1588PpsControl(ENET_QOS_Type *base,
1725 enet_qos_ptp_pps_instance_t instance,
1726 enet_qos_ptp_pps_trgt_mode_t trgtMode,
1727 enet_qos_ptp_pps_cmd_t cmd)
1728 {
1729 uint32_t reg = 0UL;
1730 uint8_t shift = (uint8_t)instance * 8U;
1731 uint32_t pps_config = ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0((uint32_t)trgtMode) |
1732 ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD((uint32_t)cmd);
1733
1734 reg = base->MAC_PPS_CONTROL;
1735
1736 /* Make sure CMD field is all zero */
1737 if ((reg & (0xFUL << shift)) != 0UL)
1738 {
1739 return kStatus_ENET_QOS_PpsBusy;
1740 }
1741
1742 reg &= ~(0xFFUL << shift);
1743 reg |= (pps_config << shift) | ENET_QOS_MAC_PPS_CONTROL_PPSEN0(1U);
1744
1745 base->MAC_PPS_CONTROL = reg;
1746
1747 return kStatus_Success;
1748 }
1749
1750 /*!
1751 * @brief Sets the ENET OQS PTP 1588 PPS target time registers.
1752 *
1753 * @param base ENET QOS peripheral base address.
1754 * @param instance The ENET QOS PTP PPS instance.
1755 * @param seconds The target seconds.
1756 * @param nanoseconds The target nanoseconds.
1757 */
1758 status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base,
1759 enet_qos_ptp_pps_instance_t instance,
1760 uint32_t seconds,
1761 uint32_t nanoseconds);
1762
1763 /*!
1764 * @brief Sets the ENET OQS PTP 1588 PPS output signal interval
1765 *
1766 * @param base ENET QOS peripheral base address.
1767 * @param instance The ENET QOS PTP PPS instance.
1768 * @param width Signal Width. It is stored in terms of number of
1769 * units of sub-second increment value. The width value must be
1770 * lesser than interval value.
1771 */
ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t width)1772 static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base,
1773 enet_qos_ptp_pps_instance_t instance,
1774 uint32_t width)
1775 {
1776 uint32_t *mac_pps_width;
1777
1778 mac_pps_width = (uint32_t *)((uintptr_t)&base->MAC_PPS0_WIDTH + 0x10U * (uint32_t)instance);
1779
1780 *mac_pps_width = ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(width);
1781 }
1782
1783 /*!
1784 * @brief Sets the ENET OQS PTP 1588 PPS output signal width
1785 *
1786 * @param base ENET QOS peripheral base address.
1787 * @param instance The ENET QOS PTP PPS instance.
1788 * @param interval Signal Interval. It is stored in terms of number of
1789 * units of sub-second increment value.
1790 */
ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t interval)1791 static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base,
1792 enet_qos_ptp_pps_instance_t instance,
1793 uint32_t interval)
1794 {
1795 uint32_t *mac_pps_interval;
1796
1797 mac_pps_interval = (uint32_t *)((uintptr_t)&base->MAC_PPS0_INTERVAL + 0x10U * (uint32_t)instance);
1798
1799 *mac_pps_interval = ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(interval);
1800 }
1801
1802 /*!
1803 * @brief Gets the current ENET time from the PTP 1588 timer.
1804 *
1805 * @param base ENET peripheral base address.
1806 * @param second The PTP 1588 system timer second.
1807 * @param nanosecond The PTP 1588 system timer nanosecond.
1808 * For the unit of the nanosecond is 1ns.so the nanosecond is the real nanosecond.
1809 */
1810 void ENET_QOS_Ptp1588GetTimer(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1811
1812 /*!
1813 * @brief Gets the time stamp of the transmit frame.
1814 *
1815 * This function is used for PTP stack to get the timestamp captured by the ENET driver.
1816 *
1817 * @param handle The ENET handler pointer.This is the same state pointer used in
1818 * ENET_QOS_Init.
1819 * @param txFrame Input parameter, pointer to @ref enet_qos_frame_info_t for saving read out frame information.
1820 * @param channel Channel for searching the tx frame.
1821 */
1822 void ENET_QOS_GetTxFrame(enet_qos_handle_t *handle, enet_qos_frame_info_t *txFrame, uint8_t channel);
1823
1824 /*!
1825 * @brief Receives one frame in specified BD ring with zero copy.
1826 *
1827 * This function will use the user-defined allocate and free callback. Every time application gets one frame through
1828 * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
1829 * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
1830 * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
1831 * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
1832 * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
1833 * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
1834 * to specific design in this case.
1835 *
1836 * @param base ENET peripheral base address.
1837 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
1838 * @param rxFrame The received frame information structure provided by user.
1839 * @param channel Channel for searching the rx frame.
1840 * @retval kStatus_Success Succeed to get one frame and allocate new memory for Rx buffer.
1841 * @retval kStatus_ENET_QOS_RxFrameEmpty There's no Rx frame in the BD.
1842 * @retval kStatus_ENET_QOS_RxFrameError There's issue in this receiving.
1843 * @retval kStatus_ENET_QOS_RxFrameDrop There's no new buffer memory for BD, drop this frame.
1844 */
1845 status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
1846 enet_qos_handle_t *handle,
1847 enet_qos_rx_frame_struct_t *rxFrame,
1848 uint8_t channel);
1849
1850 /*! @} */
1851
1852 #if defined(__cplusplus)
1853 }
1854 #endif
1855
1856 /*! @}*/
1857
1858 #endif /* FSL_ENET_QOS_H_ */
1859
