1 /*
2 * Copyright 2020-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef FSL_ENET_QOS_H_
7 #define FSL_ENET_QOS_H_
8
9 #include "fsl_common.h"
10 #if defined(FSL_ETH_ENABLE_CACHE_CONTROL)
11 #include "fsl_cache.h"
12 #endif
13 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
14 #include "fsl_memory.h"
15 #endif
16
17 #if !defined(ENET_QOS)
18 /* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */
19 #if defined(ENET_QOS_TSN)
20 #define ENET_QOS ENET_QOS_TSN
21 #endif
22 #endif
23 /*!
24 * @addtogroup enet_qos_qos
25 * @{
26 */
27
28 /*******************************************************************************
29 * Definitions
30 ******************************************************************************/
31
32 /*! @name Driver version */
33 /*! @{ */
34 /*! @brief Defines the driver version. */
35 #define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 4))
36 /*! @} */
37
38 /*! @name Control and status region bit masks of the receive buffer descriptor. */
39 /*! @{ */
40 /*! @brief Defines for read format. */
41 #define ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK (1UL << 24U) /*!< Buffer1 address valid. */
42 #define ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK (1UL << 25U) /*!< Buffer2 address valid. */
43 #define ENET_QOS_RXDESCRIP_RD_IOC_MASK (1UL << 30U) /*!< Interrupt enable on complete. */
44 #define ENET_QOS_RXDESCRIP_RD_OWN_MASK (1UL << 31U) /*!< Own bit. */
45
46 /*! @brief Defines for write back format. */
47 #define ENET_QOS_RXDESCRIP_WR_ERR_MASK ((1UL << 3U) | (1UL << 7U))
48 #define ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK (0x7UL)
49 #define ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00UL)
50 #define ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK (1UL << 12U)
51 #define ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK (1UL << 13U)
52 #define ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK (1UL << 14U)
53 #define ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFUL)
54 #define ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK (1UL << 15U)
55 #define ENET_QOS_RXDESCRIP_WR_TYPE_MASK (0x30000UL)
56 #define ENET_QOS_RXDESCRIP_WR_DE_MASK (1UL << 19U)
57 #define ENET_QOS_RXDESCRIP_WR_RE_MASK (1UL << 20U)
58 #define ENET_QOS_RXDESCRIP_WR_OE_MASK (1UL << 21U)
59 #define ENET_QOS_RXDESCRIP_WR_RWT_MASK (1UL << 22U)
60 #define ENET_QOS_RXDESCRIP_WR_GP_MASK (1UL << 22U)
61 #define ENET_QOS_RXDESCRIP_WR_CRC_MASK (1UL << 23U)
62 #define ENET_QOS_RXDESCRIP_WR_RS0V_MASK (1UL << 25U)
63 #define ENET_QOS_RXDESCRIP_WR_RS1V_MASK (1UL << 26U)
64 #define ENET_QOS_RXDESCRIP_WR_RS2V_MASK (1UL << 27U)
65 #define ENET_QOS_RXDESCRIP_WR_LD_MASK (1UL << 28U)
66 #define ENET_QOS_RXDESCRIP_WR_FD_MASK (1UL << 29U)
67 #define ENET_QOS_RXDESCRIP_WR_CTXT_MASK (1UL << 30U)
68 #define ENET_QOS_RXDESCRIP_WR_OWN_MASK (1UL << 31U)
69
70 #define ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK (1UL << 16U)
71 #define ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK (1UL << 17U)
72 /*! @} */
73
74 /*! @name Control and status bit masks of the transmit buffer descriptor. */
75 /*! @{ */
76 /*! @brief Defines for read format. */
77 #define ENET_QOS_TXDESCRIP_RD_BL1_MASK (0x3fffUL)
78 #define ENET_QOS_TXDESCRIP_RD_BL2_MASK (ENET_QOS_TXDESCRIP_RD_BL1_MASK << 16U)
79 #define ENET_QOS_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_BL1_MASK)
80 #define ENET_QOS_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_BL1_MASK) << 16)
81 #define ENET_QOS_TXDESCRIP_RD_TTSE_MASK (1UL << 30UL)
82 #define ENET_QOS_TXDESCRIP_RD_IOC_MASK (1UL << 31UL)
83
84 #define ENET_QOS_TXDESCRIP_RD_FL_MASK (0x7FFFUL)
85 #define ENET_QOS_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_FL_MASK)
86 #define ENET_QOS_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3U) << 16U)
87 #define ENET_QOS_TXDESCRIP_RD_TSE_MASK (1UL << 18U)
88 #define ENET_QOS_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0fU) << 19U)
89 #define ENET_QOS_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07U) << 23U)
90 #define ENET_QOS_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03U) << 26U)
91 #define ENET_QOS_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03U) << 28U)
92 #define ENET_QOS_TXDESCRIP_RD_LD_MASK (1UL << 28U)
93 #define ENET_QOS_TXDESCRIP_RD_FD_MASK (1UL << 29U)
94 #define ENET_QOS_TXDESCRIP_RD_CTXT_MASK (1UL << 30U)
95 #define ENET_QOS_TXDESCRIP_RD_OWN_MASK (1UL << 31U)
96
97 /*! @brief Defines for write back format. */
98 #define ENET_QOS_TXDESCRIP_WB_TTSS_MASK (1UL << 17U)
99 /*! @} */
100
101 /*! @name Bit mask for interrupt enable type. */
102 /*! @{ */
103 #define ENET_QOS_ABNORM_INT_MASK \
104 (ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK | ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RSE_MASK | \
105 ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK | ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK | ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
106 #define ENET_QOS_NORM_INT_MASK \
107 (ENET_QOS_DMA_CHX_INT_EN_TIE_MASK | ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RIE_MASK | \
108 ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
109 /*! @} */
110
111 /*! @name Defines some Ethernet parameters. */
112 /*! @{ */
113 #ifndef ENET_QOS_RING_NUM_MAX
114 #define ENET_QOS_RING_NUM_MAX (5U) /*!< The Maximum number of tx/rx descriptor rings. */
115 #endif
116 #define ENET_QOS_FRAME_MAX_FRAMELEN (1518U) /*!< Default maximum Ethernet frame size. */
117 #define ENET_QOS_FCS_LEN (4U) /*!< Ethernet FCS length. */
118 #define ENET_QOS_ADDR_ALIGNMENT (0x3U) /*!< Recommended Ethernet buffer alignment. */
119 #define ENET_QOS_BUFF_ALIGNMENT (8U) /*!< Receive buffer alignment shall be 4bytes-aligned. */
120 #define ENET_QOS_MTL_RXFIFOSIZE (8192U) /*!< The rx fifo size. */
121 #define ENET_QOS_MTL_TXFIFOSIZE (8192U) /*!< The tx fifo size. */
122 #define ENET_QOS_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */
123 #define ENET_QOS_RXP_ENTRY_COUNT (256U) /*!< RXP table entry count, implied by FRPES in MAC_HW_FEATURE3 */
124 #define ENET_QOS_RXP_BUFFER_SIZE (256U) /*!< RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3 */
125 #define ENET_QOS_EST_WID (24U) /*!< Width of the time interval in Gate Control List */
126 #define ENET_QOS_EST_DEP (512U) /*!< Maxmimum depth of Gate Control List */
127 /*! @} */
128
129 /*! @brief Defines the status return codes for transaction. */
130 enum
131 {
132 kStatus_ENET_QOS_InitMemoryFail =
133 MAKE_STATUS(kStatusGroup_ENET_QOS, 0U), /*!< Init fails since buffer memory is not enough. */
134 kStatus_ENET_QOS_RxFrameError =
135 MAKE_STATUS(kStatusGroup_ENET_QOS, 1U), /*!< A frame received but data error happen. */
136 kStatus_ENET_QOS_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 2U), /*!< Failed to receive a frame. */
137 kStatus_ENET_QOS_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET_QOS, 3U), /*!< No frame arrive. */
138 kStatus_ENET_QOS_RxFrameDrop =
139 MAKE_STATUS(kStatusGroup_ENET_QOS, 4U), /*!< Rx frame is dropped since no buffer memory. */
140 kStatus_ENET_QOS_TxFrameBusy =
141 MAKE_STATUS(kStatusGroup_ENET_QOS, 5U), /*!< Transmit descriptors are under process. */
142 kStatus_ENET_QOS_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 6U), /*!< Transmit frame fail. */
143 kStatus_ENET_QOS_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET_QOS, 7U), /*!< Transmit oversize. */
144 kStatus_ENET_QOS_Est_SwListBusy =
145 MAKE_STATUS(kStatusGroup_ENET_QOS, 8U), /*!< SW Gcl List not yet processed by HW. */
146 kStatus_ENET_QOS_Est_SwListWriteAbort = MAKE_STATUS(kStatusGroup_ENET_QOS, 9U), /*!< SW Gcl List write aborted .*/
147 kStatus_ENET_QOS_Est_InvalidParameter =
148 MAKE_STATUS(kStatusGroup_ENET_QOS, 10U), /*!< Invalid parameter in Gcl List .*/
149 kStatus_ENET_QOS_Est_BtrError = MAKE_STATUS(kStatusGroup_ENET_QOS, 11U), /*!< Base Time Error when loading list.*/
150 kStatus_ENET_QOS_TrgtBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 12U), /*!< Target time register busy.*/
151 kStatus_ENET_QOS_Timeout = MAKE_STATUS(kStatusGroup_ENET_QOS, 13U), /*!< Target time register busy.*/
152 kStatus_ENET_QOS_PpsBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 14U) /*!< Pps command busy.*/
153 };
154
155 /*! @brief Defines the MII/RGMII mode for data interface between the MAC and the PHY. */
156 typedef enum _enet_qos_mii_mode
157 {
158 kENET_QOS_MiiMode = 0U, /*!< MII mode for data interface. */
159 kENET_QOS_RgmiiMode = 1U, /*!< RGMII mode for data interface. */
160 kENET_QOS_RmiiMode = 4U /*!< RMII mode for data interface. */
161 } enet_qos_mii_mode_t;
162
163 /*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. */
164 typedef enum _enet_qos_mii_speed
165 {
166 kENET_QOS_MiiSpeed10M =
167 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 10 Mbps. */
168 kENET_QOS_MiiSpeed100M =
169 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(1U), /*!< Speed 100 Mbps. */
170 kENET_QOS_MiiSpeed1000M =
171 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 1000 Mbps. */
172 kENET_QOS_MiiSpeed2500M =
173 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(1U) /*!< Speed 2500 Mbps. */
174 } enet_qos_mii_speed_t;
175
176 /*! @brief Defines the half or full duplex for the MII data interface. */
177 typedef enum _enet_qos_mii_duplex
178 {
179 kENET_QOS_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
180 kENET_QOS_MiiFullDuplex /*!< Full duplex mode. */
181 } enet_qos_mii_duplex_t;
182
183 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
184 typedef enum _enet_qos_mii_normal_opcode
185 {
186 kENET_QOS_MiiWriteFrame =
187 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(0U) |
188 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U), /*!< Write frame operation for a valid MII management frame. */
189 kENET_QOS_MiiReadFrame =
190 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(1U) |
191 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U) /*!< Read frame operation for a valid MII management frame. */
192 } enet_qos_mii_normal_opcode;
193
194 /*! @brief Define the DMA maximum transmit burst length. */
195 typedef enum _enet_qos_dma_burstlen
196 {
197 kENET_QOS_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */
198 kENET_QOS_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */
199 kENET_QOS_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */
200 kENET_QOS_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */
201 kENET_QOS_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */
202 kENET_QOS_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */
203 kENET_QOS_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */
204 kENET_QOS_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
205 kENET_QOS_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
206 } enet_qos_dma_burstlen;
207
208 /*! @brief Define the flag for the descriptor. */
209 typedef enum _enet_qos_desc_flag
210 {
211 kENET_QOS_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
212 kENET_QOS_LastFlagOnly, /*!< It's the last descriptor of the frame. */
213 kENET_QOS_FirstFlagOnly, /*!< It's the first descriptor of the frame. */
214 kENET_QOS_FirstLastFlag /*!< It's the first and last descriptor of the frame. */
215 } enet_qos_desc_flag;
216
217 /*! @brief Define the system time adjust operation control. */
218 typedef enum _enet_qos_systime_op
219 {
220 kENET_QOS_SystimeAdd = 0U, /*!< System time add to. */
221 kENET_QOS_SystimeSubtract = 1U /*!< System time subtract. */
222 } enet_qos_systime_op;
223
224 /*! @brief Define the system time rollover control. */
225 typedef enum _enet_qos_ts_rollover_type
226 {
227 kENET_QOS_BinaryRollover = 0, /*!< System time binary rollover.*/
228 kENET_QOS_DigitalRollover = 1 /*!< System time digital rollover.*/
229 } enet_qos_ts_rollover_type;
230
231 /*! @brief Defines some special configuration for ENET.
232 *
233 * These control flags are provided for special user requirements.
234 * Normally, these is no need to set this control flags for ENET initialization.
235 * But if you have some special requirements, set the flags to specialControl
236 * in the enet_qos_config_t.
237 * @note "kENET_QOS_StoreAndForward" is recommended to be set.
238 */
239 typedef enum _enet_qos_special_config
240 {
241 /***********************DMA CONFIG**********************************************/
242 kENET_QOS_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
243 /**************************MTL************************************/
244 kENET_QOS_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
245 /***********************MAC****************************************/
246 kENET_QOS_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
247 kENET_QOS_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
248 kENET_QOS_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
249 kENET_QOS_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
250 kENET_QOS_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */
251 kENET_QOS_HashMulticastEnable = 0x0080U, /*!< The multicast packets are filtered through hash table. */
252 kENET_QOS_RxChecksumOffloadEnable = 0x0100U, /*!< The Rx checksum offload enabled. */
253 } enet_qos_special_config_t;
254
255 /*! @brief List of DMA interrupts supported by the ENET interrupt. This
256 * enumeration uses one-bot encoding to allow a logical OR of multiple
257 * members.
258 */
259 typedef enum _enet_qos_dma_interrupt_enable
260 {
261 kENET_QOS_DmaTx = ENET_QOS_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */
262 kENET_QOS_DmaTxStop = ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK, /*!< Tx stop interrupt. */
263 kENET_QOS_DmaTxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */
264 kENET_QOS_DmaRx = ENET_QOS_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */
265 kENET_QOS_DmaRxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */
266 kENET_QOS_DmaRxStop = ENET_QOS_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */
267 kENET_QOS_DmaRxWatchdogTimeout = ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
268 kENET_QOS_DmaEarlyTx = ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */
269 kENET_QOS_DmaEarlyRx = ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */
270 kENET_QOS_DmaBusErr = ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */
271 } enet_qos_dma_interrupt_enable_t;
272
273 /*! @brief List of mac interrupts supported by the ENET interrupt. This
274 * enumeration uses one-bot encoding to allow a logical OR of multiple
275 * members.
276 */
277 typedef enum _enet_qos_mac_interrupt_enable
278 {
279 kENET_QOS_MacPmt = (ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
280 kENET_QOS_MacTimestamp = (ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
281 } enet_qos_mac_interrupt_enable_t;
282
283 /*! @brief Defines the common interrupt event for callback use. */
284 typedef enum _enet_qos_event
285 {
286 kENET_QOS_RxIntEvent, /*!< Receive interrupt event. */
287 kENET_QOS_TxIntEvent, /*!< Transmit interrupt event. */
288 kENET_QOS_WakeUpIntEvent, /*!< Wake up interrupt event. */
289 kENET_QOS_TimeStampIntEvent, /*!< Time stamp interrupt event. */
290 } enet_qos_event_t;
291
292 /*! @brief Define the MTL mode for multiple queues/rings. */
293 typedef enum _enet_qos_queue_mode
294 {
295 kENET_QOS_AVB_Mode = 1U, /*!< Enable queue in AVB mode. */
296 kENET_QOS_DCB_Mode = 2U, /*!< Enable queue in DCB mode. */
297 } enet_qos_queue_mode_t;
298
299 /*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
300 typedef enum _enet_qos_mtl_multiqueue_txsche
301 {
302 kENET_QOS_txWeightRR = 0U, /*!< Tx weight round-robin. */
303 kENET_QOS_txWeightFQ = 1U, /*!< Tx weight fair queuing. */
304 kENET_QOS_txDefictWeightRR = 2U, /*!< Tx deficit weighted round-robin. */
305 kENET_QOS_txStrPrio = 3U, /*!< Tx strict priority. */
306 } enet_qos_mtl_multiqueue_txsche;
307
308 /*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
309 typedef enum _enet_qos_mtl_multiqueue_rxsche
310 {
311 kENET_QOS_rxStrPrio = 0U, /*!< Rx strict priority, Queue 0 has the lowest priority. */
312 kENET_QOS_rxWeightStrPrio, /*!< Weighted Strict Priority. */
313 } enet_qos_mtl_multiqueue_rxsche;
314
315 /*! @brief Define the MTL rx queue and DMA channel mapping. */
316 typedef enum _enet_qos_mtl_rxqueuemap
317 {
318 kENET_QOS_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) directly map to dma channel n. */
319 kENET_QOS_DynamicMap =
320 0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
321 */
322 } enet_qos_mtl_rxqueuemap_t;
323
324 /*! @brief Defines the package type for receive queue routing. */
325 typedef enum _enet_qos_rx_queue_route
326 {
327 kENET_QOS_PacketNoQ = 0x0, /* Not specific queue */
328 kENET_QOS_PacketAVCPQ = (1U << 0U), /* AV Untagged Control Packets Queue */
329 kENET_QOS_PacketPTPQ = (1U << 1U), /* PTP Packets Queue */
330 kENET_QOS_PacketDCBCPQ = (1U << 2U), /* DCB Control Packets Queue */
331 kENET_QOS_PacketUPQ = (1U << 3U), /* Untagged Packets Queue */
332 kENET_QOS_PacketMCBCQ = (1U << 4U), /* Multicast & Broadcast Packets Queue */
333 } enet_qos_rx_queue_route_t;
334
335 /*! @brief Defines the ENET PTP message related constant. */
336 typedef enum _enet_qos_ptp_event_type
337 {
338 kENET_QOS_PtpEventMsgType = 3U, /*!< PTP event message type. */
339 kENET_QOS_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
340 kENET_QOS_PtpEventPort = 319U, /*!< PTP event port number. */
341 kENET_QOS_PtpGnrlPort = 320U /*!< PTP general port number. */
342 } enet_qos_ptp_event_type_t;
343
344 /*! @brief Defines the PPS instance numbers. */
345 typedef enum _enet_qos_ptp_pps_instance
346 {
347 kENET_QOS_PtpPpsIstance0 = 0U, /*!< PPS instance 0. */
348 kENET_QOS_PtpPpsIstance1, /*!< PPS instance 1. */
349 kENET_QOS_PtpPpsIstance2, /*!< PPS instance 2. */
350 kENET_QOS_PtpPpsIstance3 /*!< PPS instance 3. */
351 } enet_qos_ptp_pps_instance_t;
352
353 /*! @brief Defines the Target Time register mode. */
354 typedef enum _enet_qos_ptp_pps_trgt_mode
355 {
356 kENET_QOS_PtpPpsTrgtModeOnlyInt = 0U, /*!< Only interrupts. */
357 kENET_QOS_PtpPpsTrgtModeIntSt = 2, /*!< Both interrupt and output signal. */
358 kENET_QOS_PtpPpsTrgtModeOnlySt = 3, /*!< Only output signal. */
359 } enet_qos_ptp_pps_trgt_mode_t;
360
361 /*! @brief Defines commands for ppscmd register. */
362 typedef enum _enet_qos_ptp_pps_cmd
363 {
364 kENET_QOS_PtpPpsCmdNC = 0U, /*!< No Command. */
365 kENET_QOS_PtpPpsCmdSSP = 1U, /*!< Start Single Pulse. */
366 kENET_QOS_PtpPpsCmdSPT = 2U, /*!< Start Pulse Train. */
367 kENET_QOS_PtpPpsCmdCS = 3U, /*!< Cancel Start. */
368 kENET_QOS_PtpPpsCmdSPTAT = 4U, /*!< Stop Pulse Train At Time. */
369 kENET_QOS_PtpPpsCmdSPTI = 5U, /*!< Stop Pulse Train Immediately. */
370 kENET_QOS_PtpPpsCmdCSPT = 6U, /*!< Cancel Stop Pulse Train. */
371 } enet_qos_ptp_pps_cmd_t;
372
373 /*! @brief Defines the enmueration of ETS list length.
374 */
375 typedef enum _enet_qos_ets_list_length
376 {
377 kENET_QOS_Ets_List_64 = 7U, /*!< List length of 64 */
378 kENET_QOS_Ets_List_128 = 8U, /*!< List length of 128 */
379 kENET_QOS_Ets_List_256 = 9U, /*!< List length of 256 */
380 kENET_QOS_Ets_List_512 = 10U, /*!< List length of 512 */
381 kENET_QOS_Ets_List_1024 = 11U, /*!< List length of 1024 */
382 } enet_qos_ets_list_length_t;
383
384 /*! @brief Defines the enmueration of ETS gate control address.
385 */
386 typedef enum _enet_qos_ets_gccr_addr
387 {
388 kENET_QOS_Ets_btr_low = 0U, /*!< BTR Low */
389 kENET_QOS_Ets_btr_high = 1U, /*!< BTR High */
390 kENET_QOS_Ets_ctr_low = 2U, /*!< CTR Low */
391 kENET_QOS_Ets_ctr_high = 3U, /*!< CTR High */
392 kENET_QOS_Ets_ter = 4U, /*!< TER */
393 kENET_QOS_Ets_llr = 5U, /*!< LLR */
394 } enet_qos_ets_gccr_addr_t;
395
396 /*! @brief Defines the enmueration of DMA channel used
397 * for rx parser entry.
398 */
399 typedef enum _enet_qos_rxp_dma_chn
400 {
401 kENET_QOS_Rxp_DMAChn0 = 1U, /*!< DMA Channel 0 used for RXP entry match */
402 kENET_QOS_Rxp_DMAChn1 = 2U, /*!< DMA Channel 1 used for RXP entry match */
403 kENET_QOS_Rxp_DMAChn2 = 4U, /*!< DMA Channel 2 used for RXP entry match */
404 kENET_QOS_Rxp_DMAChn3 = 8U, /*!< DMA Channel 3 used for RXP entry match */
405 kENET_QOS_Rxp_DMAChn4 = 16U, /*!< DMA Channel 4 used for RXP entry match */
406 } enet_qos_rxp_dma_chn_t;
407
408 /*! @brief Define the Tx checksum offload options. */
409 typedef enum _enet_qos_tx_offload
410 {
411 kENET_QOS_TxOffloadDisable = 0U, /*!< Disable Tx checksum offload. */
412 kENET_QOS_TxOffloadIPHeader = 1U, /*!< Enable IP header checksum calculation and insertion. */
413 kENET_QOS_TxOffloadIPHeaderPlusPayload =
414 2U, /*!< Enable IP header and payload checksum calculation and insertion. */
415 kENET_QOS_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */
416 } enet_qos_tx_offload_t;
417
418 /*! @brief Defines the receive descriptor structure
419 * has the read-format and write-back format structure. They both
420 * has the same size with different region definition. so
421 * we define the read-format region as the receive descriptor structure
422 * Use the read-format region mask bits in the descriptor initialization
423 * Use the write-back format region mask bits in the receive data process.
424 */
425 typedef struct _enet_qos_rx_bd_struct
426 {
427 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
428 __IO uint32_t reserved; /*!< Reserved */
429 __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
430 __IO uint32_t control; /*!< Buffer 1/2 byte counts and control */
431 } enet_qos_rx_bd_struct_t;
432
433 /*! @brief Defines the transmit descriptor structure
434 * has the read-format and write-back format structure. They both
435 * has the same size with different region definition. so
436 * we define the read-format region as the transmit descriptor structure
437 * Use the read-format region mask bits in the descriptor initialization
438 * Use the write-back format region mask bits in the transmit data process.
439 */
440 typedef struct _enet_qos_tx_bd_struct
441 {
442 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
443 __IO uint32_t buff2Addr; /*!< Buffer 2 address */
444 __IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */
445 __IO uint32_t controlStat; /*!< TDES control and status word */
446 } enet_qos_tx_bd_struct_t;
447
448 /*! @brief Defines the Tx BD configuration structure. */
449 typedef struct _enet_qos_tx_bd_config_struct
450 {
451 void *buffer1; /*!< The first buffer address in the descriptor. */
452 uint32_t bytes1; /*!< The bytes in the fist buffer. */
453 void *buffer2; /*!< The second buffer address in the descriptor. */
454 uint32_t bytes2; /*!< The bytes in the second buffer. */
455 uint32_t framelen; /*!< The length of the frame to be transmitted. */
456 bool intEnable; /*!< Interrupt enable flag. */
457 bool tsEnable; /*!< The timestamp enable. */
458 enet_qos_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option. */
459 enet_qos_desc_flag flag; /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */
460 } enet_qos_tx_bd_config_struct_t;
461
462 /*! @brief Defines the ENET PTP time stamp structure. */
463 typedef struct _enet_qos_ptp_time
464 {
465 uint64_t second; /*!< Second. */
466 uint32_t nanosecond; /*!< Nanosecond. */
467 } enet_qos_ptp_time_t;
468
469 /*! @brief Defines the frame info structure. */
470 typedef struct enet_qos_frame_info
471 {
472 void *context; /*!< User specified data, could be buffer address for free */
473 bool isTsAvail; /*!< Flag indicates timestamp available status */
474 enet_qos_ptp_time_t timeStamp; /*!< Timestamp of frame */
475 } enet_qos_frame_info_t;
476
477 /*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */
478 typedef struct _enet_qos_tx_dirty_ring
479 {
480 enet_qos_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */
481 uint16_t txGenIdx; /*!< tx generate index. */
482 uint16_t txConsumIdx; /*!< tx consume index. */
483 uint16_t txRingLen; /*!< tx ring length. */
484 bool isFull; /*!< tx ring is full flag, add this parameter to avoid waste one element. */
485 } enet_qos_tx_dirty_ring_t;
486
487 /*! @brief Defines the ENET PTP configuration structure. */
488 typedef struct _enet_qos_ptp_config
489 {
490 bool fineUpdateEnable; /*!< Use the fine update. */
491 uint32_t defaultAddend; /*!< Default addend value when fine update is enable, could be 2^32 / (refClk_Hz /
492 ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ). */
493 uint32_t systemTimeClock_Hz; /*! The desired system time frequency. Must be lower than reference clock. (Only used
494 with fine correction method). */
495 bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */
496 enet_qos_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
497 } enet_qos_ptp_config_t;
498
499 /*! @brief Defines the EST gate operation structure. */
500 typedef struct _enet_qos_est_gate_op
501 {
502 uint32_t gate;
503 uint32_t interval;
504 } enet_qos_est_gate_op_t;
505
506 /*! @brief Defines the EST gate control list structure. */
507 typedef struct _enet_qos_est_gcl
508 {
509 bool enable; /*!< Enable or disable EST */
510 uint64_t baseTime; /*! Base Time 32 bits seconds 32 bits nanoseconds */
511 uint64_t cycleTime; /*! Cycle Time 32 bits seconds 32 bits nanoseconds */
512 uint32_t extTime; /*! Time Extension 32 bits seconds 32 bits nanoseconds */
513 uint32_t numEntries; /*! Number of entries */
514 enet_qos_est_gate_op_t *opList; /*! Pointer to GCL list size */
515 } enet_qos_est_gcl_t;
516
517 /*! @brief Defines the ENET_QOS Rx parser configuration structure.*/
518 typedef struct _enet_qos_rxp_config
519 {
520 uint32_t matchData; /*! 4-byte match data used for comparing with incoming packet */
521 uint32_t matchEnable; /*! When matchEnable is set to 1, the matchData is used for comparing */
522 uint8_t acceptFrame : 1; /*! When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel */
523 uint8_t rejectFrame : 1; /*! When rejectFrame = 1 and data is matched, the frame will be dropped */
524 uint8_t inverseMatch : 1; /*! Inverse match */
525 uint8_t nextControl : 1; /*! Next instruction indexing control */
526 uint8_t reserved : 4; /*! Reserved control fields */
527 uint8_t frameOffset; /*! Frame offset in the packet data to be compared for match, in terms of 4 bytes. */
528 uint8_t okIndex; /*! Memory Index to be used next. */
529 uint8_t dmaChannel; /*! The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and
530 acceptFrame = 1 */
531 uint32_t reserved2; /*! Reserved for future enhancements */
532 } enet_qos_rxp_config_t;
533
534 /*! @brief Defines the buffer descriptor configure structure.
535 *
536 * @note
537 * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
538 * 2. The recommended minimum tx/rx ring length is 4.
539 * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
540 * of the last last descriptor. because only the descriptors between the start address and the
541 * tail address will be used by DMA.
542 * 4. The descriptor address is the start address of all used contiguous memory.
543 * for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories
544 * for rx descriptor ring 0.
545 * 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers)
546 * rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
547 * the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
548 * the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
549 * address of a rxRingLen or 2*rxRingLen array.
550 */
551 typedef struct _enet_qos_buffer_config
552 {
553 uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */
554 uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */
555 enet_qos_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
556 enet_qos_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */
557 enet_qos_frame_info_t *txDirtyStartAddr; /*!< Start address of the dirty tx frame information. */
558 enet_qos_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
559 enet_qos_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */
560 uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */
561 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
562 bool rxBuffNeedMaintain; /*!< Whether receive data buffer need cache maintain. */
563 } enet_qos_buffer_config_t;
564
565 /*! @brief Defines the CBS configuration for queue. */
566 typedef struct _enet_qos_cbs_config
567 {
568 uint16_t sendSlope; /*!< Send slope configuration. */
569 uint16_t idleSlope; /*!< Idle slope configuration. */
570 uint32_t highCredit; /*!< High credit. */
571 uint32_t lowCredit; /*!< Low credit. */
572 } enet_qos_cbs_config_t;
573
574 /*! @brief Defines the queue configuration structure. */
575 typedef struct enet_qos_tx_queue_config
576 {
577 enet_qos_queue_mode_t mode; /*!< tx queue mode configuration. */
578 uint32_t weight; /*!< Refer to the MTL TxQ Quantum Weight register. */
579 uint32_t priority; /*!< Refer to Transmit Queue Priority Mapping register. */
580 enet_qos_cbs_config_t *cbsConfig; /*!< CBS configuration if queue use AVB mode. */
581 } enet_qos_queue_tx_config_t;
582
583 /*! @brief Defines the queue configuration structure. */
584 typedef struct enet_qos_rx_queue_config
585 {
586 enet_qos_queue_mode_t mode; /*!< rx queue mode configuration. */
587 uint8_t mapChannel; /*!< tx queue map dma channel. */
588 uint32_t priority; /*!< Rx queue priority. */
589 enet_qos_rx_queue_route_t packetRoute; /*!< Receive packet routing. */
590 } enet_qos_queue_rx_config_t;
591
592 /*! @brief Defines the configuration when multi-queue is used. */
593 typedef struct enet_qos_multiqueue_config
594 {
595 enet_qos_dma_burstlen burstLen; /*!< Burst len for the multi-queue. */
596 uint8_t txQueueUse; /*!< Used Tx queue count. */
597 enet_qos_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */
598 enet_qos_queue_tx_config_t txQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Tx Queue configuration. */
599 uint8_t rxQueueUse; /*!< Used Rx queue count. */
600 enet_qos_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */
601 enet_qos_queue_rx_config_t rxQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Rx Queue configuration. */
602 } enet_qos_multiqueue_config_t;
603
604 /*! @brief Defines the Rx memory buffer alloc function pointer. */
605 typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel);
606
607 /*! @brief Defines the Rx memory buffer free function pointer. */
608 typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel);
609
610 /*! @brief Defines the basic configuration structure for the ENET device.
611 *
612 * @note Default the signal queue is used so the "*multiqueueCfg" is set default
613 * with NULL. Set the pointer with a valid configuration pointer if the multiple
614 * queues are required. If multiple queue is enabled, please make sure the
615 * buffer configuration for all are prepared also.
616 */
617 typedef struct _enet_qos_config
618 {
619 uint16_t specialControl; /*!< The logic or of enet_qos_special_config_t */
620 enet_qos_multiqueue_config_t *multiqueueCfg; /*!< Use multi-queue. */
621 /* -----------------MAC block-------------------------------*/
622 enet_qos_mii_mode_t miiMode; /*!< MII mode. */
623 enet_qos_mii_speed_t miiSpeed; /*!< MII Speed. */
624 enet_qos_mii_duplex_t miiDuplex; /*!< MII duplex. */
625 uint16_t
626 pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set. */
627 /* -----------------Timestamp -------------------------------*/
628 enet_qos_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
629 uint32_t csrClock_Hz; /*!< CSR clock frequency in HZ. */
630 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
631 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
632 } enet_qos_config_t;
633
634 /* Forward declaration of the handle typedef. */
635 typedef struct _enet_qos_handle enet_qos_handle_t;
636
637 /*! @brief ENET callback function. */
638 typedef void (*enet_qos_callback_t)(
639 ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData);
640
641 /*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
642 typedef struct _enet_qos_tx_bd_ring
643 {
644 enet_qos_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
645 uint16_t txGenIdx; /*!< tx generate index. */
646 uint16_t txConsumIdx; /*!< tx consume index. */
647 volatile uint16_t txDescUsed; /*!< tx descriptor used number. */
648 uint16_t txRingLen; /*!< tx ring length. */
649 } enet_qos_tx_bd_ring_t;
650
651 /*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
652 typedef struct _enet_qos_rx_bd_ring
653 {
654 enet_qos_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
655 uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */
656 uint16_t rxRingLen; /*!< Receive ring length. */
657 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */
658 } enet_qos_rx_bd_ring_t;
659
660 /*! @brief Defines the ENET handler structure. */
661 struct _enet_qos_handle
662 {
663 uint8_t txQueueUse; /*!< Used tx queue count. */
664 uint8_t rxQueueUse; /*!< Used rx queue count. */
665 bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */
666 bool rxintEnable; /*!< Rx interrupt enabled. */
667 bool rxMaintainEnable[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer cache maintain enabled. */
668 enet_qos_rx_bd_ring_t rxBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Receive buffer descriptor. */
669 enet_qos_tx_bd_ring_t txBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */
670 enet_qos_tx_dirty_ring_t txDirtyRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */
671 uint32_t *rxBufferStartAddr[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer start address for reInitialize. */
672 enet_qos_callback_t callback; /*!< Callback function. */
673 void *userData; /*!< Callback function parameter.*/
674 uint8_t multicastCount[64]; /*!< Multicast collisions counter */
675 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
676 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
677 };
678
679 /*! @brief Defines the ENET state structure.
680 *
681 * @note The structure contains saved state for the instance.
682 * It could be stored in enet_qos_handle_t, but that's used
683 * only with the transactional API.
684 */
685 typedef struct _enet_qos_state
686 {
687 enet_qos_mii_mode_t miiMode; /*!< MII mode. */
688 } enet_qos_state_t;
689
690 /*! @brief Defines the frame buffer structure. */
691 typedef struct _enet_qos_buffer_struct
692 {
693 void *buffer; /*!< The buffer store the whole or partial frame. */
694 uint16_t length; /*!< The byte length of this buffer. */
695 } enet_qos_buffer_struct_t;
696
697 /*! @brief Defines the Rx frame error structure. */
698 typedef struct _enet_qos_rx_frame_error
699 {
700 bool rxDstAddrFilterErr : 1; /*!< Destination Address Filter Fail. */
701 bool rxSrcAddrFilterErr : 1; /*!< SA Address Filter Fail. */
702 bool rxDribbleErr : 1; /*!< Dribble error. */
703 bool rxReceiveErr : 1; /*!< Receive error. */
704 bool rxOverFlowErr : 1; /*!< Receive over flow. */
705 bool rxWatchDogErr : 1; /*!< Watch dog timeout. */
706 bool rxGaintPacketErr : 1; /*!< Receive gaint packet. */
707 bool rxCrcErr : 1; /*!< Receive CRC error. */
708 } enet_qos_rx_frame_error_t;
709
710 typedef struct _enet_qos_rx_frame_attribute_struct
711 {
712 bool isTsAvail; /*!< Rx frame timestamp is available or not. */
713 enet_qos_ptp_time_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */
714 } enet_qos_rx_frame_attribute_t;
715
716 /*! @brief Defines the Rx frame data structure. */
717 typedef struct _enet_qos_rx_frame_struct
718 {
719 enet_qos_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */
720 uint16_t totLen; /*!< Rx frame total length. */
721 enet_qos_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */
722 enet_qos_rx_frame_error_t rxFrameError; /*!< Rx frame error. */
723 } enet_qos_rx_frame_struct_t;
724
725 /*! @brief Defines the ENET QOS transfer statistics structure. */
726 typedef struct _enet_qos_transfer_stats
727 {
728 uint32_t statsRxFrameCount; /*!< Rx frame number. */
729 uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */
730 uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */
731 uint32_t statsRxLengthErr; /*!< Rx frame length field doesn't equal to packet size. */
732 uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */
733 uint32_t statsTxFrameCount; /*!< Tx frame number. */
734 uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */
735 } enet_qos_transfer_stats_t;
736
737 /* Typedef for interrupt handler. */
738 typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle);
739
740 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
741 /*! @brief Pointers to enet clocks for each instance. */
742 extern const clock_ip_name_t s_enetqosClock[];
743 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
744
745 /*!
746 * @brief Set ENET system configuration.
747 * @note User needs to provide the implementation because the implementation is SoC specific.
748 * This function set the phy selection and enable clock.
749 * It should be called before any other ethernet operation.
750 *
751 * @param miiMode The MII/RGMII/RMII mode for interface between the phy and Ethernet.
752 */
753 extern void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode);
754
755 /*!
756 * @brief Enable/Disable ENET qos clock.
757 * @note User needs to provide the implementation because the implementation is SoC specific.
758 * This function should be called before config RMII mode.
759 *
760 */
761 extern void ENET_QOS_EnableClock(bool enable);
762
763 /*******************************************************************************
764 * API
765 ******************************************************************************/
766
767 #if defined(__cplusplus)
768 extern "C" {
769 #endif
770
771 /*!
772 * @name Initialization and De-initialization
773 * @{
774 */
775
776 /*!
777 * @brief Gets the ENET default configuration structure.
778 *
779 * The purpose of this API is to get the default ENET configure
780 * structure for @ref ENET_QOS_Init(). User may use the initialized
781 * structure unchanged in @ref ENET_QOS_Init(), or modify some fields of the
782 * structure before calling @ref ENET_QOS_Init().
783 * Example:
784 @code
785 enet_qos_config_t config;
786 ENET_QOS_GetDefaultConfig(&config);
787 @endcode
788 * @param config The ENET mac controller configuration structure pointer.
789 */
790 void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config);
791
792 /*!
793 * @brief Initializes the ENET module.
794 *
795 * This function initializes it with the ENET basic
796 * configuration.
797 *
798 * @param base ENET peripheral base address.
799 * @param config ENET mac configuration structure pointer.
800 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
801 * can be used directly. It is also possible to verify the Mac configuration using other methods.
802 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
803 * provided.
804 * @param macCount Count of macAddr in the ENET mac address array
805 * @param refclkSrc_Hz ENET input reference clock.
806 */
807 status_t ENET_QOS_Up(
808 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
809
810 /*!
811 * @brief Initializes the ENET module.
812 *
813 * This function ungates the module clock and initializes it with the ENET basic
814 * configuration.
815 *
816 * @param base ENET peripheral base address.
817 * @param config ENET mac configuration structure pointer.
818 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
819 * can be used directly. It is also possible to verify the Mac configuration using other methods.
820 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
821 * provided.
822 * @param macCount Count of macAddr in the ENET mac address array
823 * @param refclkSrc_Hz ENET input reference clock.
824 */
825 status_t ENET_QOS_Init(
826 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
827
828 /*!
829 * @brief Stops the ENET module.
830
831 * This function disables the ENET module.
832 *
833 * @param base ENET peripheral base address.
834 */
835 void ENET_QOS_Down(ENET_QOS_Type *base);
836
837 /*!
838 * @brief Deinitializes the ENET module.
839
840 * This function gates the module clock and disables the ENET module.
841 *
842 * @param base ENET peripheral base address.
843 */
844 void ENET_QOS_Deinit(ENET_QOS_Type *base);
845
846 /*!
847 * @brief Get the ENET instance from peripheral base address.
848 *
849 * @param base ENET peripheral base address.
850 * @return ENET instance.
851 */
852 uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base);
853
854 /*!
855 * @brief Initialize for all ENET descriptors.
856 *
857 * @note This function is do all tx/rx descriptors initialization. Because this API
858 * read all interrupt registers first and then set the interrupt flag for all descriptors,
859 * if the interrupt register is set. so the descriptor initialization should be called
860 * after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs
861 * are used).
862 *
863 * @param base ENET peripheral base address.
864 * @param config The configuration for ENET.
865 * @param bufferConfig All buffers configuration.
866 */
867 status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base,
868 enet_qos_config_t *config,
869 enet_qos_buffer_config_t *bufferConfig);
870
871 /*!
872 * @brief Allocates Rx buffers for all BDs.
873 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
874 * will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used
875 * to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken
876 * by application application should free those buffers after they're used.
877 *
878 * @note This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback
879 * function should be ready.
880 *
881 * @param base ENET_QOS peripheral base address.
882 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
883 */
884 status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
885
886 /*!
887 * @brief Frees Rx buffers in all BDs.
888 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
889 * will free left buffers in all BDs.
890 *
891 * @param base ENET_QOS peripheral base address.
892 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
893 */
894 void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
895
896 /*!
897 * @brief Starts the ENET rx/tx.
898 * This function enable the tx/rx and starts the rx/tx DMA.
899 * This shall be set after ENET initialization and before
900 * starting to receive the data.
901 *
902 * @param base ENET peripheral base address.
903 * @param rxRingNum The number of the used rx rings. It shall not be
904 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
905 * 1, the ring 0 will be used.
906 * @param txRingNum The number of the used tx rings. It shall not be
907 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
908 * 1, the ring 0 will be used.
909 *
910 * @note This must be called after all the ENET initialization.
911 * And should be called when the ENET receive/transmit is required.
912 */
913 void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
914
915 /*! @} */
916
917 /*!
918 * @name MII interface operation
919 * @{
920 */
921
922 /*!
923 * @brief Sets the ENET MII speed and duplex.
924 *
925 * This API is provided to dynamically change the speed and duplex for MAC.
926 *
927 * @param base ENET peripheral base address.
928 * @param speed The speed of the RMII mode.
929 * @param duplex The duplex of the RMII mode.
930 * @return kStatus_Success The ENET MII speed and duplex has been set successfully.
931 * @return kStatus_InvalidArgument Could not set the desired ENET MII speed and duplex combination.
932 */
933 status_t ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex);
934
935 /*!
936 * @brief Sets the ENET SMI(serial management interface)- MII management interface.
937 *
938 * @param base ENET peripheral base address.
939 * @param csrClock_Hz CSR clock frequency in HZ
940 */
941 void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz);
942
943 /*!
944 * @brief Checks if the SMI is busy.
945 *
946 * @param base ENET peripheral base address.
947 * @return The status of MII Busy status.
948 */
ENET_QOS_IsSMIBusy(ENET_QOS_Type * base)949 static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)
950 {
951 return ((base->MAC_MDIO_ADDRESS & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) != 0U) ? true : false;
952 }
953
954 /*!
955 * @brief Reads data from the PHY register through SMI interface.
956 *
957 * @param base ENET peripheral base address.
958 * @return The data read from PHY
959 */
ENET_QOS_ReadSMIData(ENET_QOS_Type * base)960 static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)
961 {
962 return (uint16_t)(base->MAC_MDIO_DATA & ENET_QOS_MAC_MDIO_DATA_GD_MASK);
963 }
964
965 /*!
966 * @brief Sends the MDIO IEEE802.3 Clause 22 format write command.
967 * After send command, user needs to check whether the transmission is over
968 * with ENET_QOS_IsSMIBusy().
969 *
970 * @param base ENET peripheral base address.
971 * @param phyAddr The PHY address.
972 * @param regAddr The PHY register address.
973 * @param data The data written to PHY.
974 */
975 void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
976
977 /*!
978 * @brief Sends the MDIO IEEE802.3 Clause 22 format read command.
979 * After send command, user needs to check whether the transmission is over
980 * with ENET_QOS_IsSMIBusy().
981 *
982 * @param base ENET peripheral base address.
983 * @param phyAddr The PHY address.
984 * @param regAddr The PHY register address.
985 */
986 void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr);
987
988 /*!
989 * @brief Sends the MDIO IEEE802.3 Clause 45 format write command.
990 * After send command, user needs to check whether the transmission is over
991 * with ENET_QOS_IsSMIBusy().
992 *
993 * @param base ENET peripheral base address.
994 * @param portAddr The MDIO port address(PHY address).
995 * @param devAddr The device address.
996 * @param regAddr The PHY register address.
997 * @param data The data written to PHY.
998 */
999 void ENET_QOS_StartExtC45SMIWrite(
1000 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1001
1002 /*!
1003 * @brief Sends the MDIO IEEE802.3 Clause 45 format read command.
1004 * After send command, user needs to check whether the transmission is over
1005 * with ENET_QOS_IsSMIBusy().
1006 *
1007 * @param base ENET peripheral base address.
1008 * @param portAddr The MDIO port address(PHY address).
1009 * @param devAddr The device address.
1010 * @param regAddr The PHY register address.
1011 */
1012 void ENET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr);
1013
1014 /*!
1015 * @brief MDIO write with IEEE802.3 MDIO Clause 22 format.
1016 *
1017 * @param base ENET peripheral base address.
1018 * @param phyAddr The PHY address.
1019 * @param regAddr The PHY register.
1020 * @param data The data written to PHY.
1021 * @return kStatus_Success MDIO access succeeds.
1022 * @return kStatus_Timeout MDIO access timeout.
1023 */
1024 status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
1025
1026 /*!
1027 * @brief MDIO read with IEEE802.3 MDIO Clause 22 format.
1028 *
1029 * @param base ENET peripheral base address.
1030 * @param phyAddr The PHY address.
1031 * @param regAddr The PHY register.
1032 * @param pData The data read from PHY.
1033 * @return kStatus_Success MDIO access succeeds.
1034 * @return kStatus_Timeout MDIO access timeout.
1035 */
1036 status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
1037
1038 /*!
1039 * @brief MDIO write with IEEE802.3 Clause 45 format.
1040 *
1041 * @param base ENET peripheral base address.
1042 * @param portAddr The MDIO port address(PHY address).
1043 * @param devAddr The device address.
1044 * @param regAddr The PHY register address.
1045 * @param data The data written to PHY.
1046 * @return kStatus_Success MDIO access succeeds.
1047 * @return kStatus_Timeout MDIO access timeout.
1048 */
1049 status_t ENET_QOS_MDIOC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1050
1051 /*!
1052 * @brief MDIO read with IEEE802.3 Clause 45 format.
1053 *
1054 * @param base ENET peripheral base address.
1055 * @param portAddr The MDIO port address(PHY address).
1056 * @param devAddr The device address.
1057 * @param regAddr The PHY register address.
1058 * @param pData The data read from PHY.
1059 * @return kStatus_Success MDIO access succeeds.
1060 * @return kStatus_Timeout MDIO access timeout.
1061 */
1062 status_t ENET_QOS_MDIOC45Read(
1063 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
1064
1065 /*! @} */
1066
1067 /*!
1068 * @name Other basic operation
1069 * @{
1070 */
1071
1072 /*!
1073 * @brief Sets the ENET module Mac address.
1074 *
1075 * @param base ENET peripheral base address.
1076 * @param macAddr The six-byte Mac address pointer.
1077 * The pointer is allocated by application and input into the API.
1078 * @param index Configure macAddr to MAC_ADDRESS[index] register.
1079 */
ENET_QOS_SetMacAddr(ENET_QOS_Type * base,uint8_t * macAddr,uint8_t index)1080 static inline void ENET_QOS_SetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)
1081 {
1082 uint32_t lowAddress;
1083 uint32_t highAddress;
1084
1085 assert(macAddr != NULL);
1086
1087 lowAddress = ((uint32_t)macAddr[3] << 24U) | ((uint32_t)macAddr[2] << 16U) | ((uint32_t)macAddr[1] << 8U) |
1088 ((uint32_t)macAddr[0]);
1089 highAddress = ((uint32_t)macAddr[5] << 8U) | ((uint32_t)macAddr[4]);
1090 /* Set Macaddr, the MAC address registers are configured to be double-synchronized to the MII clock
1091 domains, then the synchronization is triggered only when bits 31:24 (in little-endian mode)
1092 or bits 7:0 (in Big-Endian mode) of the MAC address low register are written to.*/
1093 base->MAC_ADDRESS[index].HIGH = highAddress | ENET_QOS_HIGH_AE_MASK;
1094 base->MAC_ADDRESS[index].LOW = lowAddress;
1095 }
1096
1097 /*!
1098 * @brief Gets the ENET module Mac address.
1099 *
1100 * @param base ENET peripheral base address.
1101 * @param macAddr The six-byte Mac address pointer.
1102 * The pointer is allocated by application and input into the API.
1103 * @param index Get macAddr from MAC_ADDRESS[index] register.
1104 */
1105 void ENET_QOS_GetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index);
1106
1107 /*!
1108 * @brief Adds the ENET_QOS device to a multicast group.
1109 *
1110 * @param base ENET_QOS peripheral base address.
1111 * @param address The six-byte multicast group address which is provided by application.
1112 */
1113 void ENET_QOS_AddMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1114
1115 /*!
1116 * @brief Moves the ENET_QOS device from a multicast group.
1117 *
1118 * @param base ENET_QOS peripheral base address.
1119 * @param address The six-byte multicast group address which is provided by application.
1120 */
1121 void ENET_QOS_LeaveMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1122
1123 /*!
1124 * @brief Enable ENET device to accept all multicast frames.
1125 *
1126 * @param base ENET peripheral base address.
1127 */
ENET_QOS_AcceptAllMulticast(ENET_QOS_Type * base)1128 static inline void ENET_QOS_AcceptAllMulticast(ENET_QOS_Type *base)
1129 {
1130 uint32_t reg = base->MAC_PACKET_FILTER;
1131
1132 base->MAC_PACKET_FILTER = reg | ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1133 }
1134
1135 /*!
1136 * @brief ENET device reject to accept all multicast frames.
1137 *
1138 * @param base ENET peripheral base address.
1139 */
ENET_QOS_RejectAllMulticast(ENET_QOS_Type * base)1140 static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base)
1141 {
1142 uint32_t reg = base->MAC_PACKET_FILTER;
1143
1144 base->MAC_PACKET_FILTER = reg & ~ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1145 }
1146
1147 /*!
1148 * @brief Set the MAC to enter into power down mode.
1149 * the remote power wake up frame and magic frame can wake up
1150 * the ENET from the power down mode.
1151 *
1152 * @param base ENET peripheral base address.
1153 * @param wakeFilter The wakeFilter provided to configure the wake up frame filter.
1154 * Set the wakeFilter to NULL is not required. But if you have the filter requirement,
1155 * please make sure the wakeFilter pointer shall be eight continuous
1156 * 32-bits configuration.
1157 */
1158 void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter);
1159
1160 /*!
1161 * @brief Set the MAC to exit power down mode.
1162 * Exit from the power down mode and recover to normal work mode.
1163 *
1164 * @param base ENET peripheral base address.
1165 */
ENET_QOS_ExitPowerDown(ENET_QOS_Type * base)1166 static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base)
1167 {
1168 /* Clear and status ans reset the power down. */
1169 base->MAC_PMT_CONTROL_STATUS &= ~ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
1170
1171 /* Restore the tx which is disabled when enter power down mode. */
1172 base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1173 base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1174 base->MAC_CONFIGURATION |= ENET_QOS_MAC_CONFIGURATION_TE_MASK;
1175 }
1176
1177 /*!
1178 * @brief Enable/Disable Rx parser,please notice that for enable/disable Rx Parser,
1179 * should better disable Receive first.
1180 *
1181 * @param base ENET_QOS peripheral base address.
1182 * @param enable Enable/Disable Rx parser function
1183 * @retval kStatus_Success Configure rx parser success.
1184 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1185 */
1186 status_t ENET_QOS_EnableRxParser(ENET_QOS_Type *base, bool enable);
1187 /*! @} */
1188
1189 /*!
1190 * @name Interrupts.
1191 * @{
1192 */
1193
1194 /*!
1195 * @brief Enables the ENET DMA and MAC interrupts.
1196 *
1197 * This function enables the ENET interrupt according to the provided mask. The mask
1198 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1199 * For example, to enable the dma and mac interrupt, do the following.
1200 * @code
1201 * ENET_QOS_EnableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1202 * @endcode
1203 *
1204 * @param base ENET peripheral base address.
1205 * @param mask ENET interrupts to enable. This is a logical OR of both
1206 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1207 */
1208 void ENET_QOS_EnableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1209
1210 /*!
1211 * @brief Disables the ENET DMA and MAC interrupts.
1212 *
1213 * This function disables the ENET interrupt according to the provided mask. The mask
1214 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1215 * For example, to disable the dma and mac interrupt, do the following.
1216 * @code
1217 * ENET_QOS_DisableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1218 * @endcode
1219 *
1220 * @param base ENET peripheral base address.
1221 * @param mask ENET interrupts to disables. This is a logical OR of both
1222 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1223 */
1224 void ENET_QOS_DisableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1225
1226 /*!
1227 * @brief Gets the ENET DMA interrupt status flag.
1228 *
1229 * @param base ENET peripheral base address.
1230 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1231 * @return The event status of the interrupt source. This is the logical OR of members
1232 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1233 */
ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel)1234 static inline uint32_t ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel)
1235 {
1236 return base->DMA_CH[channel].DMA_CHX_STAT;
1237 }
1238
1239 /*!
1240 * @brief Clear the ENET DMA interrupt status flag.
1241 *
1242 * @param base ENET peripheral base address.
1243 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1244 * @param mask The interrupt status to be cleared. This is the logical OR of members
1245 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1246 */
ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel,uint32_t mask)1247 static inline void ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel, uint32_t mask)
1248 {
1249 /* Clear the dam interrupt status bit in dma channel interrupt status register. */
1250 base->DMA_CH[channel].DMA_CHX_STAT = mask;
1251 }
1252
1253 /*!
1254 * @brief Gets the ENET MAC interrupt status flag.
1255 *
1256 * @param base ENET peripheral base address.
1257 * @return The event status of the interrupt source.
1258 * Use the enum in enet_qos_mac_interrupt_enable_t and right shift
1259 * ENET_QOS_MACINT_ENUM_OFFSET to mask the returned value to get the
1260 * exact interrupt status.
1261 */
ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type * base)1262 static inline uint32_t ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type *base)
1263 {
1264 return base->MAC_INTERRUPT_STATUS;
1265 }
1266
1267 /*!
1268 * @brief Clears the ENET mac interrupt events status flag.
1269 *
1270 * This function clears enabled ENET interrupts according to the provided mask. The mask
1271 * is a logical OR of enumeration members. See the @ref enet_qos_mac_interrupt_enable_t.
1272 * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
1273 * @code
1274 * ENET_QOS_ClearMacInterruptStatus(ENET, kENET_QOS_MacPmt);
1275 * @endcode
1276 *
1277 * @param base ENET peripheral base address.
1278 * @param mask ENET interrupt source to be cleared.
1279 * This is the logical OR of members of the enumeration :: enet_qos_mac_interrupt_enable_t.
1280 */
1281 void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask);
1282
1283 /*! @} */
1284
1285 /*!
1286 * @name Functional operation.
1287 * @{
1288 */
1289
1290 /*!
1291 * @brief Get the tx descriptor DMA Own flag.
1292 *
1293 * @param txDesc The given tx descriptor.
1294 * @retval True the dma own tx descriptor, false application own tx descriptor.
1295 *
1296 */
ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t * txDesc)1297 static inline bool ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t *txDesc)
1298 {
1299 return ((txDesc->controlStat & ENET_QOS_TXDESCRIP_RD_OWN_MASK) != 0U) ? true : false;
1300 }
1301
1302 /*!
1303 * @brief Setup a given tx descriptor.
1304 * This function is a low level functional API to setup or prepare
1305 * a given tx descriptor.
1306 *
1307 * @param txDesc The given tx descriptor.
1308 * @param buffer1 The first buffer address in the descriptor.
1309 * @param bytes1 The bytes in the fist buffer.
1310 * @param buffer2 The second buffer address in the descriptor.
1311 * @param bytes2 The bytes in the second buffer.
1312 * @param framelen The length of the frame to be transmitted.
1313 * @param intEnable Interrupt enable flag.
1314 * @param tsEnable The timestamp enable.
1315 * @param flag The flag of this tx descriptor, @ref enet_qos_desc_flag .
1316 * @param slotNum The slot num used for AV only.
1317 *
1318 * @note This must be called after all the ENET initialization.
1319 * And should be called when the ENET receive/transmit is required.
1320 * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
1321 * memory until the packet has been fully transmitted. The buffers
1322 * should be free or requeued in the transmit interrupt irq handler.
1323 */
1324 void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc,
1325 void *buffer1,
1326 uint32_t bytes1,
1327 void *buffer2,
1328 uint32_t bytes2,
1329 uint32_t framelen,
1330 bool intEnable,
1331 bool tsEnable,
1332 enet_qos_desc_flag flag,
1333 uint8_t slotNum);
1334
1335 /*!
1336 * @brief Update the tx descriptor tail pointer.
1337 * This function is a low level functional API to update the
1338 * the tx descriptor tail.
1339 * This is called after you setup a new tx descriptor to update
1340 * the tail pointer to make the new descriptor accessible by DMA.
1341 *
1342 * @param base ENET peripheral base address.
1343 * @param channel The tx DMA channel.
1344 * @param txDescTailAddrAlign The new tx tail pointer address.
1345 *
1346 */
ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t txDescTailAddrAlign)1347 static inline void ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
1348 {
1349 base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1350 }
1351
1352 /*!
1353 * @brief Update the rx descriptor tail pointer.
1354 * This function is a low level functional API to update the
1355 * the rx descriptor tail.
1356 * This is called after you setup a new rx descriptor to update
1357 * the tail pointer to make the new descriptor accessible by DMA
1358 * and to anouse the rx poll command for DMA.
1359 *
1360 * @param base ENET peripheral base address.
1361 * @param channel The rx DMA channel.
1362 * @param rxDescTailAddrAlign The new rx tail pointer address.
1363 *
1364 */
ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t rxDescTailAddrAlign)1365 static inline void ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
1366 {
1367 base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1368 }
1369
1370 /*!
1371 * @brief Gets the context in the ENET rx descriptor.
1372 * This function is a low level functional API to get the
1373 * the status flag from a given rx descriptor.
1374 *
1375 * @param rxDesc The given rx descriptor.
1376 * @retval The RDES3 regions for write-back format rx buffer descriptor.
1377 *
1378 * @note This must be called after all the ENET initialization.
1379 * And should be called when the ENET receive/transmit is required.
1380 */
ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t * rxDesc)1381 static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc)
1382 {
1383 assert(rxDesc != NULL);
1384
1385 return rxDesc->control;
1386 }
1387 /*!
1388 * @brief Updates the buffers and the own status for a given rx descriptor.
1389 * This function is a low level functional API to Updates the
1390 * buffers and the own status for a given rx descriptor.
1391 *
1392 * @param rxDesc The given rx descriptor.
1393 * @param buffer1 The first buffer address in the descriptor.
1394 * @param buffer2 The second buffer address in the descriptor.
1395 * @param intEnable Interrupt enable flag.
1396 * @param doubleBuffEnable The double buffer enable flag.
1397 *
1398 * @note This must be called after all the ENET initialization.
1399 * And should be called when the ENET receive/transmit is required.
1400 */
1401 void ENET_QOS_UpdateRxDescriptor(
1402 enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
1403
1404 /*!
1405 * @brief Configure flexible rx parser.
1406 *
1407 * This function is used to configure the flexible rx parser table.
1408 *
1409 * @param base ENET peripheral base address..
1410 * @param rxpConfig The rx parser configuration pointer.
1411 * @param entryCount The rx parser entry count.
1412 * @retval kStatus_Success Configure rx parser success.
1413 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1414 */
1415 status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount);
1416
1417 /*!
1418 * @brief Read flexible rx parser configuration at specified index.
1419 *
1420 * This function is used to read flexible rx parser configuration at specified index.
1421 *
1422 * @param base ENET peripheral base address..
1423 * @param rxpConfig The rx parser configuration pointer.
1424 * @param entryIndex The rx parser entry index to read, start from 0.
1425 * @retval kStatus_Success Configure rx parser success.
1426 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1427 */
1428 status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryIndex);
1429
1430 /*!
1431 * @brief Program Gate Control List.
1432 *
1433 * This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
1434 *
1435 * @param base ENET peripheral base address..
1436 * @param gcl Pointer to the Gate Control List structure.
1437 * @param ptpClk_Hz frequency of the PTP clock.
1438 */
1439 status_t ENET_QOS_EstProgramGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t ptpClk_Hz);
1440
1441 /*!
1442 * @brief Read Gate Control List.
1443 *
1444 * This function is used to read the Enhanced Scheduled Transmisson list. (IEEE802.1Qbv)
1445 *
1446 * @param base ENET peripheral base address..
1447 * @param gcl Pointer to the Gate Control List structure.
1448 * @param listLen length of the provided opList array in gcl structure.
1449 * @param hwList Boolean if True read HW list, false read SW list.
1450 */
1451 status_t ENET_QOS_EstReadGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t listLen, bool hwList);
1452
1453 /*!
1454 * @brief Enable Frame Preemption.
1455 *
1456 * This function is used to enable frame preemption. (IEEE802.1Qbu)
1457 *
1458 * @param base ENET peripheral base address..
1459 */
ENET_QOS_FpeEnable(ENET_QOS_Type * base)1460 static inline void ENET_QOS_FpeEnable(ENET_QOS_Type *base)
1461 {
1462 base->MAC_FPE_CTRL_STS |= ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1463 }
1464
1465 /*!
1466 * @brief Disable Frame Preemption.
1467 *
1468 * This function is used to disable frame preemption. (IEEE802.1Qbu)
1469 *
1470 * @param base ENET peripheral base address..
1471 */
ENET_QOS_FpeDisable(ENET_QOS_Type * base)1472 static inline void ENET_QOS_FpeDisable(ENET_QOS_Type *base)
1473 {
1474 base->MAC_FPE_CTRL_STS &= ~ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1475 }
1476
1477 /*!
1478 * @brief Configure preemptable transmit queues.
1479 *
1480 * This function is used to configure the preemptable queues. (IEEE802.1Qbu)
1481 *
1482 * @param base ENET peripheral base address..
1483 * @param queueMask bitmask representing queues to set in preemptable mode.
1484 * The N-th bit represents the queue N.
1485 */
ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type * base,uint8_t queueMask)1486 static inline void ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type *base, uint8_t queueMask)
1487 {
1488 uint32_t control;
1489
1490 control = base->MTL_FPE_CTRL_STS & ~ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK;
1491 control |= ENET_QOS_MTL_FPE_CTRL_STS_PEC(queueMask);
1492 base->MTL_FPE_CTRL_STS = control;
1493 }
1494
1495 /*!
1496 * @brief Sets the ENET AVB feature.
1497 *
1498 * ENET_QOS AVB feature configuration, set transmit bandwidth.
1499 * This API is called when the AVB feature is required.
1500 *
1501 * @param base ENET_QOS peripheral base address.
1502 * @param config The ENET_QOS AVB feature configuration structure.
1503 * @param queueIndex ENET_QOS queue index.
1504 */
1505 void ENET_QOS_AVBConfigure(ENET_QOS_Type *base, const enet_qos_cbs_config_t *config, uint8_t queueIndex);
1506
1507 /*!
1508 * @brief Gets statistical data in transfer.
1509 *
1510 * @param base ENET_QOS peripheral base address.
1511 * @param statistics The statistics structure pointer.
1512 */
1513 void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *statistics);
1514
1515 /*! @} */
1516
1517 /*!
1518 * @name Transactional operation
1519 * @{
1520 */
1521
1522 /*!
1523 * @brief Create ENET Handler
1524 *
1525 * This is a transactional API and it's provided to store all data which are needed
1526 * during the whole transactional process. This API should not be used when you use
1527 * functional APIs to do data tx/rx. This is function will store many data/flag for
1528 * transactional use, so all configure API such as ENET_QOS_Init(), ENET_QOS_DescriptorInit(),
1529 * ENET_QOS_EnableInterrupts() etc.
1530 *
1531 * @note as our transactional transmit API use the zero-copy transmit buffer.
1532 * so there are two thing we emphasize here:
1533 * 1. tx buffer free/requeue for application should be done in the tx
1534 * interrupt handler. Please set callback: kENET_QOS_TxIntEvent with tx buffer free/requeue
1535 * process APIs.
1536 * 2. the tx interrupt is forced to open.
1537 *
1538 * @param base ENET peripheral base address.
1539 * @param handle ENET handler.
1540 * @param config ENET configuration.
1541 * @param bufferConfig ENET buffer configuration.
1542 * @param callback The callback function.
1543 * @param userData The application data.
1544 */
1545 void ENET_QOS_CreateHandler(ENET_QOS_Type *base,
1546 enet_qos_handle_t *handle,
1547 enet_qos_config_t *config,
1548 enet_qos_buffer_config_t *bufferConfig,
1549 enet_qos_callback_t callback,
1550 void *userData);
1551
1552 /*!
1553 * @brief Gets the size of the read frame.
1554 * This function gets a received frame size from the ENET buffer descriptors.
1555 * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
1556 * After calling @ref ENET_QOS_GetRxFrameSize, @ref ENET_QOS_ReadFrame() should be called to update the
1557 * receive buffers If the result is not "kStatus_ENET_QOS_RxFrameEmpty".
1558 *
1559 * @param base ENET peripheral base address.
1560 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1561 * @param length The length of the valid frame received.
1562 * @param channel The DMAC channel for the rx.
1563 * @retval kStatus_ENET_QOS_RxFrameEmpty No frame received. Should not call ENET_QOS_ReadFrame to read frame.
1564 * @retval kStatus_ENET_QOS_RxFrameError Data error happens. @ref ENET_QOS_ReadFrame should be called with NULL data
1565 * and NULL length to update the receive buffers.
1566 * @retval kStatus_Success Receive a frame Successfully then the @ref ENET_QOS_ReadFrame
1567 * should be called with the right data buffer and the captured data length input.
1568 */
1569 status_t ENET_QOS_GetRxFrameSize(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint32_t *length, uint8_t channel);
1570
1571 /*!
1572 * @brief Reads a frame from the ENET device.
1573 * This function reads a frame from the ENET DMA descriptors.
1574 * The ENET_QOS_GetRxFrameSize should be used to get the size of the prepared data buffer.
1575 * For example use rx dma channel 0:
1576 * @code
1577 * uint32_t length;
1578 * enet_qos_handle_t g_handle;
1579 * status = ENET_QOS_GetRxFrameSize(&g_handle, &length, 0);
1580 * if (length != 0)
1581 * {
1582 * uint8_t *data = memory allocate interface;
1583 * if (!data)
1584 * {
1585 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1586 * }
1587 * else
1588 * {
1589 * status = ENET_QOS_ReadFrame(ENET, &g_handle, data, length, 0);
1590 * }
1591 * }
1592 * else if (status == kStatus_ENET_QOS_RxFrameError)
1593 * {
1594 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1595 * }
1596 * @endcode
1597 * @param base ENET peripheral base address.
1598 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1599 * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
1600 * @param length The size of the data buffer which is still the length of the received frame.
1601 * @param channel The rx DMA channel. shall not be larger than 2.
1602 * @param ts Pointer to the structure @ref enet_qos_ptp_time_t to save frame timestamp.
1603 * @return The execute status, successful or failure.
1604 */
1605 status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
1606 enet_qos_handle_t *handle,
1607 uint8_t *data,
1608 uint32_t length,
1609 uint8_t channel,
1610 enet_qos_ptp_time_t *ts);
1611
1612 /*!
1613 * @brief Transmits an ENET frame.
1614 * @note The CRC is automatically appended to the data. Input the data
1615 * to send without the CRC.
1616 *
1617 * @param base ENET peripheral base address.
1618 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1619 * @param data The data buffer provided by user to be send.
1620 * @param length The length of the data to be send.
1621 * @param channel Channel to send the frame, same with queue index.
1622 * @param isNeedTs True to enable timestamp save for the frame
1623 * @param context pointer to user context to be kept in the tx dirty frame information.
1624 * @param txOffloadOps The Tx frame checksum offload option.
1625 * @retval kStatus_Success Send frame succeed.
1626 * @retval kStatus_ENET_QOS_TxFrameBusy Transmit buffer descriptor is busy under transmission.
1627 * The transmit busy happens when the data send rate is over the MAC capacity.
1628 * The waiting mechanism is recommended to be added after each call return with
1629 * kStatus_ENET_QOS_TxFrameBusy.
1630 */
1631 status_t ENET_QOS_SendFrame(ENET_QOS_Type *base,
1632 enet_qos_handle_t *handle,
1633 uint8_t *data,
1634 uint32_t length,
1635 uint8_t channel,
1636 bool isNeedTs,
1637 void *context,
1638 enet_qos_tx_offload_t txOffloadOps);
1639
1640 /*!
1641 * @brief Reclaim tx descriptors.
1642 * This function is used to update the tx descriptor status and
1643 * store the tx timestamp when the 1588 feature is enabled.
1644 * This is called by the transmit interrupt IRQ handler after the
1645 * complete of a frame transmission.
1646 *
1647 * @param base ENET peripheral base address.
1648 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1649 * @param channel The tx DMA channel.
1650 *
1651 */
1652 void ENET_QOS_ReclaimTxDescriptor(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t channel);
1653
1654 /*!
1655 * @brief The ENET IRQ handler.
1656 *
1657 * @param base ENET peripheral base address.
1658 * @param handle The ENET handler pointer.
1659 */
1660 void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle);
1661
1662 /*!
1663 * @brief Set the second level IRQ handler, allow user to overwrite the default
1664 * second level weak IRQ handler.
1665 *
1666 * @param base ENET peripheral base address.
1667 * @param ISRHandler The handler to install.
1668 */
1669 void ENET_QOS_SetISRHandler(ENET_QOS_Type *base, enet_qos_isr_t ISRHandler);
1670
1671 /*! @} */
1672 /*!
1673 * @name ENET Enhanced function operation
1674 * @{
1675 */
1676
1677 /*!
1678 * @brief Correct the ENET PTP 1588 timer in coarse method.
1679 *
1680 * @param base ENET peripheral base address.
1681 * @param operation The system time operation, refer to "enet_qos_systime_op"
1682 * @param second The correction second.
1683 * @param nanosecond The correction nanosecond.
1684 */
1685 status_t ENET_QOS_Ptp1588CorrectTimerInCoarse(ENET_QOS_Type *base,
1686 enet_qos_systime_op operation,
1687 uint32_t second,
1688 uint32_t nanosecond);
1689
1690 /*!
1691 * @brief Correct the ENET PTP 1588 timer in fine method.
1692 *
1693 *
1694 * @param base ENET peripheral base address.
1695 * @param addend The addend value to be set in the fine method
1696 * @note Should take refer to the chapter "System time correction" and
1697 * see the description for the "fine correction method".
1698 */
1699 status_t ENET_QOS_Ptp1588CorrectTimerInFine(ENET_QOS_Type *base, uint32_t addend);
1700
1701 /*!
1702 * @brief Get the ENET Time stamp current addend value.
1703 *
1704 * @param base ENET peripheral base address.
1705 * @return The addend value.
1706 */
ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type * base)1707 static inline uint32_t ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type *base)
1708 {
1709 return base->MAC_TIMESTAMP_ADDEND;
1710 }
1711
1712 /*!
1713 * @brief Gets the current ENET time from the PTP 1588 timer without IRQ disable.
1714 *
1715 * @param base ENET peripheral base address.
1716 * @param second The PTP 1588 system timer second.
1717 * @param nanosecond The PTP 1588 system timer nanosecond.
1718 * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
1719 */
1720 void ENET_QOS_Ptp1588GetTimerNoIRQDisable(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1721
1722 /*!
1723 * @brief Sets the ENET PTP 1588 PPS control.
1724 * All channels operate in flexible PPS output mode.
1725 *
1726 * @param base ENET peripheral base address.
1727 * @param instance The ENET QOS PTP PPS instance.
1728 * @param trgtMode The target time register mode.
1729 * @param cmd The target flexible PPS output control command.
1730 */
ENET_Ptp1588PpsControl(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,enet_qos_ptp_pps_trgt_mode_t trgtMode,enet_qos_ptp_pps_cmd_t cmd)1731 static inline status_t ENET_Ptp1588PpsControl(ENET_QOS_Type *base,
1732 enet_qos_ptp_pps_instance_t instance,
1733 enet_qos_ptp_pps_trgt_mode_t trgtMode,
1734 enet_qos_ptp_pps_cmd_t cmd)
1735 {
1736 uint32_t reg = 0UL;
1737 uint8_t shift = (uint8_t)instance * 8U;
1738 uint32_t pps_config = ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0((uint32_t)trgtMode) |
1739 ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD((uint32_t)cmd);
1740
1741 reg = base->MAC_PPS_CONTROL;
1742
1743 /* Make sure CMD field is all zero */
1744 if ((reg & (0xFUL << shift)) != 0UL)
1745 {
1746 return kStatus_ENET_QOS_PpsBusy;
1747 }
1748
1749 reg &= ~(0xFFUL << shift);
1750 reg |= (pps_config << shift) | ENET_QOS_MAC_PPS_CONTROL_PPSEN0(1U);
1751
1752 base->MAC_PPS_CONTROL = reg;
1753
1754 return kStatus_Success;
1755 }
1756
1757 /*!
1758 * @brief Sets the ENET OQS PTP 1588 PPS target time registers.
1759 *
1760 * @param base ENET QOS peripheral base address.
1761 * @param instance The ENET QOS PTP PPS instance.
1762 * @param seconds The target seconds.
1763 * @param nanoseconds The target nanoseconds.
1764 */
1765 status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base,
1766 enet_qos_ptp_pps_instance_t instance,
1767 uint32_t seconds,
1768 uint32_t nanoseconds);
1769
1770 /*!
1771 * @brief Sets the ENET OQS PTP 1588 PPS output signal interval
1772 *
1773 * @param base ENET QOS peripheral base address.
1774 * @param instance The ENET QOS PTP PPS instance.
1775 * @param width Signal Width. It is stored in terms of number of
1776 * units of sub-second increment value. The width value must be
1777 * lesser than interval value.
1778 */
ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t width)1779 static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base,
1780 enet_qos_ptp_pps_instance_t instance,
1781 uint32_t width)
1782 {
1783 uint32_t *mac_pps_width;
1784
1785 mac_pps_width = (uint32_t *)((uintptr_t)&base->MAC_PPS0_WIDTH + 0x10U * (uint32_t)instance);
1786
1787 *mac_pps_width = ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(width);
1788 }
1789
1790 /*!
1791 * @brief Sets the ENET OQS PTP 1588 PPS output signal width
1792 *
1793 * @param base ENET QOS peripheral base address.
1794 * @param instance The ENET QOS PTP PPS instance.
1795 * @param interval Signal Interval. It is stored in terms of number of
1796 * units of sub-second increment value.
1797 */
ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t interval)1798 static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base,
1799 enet_qos_ptp_pps_instance_t instance,
1800 uint32_t interval)
1801 {
1802 uint32_t *mac_pps_interval;
1803
1804 mac_pps_interval = (uint32_t *)((uintptr_t)&base->MAC_PPS0_INTERVAL + 0x10U * (uint32_t)instance);
1805
1806 *mac_pps_interval = ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(interval);
1807 }
1808
1809 /*!
1810 * @brief Gets the current ENET time from the PTP 1588 timer.
1811 *
1812 * @param base ENET peripheral base address.
1813 * @param second The PTP 1588 system timer second.
1814 * @param nanosecond The PTP 1588 system timer nanosecond.
1815 * For the unit of the nanosecond is 1ns.so the nanosecond is the real nanosecond.
1816 */
1817 void ENET_QOS_Ptp1588GetTimer(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1818
1819 /*!
1820 * @brief Gets the time stamp of the transmit frame.
1821 *
1822 * This function is used for PTP stack to get the timestamp captured by the ENET driver.
1823 *
1824 * @param handle The ENET handler pointer.This is the same state pointer used in
1825 * ENET_QOS_Init.
1826 * @param txFrame Input parameter, pointer to @ref enet_qos_frame_info_t for saving read out frame information.
1827 * @param channel Channel for searching the tx frame.
1828 */
1829 void ENET_QOS_GetTxFrame(enet_qos_handle_t *handle, enet_qos_frame_info_t *txFrame, uint8_t channel);
1830
1831 /*!
1832 * @brief Receives one frame in specified BD ring with zero copy.
1833 *
1834 * This function will use the user-defined allocate and free callback. Every time application gets one frame through
1835 * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
1836 * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
1837 * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
1838 * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
1839 * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
1840 * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
1841 * to specific design in this case.
1842 *
1843 * @param base ENET peripheral base address.
1844 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
1845 * @param rxFrame The received frame information structure provided by user.
1846 * @param channel Channel for searching the rx frame.
1847 * @retval kStatus_Success Succeed to get one frame and allocate new memory for Rx buffer.
1848 * @retval kStatus_ENET_QOS_RxFrameEmpty There's no Rx frame in the BD.
1849 * @retval kStatus_ENET_QOS_RxFrameError There's issue in this receiving.
1850 * @retval kStatus_ENET_QOS_RxFrameDrop There's no new buffer memory for BD, drop this frame.
1851 */
1852 status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
1853 enet_qos_handle_t *handle,
1854 enet_qos_rx_frame_struct_t *rxFrame,
1855 uint8_t channel);
1856
1857 /*! @} */
1858
1859 #if defined(__cplusplus)
1860 }
1861 #endif
1862
1863 /*! @}*/
1864
1865 #endif /* FSL_ENET_QOS_H_ */
1866
