1 /* 2 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef _FSL_ENET_H_ 8 #define _FSL_ENET_H_ 9 10 #include "fsl_common.h" 11 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET 12 #include "fsl_memory.h" 13 #endif 14 /*! 15 * @addtogroup enet 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 23 /*! @name Driver version */ 24 /*@{*/ 25 /*! @brief Defines the driver version. */ 26 #define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) 27 /*@}*/ 28 29 /*! @name ENET DESCRIPTOR QUEUE */ 30 /*@{*/ 31 /*! @brief Defines the queue number. */ 32 #ifndef FSL_FEATURE_ENET_QUEUE 33 #define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ 34 #endif 35 /*@}*/ 36 37 /*! @name Control and status region bit masks of the receive buffer descriptor. */ 38 /*@{*/ 39 #define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ 40 #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ 41 #define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ 42 #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ 43 #define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ 44 #define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ 45 #define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ 46 #define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ 47 #define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ 48 #define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ 49 #define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ 50 #define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ 51 #define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ 52 /*@}*/ 53 54 /*! @name Control and status bit masks of the transmit buffer descriptor. */ 55 /*@{*/ 56 #define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ 57 #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ 58 #define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ 59 #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ 60 #define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ 61 #define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ 62 /*@}*/ 63 64 /* Extended control regions for enhanced buffer descriptors. */ 65 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 66 /*! @name First extended control region bit masks of the receive buffer descriptor. */ 67 /*@{*/ 68 #define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ 69 #define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ 70 #define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ 71 #define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ 72 #define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ 73 /*@}*/ 74 75 /*! @name Second extended control region bit masks of the receive buffer descriptor. */ 76 /*@{*/ 77 #define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ 78 #define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ 79 #define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ 80 #define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ 81 #define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ 82 /*@}*/ 83 84 /*! @name First extended control region bit masks of the transmit buffer descriptor. */ 85 /*@{*/ 86 #define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ 87 #define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ 88 #define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ 89 #define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ 90 #define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ 91 #define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ 92 #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ 93 /*@}*/ 94 95 /*! @name Second extended control region bit masks of the transmit buffer descriptor. */ 96 /*@{*/ 97 #define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ 98 #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ 99 #define ENET_BUFFDESCRIPTOR_TX_PROTOCHECKSUM_MASK 0x1000U /*!< Protocal checksum mask. */ 100 #define ENET_BUFFDESCRIPTOR_TX_IPCHECKSUM_MASK 0x0800U /*!< IP header checksum flag mask. */ 101 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 102 #define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ 103 #define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ 104 #define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ 105 #define ENET_BD_FTYPE(n) \ 106 (((uint32_t)(n) << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) 107 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 108 /*@}*/ 109 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 110 111 /*! @brief Defines the receive error status flag mask. */ 112 #define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ 113 (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ 114 ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) 115 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 116 #define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ 117 (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) 118 #endif 119 120 /*! @name Defines some Ethernet parameters. */ 121 /*@{*/ 122 #define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size without VLAN tag. */ 123 #define ENET_FRAME_VLAN_TAGLEN 4U /*!< Ethernet single VLAN tag size. */ 124 #define ENET_FRAME_CRC_LEN 4U /*!< CRC size in a frame. */ 125 #define ENET_FRAME_TX_LEN_LIMITATION(x) \ 126 ((((x)->RCR & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT) - ENET_FRAME_CRC_LEN) 127 128 #define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ 129 #define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ 130 #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) /*!< Maximum PHY address. */ 131 132 #if FSL_FEATURE_ENET_QUEUE > 1 133 #define ENET_TX_INTERRUPT \ 134 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt | (uint32_t)kENET_TxFrame1Interrupt | \ 135 (uint32_t)kENET_TxBuffer1Interrupt | (uint32_t)kENET_TxFrame2Interrupt | \ 136 (uint32_t)kENET_TxBuffer2Interrupt) /*!< Enet Tx interrupt flag. */ 137 #define ENET_RX_INTERRUPT \ 138 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt | (uint32_t)kENET_RxFrame1Interrupt | \ 139 (uint32_t)kENET_RxBuffer1Interrupt | (uint32_t)kENET_RxFrame2Interrupt | \ 140 (uint32_t)kENET_RxBuffer2Interrupt) /*!< Enet Rx interrupt flag. */ 141 #else 142 #define ENET_TX_INTERRUPT \ 143 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt) /*!< Enet Tx interrupt flag. */ 144 #define ENET_RX_INTERRUPT \ 145 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt) /*!< Enet Rx interrupt flag. */ 146 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 147 #define ENET_TS_INTERRUPT \ 148 ((uint32_t)kENET_TsTimerInterrupt | (uint32_t)kENET_TsAvailInterrupt) /*!< Enet timestamp interrupt flag. */ 149 #define ENET_ERR_INTERRUPT \ 150 ((uint32_t)kENET_BabrInterrupt | (uint32_t)kENET_BabtInterrupt | (uint32_t)kENET_EBusERInterrupt | \ 151 (uint32_t)kENET_LateCollisionInterrupt | (uint32_t)kENET_RetryLimitInterrupt | \ 152 (uint32_t)kENET_UnderrunInterrupt | (uint32_t)kENET_PayloadRxInterrupt) /*!< Enet error interrupt flag. */ 153 /*@}*/ 154 155 /*! @brief Defines the status return codes for transaction. */ 156 enum 157 { 158 kStatus_ENET_InitMemoryFail = 159 MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< Init fails since buffer memory is not enough. */ 160 kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< A frame received but data error happen. */ 161 kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< Failed to receive a frame. */ 162 kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< No frame arrive. */ 163 kStatus_ENET_RxFrameDrop = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Rx frame is dropped since no buffer memory. */ 164 kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Tx frame over length. */ 165 kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Tx buffer descriptors are under process. */ 166 kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 7U), /*!< Transmit frame fail. */ 167 }; 168 169 /*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ 170 typedef enum _enet_mii_mode 171 { 172 kENET_MiiMode = 0U, /*!< MII mode for data interface. */ 173 kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ 174 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 175 kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ 176 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 177 } enet_mii_mode_t; 178 179 /*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. 180 * 181 * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". 182 */ 183 typedef enum _enet_mii_speed 184 { 185 kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ 186 kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ 187 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 188 kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ 189 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 190 } enet_mii_speed_t; 191 192 /*! @brief Defines the half or full duplex for the MII data interface. */ 193 typedef enum _enet_mii_duplex 194 { 195 kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ 196 kENET_MiiFullDuplex /*!< Full duplex mode. */ 197 } enet_mii_duplex_t; 198 199 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ 200 typedef enum _enet_mii_write 201 { 202 kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ 203 kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ 204 } enet_mii_write_t; 205 206 /*! @brief Defines the read operation for the MII management frame. */ 207 typedef enum _enet_mii_read 208 { 209 kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ 210 kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ 211 } enet_mii_read_t; 212 213 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO 214 /*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ 215 typedef enum _enet_mii_extend_opcode 216 { 217 kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ 218 kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ 219 kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ 220 } enet_mii_extend_opcode; 221 #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ 222 223 /*! @brief Defines a special configuration for ENET MAC controller. 224 * 225 * These control flags are provided for special user requirements. 226 * Normally, these control flags are unused for ENET initialization. 227 * For special requirements, set the flags to 228 * macSpecialConfig in the enet_config_t. 229 * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store 230 * and forward. FIFO store and forward means that the FIFO read/send is started 231 * when a complete frame is stored in TX/RX FIFO. If this flag is set, 232 * configure rxFifoFullThreshold and txFifoWatermark 233 * in the enet_config_t. 234 */ 235 typedef enum _enet_special_control_flag 236 { 237 kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ 238 kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ 239 kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ 240 kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ 241 kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ 242 kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ 243 kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ 244 kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ 245 kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ 246 kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ 247 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 248 kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ 249 kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ 250 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 251 } enet_special_control_flag_t; 252 253 /*! @brief List of interrupts supported by the peripheral. This 254 * enumeration uses one-bit encoding to allow a logical OR of multiple 255 * members. Members usually map to interrupt enable bits in one or more 256 * peripheral registers. 257 */ 258 typedef enum _enet_interrupt_enable 259 { 260 kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ 261 kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ 262 kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ 263 kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ 264 kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ 265 kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ 266 kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ 267 kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ 268 kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ 269 kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ 270 kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ 271 kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ 272 kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ 273 kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ 274 #if FSL_FEATURE_ENET_QUEUE > 1 275 kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ 276 kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ 277 kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ 278 kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ 279 kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ 280 kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ 281 kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ 282 kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ 283 kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ 284 kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ 285 kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ 286 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 287 kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ 288 kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ 289 } enet_interrupt_enable_t; 290 291 /*! @brief Defines the common interrupt event for callback use. */ 292 typedef enum _enet_event 293 { 294 kENET_RxEvent, /*!< Receive event. */ 295 kENET_TxEvent, /*!< Transmit event. */ 296 kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ 297 kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ 298 kENET_TimeStampEvent, /*!< Time stamp event. */ 299 kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ 300 } enet_event_t; 301 302 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 303 /*! @brief Defines certain idle slope for bandwidth fraction. */ 304 typedef enum _enet_idle_slope 305 { 306 kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ 307 kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ 308 kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ 309 kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ 310 kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ 311 kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ 312 kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ 313 kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ 314 kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ 315 kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ 316 kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ 317 kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ 318 kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ 319 kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ 320 kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ 321 kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ 322 kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ 323 kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ 324 kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ 325 } enet_idle_slope_t; 326 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 327 328 /*! @brief Defines the transmit accelerator configuration. */ 329 typedef enum _enet_tx_accelerator 330 { 331 kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ 332 kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ 333 kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ 334 } enet_tx_accelerator_t; 335 336 /*! @brief Defines the receive accelerator configuration. */ 337 typedef enum _enet_rx_accelerator 338 { 339 kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ 340 kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ 341 kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ 342 kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ 343 kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ 344 } enet_rx_accelerator_t; 345 346 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 347 /*! @brief Defines the ENET PTP message related constant. */ 348 typedef enum _enet_ptp_event_type 349 { 350 kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ 351 kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ 352 kENET_PtpEventPort = 319U, /*!< PTP event port number. */ 353 kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ 354 } enet_ptp_event_type_t; 355 356 /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ 357 typedef enum _enet_ptp_timer_channel 358 { 359 kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ 360 kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ 361 kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ 362 kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ 363 } enet_ptp_timer_channel_t; 364 365 /*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ 366 typedef enum _enet_ptp_timer_channel_mode 367 { 368 kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ 369 kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ 370 kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ 371 kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ 372 kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ 373 kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ 374 kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ 375 kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ 376 kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ 377 kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ 378 kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ 379 kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ 380 } enet_ptp_timer_channel_mode_t; 381 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 382 383 /*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ 384 typedef struct _enet_rx_bd_struct 385 { 386 uint16_t length; /*!< Buffer descriptor data length. */ 387 uint16_t control; /*!< Buffer descriptor control and status. */ 388 uint32_t buffer; /*!< Data buffer pointer. */ 389 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 390 uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ 391 uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ 392 uint16_t payloadCheckSum; /*!< Internal payload checksum. */ 393 uint8_t headerLength; /*!< Header length. */ 394 uint8_t protocolTyte; /*!< Protocol type. */ 395 uint16_t reserved0; 396 uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ 397 uint32_t timestamp; /*!< Timestamp. */ 398 uint16_t reserved1; 399 uint16_t reserved2; 400 uint16_t reserved3; 401 uint16_t reserved4; 402 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 403 } enet_rx_bd_struct_t; 404 405 /*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ 406 typedef struct _enet_tx_bd_struct 407 { 408 uint16_t length; /*!< Buffer descriptor data length. */ 409 uint16_t control; /*!< Buffer descriptor control and status. */ 410 uint32_t buffer; /*!< Data buffer pointer. */ 411 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 412 uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ 413 uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ 414 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 415 uint16_t txLaunchTimeLow; /*!< Low 16-bits of transmit launch time. */ 416 uint16_t txLaunchTimeHigh; /*!< High 16-bits of transmit launch time. */ 417 #else 418 uint16_t reserved0; 419 uint16_t reserved1; 420 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 421 uint16_t reserved2; 422 uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ 423 uint32_t timestamp; /*!< Timestamp. */ 424 uint16_t reserved3; 425 uint16_t reserved4; 426 uint16_t reserved5; 427 uint16_t reserved6; 428 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 429 } enet_tx_bd_struct_t; 430 431 /*! @brief Defines the ENET data error statistics structure. */ 432 typedef struct _enet_data_error_stats 433 { 434 uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ 435 uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ 436 uint32_t statsRxFcsErr; /*!< Receive CRC error. */ 437 uint32_t statsRxOverRunErr; /*!< Receive over run. */ 438 uint32_t statsRxTruncateErr; /*!< Receive truncate. */ 439 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 440 uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ 441 uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ 442 uint32_t statsRxMacErr; /*!< Receive Mac error. */ 443 uint32_t statsRxPhyErr; /*!< Receive PHY error. */ 444 uint32_t statsRxCollisionErr; /*!< Receive collision. */ 445 uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ 446 uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ 447 uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ 448 uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ 449 uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ 450 uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ 451 uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ 452 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 453 } enet_data_error_stats_t; 454 455 /*! @brief Defines the Rx frame error structure. */ 456 typedef struct _enet_rx_frame_error 457 { 458 bool statsRxTruncateErr : 1; /*!< Receive truncate. */ 459 bool statsRxOverRunErr : 1; /*!< Receive over run. */ 460 bool statsRxFcsErr : 1; /*!< Receive CRC error. */ 461 bool : 1; 462 bool statsRxAlignErr : 1; /*!< Receive non-octet alignment. */ 463 bool statsRxLenGreaterErr : 1; /*!< Receive length greater than RCR[MAX_FL]. */ 464 uint32_t : 19; 465 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 466 bool statsRxCollisionErr : 1; /*!< Receive collision. */ 467 bool statsRxPhyErr : 1; /*!< Receive PHY error. */ 468 uint8_t : 4; 469 bool statsRxMacErr : 1; /*!< Receive Mac error. */ 470 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 471 } enet_rx_frame_error_t; 472 473 /*! @brief Defines the ENET transfer statistics structure. */ 474 typedef struct _enet_transfer_stats 475 { 476 uint32_t statsRxFrameCount; /*!< Rx frame number. */ 477 uint32_t statsRxFrameOk; /*!< Good Rx frame number. */ 478 uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */ 479 uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */ 480 uint32_t statsRxDropInvalidSFD; /*!< Dropped frame number due to invalid SFD. */ 481 uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */ 482 uint32_t statsTxFrameCount; /*!< Tx frame number. */ 483 uint32_t statsTxFrameOk; /*!< Good Tx frame number. */ 484 uint32_t statsTxCrcAlignErr; /*!< The transmit frame is error. */ 485 uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */ 486 } enet_transfer_stats_t; 487 488 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 489 /*! @brief Defines the ENET PTP time stamp structure. */ 490 typedef struct _enet_ptp_time 491 { 492 uint64_t second; /*!< Second. */ 493 uint32_t nanosecond; /*!< Nanosecond. */ 494 } enet_ptp_time_t; 495 496 /*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ 497 typedef struct _enet_ptp_time_data 498 { 499 uint8_t version; /*!< PTP version. */ 500 uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ 501 uint16_t sequenceId; /*!< PTP sequence ID. */ 502 uint8_t messageType; /*!< PTP message type. */ 503 enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ 504 } enet_ptp_time_data_t; 505 506 /*! @brief Defines the ENET PTP configuration structure. */ 507 typedef struct _enet_ptp_config 508 { 509 enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ 510 uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ 511 } enet_ptp_config_t; 512 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 513 514 /*! @brief Defines the frame info structure. */ 515 typedef struct enet_frame_info 516 { 517 void *context; /*!< User specified data */ 518 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 519 bool isTsAvail; /*!< Flag indicates timestamp available status */ 520 enet_ptp_time_t timeStamp; /*!< Timestamp of frame */ 521 #endif 522 } enet_frame_info_t; 523 524 /*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */ 525 typedef struct _enet_tx_dirty_ring 526 { 527 enet_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */ 528 uint16_t txGenIdx; /*!< tx generate index. */ 529 uint16_t txConsumIdx; /*!< tx consume index. */ 530 uint16_t txRingLen; /*!< tx ring length. */ 531 bool isFull; /*!< tx ring is full flag. */ 532 } enet_tx_dirty_ring_t; 533 534 /*! @brief Defines the ENET Rx memory buffer alloc function pointer. */ 535 typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId); 536 537 /*! @brief Defines the ENET Rx memory buffer free function pointer. */ 538 typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId); 539 540 /*! @brief Defines the receive buffer descriptor configuration structure. 541 * 542 * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. 543 * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. 544 * when the data buffers are in cacheable region when cache is enabled, all those size should be 545 * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 546 * 2. The aligned transmit and receive buffer descriptor start address must be at 547 * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. 548 * buffer descriptors should be put in non-cacheable region when cache is enabled. 549 * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. 550 * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". 551 * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". 552 * when the data buffers are in cacheable region when cache is enabled, all those size should be 553 * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 554 */ 555 typedef struct _enet_buffer_config 556 { 557 uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ 558 uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ 559 uint16_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ 560 uint16_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ 561 volatile enet_rx_bd_struct_t 562 *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ 563 volatile enet_tx_bd_struct_t 564 *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ 565 uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ 566 uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ 567 bool rxMaintainEnable; /*!< Receive buffer cache maintain. */ 568 bool txMaintainEnable; /*!< Transmit buffer cache maintain. */ 569 enet_frame_info_t *txFrameInfo; /*!< Transmit frame information start address. */ 570 } enet_buffer_config_t; 571 572 #if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE 573 /*! @brief Defines the interrupt coalescing configure structure. */ 574 typedef struct _enet_intcoalesce_config 575 { 576 uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ 577 uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ 578 uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ 579 uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ 580 } enet_intcoalesce_config_t; 581 #endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ 582 583 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 584 /*! @brief Defines the ENET AVB Configure structure. 585 * 586 * This is used for to configure the extended ring 1 and ring 2. 587 * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. 588 * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. 589 * 590 * If CMP1,2,3 are not unused, please set them to the same value as CMP0. 591 * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). 592 * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. 593 */ 594 typedef struct _enet_avb_config 595 { 596 uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ 597 enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ 598 } enet_avb_config_t; 599 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 600 601 /* Forward declaration of the handle typedef. */ 602 typedef struct _enet_handle enet_handle_t; 603 604 /*! @brief ENET callback function. */ 605 typedef void (*enet_callback_t)(ENET_Type *base, 606 enet_handle_t *handle, 607 #if FSL_FEATURE_ENET_QUEUE > 1 608 uint32_t ringId, 609 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 610 enet_event_t event, 611 enet_frame_info_t *frameInfo, 612 void *userData); 613 614 /*! @brief Defines the basic configuration structure for the ENET device. 615 * 616 * Note: 617 * 1. macSpecialConfig is used for a special control configuration, A logical OR of 618 * "enet_special_control_flag_t". For a special configuration for MAC, 619 * set this parameter to 0. 620 * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 621 * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 622 * 2 - 128 bytes written to TX FIFO .... 623 * 3 - 192 bytes written to TX FIFO .... 624 * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... 625 * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 626 * or for larger bus access latency 3 or larger due to contention for the system bus. 627 * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. 628 * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. 629 * If the end of the frame is stored in FIFO and the frame size if smaller than the 630 * txWatermark, the frame is still transmitted. The rule is the 631 * same for rxFifoFullThreshold in the receive direction. 632 * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure 633 * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold 634 * are set for flow control enabled case. 635 * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure 636 * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. 637 * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator 638 * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are 639 * recommended to be used to enable the transmit and receive accelerator. 640 * After the accelerators are enabled, the store and forward feature should be enabled. 641 * As a result, kENET_ControlStoreAndFwdDisabled should not be set. 642 * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. 643 */ 644 typedef struct _enet_config 645 { 646 uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ 647 uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ 648 uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ 649 enet_mii_mode_t miiMode; /*!< MII mode. */ 650 enet_mii_speed_t miiSpeed; /*!< MII Speed. */ 651 enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ 652 uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ 653 uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ 654 uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ 655 uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, 656 it makes MAC generate XOFF pause frame. */ 657 #if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD 658 uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, 659 independent of size, that can be accept. If the limit is reached, reception 660 continues and a pause frame is triggered. */ 661 #endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ 662 uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify 663 the MAC receive ready status. */ 664 uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO 665 before a frame transmit start. */ 666 #if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE 667 enet_intcoalesce_config_t *intCoalesceCfg; /*!< If the interrupt coalsecence is not required in the ring n(0,1,2), 668 please set to NULL. */ 669 #endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ 670 uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ 671 enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback function to alloc memory, must be provided for zero-copy Rx. */ 672 enet_rx_free_callback_t rxBuffFree; /*!< Callback function to free memory, must be provided for zero-copy Rx. */ 673 enet_callback_t callback; /*!< General callback function. */ 674 void *userData; /*!< Callback function parameter.*/ 675 } enet_config_t; 676 677 /*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */ 678 typedef struct _enet_tx_bd_ring 679 { 680 volatile enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */ 681 uint16_t txGenIdx; /*!< The current available transmit buffer descriptor pointer. */ 682 uint16_t txConsumIdx; /*!< Transmit consume index. */ 683 volatile uint16_t txDescUsed; /*!< Transmit descriptor used number. */ 684 uint16_t txRingLen; /*!< Transmit ring length. */ 685 } enet_tx_bd_ring_t; 686 687 /*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */ 688 typedef struct _enet_rx_bd_ring 689 { 690 volatile enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */ 691 uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */ 692 uint16_t rxRingLen; /*!< Receive ring length. */ 693 } enet_rx_bd_ring_t; 694 695 /*! @brief Defines the ENET handler structure. */ 696 struct _enet_handle 697 { 698 enet_rx_bd_ring_t rxBdRing[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor. */ 699 enet_tx_bd_ring_t txBdRing[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor. */ 700 uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ 701 uint16_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ 702 bool rxMaintainEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer cache maintain. */ 703 bool txMaintainEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer cache maintain. */ 704 uint8_t ringNum; /*!< Number of used rings. */ 705 enet_callback_t callback; /*!< Callback function. */ 706 void *userData; /*!< Callback function parameter.*/ 707 enet_tx_dirty_ring_t txDirtyRing[FSL_FEATURE_ENET_QUEUE]; /*!< Ring to store tx frame information.*/ 708 bool txReclaimEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Tx reclaim enable flag.*/ 709 enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback function to alloc memory for zero copy Rx. */ 710 enet_rx_free_callback_t rxBuffFree; /*!< Callback function to free memory for zero copy Rx. */ 711 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 712 volatile enet_tx_bd_struct_t 713 *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ 714 uint64_t msTimerSecond; /*!< The second for Master PTP timer. */ 715 #endif 716 uint8_t multicastCount[64]; /*!< Multicast collisions counter */ 717 #if defined(FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID) && FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID 718 uint32_t enetClock; /*!< The clock of enet peripheral, to caculate core cycles for PTP timestamp.*/ 719 uint32_t tsDelayCount; /*!< The count of core cycles for PTP timestamp capture delay.*/ 720 #endif 721 }; 722 723 typedef struct _enet_buffer_struct 724 { 725 void *buffer; /*!< The buffer store the whole or partial frame. */ 726 uint16_t length; /*!< The byte length of this buffer. */ 727 } enet_buffer_struct_t; 728 729 typedef struct _enet_rx_frame_attribute_struct 730 { 731 bool promiscuous; /*!< This frame is received because of promiscuous mode. */ 732 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 733 uint32_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */ 734 #endif 735 } enet_rx_frame_attribute_t; 736 737 typedef struct _enet_rx_frame_struct 738 { 739 enet_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */ 740 uint16_t totLen; /*!< Rx frame total length. */ 741 enet_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */ 742 enet_rx_frame_error_t rxFrameError; /*!< Rx frame error. */ 743 } enet_rx_frame_struct_t; 744 745 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 746 typedef struct _enet_tx_config_struct 747 { 748 bool intEnable : 1; 749 bool tsEnable : 1; 750 bool autoProtocolChecksum : 1; 751 bool autoIPChecksum : 1; 752 uint8_t AVBFrameType : 4; /*!< AVB class type. */ 753 bool tltEnable : 1; /*!< Transmit launch time enable. */ 754 uint16_t tltLow; /*!< Specifies when frame can be transmitted. */ 755 uint16_t tltHigh; /*!< Specifies when frame can be transmitted. */ 756 } enet_tx_config_struct_t; 757 #endif 758 759 typedef struct _enet_tx_frame_struct 760 { 761 enet_buffer_struct_t *txBuffArray; /*!< Tx frame buffer structure. */ 762 uint32_t txBuffNum; /*!< Buffer number of this Tx frame. */ 763 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 764 enet_tx_config_struct_t txConfig; /*!< Tx extra configuation. */ 765 #endif 766 void *context; /*!< Driver reclaims and gives it in Tx over callback, usually store network packet header. */ 767 } enet_tx_frame_struct_t; 768 769 /*! @brief Define interrupt IRQ handler. */ 770 #if FSL_FEATURE_ENET_QUEUE > 1 771 typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 772 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 773 typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); 774 775 /*! @brief Pointers to enet clocks for each instance. */ 776 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) 777 extern const clock_ip_name_t s_enetClock[]; 778 #if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE 779 extern const clock_ip_name_t s_enetExtraClock[]; 780 #endif 781 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ 782 783 /******************************************************************************* 784 * API 785 ******************************************************************************/ 786 787 #if defined(__cplusplus) 788 extern "C" { 789 #endif 790 791 /*! 792 * @brief Get the ENET instance from peripheral base address. 793 * 794 * @param base ENET peripheral base address. 795 * @return ENET instance. 796 */ 797 uint32_t ENET_GetInstance(ENET_Type *base); 798 799 /*! 800 * @name Initialization and De-initialization 801 * @{ 802 */ 803 804 /*! 805 * @brief Gets the ENET default configuration structure. 806 * 807 * The purpose of this API is to get the default ENET MAC controller 808 * configure structure for ENET_Init(). User may use the initialized 809 * structure unchanged in ENET_Init(), or modify some fields of the 810 * structure before calling ENET_Init(). 811 * Example: 812 @code 813 enet_config_t config; 814 ENET_GetDefaultConfig(&config); 815 @endcode 816 * @param config The ENET mac controller configuration structure pointer. 817 */ 818 void ENET_GetDefaultConfig(enet_config_t *config); 819 820 /*! 821 * @brief Initializes the ENET module. 822 * 823 * This function initializes the module with the ENET configuration. 824 * @note ENET has two buffer descriptors legacy buffer descriptors and 825 * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To 826 * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor 827 * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() 828 * to configure the 1588 feature and related buffers after calling ENET_Up(). 829 * 830 * @param base ENET peripheral base address. 831 * @param handle ENET handler pointer. 832 * @param config ENET mac configuration structure pointer. 833 * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig 834 * can be used directly. It is also possible to verify the Mac configuration using other methods. 835 * @param bufferConfig ENET buffer configuration structure pointer. 836 * The buffer configuration should be prepared for ENET Initialization. 837 * It is the start address of "ringNum" enet_buffer_config structures. 838 * To support added multi-ring features in some soc and compatible with the previous 839 * enet driver version. For single ring supported, this bufferConfig is a buffer 840 * configure structure pointer, for multi-ring supported and used case, this bufferConfig 841 * pointer should be a buffer configure structure array pointer. 842 * @param macAddr ENET mac address of Ethernet device. This MAC address should be 843 * provided. 844 * @param srcClock_Hz The internal module clock source for MII clock. 845 * @retval kStatus_Success Succeed to initialize the ethernet driver. 846 * @retval kStatus_ENET_InitMemoryFail Init fails since buffer memory is not enough. 847 * 848 */ 849 status_t ENET_Up(ENET_Type *base, 850 enet_handle_t *handle, 851 const enet_config_t *config, 852 const enet_buffer_config_t *bufferConfig, 853 uint8_t *macAddr, 854 uint32_t srcClock_Hz); 855 856 /*! 857 * @brief Initializes the ENET module. 858 * 859 * This function ungates the module clock and initializes it with the ENET configuration. 860 * @note ENET has two buffer descriptors legacy buffer descriptors and 861 * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To 862 * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor 863 * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() 864 * to configure the 1588 feature and related buffers after calling ENET_Init(). 865 * 866 * @param base ENET peripheral base address. 867 * @param handle ENET handler pointer. 868 * @param config ENET mac configuration structure pointer. 869 * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig 870 * can be used directly. It is also possible to verify the Mac configuration using other methods. 871 * @param bufferConfig ENET buffer configuration structure pointer. 872 * The buffer configuration should be prepared for ENET Initialization. 873 * It is the start address of "ringNum" enet_buffer_config structures. 874 * To support added multi-ring features in some soc and compatible with the previous 875 * enet driver version. For single ring supported, this bufferConfig is a buffer 876 * configure structure pointer, for multi-ring supported and used case, this bufferConfig 877 * pointer should be a buffer configure structure array pointer. 878 * @param macAddr ENET mac address of Ethernet device. This MAC address should be 879 * provided. 880 * @param srcClock_Hz The internal module clock source for MII clock. 881 * @retval kStatus_Success Succeed to initialize the ethernet driver. 882 * @retval kStatus_ENET_InitMemoryFail Init fails since buffer memory is not enough. 883 */ 884 status_t ENET_Init(ENET_Type *base, 885 enet_handle_t *handle, 886 const enet_config_t *config, 887 const enet_buffer_config_t *bufferConfig, 888 uint8_t *macAddr, 889 uint32_t srcClock_Hz); 890 891 /*! 892 * @brief Stops the ENET module. 893 894 * This function disables the ENET module. 895 * 896 * @param base ENET peripheral base address. 897 */ 898 void ENET_Down(ENET_Type *base); 899 900 /*! 901 * @brief Deinitializes the ENET module. 902 903 * This function gates the module clock, clears ENET interrupts, and disables the ENET module. 904 * 905 * @param base ENET peripheral base address. 906 */ 907 void ENET_Deinit(ENET_Type *base); 908 909 /*! 910 * @brief Resets the ENET module. 911 * 912 * This function restores the ENET module to reset state. 913 * Note that this function sets all registers to 914 * reset state. As a result, the ENET module can't work after calling this function. 915 * 916 * @param base ENET peripheral base address. 917 */ ENET_Reset(ENET_Type * base)918 static inline void ENET_Reset(ENET_Type *base) 919 { 920 base->ECR |= ENET_ECR_RESET_MASK; 921 } 922 923 /* @} */ 924 925 /*! 926 * @name MII interface operation 927 * @{ 928 */ 929 930 /*! 931 * @brief Sets the ENET MII speed and duplex. 932 * 933 * This API is provided to dynamically change the speed and dulpex for MAC. 934 * 935 * @param base ENET peripheral base address. 936 * @param speed The speed of the RMII mode. 937 * @param duplex The duplex of the RMII mode. 938 */ 939 void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); 940 941 /*! 942 * @brief Sets the ENET SMI(serial management interface)- MII management interface. 943 * 944 * @param base ENET peripheral base address. 945 * @param srcClock_Hz This is the ENET module clock frequency. See clock distribution. 946 * @param isPreambleDisabled The preamble disable flag. 947 * - true Enables the preamble. 948 * - false Disables the preamble. 949 */ 950 void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); 951 952 /*! 953 * @brief Gets the ENET SMI- MII management interface configuration. 954 * 955 * This API is used to get the SMI configuration to check whether the MII management 956 * interface has been set. 957 * 958 * @param base ENET peripheral base address. 959 * @return The SMI setup status true or false. 960 */ ENET_GetSMI(ENET_Type * base)961 static inline bool ENET_GetSMI(ENET_Type *base) 962 { 963 return (0U != (base->MSCR & 0x7EU)); 964 } 965 966 /*! 967 * @brief Reads data from the PHY register through an SMI interface. 968 * 969 * @param base ENET peripheral base address. 970 * @return The data read from PHY 971 */ ENET_ReadSMIData(ENET_Type * base)972 static inline uint32_t ENET_ReadSMIData(ENET_Type *base) 973 { 974 return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); 975 } 976 977 /*! 978 * @brief Sends the MDIO IEEE802.3 Clause 22 format write command. 979 * 980 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 981 * For ease of use, encapsulated ENET_MDIOWrite() can be called. For customized requirements, implement 982 * with combining separated APIs. 983 * 984 * @param base ENET peripheral base address. 985 * @param phyAddr The PHY address. Range from 0 ~ 31. 986 * @param regAddr The PHY register address. Range from 0 ~ 31. 987 * @param operation The write operation. 988 * @param data The data written to PHY. 989 */ ENET_StartSMIWrite(ENET_Type * base,uint8_t phyAddr,uint8_t regAddr,enet_mii_write_t operation,uint16_t data)990 static inline void ENET_StartSMIWrite( 991 ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data) 992 { 993 base->MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | 994 ENET_MMFR_TA(2U) | data; 995 } 996 997 /*! 998 * @brief Sends the MDIO IEEE802.3 Clause 22 format read command. 999 * 1000 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1001 * For ease of use, encapsulated ENET_MDIORead() can be called. For customized requirements, implement 1002 * with combining separated APIs. 1003 * 1004 * @param base ENET peripheral base address. 1005 * @param phyAddr The PHY address. Range from 0 ~ 31. 1006 * @param regAddr The PHY register address. Range from 0 ~ 31. 1007 * @param operation The read operation. 1008 */ ENET_StartSMIRead(ENET_Type * base,uint8_t phyAddr,uint8_t regAddr,enet_mii_read_t operation)1009 static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation) 1010 { 1011 base->MMFR = 1012 ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | ENET_MMFR_TA(2U); 1013 } 1014 1015 /*! 1016 * @brief MDIO write with IEEE802.3 Clause 22 format. 1017 * 1018 * @param base ENET peripheral base address. 1019 * @param phyAddr The PHY address. Range from 0 ~ 31. 1020 * @param regAddr The PHY register. Range from 0 ~ 31. 1021 * @param data The data written to PHY. 1022 * @return kStatus_Success MDIO access succeeds. 1023 * @return kStatus_Timeout MDIO access timeout. 1024 */ 1025 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data); 1026 1027 /*! 1028 * @brief MDIO read with IEEE802.3 Clause 22 format. 1029 * 1030 * @param base ENET peripheral base address. 1031 * @param phyAddr The PHY address. Range from 0 ~ 31. 1032 * @param regAddr The PHY register. Range from 0 ~ 31. 1033 * @param pData The data read from PHY. 1034 * @return kStatus_Success MDIO access succeeds. 1035 * @return kStatus_Timeout MDIO access timeout. 1036 */ 1037 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData); 1038 1039 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO 1040 /*! 1041 * @brief Sends the MDIO IEEE802.3 Clause 45 format write register command. 1042 * 1043 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1044 * For ease of use, encapsulated ENET_MDIOC45Write()/ENET_MDIOC45Read() can be called. For customized 1045 * requirements, implement with combining separated APIs. 1046 * 1047 * @param base ENET peripheral base address. 1048 * @param portAddr The MDIO port address(PHY address). 1049 * @param devAddr The device address. 1050 * @param regAddr The PHY register address. 1051 */ ENET_StartExtC45SMIWriteReg(ENET_Type * base,uint8_t portAddr,uint8_t devAddr,uint16_t regAddr)1052 static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr) 1053 { 1054 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(portAddr) | 1055 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); 1056 } 1057 1058 /*! 1059 * @brief Sends the MDIO IEEE802.3 Clause 45 format write data command. 1060 * 1061 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1062 * For ease of use, encapsulated ENET_MDIOC45Write() can be called. For customized requirements, implement 1063 * with combining separated APIs. 1064 * 1065 * @param base ENET peripheral base address. 1066 * @param portAddr The MDIO port address(PHY address). 1067 * @param devAddr The device address. 1068 * @param data The data written to PHY. 1069 */ ENET_StartExtC45SMIWriteData(ENET_Type * base,uint8_t portAddr,uint8_t devAddr,uint16_t data)1070 static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data) 1071 { 1072 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(portAddr) | 1073 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); 1074 } 1075 1076 /*! 1077 * @brief Sends the MDIO IEEE802.3 Clause 45 format read data command. 1078 * 1079 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1080 * For ease of use, encapsulated ENET_MDIOC45Read() can be called. For customized requirements, implement 1081 * with combining separated APIs. 1082 * 1083 * @param base ENET peripheral base address. 1084 * @param portAddr The MDIO port address(PHY address). 1085 * @param devAddr The device address. 1086 */ ENET_StartExtC45SMIReadData(ENET_Type * base,uint8_t portAddr,uint8_t devAddr)1087 static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr) 1088 { 1089 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(portAddr) | 1090 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2); 1091 } 1092 1093 /*! 1094 * @brief MDIO write with IEEE802.3 Clause 45 format. 1095 * 1096 * @param base ENET peripheral base address. 1097 * @param portAddr The MDIO port address(PHY address). 1098 * @param devAddr The device address. 1099 * @param regAddr The PHY register address. 1100 * @param data The data written to PHY. 1101 * @return kStatus_Success MDIO access succeeds. 1102 * @return kStatus_Timeout MDIO access timeout. 1103 */ 1104 status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data); 1105 1106 /*! 1107 * @brief MDIO read with IEEE802.3 Clause 45 format. 1108 * 1109 * @param base ENET peripheral base address. 1110 * @param portAddr The MDIO port address(PHY address). 1111 * @param devAddr The device address. 1112 * @param regAddr The PHY register address. 1113 * @param pData The data read from PHY. 1114 * @return kStatus_Success MDIO access succeeds. 1115 * @return kStatus_Timeout MDIO access timeout. 1116 */ 1117 status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData); 1118 #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ 1119 1120 #if ((defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) || \ 1121 (defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY)) 1122 /*! 1123 * @brief Control the usage of the delayed tx/rx RGMII clock. 1124 * 1125 * @param base ENET peripheral base address. 1126 * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. 1127 * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. 1128 */ ENET_SetRGMIIClockDelay(ENET_Type * base,bool txEnabled,bool rxEnabled)1129 static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) 1130 { 1131 uint32_t ecrReg = base->ECR; 1132 1133 #if defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY 1134 /* Set for transmit clock delay. */ 1135 if (txEnabled) 1136 { 1137 ecrReg |= ENET_ECR_TXC_DLY_MASK; 1138 } 1139 else 1140 { 1141 ecrReg &= ~ENET_ECR_TXC_DLY_MASK; 1142 } 1143 #endif /* FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY */ 1144 1145 #if defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY 1146 /* Set for receive clock delay. */ 1147 if (rxEnabled) 1148 { 1149 ecrReg |= ENET_ECR_RXC_DLY_MASK; 1150 } 1151 else 1152 { 1153 ecrReg &= ~ENET_ECR_RXC_DLY_MASK; 1154 } 1155 #endif /* FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY */ 1156 base->ECR = ecrReg; 1157 } 1158 #endif 1159 1160 /* @} */ 1161 1162 /*! 1163 * @name MAC Address Filter 1164 * @{ 1165 */ 1166 1167 /*! 1168 * @brief Sets the ENET module Mac address. 1169 * 1170 * @param base ENET peripheral base address. 1171 * @param macAddr The six-byte Mac address pointer. 1172 * The pointer is allocated by application and input into the API. 1173 */ 1174 void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); 1175 1176 /*! 1177 * @brief Gets the ENET module Mac address. 1178 * 1179 * @param base ENET peripheral base address. 1180 * @param macAddr The six-byte Mac address pointer. 1181 * The pointer is allocated by application and input into the API. 1182 */ 1183 void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); 1184 1185 /*! 1186 * @brief Adds the ENET device to a multicast group. 1187 * 1188 * @param base ENET peripheral base address. 1189 * @param address The six-byte multicast group address which is provided by application. 1190 */ 1191 void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); 1192 1193 /*! 1194 * @brief Moves the ENET device from a multicast group. 1195 * 1196 * @param base ENET peripheral base address. 1197 * @param address The six-byte multicast group address which is provided by application. 1198 */ 1199 void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); 1200 1201 /* @} */ 1202 1203 /*! 1204 * @name Other basic operation 1205 * @{ 1206 */ 1207 1208 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1209 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 1210 /*! 1211 * @brief Sets the ENET AVB feature. 1212 * 1213 * ENET AVB feature configuration, set the Receive classification match and transmit 1214 * bandwidth. This API is called when the AVB feature is required. 1215 * 1216 * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported 1217 * with the Enhanced buffer descriptors. so the AVB configuration should only done with 1218 * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the 1219 * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. 1220 * 1221 * @param base ENET peripheral base address. 1222 * @param handle ENET handler pointer. 1223 * @param config The ENET AVB feature configuration structure. 1224 */ 1225 void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); 1226 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 1227 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1228 1229 /*! 1230 * @brief Activates frame reception for multiple rings. 1231 * 1232 * This function is to active the enet read process. 1233 * @note This must be called after the MAC configuration and 1234 * state are ready. It must be called after the ENET_Init(). 1235 * This should be called when the frame reception is required. 1236 * 1237 * @param base ENET peripheral base address. 1238 */ ENET_ActiveRead(ENET_Type * base)1239 static inline void ENET_ActiveRead(ENET_Type *base) 1240 { 1241 base->RDAR = ENET_RDAR_RDAR_MASK; 1242 #if FSL_FEATURE_ENET_QUEUE > 1 1243 if (FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) > 1) 1244 { 1245 base->RDAR1 = ENET_RDAR1_RDAR_MASK; 1246 base->RDAR2 = ENET_RDAR2_RDAR_MASK; 1247 } 1248 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1249 } 1250 1251 /*! 1252 * @brief Enables/disables the MAC to enter sleep mode. 1253 * This function is used to set the MAC enter sleep mode. 1254 * When entering sleep mode, the magic frame wakeup interrupt should be enabled 1255 * to wake up MAC from the sleep mode and reset it to normal mode. 1256 * 1257 * @param base ENET peripheral base address. 1258 * @param enable True enable sleep mode, false disable sleep mode. 1259 */ ENET_EnableSleepMode(ENET_Type * base,bool enable)1260 static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) 1261 { 1262 if (enable) 1263 { 1264 /* When this field is set, MAC enters sleep mode. */ 1265 base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; 1266 } 1267 else 1268 { /* MAC exits sleep mode. */ 1269 base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); 1270 } 1271 } 1272 1273 /*! 1274 * @brief Gets ENET transmit and receive accelerator functions from MAC controller. 1275 * 1276 * @param base ENET peripheral base address. 1277 * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is 1278 * recommended to be used to as the mask to get the exact the accelerator option. 1279 * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is 1280 * recommended to be used to as the mask to get the exact the accelerator option. 1281 */ ENET_GetAccelFunction(ENET_Type * base,uint32_t * txAccelOption,uint32_t * rxAccelOption)1282 static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) 1283 { 1284 assert(txAccelOption != NULL); 1285 assert(txAccelOption != NULL); 1286 1287 *txAccelOption = base->TACC; 1288 *rxAccelOption = base->RACC; 1289 } 1290 1291 /* @} */ 1292 1293 /*! 1294 * @name Interrupts. 1295 * @{ 1296 */ 1297 1298 /*! 1299 * @brief Enables the ENET interrupt. 1300 * 1301 * This function enables the ENET interrupt according to the provided mask. The mask 1302 * is a logical OR of enumeration members. See ::enet_interrupt_enable_t. 1303 * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. 1304 * @code 1305 * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1306 * @endcode 1307 * 1308 * @param base ENET peripheral base address. 1309 * @param mask ENET interrupts to enable. This is a logical OR of the 1310 * enumeration ::enet_interrupt_enable_t. 1311 */ ENET_EnableInterrupts(ENET_Type * base,uint32_t mask)1312 static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) 1313 { 1314 base->EIMR |= mask; 1315 } 1316 1317 /*! 1318 * @brief Disables the ENET interrupt. 1319 * 1320 * This function disables the ENET interrupts according to the provided mask. The mask 1321 * is a logical OR of enumeration members. See ::enet_interrupt_enable_t. 1322 * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. 1323 * @code 1324 * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1325 * @endcode 1326 * 1327 * @param base ENET peripheral base address. 1328 * @param mask ENET interrupts to disable. This is a logical OR of the 1329 * enumeration ::enet_interrupt_enable_t. 1330 */ ENET_DisableInterrupts(ENET_Type * base,uint32_t mask)1331 static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) 1332 { 1333 base->EIMR &= ~mask; 1334 } 1335 1336 /*! 1337 * @brief Gets the ENET interrupt status flag. 1338 * 1339 * @param base ENET peripheral base address. 1340 * @return The event status of the interrupt source. This is the logical OR of members 1341 * of the enumeration ::enet_interrupt_enable_t. 1342 */ ENET_GetInterruptStatus(ENET_Type * base)1343 static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) 1344 { 1345 return base->EIR; 1346 } 1347 1348 /*! 1349 * @brief Clears the ENET interrupt events status flag. 1350 * 1351 * This function clears enabled ENET interrupts according to the provided mask. The mask 1352 * is a logical OR of enumeration members. See the ::enet_interrupt_enable_t. 1353 * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. 1354 * @code 1355 * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1356 * @endcode 1357 * 1358 * @param base ENET peripheral base address. 1359 * @param mask ENET interrupt source to be cleared. 1360 * This is the logical OR of members of the enumeration ::enet_interrupt_enable_t. 1361 */ ENET_ClearInterruptStatus(ENET_Type * base,uint32_t mask)1362 static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) 1363 { 1364 base->EIR = mask; 1365 } 1366 1367 #if FSL_FEATURE_ENET_QUEUE > 1 1368 /*! 1369 * @brief Set the second level Rx IRQ handler 1370 * 1371 * @param base ENET peripheral base address. 1372 * @param ISRHandler The handler to install. 1373 */ 1374 void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler); 1375 1376 /*! 1377 * @brief Set the second level Tx IRQ handler 1378 * 1379 * @param base ENET peripheral base address. 1380 * @param ISRHandler The handler to install. 1381 */ 1382 void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler); 1383 1384 #else 1385 /*! 1386 * @brief Set the second level Rx IRQ handler 1387 * 1388 * @param base ENET peripheral base address. 1389 * @param ISRHandler The handler to install. 1390 */ 1391 void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1392 1393 /*! 1394 * @brief Set the second level Tx IRQ handler 1395 * 1396 * @param base ENET peripheral base address. 1397 * @param ISRHandler The handler to install. 1398 */ 1399 void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1400 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1401 1402 /*! 1403 * @brief Set the second level Err IRQ handler 1404 * 1405 * @param base ENET peripheral base address. 1406 * @param ISRHandler The handler to install. 1407 */ 1408 void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1409 1410 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1411 /*! 1412 * @brief Set the second level Ts IRQ handler 1413 * 1414 * @param ISRHandler The handler to install. 1415 */ 1416 void ENET_SetTsISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1417 1418 /*! 1419 * @brief Set the second level 1588 Timer IRQ handler 1420 * 1421 * @param ISRHandler The handler to install. 1422 */ 1423 void ENET_Set1588TimerISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1424 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1425 1426 /* @} */ 1427 1428 /*! 1429 * @name Transactional operation 1430 * @{ 1431 */ 1432 1433 /*! 1434 * @brief Gets the error statistics of a received frame for ENET specified ring. 1435 * 1436 * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). 1437 * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, 1438 * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. 1439 * This is an example. 1440 * @code 1441 * status = ENET_GetRxFrameSize(&g_handle, &length, 0); 1442 * if (status == kStatus_ENET_RxFrameError) 1443 * { 1444 * Comments: Get the error information of the received frame. 1445 * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic, 0); 1446 * Comments: update the receive buffer. 1447 * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); 1448 * } 1449 * @endcode 1450 * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. 1451 * @param eErrorStatic The error statistics structure pointer. 1452 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1453 */ 1454 void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId); 1455 1456 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1457 /*! 1458 * @brief Gets the ENET transmit frame statistics after the data send for specified ring. 1459 * 1460 * This interface gets the error statistics of the transmit frame. 1461 * Because the error information is reported by the uDMA after the data delivery, this interface 1462 * should be called after the data transmit API. It is recommended to call this function on 1463 * transmit interrupt handler. After calling the ENET_SendFrame, the 1464 * transmit interrupt notifies the transmit completion. 1465 * 1466 * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. 1467 * @param eErrorStatic The error statistics structure pointer. 1468 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1469 * @return The execute status. 1470 */ 1471 status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId); 1472 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1473 1474 /*! 1475 * @brief Gets statistical data in transfer. 1476 * 1477 * @param base ENET peripheral base address. 1478 * @param statistics The statistics structure pointer. 1479 */ 1480 void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics); 1481 1482 /*! 1483 * @brief Gets the size of the read frame for specified ring. 1484 * 1485 * This function gets a received frame size from the ENET buffer descriptors. 1486 * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. 1487 * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to receive frame and update the BD 1488 * if the result is not "kStatus_ENET_RxFrameEmpty". 1489 * 1490 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1491 * @param length The length of the valid frame received. 1492 * @param ringId The ring index or ring number. 1493 * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. 1494 * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data 1495 * and NULL length to update the receive buffers. 1496 * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame 1497 * should be called with the right data buffer and the captured data length input. 1498 */ 1499 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId); 1500 1501 /*! 1502 * @brief Reads a frame from the ENET device. 1503 * This function reads a frame (both the data and the length) from the ENET buffer descriptors. 1504 * User can get timestamp through ts pointer if the ts is not NULL. 1505 * @note It doesn't store the timestamp in the receive timestamp queue. 1506 * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. 1507 * This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer 1508 * in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time 1509 * consumption. 1510 * This is an example: 1511 * @code 1512 * uint32_t length; 1513 * enet_handle_t g_handle; 1514 * Comments: Get the received frame size firstly. 1515 * status = ENET_GetRxFrameSize(&g_handle, &length, 0); 1516 * if (length != 0) 1517 * { 1518 * Comments: Allocate memory here with the size of "length" 1519 * uint8_t *data = memory allocate interface; 1520 * if (!data) 1521 * { 1522 * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL); 1523 * Comments: Add the console warning log. 1524 * } 1525 * else 1526 * { 1527 * status = ENET_ReadFrame(ENET, &g_handle, data, length, 0, NULL); 1528 * Comments: Call stack input API to deliver the data to stack 1529 * } 1530 * } 1531 * else if (status == kStatus_ENET_RxFrameError) 1532 * { 1533 * Comments: Update the received buffer when a error frame is received. 1534 * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL); 1535 * } 1536 * @endcode 1537 * @param base ENET peripheral base address. 1538 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1539 * @param data The data buffer provided by user to store the frame which memory size should be at least "length". 1540 * @param length The size of the data buffer which is still the length of the received frame. 1541 * @param ringId The ring index or ring number. 1542 * @param ts The timestamp address to store received timestamp. 1543 * @return The execute status, successful or failure. 1544 */ 1545 status_t ENET_ReadFrame( 1546 ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts); 1547 1548 /*! 1549 * @brief Transmits an ENET frame for specified ring. 1550 * @note The CRC is automatically appended to the data. Input the data to send without the CRC. 1551 * This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer 1552 * in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time 1553 * consumption. 1554 * 1555 * 1556 * @param base ENET peripheral base address. 1557 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1558 * @param data The data buffer provided by user to send. 1559 * @param length The length of the data to send. 1560 * @param ringId The ring index or ring number. 1561 * @param tsFlag Timestamp enable flag. 1562 * @param context Used by user to handle some events after transmit over. 1563 * @retval kStatus_Success Send frame succeed. 1564 * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. 1565 * The transmit busy happens when the data send rate is over the MAC capacity. 1566 * The waiting mechanism is recommended to be added after each call return with 1567 * kStatus_ENET_TxFrameBusy. 1568 */ 1569 status_t ENET_SendFrame(ENET_Type *base, 1570 enet_handle_t *handle, 1571 const uint8_t *data, 1572 uint32_t length, 1573 uint8_t ringId, 1574 bool tsFlag, 1575 void *context); 1576 1577 /*! 1578 * @brief Enable or disable tx descriptors reclaim mechanism. 1579 * @note This function must be called when no pending send frame action. 1580 * Set enable if you want to reclaim context or timestamp in interrupt. 1581 * 1582 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1583 * @param isEnable Enable or disable flag. 1584 * @param ringId The ring index or ring number. 1585 * @retval kStatus_Success Succeed to enable/disable Tx reclaim. 1586 * @retval kStatus_Fail Fail to enable/disable Tx reclaim. 1587 */ 1588 status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId); 1589 1590 /*! 1591 * @brief Reclaim tx descriptors. 1592 * This function is used to update the tx descriptor status and 1593 * store the tx timestamp when the 1588 feature is enabled. 1594 * This is called by the transmit interupt IRQ handler after the 1595 * complete of a frame transmission. 1596 * 1597 * @param base ENET peripheral base address. 1598 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1599 * @param ringId The ring index or ring number. 1600 */ 1601 void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId); 1602 1603 /*! 1604 * @brief Receives one frame in specified BD ring with zero copy. 1605 * 1606 * This function uses the user-defined allocation and free callbacks. Every time application gets one frame through 1607 * this function, driver stores the buffer address(es) in enet_buffer_struct_t and allocate new buffer(s) for the BD(s). 1608 * If there's no memory buffer in the pool, this function drops current one frame to keep the Rx frame in BD ring is as 1609 * fresh as possible. 1610 * @note Application must provide a memory pool including at least BD number + n buffers in order for this function to work 1611 * properly, because each BD must always take one buffer while driver is running, then other extra n buffer(s) can be taken 1612 * by application. Here n is the ceil(max_frame_length(set by RCR) / bd_rx_size(set by MRBR)). Application must also provide 1613 * an array structure in rxFrame->rxBuffArray with n index to receive one complete frame in any case. 1614 * 1615 * @param base ENET peripheral base address. 1616 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1617 * @param rxFrame The received frame information structure provided by user. 1618 * @param ringId The ring index or ring number. 1619 * @retval kStatus_Success Succeed to get one frame and allocate new memory for Rx buffer. 1620 * @retval kStatus_ENET_RxFrameEmpty There's no Rx frame in the BD. 1621 * @retval kStatus_ENET_RxFrameError There's issue in this receiving. 1622 * @retval kStatus_ENET_RxFrameDrop There's no new buffer memory for BD, drop this frame. 1623 */ 1624 status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId); 1625 1626 /*! 1627 * @brief Sends one frame in specified BD ring with zero copy. 1628 * 1629 * This function supports scattered buffer transmit, user needs to provide the buffer array. 1630 * @note Tx reclaim should be enabled to ensure the Tx buffer ownership can be given back to 1631 * application after Tx is over. 1632 * 1633 * @param base ENET peripheral base address. 1634 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1635 * @param txFrame The Tx frame structure. 1636 * @param ringId The ring index or ring number. 1637 * @retval kStatus_Success Succeed to send one frame. 1638 * @retval kStatus_ENET_TxFrameBusy The BD is not ready for Tx or the reclaim operation still not finishs. 1639 * @retval kStatus_ENET_TxFrameOverLen The Tx frame length is over max ethernet frame length. 1640 */ 1641 status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId); 1642 1643 #if FSL_FEATURE_ENET_QUEUE > 1 1644 /*! 1645 * @brief The transmit IRQ handler. 1646 * 1647 * @param base ENET peripheral base address. 1648 * @param handle The ENET handler pointer. 1649 * @param ringId The ring id or ring number. 1650 */ 1651 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 1652 1653 /*! 1654 * @brief The receive IRQ handler. 1655 * 1656 * @param base ENET peripheral base address. 1657 * @param handle The ENET handler pointer. 1658 * @param ringId The ring id or ring number. 1659 */ 1660 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 1661 1662 /*! 1663 * @brief the common IRQ handler for the tx/rx irq handler. 1664 * 1665 * This is used for the combined tx/rx interrupt for multi-ring (frame 1). 1666 * 1667 * @param base ENET peripheral base address. 1668 */ 1669 void ENET_CommonFrame1IRQHandler(ENET_Type *base); 1670 1671 /*! 1672 * @brief the common IRQ handler for the tx/rx irq handler. 1673 * 1674 * This is used for the combined tx/rx interrupt for multi-ring (frame 2). 1675 * 1676 * @param base ENET peripheral base address. 1677 */ 1678 void ENET_CommonFrame2IRQHandler(ENET_Type *base); 1679 #else 1680 /*! 1681 * @brief The transmit IRQ handler. 1682 * 1683 * @param base ENET peripheral base address. 1684 * @param handle The ENET handler pointer. 1685 */ 1686 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); 1687 1688 /*! 1689 * @brief The receive IRQ handler. 1690 * 1691 * @param base ENET peripheral base address. 1692 * @param handle The ENET handler pointer. 1693 */ 1694 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); 1695 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1696 1697 /*! 1698 * @brief Some special IRQ handler including the error, mii, wakeup irq handler. 1699 * 1700 * @param base ENET peripheral base address. 1701 * @param handle The ENET handler pointer. 1702 */ 1703 void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); 1704 1705 /*! 1706 * @brief the common IRQ handler for the 1588 irq handler. 1707 * 1708 * This is used for the 1588 timer interrupt. 1709 * 1710 * @param base ENET peripheral base address. 1711 */ 1712 void ENET_Ptp1588IRQHandler(ENET_Type *base); 1713 1714 /*! 1715 * @brief the common IRQ handler for the tx/rx/error etc irq handler. 1716 * 1717 * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). 1718 * 1719 * @param base ENET peripheral base address. 1720 */ 1721 void ENET_CommonFrame0IRQHandler(ENET_Type *base); 1722 /* @} */ 1723 1724 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1725 /*! 1726 * @name ENET PTP 1588 function operation 1727 * @{ 1728 */ 1729 void ENET_Ptp1588ConfigureHandler(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); 1730 1731 /*! 1732 * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. 1733 * The function sets the clock for PTP 1588 timer and enables 1734 * time stamp interrupts and transmit interrupts for PTP 1588 features. 1735 * This API should be called when the 1588 feature is enabled 1736 * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. 1737 * ENET_Init should be called before calling this API. 1738 * 1739 * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler 1740 * and the transmit time-stamp store is done through transmit interrupt handler. 1741 * As a result, the TS interrupt and TX interrupt are enabled when you call this API. 1742 * 1743 * @param base ENET peripheral base address. 1744 * @param handle ENET handler pointer. 1745 * @param ptpConfig The ENET PTP1588 configuration. 1746 */ 1747 void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); 1748 1749 /*! 1750 * @brief Starts the ENET PTP 1588 Timer. 1751 * This function is used to initialize the PTP timer. After the PTP starts, 1752 * the PTP timer starts running. 1753 * 1754 * @param base ENET peripheral base address. 1755 * @param ptpClkSrc The clock source of the PTP timer. 1756 */ 1757 void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); 1758 1759 /*! 1760 * @brief Stops the ENET PTP 1588 Timer. 1761 * This function is used to stops the ENET PTP timer. 1762 * 1763 * @param base ENET peripheral base address. 1764 */ ENET_Ptp1588StopTimer(ENET_Type * base)1765 static inline void ENET_Ptp1588StopTimer(ENET_Type *base) 1766 { 1767 /* Disable PTP timer and reset the timer. */ 1768 base->ATCR &= ~ENET_ATCR_EN_MASK; 1769 base->ATCR |= ENET_ATCR_RESTART_MASK; 1770 } 1771 1772 /*! 1773 * @brief Adjusts the ENET PTP 1588 timer. 1774 * 1775 * @param base ENET peripheral base address. 1776 * @param corrIncrease The correction increment value. This value is added every time the correction 1777 * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, 1778 * a value greater than the 1/ptpClkSrc speeds up the timer. 1779 * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how 1780 * many timer clock the correction counter should be reset and trigger a correction 1781 * increment on the timer. A value of 0 disables the correction counter and no correction occurs. 1782 */ 1783 void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); 1784 1785 /*! 1786 * @brief Sets the ENET PTP 1588 timer channel mode. 1787 * 1788 * @param base ENET peripheral base address. 1789 * @param channel The ENET PTP timer channel number. 1790 * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". 1791 * @param intEnable Enables or disables the interrupt. 1792 */ ENET_Ptp1588SetChannelMode(ENET_Type * base,enet_ptp_timer_channel_t channel,enet_ptp_timer_channel_mode_t mode,bool intEnable)1793 static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, 1794 enet_ptp_timer_channel_t channel, 1795 enet_ptp_timer_channel_mode_t mode, 1796 bool intEnable) 1797 { 1798 uint32_t tcrReg = 0; 1799 1800 tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0U); 1801 1802 /* Disable channel mode first. */ 1803 base->CHANNEL[channel].TCSR = 0; 1804 base->CHANNEL[channel].TCSR = tcrReg; 1805 } 1806 1807 #if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL 1808 /*! 1809 * @brief Sets ENET PTP 1588 timer channel mode pulse width. 1810 * 1811 * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare 1812 * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. 1813 * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. 1814 * so call this function if you need to set the timer channel mode for 1815 * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare 1816 * with pulse width more than one 1588 clock, 1817 * 1818 * @param base ENET peripheral base address. 1819 * @param channel The ENET PTP timer channel number. 1820 * @param isOutputLow True --- timer channel is configured for output compare 1821 * pulse output low. 1822 * false --- timer channel is configured for output compare 1823 * pulse output high. 1824 * @param pulseWidth The pulse width control value, range from 0 ~ 31. 1825 * 0 --- pulse width is one 1588 clock cycle. 1826 * 31 --- pulse width is thirty two 1588 clock cycles. 1827 * @param intEnable Enables or disables the interrupt. 1828 */ ENET_Ptp1588SetChannelOutputPulseWidth(ENET_Type * base,enet_ptp_timer_channel_t channel,bool isOutputLow,uint8_t pulseWidth,bool intEnable)1829 static inline void ENET_Ptp1588SetChannelOutputPulseWidth( 1830 ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) 1831 { 1832 uint32_t tcrReg; 1833 1834 tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); 1835 1836 if (isOutputLow) 1837 { 1838 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); 1839 } 1840 else 1841 { 1842 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); 1843 } 1844 1845 /* Disable channel mode first. */ 1846 base->CHANNEL[channel].TCSR = 0; 1847 base->CHANNEL[channel].TCSR = tcrReg; 1848 } 1849 #endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ 1850 1851 /*! 1852 * @brief Sets the ENET PTP 1588 timer channel comparison value. 1853 * 1854 * @param base ENET peripheral base address. 1855 * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". 1856 * @param cmpValue The compare value for the compare setting. 1857 */ ENET_Ptp1588SetChannelCmpValue(ENET_Type * base,enet_ptp_timer_channel_t channel,uint32_t cmpValue)1858 static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) 1859 { 1860 base->CHANNEL[channel].TCCR = cmpValue; 1861 } 1862 1863 /*! 1864 * @brief Gets the ENET PTP 1588 timer channel status. 1865 * 1866 * @param base ENET peripheral base address. 1867 * @param channel The IEEE 1588 timer channel number. 1868 * @return True or false, Compare or capture operation status 1869 */ ENET_Ptp1588GetChannelStatus(ENET_Type * base,enet_ptp_timer_channel_t channel)1870 static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) 1871 { 1872 return (0U != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); 1873 } 1874 1875 /*! 1876 * @brief Clears the ENET PTP 1588 timer channel status. 1877 * 1878 * @param base ENET peripheral base address. 1879 * @param channel The IEEE 1588 timer channel number. 1880 */ ENET_Ptp1588ClearChannelStatus(ENET_Type * base,enet_ptp_timer_channel_t channel)1881 static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) 1882 { 1883 base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; 1884 base->TGSR = (1UL << (uint32_t)channel); 1885 } 1886 1887 /*! 1888 * @brief Get the ENET PTP 1588 timer global status. 1889 * 1890 * @param base ENET peripheral base address. 1891 */ ENET_Ptp1588GetGlobalStatus(ENET_Type * base)1892 static inline uint32_t ENET_Ptp1588GetGlobalStatus(ENET_Type *base) 1893 { 1894 return base->TGSR; 1895 } 1896 1897 /*! 1898 * @brief Gets the current ENET time from the PTP 1588 timer. 1899 * A variant of ENET_Ptp1588GetTimer() which does not disable interrupts. 1900 * 1901 * @param base ENET peripheral base address. 1902 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 1903 * @param ptpTime The PTP timer structure. 1904 */ 1905 void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 1906 1907 /*! 1908 * @brief Gets the current ENET time from the PTP 1588 timer. 1909 * 1910 * @param base ENET peripheral base address. 1911 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 1912 * @param ptpTime The PTP timer structure. 1913 */ 1914 void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 1915 1916 /*! 1917 * @brief Sets the ENET PTP 1588 timer to the assigned time. 1918 * 1919 * @param base ENET peripheral base address. 1920 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 1921 * @param ptpTime The timer to be set to the PTP timer. 1922 */ 1923 void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 1924 1925 /*! 1926 * @brief The IEEE 1588 PTP time stamp interrupt handler. 1927 * 1928 * @param base ENET peripheral base address. 1929 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 1930 */ 1931 void ENET_TimeStampIRQHandler(ENET_Type *base, enet_handle_t *handle); 1932 1933 /* @} */ 1934 1935 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1936 1937 #if defined(__cplusplus) 1938 } 1939 #endif 1940 1941 /*! @}*/ 1942 1943 #endif /* _FSL_ENET_H_ */ 1944