1 /*
2 * Copyright 2022-2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef FSL_CMC_H_
8 #define FSL_CMC_H_
9 #include "fsl_common.h"
10
11 /*!
12 * @addtogroup mcx_cmc
13 * @{
14 */
15 /*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18 /*! @name Driver version */
19 /*@{*/
20 /*! @brief CMC driver version 2.2.2. */
21 #define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
22 /* @} */
23
24 /*!
25 * @brief CMC power mode Protection enumeration.
26 */
27 enum _cmc_power_mode_protection
28 {
29 kCMC_AllowDeepSleepMode = 0x1UL, /*!< Allow Deep Sleep mode. */
30 kCMC_AllowPowerDownMode = 0x2UL, /*!< Allow Power Down mode. */
31 kCMC_AllowDeepPowerDownMode = 0x8UL, /*!< Allow Deep Power Down mode. */
32 kCMC_AllowAllLowPowerModes = 0xFUL, /*!< Allow Deep Sleep, Power Down, Deep Power Down modes. */
33 };
34
35 /*!
36 * @brief Wake up sources from the previous low power mode entry.
37 *
38 * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family.
39 */
40 enum _cmc_wakeup_sources
41 {
42 kCMC_WakeupFromResetInterruptOrPowerDown =
43 CMC_CKSTAT_WAKEUP(1U << 0U), /*!< Wakeup source is reset interrupt, or wake up from Deep Power Down. */
44 kCMC_WakeupFromDebugReuqest = CMC_CKSTAT_WAKEUP(1U << 1U), /*!< Wakeup source is debug request. */
45 kCMC_WakeupFromInterrupt = CMC_CKSTAT_WAKEUP(1U << 2U), /*!< Wakeup source is interrupt. */
46 kCMC_WakeupFromDMAWakeup = CMC_CKSTAT_WAKEUP(1U << 3U), /*!< Wakeup source is DMA Wakeup. */
47 kCMC_WakeupFromWUURequest = CMC_CKSTAT_WAKEUP(1U << 4U), /*!< Wakeup source is WUU request. */
48 kCMC_WakeupFromUsbFs = CMC_CKSTAT_WAKEUP(1U << 5U), /*!< Wakeup source is USBFS(USB0). */
49 kCMC_WakeupFromITRC = CMC_CKSTAT_WAKEUP(1U << 6U), /*!< Wakeup source is ITRC. */
50 kCMC_WakeupFromCpu1 = CMC_CKSTAT_WAKEUP(1U << 7U), /*!< Wakeup source is CPU1. */
51 };
52
53 /*!
54 * @brief System Reset Interrupt enable enumeration.
55 */
56 enum _cmc_system_reset_interrupt_enable
57 {
58 kCMC_PinResetInterruptEnable = CMC_SRIE_PIN_MASK, /*!< Pin Reset interrupt enable. */
59 kCMC_DAPResetInterruptEnable = CMC_SRIE_DAP_MASK, /*!< DAP Reset interrupt enable. */
60 kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable = CMC_SRIE_LPACK_MASK, /*!< Low Power Acknowledge Timeout
61 Reset interrupt enable. */
62 kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset
63 interrupt enable. */
64 kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */
65 kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */
66 #if defined(CMC_SRIE_CPU1_MASK)
67 kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */
68 #endif /* CMC_SRIE_CPU1_MASK */
69 #if defined(CMC_SRIE_ADVC_MASK)
70 kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK, /*!< ADVC Reset interrupt enable. */
71 #endif /* CMC_SRIE_ADVC_MASK */
72 #if defined(CMC_SRIE_VBAT_MASK)
73 kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */
74 #endif /* CMC_SRIE_VBAT_MASK */
75 #if defined(CMC_SRIE_WWDT1_MASK)
76 kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset
77 interrupt enable. */
78 #endif /* CMC_SRIE_WWDT1_MASK */
79 kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */
80 #if defined(CMC_SRIE_CDOG1_MASK)
81 kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */
82 #endif /* CMC_SRIE_CDOG1_MASK */
83 };
84
85 /*!
86 * @brief CMC System Reset Interrupt Status flag.
87 */
88 enum _cmc_system_reset_interrupt_flag
89 {
90 kCMC_PinResetInterruptFlag = CMC_SRIF_PIN_MASK, /*!< Pin Reset interrupt flag. */
91 kCMC_DAPResetInterruptFlag = CMC_SRIF_DAP_MASK, /*!< DAP Reset interrupt flag. */
92 kCMC_LowPowerAcknowledgeTimeoutResetFlag = CMC_SRIF_LPACK_MASK, /*!< Low Power Acknowledge
93 Timeout Reset interrupt flag. */
94 kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */
95 kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */
96 kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */
97 #if defined(CMC_SRIF_CPU1_MASK)
98 kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */
99 #endif /* CMC_SRIF_CPU1_MASK */
100 #if defined(CMC_SRIF_ADVC_MASK)
101 kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK, /*!< ADVC Reset interrupt flag. */
102 #endif /* CMC_SRIF_ADVC_MASK */
103 #if defined(CMC_SRIF_VBAT_MASK)
104 kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */
105 #endif /* CMC_SRIF_VBAT_MASK */
106 #if defined(CMC_SRIF_WWDT1_MASK)
107 kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */
108 #endif /* CMC_SRIF_WWDT1_MASK */
109 kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */
110 #if defined(CMC_SRIF_CDOG1_MASK)
111 kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */
112 #endif /* CMC_SRIF_CDOG1_MASK */
113 };
114
115 #if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
116 /*!
117 * @brief CMC System SRAM arrays low power mode enable enumeration.
118 */
119 enum _cmc_system_sram_arrays
120 {
121 kCMC_RAMX0 = 1UL << 0UL, /*!< Used to control RAMX0. */
122 kCMC_RAMX1 = 1UL << 1UL, /*!< Used to control RAMX1. */
123 kCMC_RAMX2 = 1UL << 2UL, /*!< Used to control RAMX2. */
124 kCMC_RAMB = 1UL << 3UL, /*!< Used to control RAMB. */
125 kCMC_RAMC0 = 1UL << 4UL, /*!< Used to control RAMC0. */
126 kCMC_RAMC1 = 1UL << 5UL, /*!< Used to control RAMC1. */
127 kCMC_RAMD0 = 1UL << 6UL, /*!< Used to control RAMD0. */
128 kCMC_RAMD1 = 1UL << 7UL, /*!< Used to control RAMD1. */
129 kCMC_RAME0 = 1UL << 8UL, /*!< Used to control RAME0. */
130 kCMC_RAME1 = 1UL << 9UL, /*!< Used to control RAME1. */
131 kCMC_RAMF0 = 1UL << 10UL, /*!< Used to control RAMF0. */
132 kCMC_RAMF1 = 1UL << 11UL, /*!< Used to control RAMF1. */
133 kCMC_RAMG0_RAMG1 = 1UL << 12UL, /*!< Used to control RAMG0 and RAMG1. */
134 kCMC_RAMG2_RAMG3 = 1UL << 13UL, /*!< Used to control RAMG2 and RAMG3. */
135 kCMC_RAMH0_RAMH1 = 1UL << 14UL, /*!< Used to control RAMH0 and RAMH1. */
136 kCMC_LPCAC = 1UL << 24UL, /*!< Used to control LPCAC. */
137 kCMC_DMA0_DMA1_PKC = 1UL << 25UL, /*!< Used to control DMA0, DMA1 and PKC. */
138 kCMC_USB0 = 1UL << 26UL, /*!< Used to control USB0. */
139 kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */
140 kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */
141 kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */
142
143 kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 |
144 kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 |
145 kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ |
146 kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */
147 };
148 #endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
149
150 /*!
151 * @brief System reset sources enumeration.
152 */
153 enum _cmc_system_reset_sources
154 {
155 kCMC_WakeUpReset = CMC_SRS_WAKEUP_MASK, /*!< The reset caused by a wakeup from Power Down or
156 Deep Power Down mode. */
157 kCMC_PORReset = CMC_SRS_POR_MASK, /*!< The reset caused by power on reset detection logic. */
158 kCMC_VDReset = CMC_SRS_VD_MASK, /*!< The reset caused by an LVD or HVD. */
159 kCMC_WarmReset = CMC_SRS_WARM_MASK, /*!< The last reset source is a warm reset source. */
160 kCMC_FatalReset = CMC_SRS_FATAL_MASK, /*!< The last reset source is a fatal reset source. */
161 kCMC_PinReset = CMC_SRS_PIN_MASK, /*!< The reset caused by the RESET_b pin. */
162 kCMC_DAPReset = CMC_SRS_DAP_MASK, /*!< The reset caused by a reset request from the Debug Access port. */
163 kCMC_ResetTimeout = CMC_SRS_RSTACK_MASK, /*!< The reset caused by a timeout or other error condition in the system
164 reset generation. */
165 kCMC_LowPowerAcknowledgeTimeoutReset = CMC_SRS_LPACK_MASK, /*!< The reset caused by a timeout in
166 low power mode entry logic. */
167 kCMC_SCGReset = CMC_SRS_SCG_MASK, /*!< The reset caused by a loss of clock or loss of lock event in the SCG. */
168 kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */
169 kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */
170 kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */
171 #if defined(CMC_SRS_CPU1_MASK)
172 kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */
173 #endif /* CMC_SRS_CPU1_MASK */
174 #if defined(CMC_SRS_ADVC_MASK)
175 kCMC_AdvcReset = CMC_SRS_ADVC_MASK, /*!< The reset caused by ADVC critical reset. */
176 #endif /* CMC_SRS_ADVC_MASK */
177 #if defined(CMC_SRS_VBAT_MASK)
178 kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */
179 #endif /* CMC_SRS_VBAT_MASK */
180 #if defined(CMC_SRS_WWDT1_MASK)
181 kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */
182 #endif /* CMC_SRS_WWDT1_MASK */
183 kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */
184 #if defined(CMC_SRS_CDOG1_MASK)
185 kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */
186 #endif /* CMC_SRS_CDOG1_MASK */
187 kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */
188 #if defined(CMC_SRS_SECVIO_MASK)
189 kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */
190 #endif /* CMC_SRS_SECVIO_MASK */
191 #if defined(CMC_SRS_TAMPER_MASK)
192 kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */
193 #endif /* CMC_SRS_TAMPER_MASK */
194 };
195
196 /*!
197 * @brief Indicate the core clock was gated.
198 */
199 typedef enum _cmc_core_clock_gate_status
200 {
201 kCMC_CoreClockNotGated = 0U, /*!< Core clock not gated. */
202 kCMC_CoreClockGated = 1U /*!< Core clock was gated due to low power mode entry. */
203 } cmc_core_clock_gate_status_t;
204
205 /*!
206 * @brief CMC clock mode enumeration.
207 */
208 typedef enum _cmc_clock_mode
209 {
210 kCMC_GateNoneClock = 0x00U, /*!< No clock gating. */
211 kCMC_GateCoreClock = 0x01U, /*!< Gate Core clock. */
212 kCMC_GateCorePlatformClock = 0x03U, /*!< Gate Core clock and platform clock. */
213 kCMC_GateAllSystemClocks = 0x07U, /*!< Gate all System clocks, without getting core entering into low power mode. */
214 kCMC_GateAllSystemClocksEnterLowPowerMode = 0x0FU /*!< Gate all System clocks, with core
215 entering into low power mode. */
216 } cmc_clock_mode_t;
217
218 /*!
219 * @brief CMC power mode enumeration.
220 */
221 typedef enum _cmc_low_power_mode
222 {
223 kCMC_ActiveOrSleepMode = 0x0U, /*!< Select Active/Sleep mode. */
224 kCMC_DeepSleepMode = 0x1U, /*!< Select Deep Sleep mode when a core executes WFI or WFE instruction. */
225 kCMC_PowerDownMode = 0x3U, /*!< Select Power Down mode when a core executes WFI or WFE instruction. */
226 kCMC_DeepPowerDown = 0xFU, /*!< Select Deep Power Down mode when a core executes WFI or WFE instruction. */
227 } cmc_low_power_mode_t;
228
229 /*!
230 * @brief CMC reset pin configuration.
231 */
232 typedef struct _cmc_reset_pin_config
233 {
234 bool lowpowerFilterEnable; /*!< Low Power Filter enable. */
235 bool resetFilterEnable; /*!< Reset Filter enable. */
236 uint8_t resetFilterWidth; /*!< Width of the Reset Filter. */
237 } cmc_reset_pin_config_t;
238
239 /*!
240 * @brief power mode configuration for each power domain.
241 */
242 typedef struct _cmc_power_domain_config
243 {
244 cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */
245 cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */
246 #if (CMC_PMCTRL_COUNT > 1U)
247 cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */
248 #endif /* (CMC_PMCTRL_COUNT > 1U) */
249 } cmc_power_domain_config_t;
250
251 /*******************************************************************************
252 * API
253 ******************************************************************************/
254 #if defined(__cplusplus)
255 extern "C" {
256 #endif /* __cplusplus */
257
258 /*!
259 * @name CLOCK mode configuration.
260 * @{
261 */
262
263 /*!
264 * @brief Sets clock mode.
265 *
266 * This function configs the amount of clock gating when the core asserts
267 * Sleeping due to WFI, WFE or SLEEPONEXIT.
268 *
269 * @param base CMC peripheral base address.
270 * @param mode System clock mode.
271 */
272 void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode);
273
274 /*!
275 * @brief Locks the clock mode setting.
276 *
277 * After invoking this function, any clock mode setting will be blocked.
278 *
279 * @param base CMC peripheral base address.
280 */
CMC_LockClockModeSetting(CMC_Type * base)281 static inline void CMC_LockClockModeSetting(CMC_Type *base)
282 {
283 base->CKCTRL |= CMC_CKCTRL_LOCK_MASK;
284 }
285
286 /* @} */
287
288 /*!
289 * @name Gets/Clears the Clock Mode, the wake up source, the Reset source.
290 * @{
291 */
292
293 /*!
294 * @brief Gets the core clock gated status.
295 *
296 * This function get the status to indicate whether the core clock is gated.
297 * The core clock gated status can be cleared by software.
298 *
299 * @param base CMC peripheral base address.
300 * @return The status to indicate whether the core clock is gated.
301 */
CMC_GetCoreClockGatedStatus(CMC_Type * base)302 static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base)
303 {
304 return (cmc_core_clock_gate_status_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_VALID_MASK) >> CMC_CKSTAT_VALID_SHIFT);
305 }
306
307 /*!
308 * @brief Clears the core clock gated status.
309 *
310 * This function clear clock status flag by software.
311 *
312 * @param base CMC peripheral base address.
313 */
CMC_ClearCoreClockGatedStatus(CMC_Type * base)314 static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base)
315 {
316 base->CKSTAT |= CMC_CKSTAT_VALID_MASK;
317 }
318
319 /*!
320 * @brief Gets the Wakeup Source.
321 *
322 * This function gets the Wakeup sources from the previous low power mode entry.
323 *
324 * @param base CMC peripheral base address.
325 * @return The Wakeup sources from the previous low power mode entry. See @ref _cmc_wakeup_sources for details.
326 */
CMC_GetWakeupSource(CMC_Type * base)327 static inline uint8_t CMC_GetWakeupSource(CMC_Type *base)
328 {
329 return ((uint8_t)((base->CKSTAT & CMC_CKSTAT_WAKEUP_MASK) >> CMC_CKSTAT_WAKEUP_SHIFT));
330 }
331
332 /*!
333 * @brief Gets the Clock mode.
334 *
335 * This function gets the clock mode of the previous low power mode entry.
336 *
337 * @param base CMC peripheral base address.
338 * @return The Low Power status.
339 */
CMC_GetClockMode(CMC_Type * base)340 static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base)
341 {
342 return (cmc_clock_mode_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_CKMODE_MASK) >> CMC_CKSTAT_CKMODE_SHIFT);
343 }
344
345 /*!
346 * @brief Gets the System reset status.
347 *
348 * This function returns the system reset status. Those status
349 * updates on every MAIN Warm Reset to indicate the type/source
350 * of the most recent reset.
351 *
352 * @param base CMC peripheral base address.
353 * @return The most recent system reset status. See @ref _cmc_system_reset_sources for details.
354 */
CMC_GetSystemResetStatus(CMC_Type * base)355 static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base)
356 {
357 return base->SRS;
358 }
359
360 /*!
361 * @brief Gets the sticky system reset status since the last WAKE Cold Reset.
362 *
363 * This function gets all source of system reset that have generated a
364 * system reset since the last WAKE Cold Reset, and that have not been
365 * cleared by software.
366 *
367 * @param base CMC peripheral base address.
368 * @return System reset status that have not been cleared by software. See @ref _cmc_system_reset_sources for details.
369 */
CMC_GetStickySystemResetStatus(CMC_Type * base)370 static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base)
371 {
372 return base->SSRS;
373 }
374
375 /*!
376 * @brief Clears the sticky system reset status flags.
377 *
378 * @param base CMC peripheral base address.
379 * @param mask Bitmap of the sticky system reset status to be cleared.
380 */
CMC_ClearStickySystemResetStatus(CMC_Type * base,uint32_t mask)381 static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask)
382 {
383 base->SSRS = mask;
384 }
385
386 #if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG)
387 /*!
388 * @brief Gets the number of reset sequences completed since the last Cold Reset.
389 *
390 * @param base CMC peripheral base address.
391 * @return The number of reset sequences.
392 */
CMC_GetResetCount(CMC_Type * base)393 static inline uint8_t CMC_GetResetCount(CMC_Type *base)
394 {
395 return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK);
396 }
397 #endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */
398
399 /* @} */
400
401 /*!
402 * @name Power mode configuration.
403 * @{
404 */
405
406 /*!
407 * @brief Configures all power mode protection settings.
408 *
409 * This function configures the power mode protection settings for
410 * supported power modes. This should be done before set the lowPower mode
411 * for each power doamin.
412 *
413 * The allowed lowpower modes are passed as bit map. For example, to allow
414 * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode).
415 * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes).
416 *
417 * @param base CMC peripheral base address.
418 * @param allowedModes Bitmaps of the allowed power modes. See @ref _cmc_power_mode_protection for details.
419 */
420 void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes);
421
422 /*!
423 * @brief Locks the power mode protection.
424 *
425 * This function locks the power mode protection. After invoking this function,
426 * any power mode protection setting will be ignored.
427 *
428 * @param base CMC peripheral base address.
429 */
CMC_LockPowerModeProtectionSetting(CMC_Type * base)430 static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base)
431 {
432 base->PMPROT |= CMC_PMPROT_LOCK_MASK;
433 }
434
435 /*!
436 * @brief Config the same lowPower mode for all power domain.
437 *
438 * This function configures the same low power mode for MAIN power domian and WAKE power domain.
439 *
440 * @param base CMC peripheral base address.
441 * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details.
442 */
CMC_SetGlobalPowerMode(CMC_Type * base,cmc_low_power_mode_t lowPowerMode)443 static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)
444 {
445 base->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)lowPowerMode);
446 }
447
448 /*!
449 * @brief Configures entry into low power mode for the MAIN Power domain.
450 *
451 * This function configures the low power mode for the MAIN power domian,
452 * when the core executes WFI/WFE instruction. The available lowPower modes
453 * are defined in the @ref cmc_low_power_mode_t.
454 *
455 * @param base CMC peripheral base address.
456 * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details.
457 *
458 */
CMC_SetMAINPowerMode(CMC_Type * base,cmc_low_power_mode_t lowPowerMode)459 static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)
460 {
461 base->PMCTRL[0] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode);
462 }
463
464 /*!
465 * @brief Gets the power mode of the MAIN Power domain.
466 *
467 * @param base CMC peripheral base address.
468 * @return The power mode of MAIN Power domain. See @ref cmc_low_power_mode_t for details.
469 */
CMC_GetMAINPowerMode(CMC_Type * base)470 static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base)
471 {
472 return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK);
473 }
474
475 #if (CMC_PMCTRL_COUNT > 1U)
476 /*!
477 * @brief Configure entry into low power mode for the WAKE Power domain.
478 *
479 * This function configures the low power mode for the WAKE power domian,
480 * when the core executes WFI/WFE instruction. The available lowPower mode
481 * are defined in the @ref cmc_low_power_mode_t.
482 *
483 * @note The lowPower Mode for the WAKE domain must not be configured to a
484 * lower power mode than any other power domain.
485 *
486 * @param base CMC peripheral base address.
487 * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details.
488 *
489 */
CMC_SetWAKEPowerMode(CMC_Type * base,cmc_low_power_mode_t lowPowerMode)490 static inline void CMC_SetWAKEPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)
491 {
492 base->PMCTRL[1] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode);
493 }
494
495 /*!
496 * @brief Gets the power mode of the WAKE Power domain.
497 *
498 * @param base CMC peripheral base address.
499 * @return The power mode of WAKE Power domain. See @ref cmc_low_power_mode_t for details.
500 */
CMC_GetWAKEPowerMode(CMC_Type * base)501 static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base)
502 {
503 return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK);
504 }
505 #endif /* CMC_PMCTRL_COUNT > 1U */
506
507 /* @} */
508
509 /*!
510 * @name Reset Pin configuration.
511 * @{
512 */
513
514 /*!
515 * @brief Configure reset pin.
516 *
517 * This function configures reset pin. When enabled, the low power filter is enabled in both
518 * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers
519 * are enabled, they operate in series.
520 *
521 * @param base CMC peripheral base address.
522 * @param config Pointer to the reset pin config structure.
523 */
524 void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config);
525
526 /* @} */
527
528 /*!
529 * @name System Reset Interrupts.
530 * @{
531 */
532
533 /*!
534 * @brief Enable system reset interrupts.
535 *
536 * This function enables the system reset interrupts. The assertion of
537 * non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock
538 * while an enabled interrupt is generated. Then Software can perform a graceful
539 * shutdown or abort the non-fatal warm reset provided the pending reset source is cleared
540 * by resetting the reset source and then clearing the pending flag.
541 *
542 * @param base CMC peripheral base address.
543 * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details.
544 *
545 */
CMC_EnableSystemResetInterrupt(CMC_Type * base,uint32_t mask)546 static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask)
547 {
548 base->SRIE |= mask;
549 }
550
551 /*!
552 * @brief Disable system reset interrupts.
553 *
554 * This function disables the system reset interrupts.
555 *
556 * @param base CMC peripheral base address.
557 * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details.
558 */
CMC_DisableSystemResetInterrupt(CMC_Type * base,uint32_t mask)559 static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask)
560 {
561 base->SRIE &= (uint32_t)(~mask);
562 }
563
564 /*!
565 * @brief Gets System Reset interrupt flags.
566 *
567 * This function returns the System reset interrupt flags.
568 *
569 * @param base CMC peripheral base address.
570 * @return System reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details.
571 */
CMC_GetSystemResetInterruptFlags(CMC_Type * base)572 static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base)
573 {
574 return base->SRIF;
575 }
576
577 /*!
578 * @brief Clears System Reset interrupt flags.
579 *
580 * This function clears system reset interrupt flags. The pending reset source
581 * can be cleared by resetting the source of the reset and then clearing the pending
582 * flags.
583 *
584 * @param base CMC peripheral base address.
585 * @param mask System Reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details.
586 *
587 */
CMC_ClearSystemResetInterruptFlags(CMC_Type * base,uint32_t mask)588 static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask)
589 {
590 base->SRIF = mask;
591 }
592
593 /* @} */
594
595 /*!
596 * @name Non Maskable Pin interrupt.
597 * @{
598 */
599
600 /*!
601 * @brief Enable/Disable Non maskable Pin interrupt.
602 *
603 * @param base CMC peripheral base address.
604 * @param enable Enable or disable Non maskable pin interrupt.
605 * true - enable Non-maskable pin interrupt.
606 * false - disable Non-maskable pin interupt.
607 */
CMC_EnableNonMaskablePinInterrupt(CMC_Type * base,bool enable)608 static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable)
609 {
610 if (enable)
611 {
612 base->CORECTL |= CMC_CORECTL_NPIE_MASK;
613 }
614 else
615 {
616 base->CORECTL &= ~CMC_CORECTL_NPIE_MASK;
617 }
618 }
619
620 /* @} */
621
622 /*!
623 * @name Boot Configuration.
624 * @{
625 */
626
627 /*!
628 * @brief Gets the logic state of the ISPMODE_n pin.
629 *
630 * This function returns the logic state of the ISPMODE_n pin
631 * on the last negation of RESET_b pin.
632 *
633 * @param base CMC peripheral base address.
634 * @return The logic state of the ISPMODE_n pin on the last negation of RESET_b pin.
635 */
CMC_GetISPMODEPinLogic(CMC_Type * base)636 static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base)
637 {
638 return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT);
639 }
640
641 /*!
642 * @brief Clears ISPMODE_n pin state.
643 *
644 * @param base CMC peripheral base address.
645 */
CMC_ClearISPMODEPinLogic(CMC_Type * base)646 static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base)
647 {
648 base->MR[0] = CMC_MR_ISPMODE_n_MASK;
649 }
650
651 /*!
652 * @brief Set the logic state of the BOOT_CONFIGn pin.
653 *
654 * This function force the logic state of the Boot_Confign pin to assert
655 * on next system reset.
656 *
657 * @param base CMC peripheral base address.
658 * @param assert Assert the corresponding pin or not.
659 * true - Assert corresponding pin on next system reset.
660 * false - No effect.
661 */
CMC_ForceBootConfiguration(CMC_Type * base,bool assert)662 static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert)
663 {
664 if (assert)
665 {
666 base->FM[0] |= CMC_FM_FORCECFG_MASK;
667 }
668 else
669 {
670 base->FM[0] &= ~CMC_FM_FORCECFG_MASK;
671 }
672 }
673
674 /* @} */
675
676 /*!
677 * @name BootROM Status.
678 * @{
679 */
680
681 #if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG)
682 /*!
683 * @brief Gets the status information written by the BootROM.
684 *
685 * @param base CMC peripheral base address.
686 * @return The status information written by the BootROM.
687 */
CMC_GetBootRomStatus(CMC_Type * base)688 static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base)
689 {
690 return base->BSR;
691 }
692
693 /*!
694 * @brief Sets the bootROM status value.
695 *
696 * @note This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true.
697 *
698 * @param base CMC peripheral base address.
699 * @param stat The state value to set.
700 */
CMC_SetBootRomStatus(CMC_Type * base,uint32_t statValue)701 static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue)
702 {
703 base->BSR = CMC_BSR_STAT(statValue);
704 }
705 #endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */
706
707 #if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG)
708 /*!
709 * @brief Check if BootROM status and lock registers is writtable.
710 *
711 * @param base CMC peripheral base address.
712 * @return The result of whether BootROM status and lock register is writtable.
713 * - \b true BootROM status and lock registers are writtable;
714 * - \b false BootROM status and lock registers are not writtable.
715 */
CMC_CheckBootRomRegisterWrittable(CMC_Type * base)716 static inline bool CMC_CheckBootRomRegisterWrittable(CMC_Type *base)
717 {
718 return (base->BLR == 0x2UL);
719 }
720
721 /*!
722 * @brief After invoking this function, BootROM status and lock registers cannot be written.
723 *
724 * @param base CMC peripheral base address.
725 */
CMC_LockBootRomStatusWritten(CMC_Type * base)726 static inline void CMC_LockBootRomStatusWritten(CMC_Type *base)
727 {
728 base->BLR = CMC_BLR_LOCK(0x5U);
729 }
730
731 /*!
732 * @brief After invoking this function, BootROM status and lock register can be written.s
733 *
734 * @param base
735 */
CMC_UnlockBootRomStatusWritten(CMC_Type * base)736 static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
737 {
738 base->BLR = CMC_BLR_LOCK(0x2U);
739 }
740 #endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */
741
742 /* @} */
743
744 #if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
745 /*!
746 * @name System SRAM Configuration.
747 * @{
748 */
749
750 /*!
751 * @brief Power off the selected system SRAM always.
752 *
753 * @note This function power off the selected system SRAM always. The SRAM arrays should
754 * not be accessed while they are shut down. SRAM array contents are not retained
755 * if they are powered off.
756 *
757 * @note Once invoked, the previous settings will be overwritten.
758 *
759 * @param base CMC peripheral base address.
760 * @param mask Bitmap of the SRAM arrays to be powered off all modes.
761 * See @ref _cmc_system_sram_arrays for details.
762 * Check Reference Manual for the SRAM region and mask bit relationship.
763 */
764 void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask);
765
766 /*!
767 * @brief Power on SRAM during all mode.
768 *
769 * @note Once invoked, the previous settings will be overwritten.
770 *
771 * @param base CMC peripheral base address.
772 * @param mask Bitmap of the SRAM arrays to be powered on all modes.
773 * See @ref _cmc_system_sram_arrays for details.
774 * Check Reference Manual for the SRAM region and mask bit relationship.
775 */
CMC_PowerOnSRAMAllMode(CMC_Type * base,uint32_t mask)776 static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask)
777 {
778 base->SRAMDIS[0] &= CMC_SRAMDIS_DIS((uint32_t)(~mask));
779 }
780
781 /*!
782 * @brief Power off the selected system SRAM during low power modes only.
783 *
784 * This function power off the selected system SRAM only during low power mode.
785 * SRAM array contents are not retained if they are power off.
786 *
787 * @param base CMC peripheral base address.
788 * @param mask Bitmap of the SRAM arrays to be power off during low power mode only.
789 * See @ref _cmc_system_sram_arrays for details.
790 * Check Reference Manual for the SRAM region and mask bit relationship.
791 */
792 void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask);
793
794 /*!
795 * @brief Power on the selected system SRAM during low power modes only.
796 *
797 * This function power on the selected system SRAM. The SRAM arrray contents are
798 * retained in low power modes.
799 *
800 * @param base CMC peripheral base address.
801 * @param mask Bitmap of the SRAM arrays to be power on during low power mode only.
802 * See @ref _cmc_system_sram_arrays for details.
803 * Check Reference Manual for the SRAM region and mask bit relationship.
804 */
CMC_PowerOnSRAMLowPowerOnly(CMC_Type * base,uint32_t mask)805 static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
806 {
807 base->SRAMRET[0] &= CMC_SRAMRET_RET((uint32_t)(~mask));
808 }
809
810 /* @} */
811 #endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
812
813 /*!
814 * @name Flash Low Power Mode configuration.
815 * @{
816 */
817
818 #if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
819 /*!
820 * @brief Configs the low power mode of the on-chip flash memory.
821 *
822 * This function configs the low power mode of the on-chip flash memory.
823 *
824 * @param base CMC peripheral base address.
825 * @param doze true: Flash is disabled while core is sleeping
826 * false: No effect.
827 * @param disable true: Flash memory is placed in low power state.
828 * false: No effect.
829 */
830 void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable);
831 #else
832 /*!
833 * @brief Configs the low power mode of the on-chip flash memory.
834 *
835 * This function configs the low power mode of the on-chip flash memory.
836 *
837 * @param base CMC peripheral base address.
838 * @param wake true: Flash will exit low power state during the flash memory accesses.
839 * false: No effect.
840 * @param doze true: Flash is disabled while core is sleeping
841 * false: No effect.
842 * @param disable true: Flash memory is placed in low power state.
843 * false: No effect.
844 */
845 void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable);
846 #endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
847 /* @} */
848
849 /*!
850 * @name Debug Configuration.
851 */
852
853 /*!
854 * @brief Enables/Disables debug Operation when the core sleep.
855 *
856 * This function configs what happens to debug when core sleeps.
857 *
858 * @param base CMC peripheral base address.
859 * @param enable Enable or disable Debug when Core is sleeping.
860 * true - Debug remains enabled when the core is sleeping.
861 * false - Debug is disabled when the core is sleeping.
862 */
CMC_EnableDebugOperation(CMC_Type * base,bool enable)863 static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable)
864 {
865 if (enable)
866 {
867 base->DBGCTL &= ~CMC_DBGCTL_SOD_MASK;
868 }
869 else
870 {
871 base->DBGCTL |= CMC_DBGCTL_SOD_MASK;
872 }
873 }
874
875 /* @} */
876
877 /*!
878 * @name Low Power modes enter.
879 * @{
880 */
881 /*!
882 * @brief Prepares to enter low power modes.
883 *
884 * This function should be called before entering low power modes.
885 *
886 */
887 void CMC_PreEnterLowPowerMode(void);
888
889 /*!
890 * @brief Recovers after wake up from low power modes.
891 *
892 * This function should be called after wake up from low power modes.
893 * This function should be used with CMC_PreEnterLowPowerMode()
894 *
895 */
896 void CMC_PostExitLowPowerMode(void);
897
898 /*!
899 * @brief Configs the entry into the same low power mode for each power domains.
900 *
901 * This function provides the feature to entry into the same low power mode for each power
902 * domains. Before invoking this function, please ensure the selected power mode have been allowed.
903 *
904 * @param base CMC peripheral base address.
905 * @param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details.
906 *
907 */
908 void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode);
909
910 /*!
911 * @brief Configs the entry into different low power modes for each power domains.
912 *
913 * This function provides the feature to entry into different low power modes for
914 * each power domains. Before invoking this function please ensure the selected
915 * modes are allowed.
916 *
917 * @param base CMC peripheral base address.
918 * @param config Pointer to the cmc_power_domain_config_t structure.
919 */
920 void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config);
921
922 /* @} */
923
924 #if defined(__cplusplus)
925 }
926 #endif /* __cplusplus */
927
928 /*! @}*/
929 #endif /* FSL_CMC_H_ */
930
