1 /* 2 * Copyright 2018-2019 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_AK4497_H_ 9 #define _FSL_AK4497_H_ 10 11 #include "fsl_common.h" 12 #include "fsl_codec_i2c.h" 13 /*! 14 * @addtogroup ak4497 15 * @ingroup codec 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 /*! @name Driver version */ 23 /*@{*/ 24 /*! @brief CLOCK driver version 2.1.2 */ 25 #define FSL_AK4497_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) 26 /*@}*/ 27 28 /*! @brief ak4497 handle size */ 29 #ifndef AK4497_I2C_HANDLER_SIZE 30 #define AK4497_I2C_HANDLER_SIZE CODEC_I2C_MASTER_HANDLER_SIZE 31 #endif 32 33 /*! @brief define the registers offset of AK4497. */ 34 #define AK4497_CONTROL1 (0x00U) 35 #define AK4497_CONTROL2 (0x01U) 36 #define AK4497_CONTROL3 (0x02U) 37 #define AK4497_LCHATT (0x03U) 38 #define AK4497_RCHATT (0x04U) 39 #define AK4497_CONTROL4 (0x05U) 40 #define AK4497_DSD1 (0x06U) 41 #define AK4497_CONTROL5 (0x07U) 42 #define AK4497_SOUNDCONTROL (0x08U) 43 #define AK4497_DSD2 (0x09U) 44 #define AK4497_CONTROL7 (0x0AU) 45 #define AK4497_CONTROL8 (0x0BU) 46 #define AK4497_DFSREAD (0x15U) 47 /*! @brief define BIT info of AK4497. */ 48 #define AK4497_CONTROL1_RSTN_MASK (0x1U) 49 #define AK4497_CONTROL1_RSTN_SHIFT (0U) 50 #define AK4497_CONTROL1_DIF0_MASK (0x2U) 51 #define AK4497_CONTROL1_DIF0_SHIFT (1U) 52 #define AK4497_CONTROL1_DIF1_MASK (0x4U) 53 #define AK4497_CONTROL1_DIF1_SHIFT (2U) 54 #define AK4497_CONTROL1_DIF2_MASK (0x8U) 55 #define AK4497_CONTROL1_DIF2_SHIFT (3U) 56 #define AK4497_CONTROL1_AFSD_MASK (0x10U) 57 #define AK4497_CONTROL1_AFSD_SHIFT (4U) 58 #define AK4497_CONTROL1_ECS_MASK (0x20U) 59 #define AK4497_CONTROL1_ECS_SHIFT (5U) 60 #define AK4497_CONTROL1_EXDF_MASK (0x40U) 61 #define AK4497_CONTROL1_EXDF_SHIFT (6U) 62 #define AK4497_CONTROL1_ACKS_MASK (0x80U) 63 #define AK4497_CONTROL1_ACKS_SHIFT (7U) 64 65 #define AK4497_CONTROL2_SMUTE_MASK (0x1U) 66 #define AK4497_CONTROL2_SMUTE_SHIFT (0U) 67 #define AK4497_CONTROL2_DEM0_MASK (0x2U) 68 #define AK4497_CONTROL2_DEM0_SHIFT (1U) 69 #define AK4497_CONTROL2_DEM1_MASK (0x4U) 70 #define AK4497_CONTROL2_DEM1_SHIFT (2U) 71 #define AK4497_CONTROL2_DFS0_MASK (0x8U) 72 #define AK4497_CONTROL2_DFS0_SHIFT (3U) 73 #define AK4497_CONTROL2_DFS1_MASK (0x10U) 74 #define AK4497_CONTROL2_DFS1_SHIFT (4U) 75 #define AK4497_CONTROL2_SD_MASK (0x20U) 76 #define AK4497_CONTROL2_SD_SHIFT (5U) 77 #define AK4497_CONTROL2_DZFM_MASK (0x40U) 78 #define AK4497_CONTROL2_DZFM_SHIFT (6U) 79 #define AK4497_CONTROL2_DZFE_MASK (0x80U) 80 #define AK4497_CONTROL2_DZFE_SHIFT (7U) 81 82 #define AK4497_CONTROL3_SLOW_MASK (0x1U) 83 #define AK4497_CONTROL3_SLOW_SHIFT (0U) 84 #define AK4497_CONTROL3_SELLR_MASK (0x2U) 85 #define AK4497_CONTROL3_SELLR_SHIFT (1U) 86 #define AK4497_CONTROL3_DZFB_MASK (0x4U) 87 #define AK4497_CONTROL3_DZFB_SHIFT (2U) 88 #define AK4497_CONTROL3_MONO_MASK (0x8U) 89 #define AK4497_CONTROL3_MONO_SHIFT (3U) 90 #define AK4497_CONTROL3_DCKB_MASK (0x10U) 91 #define AK4497_CONTROL3_DCKB_SHIFT (4U) 92 #define AK4497_CONTROL3_DCKS_MASK (0x20U) 93 #define AK4497_CONTROL3_DCKS_SHIFT (5U) 94 #define AK4497_CONTROL3_DP_MASK (0x80U) 95 #define AK4497_CONTROL3_DP_SHIFT (7U) 96 97 #define AK4497_CONTROL4_SSLOW_MASK (0x1U) 98 #define AK4497_CONTROL4_SSLOW_SHIFT (0U) 99 #define AK4497_CONTROL4_DFS2_MASK (0x2U) 100 #define AK4497_CONTROL4_DFS2_SHIFT (1U) 101 #define AK4497_CONTROL4_INVR_MASK (0x40U) 102 #define AK4497_CONTROL4_INVR_SHIFT (6U) 103 #define AK4497_CONTROL4_INVL_MASK (0x80U) 104 #define AK4497_CONTROL4_INVL_SHIFT (7U) 105 106 #define AK4497_DSD1_DSDSEL0_MASK (0x1U) 107 #define AK4497_DSD1_DSDSEL0_SHIFT (0U) 108 #define AK4497_DSD1_DSDD_MASK (0x2U) 109 #define AK4497_DSD1_DSDD_SHIFT (1U) 110 #define AK4497_DSD1_DMRE_MASK (0x8U) 111 #define AK4497_DSD1_DMRE_SHIFT (3U) 112 #define AK4497_DSD1_DMC_MASK (0x10U) 113 #define AK4497_DSD1_DMC_SHIFT (4U) 114 #define AK4497_DSD1_DMR_MASK (0x20U) 115 #define AK4497_DSD1_DMR_SHIFT (5U) 116 #define AK4497_DSD1_DML_MASK (0x40U) 117 #define AK4497_DSD1_DML_SHIFT (6U) 118 #define AK4497_DSD1_DDM_MASK (0x80U) 119 #define AK4497_DSD1_DDM_SHIFT (7U) 120 121 #define AK4497_CONTROL5_SYNCE_MASK (0x1U) 122 #define AK4497_CONTROL5_SYNCE_SHIFT (0U) 123 #define AK4497_CONTROL5_GC0_MASK (0x2U) 124 #define AK4497_CONTROL5_GC0_SHIFT (1U) 125 #define AK4497_CONTROL5_GC1_MASK (0x4U) 126 #define AK4497_CONTROL5_GC1_SHIFT (2U) 127 #define AK4497_CONTROL5_GC2_MASK (0x8U) 128 #define AK4497_CONTROL5_GC2_SHIFT (3U) 129 130 #define AK4497_SOUNDCONTROL_SC0_MASK (0x1U) 131 #define AK4497_SOUNDCONTROL_SC0_SHIFT (0U) 132 #define AK4497_SOUNDCONTROL_SC1_MASK (0x2U) 133 #define AK4497_SOUNDCONTROL_SC1_SHIFT (1U) 134 #define AK4497_SOUNDCONTROL_SC2_MASK (0x4U) 135 #define AK4497_SOUNDCONTROL_SC2_SHIFT (2U) 136 #define AK4497_SOUNDCONTROL_HLOAD_MASK (0x8U) 137 #define AK4497_SOUNDCONTROL_HLOAD_SHIFT (3U) 138 139 #define AK4497_DSD2_DSDSEL1_MASK (0x1U) 140 #define AK4497_DSD2_DSDSEL1_SHIFT (0U) 141 #define AK4497_DSD2_DSDF_MASK (0x2U) 142 #define AK4497_DSD2_DSDF_SHIFT (1U) 143 #define AK4497_DSD2_DSDPATH_MASK (0x4U) 144 #define AK4497_DSD2_DSDPATH_SHIFT (2U) 145 146 #define AK4497_CONTROL7_PW_MASK (0x4U) 147 #define AK4497_CONTROL7_PW_SHIFT (2U) 148 #define AK4497_CONTROL7_SDS2_MASK (0x10U) 149 #define AK4497_CONTROL7_SDS2_SHIFT (4U) 150 #define AK4497_CONTROL7_SDS1_MASK (0x20U) 151 #define AK4497_CONTROL7_SDS1_SHIFT (5U) 152 #define AK4497_CONTROL7_TDM0_MASK (0x40U) 153 #define AK4497_CONTROL7_TDM0_SHIFT (6U) 154 #define AK4497_CONTROL7_TDM1_MASK (0x80U) 155 #define AK4497_CONTROL7_TDM1_SHIFT (7U) 156 157 #define AK4497_CONTROL8_TSET_MASK (0x1U) 158 #define AK4497_CONTROL8_TSET_SHIFT (0U) 159 #define AK4497_CONTROL8_DCHAIN_MASK (0x2U) 160 #define AK4497_CONTROL8_DCHAIN_SHIFT (1U) 161 #define AK4497_CONTROL8_SDS0_MASK (0x10U) 162 #define AK4497_CONTROL8_SDS0_SHIFT (4U) 163 #define AK4497_CONTROL8_ATS0_MASK (0x40U) 164 #define AK4497_CONTROL8_ATS0_SHIFT (6U) 165 #define AK4497_CONTROL8_ATS1_MASK (0x80U) 166 #define AK4497_CONTROL8_ATS1_SHIFT (7U) 167 168 /*! @brief AK4497 I2C address. */ 169 #define AK4497_I2C_ADDR (0x11U) 170 /*! @brief AK4497 i2c baudrate */ 171 #define AK4497_I2C_BITRATE (100000U) 172 /*! @brief The AK4497 playback mode */ 173 typedef enum _ak4497_mode 174 { 175 kAK4497_PcmMode = 0x0, 176 kAK4497_DsdMode = 0x1, 177 kAK4497_ExdfMode = 0x2, 178 } ak4497_mode_t; 179 180 /*! @brief The Data selection of L-channel and R-channel for DSD mode, defined by SELLR bit */ 181 typedef enum _ak4497_data_channel_mode 182 { 183 kAK4497_NormalMode = 0x0, /*!< L-channel output L-channel data, R-channel output R-channel data. */ 184 kAK4497_ExchangeMode = 0x1, /*!< L-channel output R-channel data, R-channel output L-channel data. */ 185 } ak4497_data_channel_mode_t; 186 187 /*! @brief The data path select for DSD mode */ 188 typedef enum _ak4497_dsd_input_path 189 { 190 kAK4497_Path0 = 0x0, /*!< Pin 16,17,19 used. */ 191 kAK4497_Path1 = 0x1, /*!< Pin 3,4,5 used. */ 192 } ak4497_dsd_input_path_t; 193 194 /*! @brief The MCLK select for DSD mode, defined by DCKS bit */ 195 typedef enum _ak4497_dsd_mclk 196 { 197 kAK4497_mclk512fs = 0x0, /*!< MCLK equals 512fs. */ 198 kAK4497_mclk768fs = 0x1, /*!< MCLK equals 768fs. */ 199 } ak4497_dsd_mclk_t; 200 201 /*! @brief The DCLK select for DSD mode, defined by DSDSEL[1:0] */ 202 typedef enum _ak4497_dsd_dclk 203 { 204 kAK4497_dclk64fs = 0x0, /*!< DCLK equals 64fs. */ 205 kAK4497_dclk128fs = 0x1, /*!< DCLK equals 128fs. */ 206 kAK4497_dclk256fs = 0x2, /*!< DCLK equals 256fs. */ 207 kAK4497_dclk512fs = 0x3, /*!< DCLK equals 512fs. */ 208 } ak4497_dsd_dclk_t; 209 210 /*! @brief DSD playback path */ 211 typedef enum _ak4497_dsd_playback_path 212 { 213 kAK4497_NormalPath = 0x0, /*!< Normal path mode. */ 214 kAK4497_VolumeBypass = 0x1, /*!< Volume Bypass mode. */ 215 } ak4497_dsd_playback_path_t; 216 217 /*! @brief DSD mute flag */ 218 typedef enum _ak4497_dsd_data_mute 219 { 220 kAK4497_DsdMuteDisable = 0x0, 221 kAK4497_DsdMuteEnable = 0x1, 222 } ak4497_dsd_data_mute_t; 223 224 /*! @brief DSD bclk polarity */ 225 typedef enum _ak4497_dsd_dclk_polarity 226 { 227 kAK4497_FallingEdge = 0x0, /*!< DSD data is output from DCLK falling edge. */ 228 kAK4497_RisingEdge = 0x1, /*!< DSD data is output from DCLK rising edge. */ 229 } ak4497_dsd_dclk_polarity_t; 230 /*! @brief The sampling frequency mode for PCM and EXDF mode, defined by CR01[AFSD], CR00[ACKS]*/ 231 typedef enum _ak4497_pcm_samplefreqmode 232 { 233 kAK4497_ManualSettingMode = 0x0, /*!< Manual setting mode */ 234 kAK4497_AutoSettingMode = 0x1, /*!< Auto setting mode */ 235 kAK4497_FsAutoDetectMode = 0x2, /*!< Auto detect mode */ 236 } ak4497_pcm_samplefreqmode_t; 237 /*! @brief The sampling speed select, defined by DFS[2:0]*/ 238 typedef enum _ak4497_pcm_samplefreqselect 239 { 240 kAK4497_NormalSpeed = 0x0, /*!< 8kHZ ~ 54kHZ */ 241 kAK4497_DoubleSpeed = 0x1, /*!< 54kHZ ~ 108kHZ */ 242 kAK4497_QuadSpeed = 0x2, /*!< 120kHZ ~ 216kHZ, note that value 3 also stands for Quad Speed Mode */ 243 kAK4497_OctSpeed = 0x4, /*!< 384kHZ, note that value 6 also stands for Oct Speed Mode */ 244 kAK4497_HexSpeed = 0x5, /*!< 768kHZ, note that value 7 also stands for Hex Speed Mode */ 245 } ak4497_pcm_samplefreqselect_t; 246 247 /*! @brief The audio data interface modes, defined by DIF[2:0]*/ 248 typedef enum _ak4497_pcm_sdata_format 249 { 250 kAK4497_16BitLSB = 0x0, /*!< 16-bit LSB justified */ 251 kAK4497_20BitLSB = 0x1, /*!< 20-bit LSB justified */ 252 kAK4497_24BitMSB = 0x2, /*!< 24-bit MSB justified */ 253 kAK4497_16_24BitI2S = 0x3, /*!< 16 and 24-bit I2S compatible */ 254 kAK4497_24BitLSB = 0x4, /*!< 24-bit LSB justified */ 255 kAK4497_32BitLSB = 0x5, /*!< 32-bit LSB justified */ 256 kAK4497_32BitMSB = 0x6, /*!< 32-bit MSB justified */ 257 kAK4497_32BitI2S = 0x7, /*!< 32-bit I2S compatible */ 258 } ak4497_pcm_sdata_format_t; 259 260 /*! @brief The TDM mode select, defined by TDM[1:0]*/ 261 typedef enum _ak4497_pcm_tdm_mode 262 { 263 kAK4497_Normal = 0x0, /*!< Normal mode */ 264 kAK4497_TDM128 = 0x1, /*!< BCLK is fixed to 128fs */ 265 kAK4497_TDM256 = 0x2, /*!< BCLK is fixed to 256fs */ 266 kAK4497_TDM512 = 0x3, /*!< BCLK is fixed to 512fs */ 267 } ak4497_pcm_tdm_mode_t; 268 269 /*! @brief The audio data slot selection, defined by SDS[2:0]*/ 270 typedef enum _ak4497_pcm_sds_select 271 { 272 kAK4497_L1R1 = 0x0, 273 kAK4497_L2R2 = 0x1, 274 kAK4497_L3R3 = 0x2, 275 kAK4497_L4R4 = 0x3, 276 kAK4497_L5R5 = 0x4, 277 kAK4497_L6R6 = 0x5, 278 kAK4497_L7R7 = 0x6, 279 kAK4497_L8R8 = 0x7, 280 } ak4497_pcm_sds_select_t; 281 282 /*! @brief audio codec module control cmd */ 283 typedef enum _ak4497_module_ctrl_cmd 284 { 285 kAK4497_ModuleSwitchI2SInInterface = 0U, /*!< module digital interface siwtch. */ 286 } ak4497_module_ctrl_cmd_t; 287 288 /*! @brief audio codec module digital interface 289 * @anchor _ak4497_module_ctrl_i2s_in_interface 290 */ 291 enum 292 { 293 kAK4497_ModuleI2SInInterfacePCM = 0U, /*!< Pcm interface*/ 294 kAK4497_ModuleI2SInInterfaceDSD = 1U, /*!< DSD interface */ 295 }; 296 297 /*! @brief Initialize DSD mode structure of AK4497 */ 298 typedef struct _ak4497_dsd_config 299 { 300 ak4497_dsd_input_path_t dsdPath; 301 ak4497_dsd_mclk_t dsdMclk; 302 ak4497_dsd_playback_path_t dsdPlaybackPath; 303 ak4497_dsd_data_mute_t dsdDataMute; 304 ak4497_dsd_dclk_polarity_t dsdDclkPolarity; 305 } ak4497_dsd_config_t; 306 307 /*! @brief Initialize PCM mode structure of AK4497 */ 308 typedef struct _ak4497_pcm_config 309 { 310 ak4497_pcm_samplefreqmode_t pcmSampleFreqMode; 311 ak4497_pcm_sdata_format_t pcmSdataFormat; 312 ak4497_pcm_tdm_mode_t pcmTdmMode; 313 ak4497_pcm_sds_select_t pcmSdsSlot; 314 } ak4497_pcm_config_t; 315 316 /*! @brief Initialize structure of AK4497 */ 317 typedef struct _ak4497_config 318 { 319 ak4497_mode_t ak4497Mode; 320 ak4497_data_channel_mode_t dataChannelMode; 321 ak4497_pcm_config_t pcmConfig; 322 ak4497_dsd_config_t dsdConfig; 323 324 uint8_t slaveAddress; /*!< code device slave address */ 325 codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ 326 } ak4497_config_t; 327 328 /*! @brief ak4497 codec handler 329 */ 330 typedef struct _ak4497_handle 331 { 332 ak4497_config_t *config; /*!< ak4497 config pointer */ 333 uint8_t i2cHandle[AK4497_I2C_HANDLER_SIZE]; /*!< i2c handle */ 334 } ak4497_handle_t; 335 336 /******************************************************************************* 337 * API 338 ******************************************************************************/ 339 #if defined(__cplusplus) 340 extern "C" { 341 #endif 342 343 /*! 344 * @brief Default initializes AK4497. 345 * 346 * @param config AK4497 configure structure. 347 */ 348 void AK4497_DefaultConfig(ak4497_config_t *config); 349 /*! 350 * @brief Initializes AK4497. 351 * 352 * @param handle AK4497 handle structure. 353 * @param config AK4497 configure structure. 354 */ 355 status_t AK4497_Init(ak4497_handle_t *handle, ak4497_config_t *config); 356 /*! 357 * @brief Set the codec PCM mode or DSD mode based on the format info 358 * 359 * This function would configure the codec playback mode. 360 * 361 * @param handle AK4497 handle structure pointer. 362 * @param format info. 363 */ 364 status_t AK4497_SetEncoding(ak4497_handle_t *handle, uint8_t format); 365 /*! 366 * @brief Configure the data format of audio data. 367 * 368 * This function would configure the registers about the sample rate, bit depths. 369 * 370 * @param handle AK4497 handle structure pointer. 371 * @param mclk system clock of the codec which can be generated by MCLK or PLL output. 372 * @param sampleRate Sample rate of audio file running in AK4497. 373 * @param bitWidth Bit depth of audio file. 374 */ 375 status_t AK4497_ConfigDataFormat(ak4497_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); 376 377 /*! 378 * @brief Set the volume of different modules in AK4497. 379 * 380 * This function would set the volume of AK4497 modules. Users need to appoint the module. 381 * The function assume that left channel and right channel has the same volume. 382 * 383 * @param handle AK4497 handle structure. 384 * @param value Volume value need to be set. 385 */ 386 status_t AK4497_SetVolume(ak4497_handle_t *handle, uint8_t value); 387 388 /*! 389 * @brief Get the volume of different modules in AK4497. 390 * 391 * This function gets the volume of AK4497. Users need to appoint the module. 392 * The function assume that left channel and right channel has the same volume. 393 * 394 * @param handle AK4497 handle structure. 395 * @param value volume value 396 * @return value value of the module. 397 */ 398 status_t AK4497_GetVolume(ak4497_handle_t *handle, uint8_t *value); 399 400 /*! 401 * @brief AK4497 codec module control. 402 * 403 * @param handle AK4497 handle structure pointer. 404 * @param cmd module control command, support cmd kAK4497_ModuleSwitchDigitalInterface. 405 * @param data control data, support data kCODEC_ModuleDigitalInterfacePCM/kCODEC_ModuleDigitalInterfaceDSD. 406 */ 407 status_t AK4497_ModuleControl(ak4497_handle_t *handle, ak4497_module_ctrl_cmd_t cmd, uint32_t data); 408 409 /*! 410 * @brief Deinit the AK4497 codec. 411 * 412 * This function close all modules in AK4497 to save power. 413 * 414 * @param handle AK4497 handle structure pointer. 415 */ 416 status_t AK4497_Deinit(ak4497_handle_t *handle); 417 /*! 418 * @brief Write register to AK4497 using I2C. 419 * 420 * @param handle AK4497 handle structure. 421 * @param reg The register address in AK4497. 422 * @param val Value needs to write into the register. 423 */ 424 status_t AK4497_WriteReg(ak4497_handle_t *handle, uint8_t reg, uint8_t val); 425 426 /*! 427 * @brief Read register from AK4497 using I2C. 428 * @param handle AK4497 handle structure. 429 * @param reg The register address in AK4497. 430 * @param val Value written to. 431 */ 432 status_t AK4497_ReadReg(ak4497_handle_t *handle, uint8_t reg, uint8_t *val); 433 434 /*! 435 * @brief Modify some bits in the register using I2C. 436 * @param handle AK4497 handle structure. 437 * @param reg The register address in AK4497. 438 * @param mask The mask code for the bits want to write. The bit you want to write should be 0. 439 * @param val Value needs to write into the register. 440 */ 441 status_t AK4497_ModifyReg(ak4497_handle_t *handle, uint8_t reg, uint8_t mask, uint8_t val); 442 443 #if defined(__cplusplus) 444 } 445 #endif 446 447 /*! @} */ 448 #endif /* _FSL_AK4497_H_ */ 449
