1 /* 2 * Copyright 2019,2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_ANATOP_AI_H_ 9 #define _FSL_ANATOP_AI_H_ 10 11 #include "fsl_common.h" 12 /*! @addtogroup anatop_ai */ 13 /*! @{ */ 14 15 /*! @file */ 16 17 /*! @name Driver version */ 18 /*@{*/ 19 /*! @brief Anatop AI driver version 1.0.0. */ 20 #define FSL_ANATOP_AI_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) 21 /*@}*/ 22 23 /*! 24 * @brief Anatop AI ITF enumeration. 25 */ 26 typedef enum _anatop_ai_itf 27 { 28 kAI_Itf_Ldo = 0, /*!< LDO ITF. */ 29 kAI_Itf_1g = 1, /*!< 1G PLL ITF. */ 30 kAI_Itf_Audio = 2, /*!< Audio PLL ITF. */ 31 kAI_Itf_Video = 3, /*!< Video PLL ITF. */ 32 kAI_Itf_400m = 4, /*!< 400M OSC ITF. */ 33 kAI_Itf_Temp = 5, /*!< Temperature Sensor ITF. */ 34 kAI_Itf_Bandgap = 6, /*!< Bandgap ITF. */ 35 } anatop_ai_itf_t; 36 37 /*! 38 * @brief The enumeration of ANATOP AI Register. 39 */ 40 typedef enum _anatop_ai_reg 41 { 42 kAI_PHY_LDO_CTRL0 = 0x0, /*!< PHY LDO CTRL0 Register. */ 43 kAI_PHY_LDO_CTRL0_SET = 0x4, /*!< PHY LDO CTRL0 Set Register. */ 44 kAI_PHY_LDO_CTRL0_CLR = 0x8, /*!< PHY LDO CTRL0 Clr Register. */ 45 kAI_PHY_LDO_CTRL0_TOG = 0xC, /*!< PHY LDO CTRL0 TOG Register. */ 46 kAI_PHY_LDO_STAT0 = 0x50, /*!< PHY LDO STAT0 Register. */ 47 kAI_PHY_LDO_STAT0_SET = 0x54, /*!< PHY LDO STAT0 Set Register. */ 48 kAI_PHY_LDO_STAT0_CLR = 0x58, /*!< PHY LDO STAT0 Clr Register. */ 49 kAI_PHY_LDO_STAT0_TOG = 0x5C, /*!< PHY LDO STAT0 Tog Register. */ 50 51 kAI_BANDGAP_CTRL0 = 0x0, /*!< BANDGAP CTRL0 Register. */ 52 kAI_BANDGAP_STAT0 = 0x50, /*!< BANDGAP STAT0 Register. */ 53 54 kAI_RCOSC400M_CTRL0 = 0x0, /*!< RC OSC 400M CTRL0 Register. */ 55 kAI_RCOSC400M_CTRL0_SET = 0x4, /*!< RC OSC 400M CTRL0 SET Register. */ 56 kAI_RCOSC400M_CTRL0_CLR = 0x8, /*!< RC OSC 400M CTRL0 CLR Register. */ 57 kAI_RCOSC400M_CTRL0_TOG = 0xC, /*!< RC OSC 400M CTRL0 TOG Register. */ 58 kAI_RCOSC400M_CTRL1 = 0x10, /*!< RC OSC 400M CTRL1 Register. */ 59 kAI_RCOSC400M_CTRL1_SET = 0x14, /*!< RC OSC 400M CTRL1 SET Register. */ 60 kAI_RCOSC400M_CTRL1_CLR = 0x18, /*!< RC OSC 400M CTRL1 CLR Register. */ 61 kAI_RCOSC400M_CTRL1_TOG = 0x1C, /*!< RC OSC 400M CTRL1 TOG Register. */ 62 kAI_RCOSC400M_CTRL2 = 0x20, /*!< RC OSC 400M CTRL2 Register. */ 63 kAI_RCOSC400M_CTRL2_SET = 0x24, /*!< RC OSC 400M CTRL2 SET Register. */ 64 kAI_RCOSC400M_CTRL2_CLR = 0x28, /*!< RC OSC 400M CTRL2 CLR Register. */ 65 kAI_RCOSC400M_CTRL2_TOG = 0x2C, /*!< RC OSC 400M CTRL2 TOG Register. */ 66 kAI_RCOSC400M_CTRL3 = 0x30, /*!< RC OSC 400M CTRL3 Register. */ 67 kAI_RCOSC400M_CTRL3_SET = 0x34, /*!< RC OSC 400M CTRL3 SET Register. */ 68 kAI_RCOSC400M_CTRL3_CLR = 0x38, /*!< RC OSC 400M CTRL3 CLR Register. */ 69 kAI_RCOSC400M_CTRL3_TOG = 0x3C, /*!< RC OSC 400M CTRL3 TOG Register. */ 70 kAI_RCOSC400M_STAT0 = 0x50, /*!< RC OSC 400M STAT0 Register. */ 71 kAI_RCOSC400M_STAT0_SET = 0x54, /*!< RC OSC 400M STAT0 SET Register. */ 72 kAI_RCOSC400M_STAT0_CLR = 0x58, /*!< RC OSC 400M STAT0 CLR Register. */ 73 kAI_RCOSC400M_STAT0_TOG = 0x5C, /*!< RC OSC 400M STAT0 TOG Register. */ 74 kAI_RCOSC400M_STAT1 = 0x60, /*!< RC OSC 400M STAT1 Register. */ 75 kAI_RCOSC400M_STAT1_SET = 0x64, /*!< RC OSC 400M STAT1 SET Register. */ 76 kAI_RCOSC400M_STAT1_CLR = 0x68, /*!< RC OSC 400M STAT1 CLR Register. */ 77 kAI_RCOSC400M_STAT1_TOG = 0x6C, /*!< RC OSC 400M STAT1 TOG Register. */ 78 kAI_RCOSC400M_STAT2 = 0x70, /*!< RC OSC 400M STAT2 Register. */ 79 kAI_RCOSC400M_STAT2_SET = 0x74, /*!< RC OSC 400M STAT2 SET Register. */ 80 kAI_RCOSC400M_STAT2_CLR = 0x78, /*!< RC OSC 400M STAT2 CLR Register. */ 81 kAI_RCOSC400M_STAT2_TOG = 0x7C, /*!< RC OSC 400M STAT2 TOG Register. */ 82 83 kAI_PLL1G_CTRL0 = 0x0, /*!< 1G PLL CTRL0 Register. */ 84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ 85 kAI_PLL1G_CTRL0_CLR = 0x8, /*!< 1G PLL CTRL0 CLR Register. */ 86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ 87 kAI_PLL1G_CTRL1_SET = 0x14, /*!< 1G PLL CTRL1 SET Register. */ 88 kAI_PLL1G_CTRL1_CLR = 0x18, /*!< 1G PLL CTRL1 CLR Register. */ 89 kAI_PLL1G_CTRL2 = 0x20, /*!< 1G PLL CTRL2 Register. */ 90 kAI_PLL1G_CTRL2_SET = 0x24, /*!< 1G PLL CTRL2 SET Register. */ 91 kAI_PLL1G_CTRL2_CLR = 0x28, /*!< 1G PLL CTRL2 CLR Register. */ 92 kAI_PLL1G_CTRL3 = 0x30, /*!< 1G PLL CTRL3 Register. */ 93 kAI_PLL1G_CTRL3_SET = 0x34, /*!< 1G PLL CTRL3 SET Register. */ 94 kAI_PLL1G_CTRL3_CLR = 0x38, /*!< 1G PLL CTRL3 CLR Register. */ 95 96 kAI_PLLAUDIO_CTRL0 = 0x0, /*!< AUDIO PLL CTRL0 Register. */ 97 kAI_PLLAUDIO_CTRL0_SET = 0x4, /*!< AUDIO PLL CTRL0 SET Register. */ 98 kAI_PLLAUDIO_CTRL0_CLR = 0x8, /*!< AUDIO PLL CTRL0 CLR Register. */ 99 kAI_PLLAUDIO_CTRL1 = 0x10, /*!< AUDIO PLL CTRL1 Register. */ 100 kAI_PLLAUDIO_CTRL1_SET = 0x14, /*!< AUDIO PLL CTRL1 SET Register. */ 101 kAI_PLLAUDIO_CTRL1_CLR = 0x18, /*!< AUDIO PLL CTRL1 CLR Register. */ 102 kAI_PLLAUDIO_CTRL2 = 0x20, /*!< AUDIO PLL CTRL2 Register. */ 103 kAI_PLLAUDIO_CTRL2_SET = 0x24, /*!< AUDIO PLL CTRL2 SET Register. */ 104 kAI_PLLAUDIO_CTRL2_CLR = 0x28, /*!< AUDIO PLL CTRL2 CLR Register. */ 105 kAI_PLLAUDIO_CTRL3 = 0x30, /*!< AUDIO PLL CTRL3 Register. */ 106 kAI_PLLAUDIO_CTRL3_SET = 0x34, /*!< AUDIO PLL CTRL3 SET Register. */ 107 kAI_PLLAUDIO_CTRL3_CLR = 0x38, /*!< AUDIO PLL CTRL3 CLR Register. */ 108 109 kAI_PLLVIDEO_CTRL0 = 0x0, /*!< VIDEO PLL CTRL0 Register. */ 110 kAI_PLLVIDEO_CTRL0_SET = 0x4, /*!< VIDEO PLL CTRL0 SET Register. */ 111 kAI_PLLVIDEO_CTRL0_CLR = 0x8, /*!< VIDEO PLL CTRL0 CLR Register. */ 112 kAI_PLLVIDEO_CTRL1 = 0x10, /*!< VIDEO PLL CTRL1 Register. */ 113 kAI_PLLVIDEO_CTRL1_SET = 0x14, /*!< VIDEO PLL CTRL1 SET Register. */ 114 kAI_PLLVIDEO_CTRL1_CLR = 0x18, /*!< VIDEO PLL CTRL1 CLR Register. */ 115 kAI_PLLVIDEO_CTRL2 = 0x20, /*!< VIDEO PLL CTRL2 Register. */ 116 kAI_PLLVIDEO_CTRL2_SET = 0x24, /*!< VIDEO PLL CTRL2 SET Register. */ 117 kAI_PLLVIDEO_CTRL2_CLR = 0x28, /*!< VIDEO PLL CTRL2 CLR Register. */ 118 kAI_PLLVIDEO_CTRL3 = 0x30, /*!< VIDEO PLL CTRL3 Register. */ 119 kAI_PLLVIDEO_CTRL3_SET = 0x34, /*!< VIDEO PLL CTRL3 SET Register. */ 120 kAI_PLLVIDEO_CTRL3_CLR = 0x38, /*!< VIDEO PLL CTRL3 CLR Register. */ 121 } anatop_ai_reg_t; 122 123 /* ---------------------------------------------------------------------------- 124 -- AI PHY_LDO CTRL0 Register Masks 125 ---------------------------------------------------------------------------- */ 126 127 /*! @name CTRL0 - CTRL0 Register */ 128 /*! @{ */ 129 #define AI_PHY_LDO_CTRL0_LINREG_EN(x) \ 130 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK) 131 #define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) 132 #define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) 133 134 /*! LINREG_EN - LinReg master enable 135 * LinReg master enable. Setting this bit will enable the regular 136 */ 137 138 #define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) \ 139 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK) 140 #define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U) 141 #define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U) 142 /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable 143 * 0b0..Internal pull-down enabled 144 * 0b1..Internal pull-down disabled 145 */ 146 147 #define AI_PHY_LDO_CTRL0_LIMIT_EN(x) \ 148 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK) 149 #define AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U) 150 #define AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U) 151 /*! LINREG_LIMIT_EN - LinReg current limit enable 152 * LinReg current-limit enable. Setting this bit will enable the 153 * current-limiter in the regulator 154 */ 155 156 #define AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) \ 157 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK) 158 #define AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U) 159 #define AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U) 160 /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting 161 * 0b00000..Set output voltage to x.xV 162 * 0b10000..Set output voltage to 1.0V 163 * 0b11111..Set output voltage to x.xV 164 */ 165 166 #define AI_PHY_LDO_CTRL0_PHY_ISO_B(x) \ 167 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK) 168 #define AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U) 169 #define AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U) 170 /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load 171 * This control bit is to be used by the system controller to isolate the 172 * attached PHY load when the LinReg is powered down. During a power-up 173 * event of the regulator it is expected that this control signal is set high 174 * at least 100us after the main regulator is enabled. During a power-down 175 * event of the regulator it is expected that this control signal is set low 176 * before the main regulator is disabled/power-down. 177 */ 178 /*! @} */ 179 180 /*! @name STAT0 - STAT0 Register */ 181 /*! @{ */ 182 #define AI_PHY_LDO_STAT0_LINREG_STAT(x) \ 183 (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK) 184 #define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) 185 #define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) 186 187 /*! LINREG_STAT - LinReg status bits 188 * LinReg status bits. 189 */ 190 191 /*! @} */ 192 193 /*! @name CTRL0 - CTRL0 Register */ 194 /*! @{ */ 195 #define AI_BANDGAP_CTRL0_REFTOP_PWD(x) \ 196 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK) 197 #define AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) 198 #define AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) 199 /*! REFTOP_PWD - This bit fully powers down the bandgap module. 200 * Setting this bit high will disable reference output currents and voltages from the 201 * bandgap and will affect functionality and validity of the voltage detectors. 202 */ 203 204 #define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) \ 205 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & \ 206 AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK) 207 #define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) 208 #define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) 209 /*! 210 * REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap. 211 * Setting this bit high will affect functionality and validity 212 * of the voltage detectors. 213 */ 214 215 #define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) \ 216 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) 217 #define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) 218 #define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) 219 /*! 220 * REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap 221 * without affecting any additional functionality. 222 */ 223 224 #define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) \ 225 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) 226 #define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) 227 #define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) 228 /*! 229 * REFTOP_LOWPOWER - This bit enables the low-power operation of the 230 * bandgap by cutting the bias currents in half to the main amplifiers. 231 * This will save power but could affect the accuracy of the output voltages and currents. 232 */ 233 234 #define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) \ 235 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \ 236 AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK) 237 #define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) 238 #define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) 239 /*! 240 * REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap. 241 * The self-bias circuit is used by the bandgap during startup. This bit should be 242 * set high after the bandgap has stabilized and is necessary for best noise performance 243 * of modules using the outputs of the bandgap. It is expected that this control bit 244 * be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed. 245 */ 246 247 #define AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) \ 248 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK) 249 #define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) 250 #define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U) 251 /*! 252 * REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed 253 * 000 : nominal 254 * 001 : +10mV 255 * 010 : +20mV 256 * 011 : +30mV 257 * 100 : -10mV 258 * 101 : -20mV 259 * 110 : -30mV 260 * 111 : -40mV 261 */ 262 263 #define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) \ 264 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK) 265 #define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) 266 #define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) 267 /*! 268 * REFTOP_IBZTCADJ - These bits allow trimming of the ZTC bias currents from the bandgap to 269 * the temperature sensors. Assuming a typical process corner the expected values of output 270 * currents are: 271 * 000 : 11.5 uA 272 * 001 : 11.8 uA 273 * 010 : 12.1 uA 274 * 100 : 12.4 uA (Nominal expected from MX8QM tempsensor) 275 * 101 : 12.7 uA 276 * 110 : 13.0 uA 277 * 111 : 13.3 uA 278 */ 279 280 /*! @} */ 281 282 /*! @name STAT0 - STAT0 Register */ 283 /*! @{ */ 284 #define AI_BANDGAP_STAT0_REFTOP_VBGUP(x) \ 285 (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) 286 #define AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U) 287 #define AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U) 288 /*! @} */ 289 290 /*! @name CTRL0 - CTRL0 Register */ 291 /*! @{ */ 292 #define AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) \ 293 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) 294 #define AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) 295 #define AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U) 296 /*! @} */ 297 298 /*! @name CTRL1 - CTRL1 Register */ 299 /*! @{ */ 300 #define AI_RCOSC400M_CTRL1_HYST_MINUS(x) \ 301 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK) 302 #define AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU) 303 #define AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U) 304 305 #define AI_RCOSC400M_CTRL1_HYST_PLUS(x) \ 306 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK) 307 #define AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U) 308 #define AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U) 309 310 #define AI_RCOSC400M_CTRL1_TARGET_COUNT(x) \ 311 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) 312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) 313 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U) 314 /*! @} */ 315 316 /*! @name CTRL2 - CTRL2 Register */ 317 /*! @{ */ 318 #define AI_RCOSC400M_CTRL2_TUNE_BYP(x) \ 319 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK) 320 #define AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U) 321 #define AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U) 322 323 #define AI_RCOSC400M_CTRL2_TUNE_EN(x) \ 324 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK) 325 #define AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U) 326 #define AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U) 327 328 #define AI_RCOSC400M_CTRL2_TUNE_START(x) \ 329 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK) 330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) 331 #define AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U) 332 333 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) \ 334 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK) 335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) 336 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) 337 /*! @} */ 338 339 /*! @name CTRL3 - CTRL3 Register */ 340 /*! @{ */ 341 #define AI_RCOSC400M_CTRL3_CLR_ERR(x) \ 342 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK) 343 #define AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U) 344 #define AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U) 345 346 #define AI_RCOSC400M_CTRL3_EN_1M_CLK(x) \ 347 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK) 348 #define AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U) 349 #define AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U) 350 351 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) \ 352 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK) 353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) 354 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U) 355 356 #define AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) \ 357 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK) 358 #define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) 359 #define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U) 360 /*! @} */ 361 362 /*! @name STAT0 - STAT0 Register */ 363 /*! @{ */ 364 #define AI_RCOSC400M_STAT0_CLK1M_ERR(x) \ 365 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) 366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) 367 #define AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U) 368 /*! @} */ 369 370 /*! @name STAT1 - STAT1 Register */ 371 /*! @{ */ 372 #define AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) \ 373 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK) 374 #define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) 375 #define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U) 376 /*! @} */ 377 378 /*! @name STAT2 - STAT2 Register */ 379 /*! @{ */ 380 #define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) \ 381 (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & \ 382 AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK) 383 #define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) 384 #define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) 385 /*! @} */ 386 387 /*! @name CTRL0 - CTRL0 Register */ 388 /*! @{ */ 389 #define AI_PLL1G_CTRL0_HOLD_RING_OFF(x) \ 390 (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK) 391 #define AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) 392 #define AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U) 393 394 #define AI_PLL1G_CTRL0_POWER_UP(x) \ 395 (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK) 396 #define AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL) 397 #define AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U) 398 399 #define AI_PLL1G_CTRL0_ENABLE(x) \ 400 (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK) 401 #define AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL) 402 #define AI_PLL1G_CTRL0_ENABLE_SHIFT (15U) 403 404 #define AI_PLL1G_CTRL0_BYPASS(x) \ 405 (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK) 406 #define AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL) 407 #define AI_PLL1G_CTRL0_BYPASS_SHIFT (16U) 408 409 #define AI_PLL1G_CTRL0_PLL_REG_EN(x) \ 410 (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK) 411 #define AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL) 412 #define AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U) 413 /*! @} */ 414 415 /*! @name CTRL0 - CTRL0 Register */ 416 /*! @{ */ 417 #define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) \ 418 (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK) 419 #define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) 420 #define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U) 421 422 #define AI_PLLAUDIO_CTRL0_POWER_UP(x) \ 423 (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK) 424 #define AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL) 425 #define AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U) 426 427 #define AI_PLLAUDIO_CTRL0_ENABLE(x) \ 428 (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK) 429 #define AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL) 430 #define AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U) 431 432 #define AI_PLLAUDIO_CTRL0_BYPASS(x) \ 433 (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK) 434 #define AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL) 435 #define AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U) 436 437 #define AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) \ 438 (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK) 439 #define AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL) 440 #define AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U) 441 /*! @} */ 442 443 /*! @name CTRL0 - CTRL0 Register */ 444 /*! @{ */ 445 #define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) \ 446 (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK) 447 #define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) 448 #define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U) 449 450 #define AI_PLLVIDEO_CTRL0_POWER_UP(x) \ 451 (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK) 452 #define AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL) 453 #define AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U) 454 455 #define AI_PLLVIDEO_CTRL0_ENABLE(x) \ 456 (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK) 457 #define AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL) 458 #define AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U) 459 460 #define AI_PLLVIDEO_CTRL0_BYPASS(x) \ 461 (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK) 462 #define AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL) 463 #define AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U) 464 465 #define AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) \ 466 (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK) 467 #define AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL) 468 #define AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U) 469 /*! @} */ 470 471 /*! @} */ 472 473 /******************************************************************************* 474 * API 475 ******************************************************************************/ 476 477 #if defined(__cplusplus) 478 extern "C" { 479 #endif /* __cplusplus */ 480 481 /*! 482 * @brief AI interface access 483 * 484 * @param itf AI interface name 485 * @param isWrite write enable 486 * @param addr address 487 * @param wdata data to be set 488 * 489 */ 490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata); 491 492 /*! 493 * @brief AI interface writing 494 * 495 * @param itf AI interface name 496 * @param addr address 497 * @param wdata data to be set 498 * 499 */ 500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata); 501 502 /*! 503 * @brief AI interface reading 504 * 505 * @param itf AI interface name 506 * @param addr address 507 * @return data read 508 * 509 */ 510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr); 511 512 /*! 513 * @brief AI interface write with mask and shift 514 * 515 * @param itf AI interface name 516 * @param addr address 517 * @param wdata data to be written 518 * @param mask bit field mask 519 * @param shift bit field shift 520 * 521 */ 522 void ANATOP_AI_WriteWithMaskShift( 523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift); 524 525 /* @} */ 526 527 #if defined(__cplusplus) 528 } 529 #endif /* __cplusplus */ 530 531 /*! @} */ 532 533 #endif /* _FSL_ANATOP_AI_H_ */ 534
