1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_ADC_ETC_H_
10 #define _FSL_ADC_ETC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup adc_etc
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22 /*! @brief ADC_ETC driver version */
23 #define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
24 /*! @brief The mask of status flags cleared by writing 1. */
25 #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
26
27 /*!
28 * @brief ADC_ETC customized status flags mask.
29 */
30 enum _adc_etc_status_flag_mask
31 {
32 kADC_ETC_Done0StatusFlagMask = 1U << 0U,
33 kADC_ETC_Done1StatusFlagMask = 1U << 1U,
34 kADC_ETC_Done2StatusFlagMask = 1U << 2U,
35 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
36 kADC_ETC_Done3StatusFlagMask = 1U << 3U,
37 kADC_ETC_ErrorStatusFlagMask = 1U << 4U,
38 #else
39 kADC_ETC_ErrorStatusFlagMask = 1U << 3U,
40 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
41 };
42
43 /*!
44 * @brief External triggers sources.
45 */
46 typedef enum _adc_etc_external_trigger_source
47 {
48 /* External XBAR sources. Support HW or SW mode. */
49 kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
50 kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
51 kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
52 kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
53 kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
54 kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
55 kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
56 kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
57 /* External TSC sources. Only support HW mode. */
58 kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
59 kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
60 } adc_etc_external_trigger_source_t;
61
62 /*!
63 * @brief Interrupt enable/disable mask.
64 */
65 typedef enum _adc_etc_interrupt_enable
66 {
67 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
68 kADC_ETC_Done0InterruptEnable = 0U, /* Enable the DONE0 interrupt when ADC conversions complete. */
69 kADC_ETC_Done1InterruptEnable = 1U, /* Enable the DONE1 interrupt when ADC conversions complete. */
70 kADC_ETC_Done2InterruptEnable = 2U, /* Enable the DONE2 interrupt when ADC conversions complete. */
71 kADC_ETC_Done3InterruptEnable = 3U, /* Enable the DONE3 interrupt when ADC conversions complete. */
72 #else
73 kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
74 kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
75 kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
76 kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
77 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
78 } adc_etc_interrupt_enable_t;
79
80 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
81 /*!
82 * @brief DMA mode selection.
83 */
84 typedef enum _adc_etc_dma_mode_selection
85 {
86 kADC_ETC_TrigDMAWithLatchedSignal =
87 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
88 kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
89 } adc_etc_dma_mode_selection_t;
90 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
91
92 /*!
93 * @brief ADC_ETC configuration.
94 */
95 typedef struct _adc_etc_config
96 {
97 #if ((!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
98 (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)))
99 bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
100 Otherwise TSC would trigger ADC through ADC_ETC. */
101 #endif
102
103 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
104 bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
105 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
106
107 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
108 bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
109 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
110
111 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
112 adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
113 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
114
115 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
116 uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
117 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
118
119 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
120 uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
121 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
122 uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
123 Clock would be divided by (clockPreDivider+1). */
124 uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
125 trigger7:0x80
126 For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
127 enabled. */
128 } adc_etc_config_t;
129
130 /*!
131 * @brief ADC_ETC trigger chain configuration.
132 */
133 typedef struct _adc_etc_trigger_chain_config
134 {
135 bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
136 wait until interval delay is reached. */
137 uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
138 uint32_t ADCChannelSelect; /* Select ADC sample channel. */
139 adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
140 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
141 bool enableIrq; /* Enable IRQ for selected interrupt enable choice in "InterruptEnable" */
142 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
143 } adc_etc_trigger_chain_config_t;
144
145 /*!
146 * @brief ADC_ETC trigger configuration.
147 */
148 typedef struct _adc_etc_trigger_config
149 {
150 bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
151 In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
152 bool enableSWTriggerMode; /* Enable the sofware trigger mode. */
153 uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
154 uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */
155 uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
156 uint32_t initialDelay; /* Set trigger initial delay. */
157 } adc_etc_trigger_config_t;
158
159 /*******************************************************************************
160 * API
161 ******************************************************************************/
162 #if defined(__cplusplus)
163 extern "C" {
164 #endif
165
166 /*!
167 * @name Initialization
168 * @{
169 */
170
171 /*!
172 * @brief Initialize the ADC_ETC module.
173 *
174 * @param base ADC_ETC peripheral base address.
175 * @param config Pointer to "adc_etc_config_t" structure.
176 */
177 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
178
179 /*!
180 * @brief De-Initialize the ADC_ETC module.
181 *
182 * @param base ADC_ETC peripheral base address.
183 */
184 void ADC_ETC_Deinit(ADC_ETC_Type *base);
185
186 /*!
187 * @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
188 * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
189 * @code
190 * config->enableTSCBypass = true;
191 * config->enableTSC0Trigger = false;
192 * config->enableTSC1Trigger = false;
193 * config->TSC0triggerPriority = 0U;
194 * config->TSC1triggerPriority = 0U;
195 * config->clockPreDivider = 0U;
196 * config->XBARtriggerMask = 0U;
197 * @endcode
198 *
199 * @param config Pointer to "adc_etc_config_t" structure.
200 */
201 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
202
203 /*!
204 * @brief Set the external XBAR trigger configuration.
205 *
206 * @param base ADC_ETC peripheral base address.
207 * @param triggerGroup Trigger group index.
208 * @param config Pointer to "adc_etc_trigger_config_t" structure.
209 */
210 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
211
212 /*!
213 * @brief Set the external XBAR trigger chain configuration.
214 * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
215 * configurated.
216 *
217 * @param base ADC_ETC peripheral base address.
218 * @param triggerGroup Trigger group index. Available number is 0~7.
219 * @param chainGroup Trigger chain group index. Available number is 0~7.
220 * @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
221 */
222 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
223 uint32_t triggerGroup,
224 uint32_t chainGroup,
225 const adc_etc_trigger_chain_config_t *config);
226
227 /*!
228 * @brief Gets the interrupt status flags of external XBAR and TSC triggers.
229 *
230 * @param base ADC_ETC peripheral base address.
231 * @param sourceIndex trigger source index.
232 *
233 * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
234 */
235 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
236
237 /*!
238 * @brief Clears the ADC_ETC's interrupt status falgs.
239 *
240 * @param base ADC_ETC peripheral base address.
241 * @param sourceIndex trigger source index.
242 * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
243 */
244 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
245 adc_etc_external_trigger_source_t sourceIndex,
246 uint32_t mask);
247
248 /*!
249 * @brief Enable the DMA corresponding to each trigger source.
250 *
251 * @param base ADC_ETC peripheral base address.
252 * @param triggerGroup Trigger group index. Available number is 0~7.
253 */
ADC_ETC_EnableDMA(ADC_ETC_Type * base,uint32_t triggerGroup)254 static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
255 {
256 /* Avoid clearing status flags at the same time. */
257 base->DMA_CTRL = (base->DMA_CTRL | ((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
258 ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
259 }
260
261 /*!
262 * @brief Disable the DMA corresponding to each trigger sources.
263 *
264 * @param base ADC_ETC peripheral base address.
265 * @param triggerGroup Trigger group index. Available number is 0~7.
266 */
ADC_ETC_DisableDMA(ADC_ETC_Type * base,uint32_t triggerGroup)267 static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
268 {
269 /* Avoid clearing status flags at the same time. */
270 base->DMA_CTRL = (base->DMA_CTRL & ~((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
271 ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
272 }
273
274 /*!
275 * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
276 *
277 * @param base ADC_ETC peripheral base address.
278 * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
279 * trigger7:0x80.
280 */
ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type * base)281 static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
282 {
283 return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
284 }
285
286 /*!
287 * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
288 *
289 * @param base ADC_ETC peripheral base address.
290 * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
291 * trigger7:0x80.
292 */
ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type * base,uint32_t mask)293 static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
294 {
295 base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
296 }
297
298 /*!
299 * @brief When enable, all logical will be reset.
300 *
301 * @param base ADC_ETC peripheral base address.
302 * @param enable Enable/Disable the software reset.
303 */
ADC_ETC_DoSoftwareReset(ADC_ETC_Type * base,bool enable)304 static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
305 {
306 if (enable)
307 {
308 base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
309 }
310 else
311 {
312 base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
313 }
314 }
315
316 /*!
317 * @brief Do software trigger corresponding to each XBAR trigger sources.
318 * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
319 * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
320 * can only work in hardware trigger mode.
321 *
322 * @param base ADC_ETC peripheral base address.
323 * @param triggerGroup Trigger group index. Available number is 0~7.
324 */
ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type * base,uint32_t triggerGroup)325 static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
326 {
327 assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
328
329 base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
330 }
331
332 /*!
333 * @brief Get ADC conversion result from external XBAR sources.
334 * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
335 * return Trigger0 source's chain1 conversion result.
336 *
337 * @param base ADC_ETC peripheral base address.
338 * @param triggerGroup Trigger group index. Available number is 0~7.
339 * @param chainGroup Trigger chain group index. Available number is 0~7.
340 * @return ADC conversion result value.
341 */
342 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
343
344 /* @} */
345
346 #if defined(__cplusplus)
347 }
348 #endif
349
350 /* @} */
351
352 #endif /* _FSL_ADC_ETC_H_ */
353
