1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <assert.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gicv3.h> 13 #include <lib/utils.h> 14 #include <lib/mmio.h> 15 #include <plat/common/platform.h> 16 17 #include <k3_gicv3.h> 18 19 /* The GICv3 driver only needs to be initialized in EL3 */ 20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 21 22 #if K3_PM_SYSTEM_SUSPEND 23 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT]; 24 static gicv3_dist_ctx_t dist_ctx; 25 #endif 26 27 static const interrupt_prop_t k3_interrupt_props[] = { 28 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 29 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) 30 }; 31 k3_mpidr_to_core_pos(unsigned long mpidr)32static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr) 33 { 34 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 35 } 36 37 gicv3_driver_data_t k3_gic_data = { 38 .rdistif_num = PLATFORM_CORE_COUNT, 39 .rdistif_base_addrs = rdistif_base_addrs, 40 .interrupt_props = k3_interrupt_props, 41 .interrupt_props_num = ARRAY_SIZE(k3_interrupt_props), 42 .mpidr_to_core_pos = k3_mpidr_to_core_pos, 43 }; 44 k3_gic_driver_init(uintptr_t gic_base)45void k3_gic_driver_init(uintptr_t gic_base) 46 { 47 /* GIC Distributor is always at the base of the IP */ 48 uintptr_t gicd_base = gic_base; 49 /* GIC Redistributor base is run-time detected */ 50 uintptr_t gicr_base = 0; 51 52 for (unsigned int gicr_shift = 18; gicr_shift < 21; gicr_shift++) { 53 uintptr_t gicr_check = gic_base + BIT(gicr_shift); 54 uint32_t iidr = mmio_read_32(gicr_check + GICR_IIDR); 55 if (iidr != 0) { 56 /* Found the GICR base */ 57 gicr_base = gicr_check; 58 break; 59 } 60 } 61 /* Assert if we have not found the GICR base */ 62 assert(gicr_base != 0); 63 64 /* 65 * The GICv3 driver is initialized in EL3 and does not need 66 * to be initialized again in SEL1. This is because the S-EL1 67 * can use GIC system registers to manage interrupts and does 68 * not need GIC interface base addresses to be configured. 69 */ 70 k3_gic_data.gicd_base = gicd_base; 71 k3_gic_data.gicr_base = gicr_base; 72 gicv3_driver_init(&k3_gic_data); 73 } 74 k3_gic_init(void)75void k3_gic_init(void) 76 { 77 gicv3_distif_init(); 78 gicv3_rdistif_init(plat_my_core_pos()); 79 gicv3_cpuif_enable(plat_my_core_pos()); 80 } 81 k3_gic_cpuif_enable(void)82void k3_gic_cpuif_enable(void) 83 { 84 gicv3_cpuif_enable(plat_my_core_pos()); 85 } 86 k3_gic_cpuif_disable(void)87void k3_gic_cpuif_disable(void) 88 { 89 gicv3_cpuif_disable(plat_my_core_pos()); 90 } 91 k3_gic_pcpu_init(void)92void k3_gic_pcpu_init(void) 93 { 94 gicv3_rdistif_init(plat_my_core_pos()); 95 } 96 97 #if K3_PM_SYSTEM_SUSPEND k3_gic_save_context(void)98void k3_gic_save_context(void) 99 { 100 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { 101 gicv3_rdistif_save(i, &rdist_ctx[i]); 102 } 103 gicv3_distif_save(&dist_ctx); 104 } 105 k3_gic_restore_context(void)106void k3_gic_restore_context(void) 107 { 108 gicv3_distif_init_restore(&dist_ctx); 109 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { 110 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); 111 } 112 } 113 #endif 114
