1 /**
2 ******************************************************************************
3 * @file ism330is_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ISM330IS driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ism330is_reg.h"
21
22 /**
23 * @defgroup ISM330IS
24 * @brief This file provides a set of functions needed to drive the
25 * ism330is enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ism330is_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx communication interface handler.(ptr)
64 * @param reg first register address to write.
65 * @param data the buffer contains data to be written.(ptr)
66 * @param len number of consecutive register to write.
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
ism330is_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup ISM330IS_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
ism330is_from_fs2g_to_mg(int16_t lsb)93 float_t ism330is_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
ism330is_from_fs4g_to_mg(int16_t lsb)98 float_t ism330is_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
ism330is_from_fs8g_to_mg(int16_t lsb)103 float_t ism330is_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
ism330is_from_fs16g_to_mg(int16_t lsb)108 float_t ism330is_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
ism330is_from_fs125dps_to_mdps(int16_t lsb)113 float_t ism330is_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
ism330is_from_fs250dps_to_mdps(int16_t lsb)118 float_t ism330is_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.75f);
121 }
122
ism330is_from_fs500dps_to_mdps(int16_t lsb)123 float_t ism330is_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
ism330is_from_fs1000dps_to_mdps(int16_t lsb)128 float_t ism330is_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
ism330is_from_fs2000dps_to_mdps(int16_t lsb)133 float_t ism330is_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
ism330is_from_lsb_to_celsius(int16_t lsb)138 float_t ism330is_from_lsb_to_celsius(int16_t lsb)
139 {
140 return (((float_t)lsb / 256.0f) + 25.0f);
141 }
142
143 /**
144 * @defgroup Common
145 * @brief Common
146 * @{/
147 *
148 */
149
150 /**
151 * @brief Difference in percentage of the effective ODR (and timestamp rate)
152 * with respect to the typical.[set]
153 * Step: 0.15%. 8-bit format, 2's complement.
154 *
155 * @param ctx Read / write interface definitions.(ptr)
156 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
157 * @retval Interface status (MANDATORY: return 0 -> no Error).
158 *
159 */
ism330is_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)160 int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
161 {
162 ism330is_internal_freq_fine_t internal_freq_fine;
163 int32_t ret;
164
165 ret = ism330is_read_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE,
166 (uint8_t *)&internal_freq_fine, 1);
167
168 if (ret == 0)
169 {
170 internal_freq_fine.freq_fine = (uint8_t)val;
171 ret = ism330is_write_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE,
172 (uint8_t *)&internal_freq_fine, 1);
173 }
174
175 return ret;
176 }
177
178 /**
179 * @brief Difference in percentage of the effective ODR (and timestamp rate)
180 * with respect to the typical.[get]
181 * Step: 0.15%. 8-bit format, 2's complement.
182 *
183 * @param ctx Read / write interface definitions.(ptr)
184 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
185 * @retval Interface status (MANDATORY: return 0 -> no Error).
186 *
187 */
ism330is_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)188 int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
189 {
190 ism330is_internal_freq_fine_t internal_freq_fine;
191 int32_t ret;
192
193 ret = ism330is_read_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE,
194 (uint8_t *)&internal_freq_fine, 1);
195 *val = internal_freq_fine.freq_fine;
196
197 return ret;
198 }
199
200 /**
201 * @brief Change memory bank.[set]
202 *
203 * @param ctx read / write interface definitions
204 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
205 * @retval interface status (MANDATORY: return 0 -> no Error)
206 *
207 */
ism330is_mem_bank_set(stmdev_ctx_t * ctx,ism330is_mem_bank_t val)208 int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val)
209 {
210 ism330is_func_cfg_access_t func_cfg_access = {0x0};
211 int32_t ret;
212
213 /* no need to read it first as the only other field is a ispu reset bit */
214 func_cfg_access.shub_reg_access = (val == ISM330IS_SENSOR_HUB_MEM_BANK) ? 0x1U : 0x0U;
215 func_cfg_access.ispu_reg_access = (val == ISM330IS_ISPU_MEM_BANK) ? 0x1U : 0x0U;
216 ret = ism330is_write_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
217
218 return ret;
219 }
220
221 /**
222 * @brief Change memory bank.[get]
223 *
224 * @param ctx read / write interface definitions
225 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
226 * @retval interface status (MANDATORY: return 0 -> no Error)
227 *
228 */
ism330is_mem_bank_get(stmdev_ctx_t * ctx,ism330is_mem_bank_t * val)229 int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val)
230 {
231 ism330is_func_cfg_access_t func_cfg_access;
232 int32_t ret;
233
234 ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
235
236 if (func_cfg_access.shub_reg_access == 1U)
237 {
238 *val = ISM330IS_SENSOR_HUB_MEM_BANK;
239 }
240 else if (func_cfg_access.ispu_reg_access == 1U)
241 {
242 *val = ISM330IS_ISPU_MEM_BANK;
243 }
244 else
245 {
246 *val = ISM330IS_MAIN_MEM_BANK;
247 }
248
249 return ret;
250 }
251
252 /**
253 * @brief Enables pulsed data-ready mode (~75 us).[set]
254 *
255 * @param ctx read / write interface definitions
256 * @param val DRDY_LATCHED, DRDY_PULSED,
257 * @retval interface status (MANDATORY: return 0 -> no Error)
258 *
259 */
ism330is_data_ready_mode_set(stmdev_ctx_t * ctx,ism330is_data_ready_mode_t val)260 int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx,
261 ism330is_data_ready_mode_t val)
262 {
263 ism330is_drdy_pulsed_reg_t drdy_pulsed_reg;
264 int32_t ret;
265
266 ret = ism330is_read_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
267
268 if (ret == 0)
269 {
270 drdy_pulsed_reg.drdy_pulsed = ((uint8_t)val & 0x1U);
271 ret = ism330is_write_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
272 }
273
274 return ret;
275 }
276
277 /**
278 * @brief Enables pulsed data-ready mode (~75 us).[get]
279 *
280 * @param ctx read / write interface definitions
281 * @param val DRDY_LATCHED, DRDY_PULSED,
282 * @retval interface status (MANDATORY: return 0 -> no Error)
283 *
284 */
ism330is_data_ready_mode_get(stmdev_ctx_t * ctx,ism330is_data_ready_mode_t * val)285 int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx,
286 ism330is_data_ready_mode_t *val)
287 {
288 ism330is_drdy_pulsed_reg_t drdy_pulsed_reg;
289 int32_t ret;
290
291 ret = ism330is_read_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
292
293 switch ((drdy_pulsed_reg.drdy_pulsed))
294 {
295 case ISM330IS_DRDY_LATCHED:
296 *val = ISM330IS_DRDY_LATCHED;
297 break;
298
299 case ISM330IS_DRDY_PULSED:
300 *val = ISM330IS_DRDY_PULSED;
301 break;
302
303 default:
304 *val = ISM330IS_DRDY_LATCHED;
305 break;
306 }
307 return ret;
308 }
309
310 /**
311 * @brief Device ID.[get]
312 *
313 * @param ctx read / write interface definitions
314 * @param val Device ID.
315 * @retval interface status (MANDATORY: return 0 -> no Error)
316 *
317 */
ism330is_device_id_get(stmdev_ctx_t * ctx,uint8_t * val)318 int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val)
319 {
320 int32_t ret;
321
322 ret = ism330is_read_reg(ctx, ISM330IS_WHO_AM_I, (uint8_t *)val, 1);
323
324 return ret;
325 }
326
327 /**
328 * @brief Software reset. Restore the default values in user registers.[set]
329 *
330 * @param ctx Read / write interface definitions.(ptr)
331 * @retval Interface status (MANDATORY: return 0 -> no Error).
332 *
333 */
ism330is_software_reset(stmdev_ctx_t * ctx)334 int32_t ism330is_software_reset(stmdev_ctx_t *ctx)
335 {
336 ism330is_ctrl3_c_t ctrl3_c;
337 int32_t ret;
338
339 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
340
341 if (ret == 0)
342 {
343 ret += ism330is_xl_data_rate_set(ctx, ISM330IS_XL_ODR_OFF);
344 ret += ism330is_gy_data_rate_set(ctx, ISM330IS_GY_ODR_OFF);
345
346 ctrl3_c.sw_reset = PROPERTY_ENABLE;
347 ret += ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
348
349 do {
350 ret += ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
351 } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE);
352 }
353
354 return ret;
355 }
356
357 /**
358 * @brief Reboot memory content. Reload the calibration parameters.[set]
359 *
360 * @param ctx Read / write interface definitions.(ptr)
361 * @param val Change the values of boot in reg CTRL_REG1
362 * @retval Interface status (MANDATORY: return 0 -> no Error).
363 *
364 */
ism330is_boot_set(stmdev_ctx_t * ctx,uint8_t val)365 int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val)
366 {
367 ism330is_ctrl3_c_t ctrl3_c;
368 int32_t ret;
369
370 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
371
372 if (ret == 0)
373 {
374 ctrl3_c.boot = val;
375 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
376 }
377
378 return ret;
379 }
380
381 /**
382 * @brief Reboot memory content. Reload the calibration parameters.[get]
383 *
384 * @param ctx Read / write interface definitions.(ptr)
385 * @param val Get the values of boot in reg CTRL_REG1.(ptr)
386 * @retval Interface status (MANDATORY: return 0 -> no Error).
387 *
388 */
ism330is_boot_get(stmdev_ctx_t * ctx,uint8_t * val)389 int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
390 {
391 ism330is_ctrl3_c_t ctrl3_c;
392 int32_t ret;
393
394 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
395 *val = ctrl3_c.boot;
396
397 return ret;
398 }
399
400 /**
401 * @brief Enable disable high-performance mode[set]
402 *
403 * @param ctx read / write interface definitions
404 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
405 * @retval interface status (MANDATORY: return 0 -> no Error)
406 *
407 */
ism330is_xl_hm_mode_set(stmdev_ctx_t * ctx,ism330is_hm_mode_t val)408 int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val)
409 {
410 ism330is_ctrl6_c_t ctrl6_c;
411 int32_t ret;
412
413 ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
414
415 if (ret == 0)
416 {
417 ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x1U);
418 ret = ism330is_write_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
419 }
420
421 return ret;
422 }
423
424 /**
425 * @brief Enable disable high-performance mode[get]
426 *
427 * @param ctx read / write interface definitions
428 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
429 * @retval interface status (MANDATORY: return 0 -> no Error)
430 *
431 */
ism330is_xl_hm_mode_get(stmdev_ctx_t * ctx,ism330is_hm_mode_t * val)432 int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val)
433 {
434 ism330is_ctrl6_c_t ctrl6_c;
435 int32_t ret;
436
437 ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
438
439 switch ((ctrl6_c.xl_hm_mode))
440 {
441 case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED:
442 *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED;
443 break;
444
445 case ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED:
446 *val = ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED;
447 break;
448
449 default:
450 *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED;
451 break;
452 }
453 return ret;
454 }
455
456 /**
457 * @brief Accelerometer full-scale selection.[set]
458 *
459 * @param ctx read / write interface definitions
460 * @param val 2g, 4g, 8g, 16g,
461 * @retval interface status (MANDATORY: return 0 -> no Error)
462 *
463 */
ism330is_xl_full_scale_set(stmdev_ctx_t * ctx,ism330is_xl_full_scale_t val)464 int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx,
465 ism330is_xl_full_scale_t val)
466 {
467 ism330is_ctrl1_xl_t ctrl1_xl;
468 int32_t ret;
469
470 ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
471
472 if (ret == 0)
473 {
474 ctrl1_xl.fs_xl = ((uint8_t)val & 0x3U);
475 ret = ism330is_write_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
476 }
477
478 return ret;
479 }
480
481 /**
482 * @brief Accelerometer full-scale selection.[get]
483 *
484 * @param ctx read / write interface definitions
485 * @param val 2g, 4g, 8g, 16g,
486 * @retval interface status (MANDATORY: return 0 -> no Error)
487 *
488 */
ism330is_xl_full_scale_get(stmdev_ctx_t * ctx,ism330is_xl_full_scale_t * val)489 int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx,
490 ism330is_xl_full_scale_t *val)
491 {
492 ism330is_ctrl1_xl_t ctrl1_xl;
493 int32_t ret;
494
495 ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
496
497 switch ((ctrl1_xl.fs_xl))
498 {
499 case ISM330IS_2g:
500 *val = ISM330IS_2g;
501 break;
502
503 case ISM330IS_4g:
504 *val = ISM330IS_4g;
505 break;
506
507 case ISM330IS_8g:
508 *val = ISM330IS_8g;
509 break;
510
511 case ISM330IS_16g:
512 *val = ISM330IS_16g;
513 break;
514
515 default:
516 *val = ISM330IS_2g;
517 break;
518 }
519 return ret;
520 }
521
522 /**
523 * @brief Accelerometer output data rate (ODR) selection.[set]
524 *
525 * @param ctx read / write interface definitions
526 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
527 * @retval interface status (MANDATORY: return 0 -> no Error)
528 *
529 */
ism330is_xl_data_rate_set(stmdev_ctx_t * ctx,ism330is_xl_data_rate_t val)530 int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx,
531 ism330is_xl_data_rate_t val)
532 {
533 ism330is_ctrl1_xl_t ctrl1_xl;
534 int32_t ret;
535
536 ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
537
538 if (ret == 0)
539 {
540 if (((uint8_t)val & 0x10U) == 0x10U)
541 {
542 ret += ism330is_xl_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED);
543 }
544 else
545 {
546 ret += ism330is_xl_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED);
547 }
548
549 ctrl1_xl.odr_xl = ((uint8_t)val & 0xfU);
550 ret += ism330is_write_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
551 }
552
553 return ret;
554 }
555
556 /**
557 * @brief Accelerometer output data rate (ODR) selection.[get]
558 *
559 * @param ctx read / write interface definitions
560 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
561 * @retval interface status (MANDATORY: return 0 -> no Error)
562 *
563 */
ism330is_xl_data_rate_get(stmdev_ctx_t * ctx,ism330is_xl_data_rate_t * val)564 int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx,
565 ism330is_xl_data_rate_t *val)
566 {
567 ism330is_ctrl1_xl_t ctrl1_xl;
568 ism330is_ctrl6_c_t ctrl6_c;
569 int32_t ret;
570
571 ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
572 ret += ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
573
574 switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl))
575 {
576 case ISM330IS_XL_ODR_OFF:
577 *val = ISM330IS_XL_ODR_OFF;
578 break;
579
580 case ISM330IS_XL_ODR_AT_12Hz5_HP:
581 *val = ISM330IS_XL_ODR_AT_12Hz5_HP;
582 break;
583
584 case ISM330IS_XL_ODR_AT_26H_HP:
585 *val = ISM330IS_XL_ODR_AT_26H_HP;
586 break;
587
588 case ISM330IS_XL_ODR_AT_52Hz_HP:
589 *val = ISM330IS_XL_ODR_AT_52Hz_HP;
590 break;
591
592 case ISM330IS_XL_ODR_AT_104Hz_HP:
593 *val = ISM330IS_XL_ODR_AT_104Hz_HP;
594 break;
595
596 case ISM330IS_XL_ODR_AT_208Hz_HP:
597 *val = ISM330IS_XL_ODR_AT_208Hz_HP;
598 break;
599
600 case ISM330IS_XL_ODR_AT_416Hz_HP:
601 *val = ISM330IS_XL_ODR_AT_416Hz_HP;
602 break;
603
604 case ISM330IS_XL_ODR_AT_833Hz_HP:
605 *val = ISM330IS_XL_ODR_AT_833Hz_HP;
606 break;
607
608 case ISM330IS_XL_ODR_AT_1667Hz_HP:
609 *val = ISM330IS_XL_ODR_AT_1667Hz_HP;
610 break;
611
612 case ISM330IS_XL_ODR_AT_3333Hz_HP:
613 *val = ISM330IS_XL_ODR_AT_3333Hz_HP;
614 break;
615
616 case ISM330IS_XL_ODR_AT_6667Hz_HP:
617 *val = ISM330IS_XL_ODR_AT_6667Hz_HP;
618 break;
619
620 case ISM330IS_XL_ODR_AT_12Hz5_LP:
621 *val = ISM330IS_XL_ODR_AT_12Hz5_LP;
622 break;
623
624 case ISM330IS_XL_ODR_AT_26H_LP:
625 *val = ISM330IS_XL_ODR_AT_26H_LP;
626 break;
627
628 case ISM330IS_XL_ODR_AT_52Hz_LP:
629 *val = ISM330IS_XL_ODR_AT_52Hz_LP;
630 break;
631
632 case ISM330IS_XL_ODR_AT_104Hz_LP:
633 *val = ISM330IS_XL_ODR_AT_104Hz_LP;
634 break;
635
636 case ISM330IS_XL_ODR_AT_208Hz_LP:
637 *val = ISM330IS_XL_ODR_AT_208Hz_LP;
638 break;
639
640 case ISM330IS_XL_ODR_AT_416Hz_LP:
641 *val = ISM330IS_XL_ODR_AT_416Hz_LP;
642 break;
643
644 case ISM330IS_XL_ODR_AT_833Hz_LP:
645 *val = ISM330IS_XL_ODR_AT_833Hz_LP;
646 break;
647
648 case ISM330IS_XL_ODR_AT_1667Hz_LP:
649 *val = ISM330IS_XL_ODR_AT_1667Hz_LP;
650 break;
651
652 case ISM330IS_XL_ODR_AT_3333Hz_LP:
653 *val = ISM330IS_XL_ODR_AT_3333Hz_LP;
654 break;
655
656 case ISM330IS_XL_ODR_AT_6667Hz_LP:
657 *val = ISM330IS_XL_ODR_AT_6667Hz_LP;
658 break;
659
660 case ISM330IS_XL_ODR_AT_1Hz6_LP:
661 *val = ISM330IS_XL_ODR_AT_1Hz6_LP;
662 break;
663
664 default:
665 *val = ISM330IS_XL_ODR_OFF;
666 break;
667 }
668
669 return ret;
670 }
671
672 /**
673 * @brief Enable disable high-performance mode[set]
674 *
675 * @param ctx read / write interface definitions
676 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
677 * @retval interface status (MANDATORY: return 0 -> no Error)
678 *
679 */
ism330is_gy_hm_mode_set(stmdev_ctx_t * ctx,ism330is_hm_mode_t val)680 int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val)
681 {
682 ism330is_ctrl7_g_t ctrl7_g;
683 int32_t ret;
684
685 ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
686
687 if (ret == 0)
688 {
689 ctrl7_g.g_hm_mode = ((uint8_t)val & 0x1U);
690 ret = ism330is_write_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
691 }
692
693 return ret;
694 }
695
696 /**
697 * @brief Enable disable high-performance mode[get]
698 *
699 * @param ctx read / write interface definitions
700 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
701 * @retval interface status (MANDATORY: return 0 -> no Error)
702 *
703 */
ism330is_gy_hm_mode_get(stmdev_ctx_t * ctx,ism330is_hm_mode_t * val)704 int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val)
705 {
706 ism330is_ctrl7_g_t ctrl7_g;
707 int32_t ret;
708
709 ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
710
711 switch ((ctrl7_g.g_hm_mode))
712 {
713 case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED:
714 *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED;
715 break;
716
717 case ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED:
718 *val = ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED;
719 break;
720
721 default:
722 *val = ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED;
723 break;
724 }
725 return ret;
726 }
727
728 /**
729 * @brief Gyroscope full-scale selection[set]
730 *
731 * @param ctx read / write interface definitions
732 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
733 * @retval interface status (MANDATORY: return 0 -> no Error)
734 *
735 */
ism330is_gy_full_scale_set(stmdev_ctx_t * ctx,ism330is_gy_full_scale_t val)736 int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx,
737 ism330is_gy_full_scale_t val)
738 {
739 ism330is_ctrl2_g_t ctrl2_g;
740 int32_t ret;
741
742 ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
743
744 if (ret == 0)
745 {
746 ctrl2_g.fs_g = ((uint8_t)val & 0x3U);
747 ctrl2_g.fs_125 = ((uint8_t)val >> 4);
748 ret = ism330is_write_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
749 }
750
751 return ret;
752 }
753
754 /**
755 * @brief Gyroscope full-scale selection[get]
756 *
757 * @param ctx read / write interface definitions
758 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
759 * @retval interface status (MANDATORY: return 0 -> no Error)
760 *
761 */
ism330is_gy_full_scale_get(stmdev_ctx_t * ctx,ism330is_gy_full_scale_t * val)762 int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx,
763 ism330is_gy_full_scale_t *val)
764 {
765 ism330is_ctrl2_g_t ctrl2_g;
766 int32_t ret;
767
768 ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
769
770 switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g))
771 {
772 case ISM330IS_125dps:
773 *val = ISM330IS_125dps;
774 break;
775
776 case ISM330IS_250dps:
777 *val = ISM330IS_250dps;
778 break;
779
780 case ISM330IS_500dps:
781 *val = ISM330IS_500dps;
782 break;
783
784 case ISM330IS_1000dps:
785 *val = ISM330IS_1000dps;
786 break;
787
788 case ISM330IS_2000dps:
789 *val = ISM330IS_2000dps;
790 break;
791
792 default:
793 *val = ISM330IS_125dps;
794 break;
795 }
796 return ret;
797 }
798
799 /**
800 * @brief Gyroscope output data rate (ODR) selection.[set]
801 *
802 * @param ctx read / write interface definitions
803 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
804 * @retval interface status (MANDATORY: return 0 -> no Error)
805 *
806 */
ism330is_gy_data_rate_set(stmdev_ctx_t * ctx,ism330is_gy_data_rate_t val)807 int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx,
808 ism330is_gy_data_rate_t val)
809 {
810 ism330is_ctrl2_g_t ctrl2_g;
811 int32_t ret;
812
813 ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
814
815 if (ret == 0)
816 {
817 if (((uint8_t)val & 0x10U) == 0x10U)
818 {
819 ret += ism330is_gy_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED);
820 }
821 else
822 {
823 ret += ism330is_gy_hm_mode_set(ctx, ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED);
824 }
825
826 ctrl2_g.odr_g = ((uint8_t)val & 0xfU);
827 ret += ism330is_write_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
828 }
829
830 return ret;
831 }
832
833 /**
834 * @brief Gyroscope output data rate (ODR) selection.[get]
835 *
836 * @param ctx read / write interface definitions
837 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
838 * @retval interface status (MANDATORY: return 0 -> no Error)
839 *
840 */
ism330is_gy_data_rate_get(stmdev_ctx_t * ctx,ism330is_gy_data_rate_t * val)841 int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx,
842 ism330is_gy_data_rate_t *val)
843 {
844 ism330is_ctrl2_g_t ctrl2_g;
845 ism330is_ctrl7_g_t ctrl7_g;
846 int32_t ret;
847
848 ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
849 ret += ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
850
851 switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g))
852 {
853 case ISM330IS_GY_ODR_OFF:
854 *val = ISM330IS_GY_ODR_OFF;
855 break;
856
857 case ISM330IS_GY_ODR_AT_12Hz5_HP:
858 *val = ISM330IS_GY_ODR_AT_12Hz5_HP;
859 break;
860
861 case ISM330IS_GY_ODR_AT_26H_HP:
862 *val = ISM330IS_GY_ODR_AT_26H_HP;
863 break;
864
865 case ISM330IS_GY_ODR_AT_52Hz_HP:
866 *val = ISM330IS_GY_ODR_AT_52Hz_HP;
867 break;
868
869 case ISM330IS_GY_ODR_AT_104Hz_HP:
870 *val = ISM330IS_GY_ODR_AT_104Hz_HP;
871 break;
872
873 case ISM330IS_GY_ODR_AT_208Hz_HP:
874 *val = ISM330IS_GY_ODR_AT_208Hz_HP;
875 break;
876
877 case ISM330IS_GY_ODR_AT_416Hz_HP:
878 *val = ISM330IS_GY_ODR_AT_416Hz_HP;
879 break;
880
881 case ISM330IS_GY_ODR_AT_833Hz_HP:
882 *val = ISM330IS_GY_ODR_AT_833Hz_HP;
883 break;
884
885 case ISM330IS_GY_ODR_AT_1667Hz_HP:
886 *val = ISM330IS_GY_ODR_AT_1667Hz_HP;
887 break;
888
889 case ISM330IS_GY_ODR_AT_3333Hz_HP:
890 *val = ISM330IS_GY_ODR_AT_3333Hz_HP;
891 break;
892
893 case ISM330IS_GY_ODR_AT_6667Hz_HP:
894 *val = ISM330IS_GY_ODR_AT_6667Hz_HP;
895 break;
896
897 case ISM330IS_GY_ODR_AT_12Hz5_LP:
898 *val = ISM330IS_GY_ODR_AT_12Hz5_LP;
899 break;
900
901 case ISM330IS_GY_ODR_AT_26H_LP:
902 *val = ISM330IS_GY_ODR_AT_26H_LP;
903 break;
904
905 case ISM330IS_GY_ODR_AT_52Hz_LP:
906 *val = ISM330IS_GY_ODR_AT_52Hz_LP;
907 break;
908
909 case ISM330IS_GY_ODR_AT_104Hz_LP:
910 *val = ISM330IS_GY_ODR_AT_104Hz_LP;
911 break;
912
913 case ISM330IS_GY_ODR_AT_208Hz_LP:
914 *val = ISM330IS_GY_ODR_AT_208Hz_LP;
915 break;
916
917 case ISM330IS_GY_ODR_AT_416Hz_LP:
918 *val = ISM330IS_GY_ODR_AT_416Hz_LP;
919 break;
920
921 case ISM330IS_GY_ODR_AT_833Hz_LP:
922 *val = ISM330IS_GY_ODR_AT_833Hz_LP;
923 break;
924
925 case ISM330IS_GY_ODR_AT_1667Hz_LP:
926 *val = ISM330IS_GY_ODR_AT_1667Hz_LP;
927 break;
928
929 case ISM330IS_GY_ODR_AT_3333Hz_LP:
930 *val = ISM330IS_GY_ODR_AT_3333Hz_LP;
931 break;
932
933 case ISM330IS_GY_ODR_AT_6667Hz_LP:
934 *val = ISM330IS_GY_ODR_AT_6667Hz_LP;
935 break;
936
937 default:
938 *val = ISM330IS_GY_ODR_OFF;
939 break;
940 }
941
942 return ret;
943 }
944
945 /**
946 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
947 *
948 * @param ctx read / write interface definitions
949 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
950 * @retval interface status (MANDATORY: return 0 -> no Error)
951 *
952 */
ism330is_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)953 int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
954 {
955 ism330is_ctrl3_c_t ctrl3_c;
956 int32_t ret;
957
958 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
959
960 if (ret == 0)
961 {
962 ctrl3_c.if_inc = val;
963 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
964 }
965
966 return ret;
967 }
968
969 /**
970 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
971 *
972 * @param ctx read / write interface definitions
973 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
974 * @retval interface status (MANDATORY: return 0 -> no Error)
975 *
976 */
ism330is_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)977 int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
978 {
979 ism330is_ctrl3_c_t ctrl3_c;
980 int32_t ret;
981
982 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
983
984 *val = ctrl3_c.if_inc;
985
986 return ret;
987 }
988
989 /**
990 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
991 *
992 * @param ctx read / write interface definitions
993 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
994 * @retval interface status (MANDATORY: return 0 -> no Error)
995 *
996 */
ism330is_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)997 int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
998 {
999 ism330is_ctrl3_c_t ctrl3_c;
1000 int32_t ret;
1001
1002 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1003
1004 if (ret == 0)
1005 {
1006 ctrl3_c.bdu = val;
1007 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1008 }
1009
1010 return ret;
1011 }
1012
1013 /**
1014 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1015 *
1016 * @param ctx read / write interface definitions
1017 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1018 * @retval interface status (MANDATORY: return 0 -> no Error)
1019 *
1020 */
ism330is_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)1021 int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
1022 {
1023 ism330is_ctrl3_c_t ctrl3_c;
1024 int32_t ret;
1025
1026 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1027
1028 *val = ctrl3_c.bdu;
1029
1030 return ret;
1031 }
1032
1033 /**
1034 * @brief Enables gyroscope sleep mode[set]
1035 *
1036 * @param ctx read / write interface definitions
1037 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1038 * @retval interface status (MANDATORY: return 0 -> no Error)
1039 *
1040 */
ism330is_sleep_set(stmdev_ctx_t * ctx,ism330is_sleep_t val)1041 int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val)
1042 {
1043 ism330is_ctrl4_c_t ctrl4_c;
1044 int32_t ret;
1045
1046 ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1047
1048 if (ret == 0)
1049 {
1050 ctrl4_c.sleep_g = ((uint8_t)val & 0x1U);
1051 ret = ism330is_write_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1052 }
1053
1054 return ret;
1055 }
1056
1057 /**
1058 * @brief Enables gyroscope sleep mode[get]
1059 *
1060 * @param ctx read / write interface definitions
1061 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1062 * @retval interface status (MANDATORY: return 0 -> no Error)
1063 *
1064 */
ism330is_sleep_get(stmdev_ctx_t * ctx,ism330is_sleep_t * val)1065 int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val)
1066 {
1067 ism330is_ctrl4_c_t ctrl4_c;
1068 int32_t ret;
1069
1070 ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1071
1072 switch ((ctrl4_c.sleep_g))
1073 {
1074 case ISM330IS_SLEEP_G_ENABLE:
1075 *val = ISM330IS_SLEEP_G_ENABLE;
1076 break;
1077
1078 case ISM330IS_SLEEP_G_DISABLE:
1079 *val = ISM330IS_SLEEP_G_DISABLE;
1080 break;
1081
1082 default:
1083 *val = ISM330IS_SLEEP_G_ENABLE;
1084 break;
1085 }
1086 return ret;
1087 }
1088
1089 /**
1090 * @brief Accelerometer self-test selection.[set]
1091 *
1092 * @param ctx read / write interface definitions
1093 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1094 * @retval interface status (MANDATORY: return 0 -> no Error)
1095 *
1096 */
ism330is_xl_self_test_set(stmdev_ctx_t * ctx,ism330is_xl_self_test_t val)1097 int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx,
1098 ism330is_xl_self_test_t val)
1099 {
1100 ism330is_ctrl5_c_t ctrl5_c;
1101 int32_t ret;
1102
1103 ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1104
1105 if (ret == 0)
1106 {
1107 ctrl5_c.st_xl = ((uint8_t)val & 0x3U);
1108 ret = ism330is_write_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1109 }
1110
1111 return ret;
1112 }
1113
1114 /**
1115 * @brief Accelerometer self-test selection.[get]
1116 *
1117 * @param ctx read / write interface definitions
1118 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1119 * @retval interface status (MANDATORY: return 0 -> no Error)
1120 *
1121 */
ism330is_xl_self_test_get(stmdev_ctx_t * ctx,ism330is_xl_self_test_t * val)1122 int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx,
1123 ism330is_xl_self_test_t *val)
1124 {
1125 ism330is_ctrl5_c_t ctrl5_c;
1126 int32_t ret;
1127
1128 ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1129
1130 switch ((ctrl5_c.st_xl))
1131 {
1132 case ISM330IS_XL_ST_DISABLE:
1133 *val = ISM330IS_XL_ST_DISABLE;
1134 break;
1135
1136 case ISM330IS_XL_ST_POSITIVE:
1137 *val = ISM330IS_XL_ST_POSITIVE;
1138 break;
1139
1140 case ISM330IS_XL_ST_NEGATIVE:
1141 *val = ISM330IS_XL_ST_NEGATIVE;
1142 break;
1143
1144 default:
1145 *val = ISM330IS_XL_ST_DISABLE;
1146 break;
1147 }
1148 return ret;
1149 }
1150
1151 /**
1152 * @brief Gyroscope self-test selection.[set]
1153 *
1154 * @param ctx read / write interface definitions
1155 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1156 * @retval interface status (MANDATORY: return 0 -> no Error)
1157 *
1158 */
ism330is_gy_self_test_set(stmdev_ctx_t * ctx,ism330is_gy_self_test_t val)1159 int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx,
1160 ism330is_gy_self_test_t val)
1161 {
1162 ism330is_ctrl5_c_t ctrl5_c;
1163 int32_t ret;
1164
1165 ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1166
1167 if (ret == 0)
1168 {
1169 ctrl5_c.st_g = ((uint8_t)val & 0x3U);
1170 ret = ism330is_write_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1171 }
1172
1173 return ret;
1174 }
1175
1176 /**
1177 * @brief Gyroscope self-test selection.[get]
1178 *
1179 * @param ctx read / write interface definitions
1180 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1181 * @retval interface status (MANDATORY: return 0 -> no Error)
1182 *
1183 */
ism330is_gy_self_test_get(stmdev_ctx_t * ctx,ism330is_gy_self_test_t * val)1184 int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx,
1185 ism330is_gy_self_test_t *val)
1186 {
1187 ism330is_ctrl5_c_t ctrl5_c;
1188 int32_t ret;
1189
1190 ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1191
1192 switch ((ctrl5_c.st_g))
1193 {
1194 case ISM330IS_GY_ST_DISABLE:
1195 *val = ISM330IS_GY_ST_DISABLE;
1196 break;
1197
1198 case ISM330IS_GY_ST_POSITIVE:
1199 *val = ISM330IS_GY_ST_POSITIVE;
1200 break;
1201
1202 case ISM330IS_GY_ST_NEGATIVE:
1203 *val = ISM330IS_GY_ST_NEGATIVE;
1204 break;
1205
1206 default:
1207 *val = ISM330IS_GY_ST_DISABLE;
1208 break;
1209 }
1210 return ret;
1211 }
1212
1213 /**
1214 * @defgroup Serial Interfaces
1215 * @brief Serial Interfaces
1216 * @{/
1217 *
1218 */
1219 /**
1220 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
1221 *
1222 * @param ctx read / write interface definitions
1223 * @param val Enables pull-up on SDO pin of UI (User Interface).
1224 * @retval interface status (MANDATORY: return 0 -> no Error)
1225 *
1226 */
ism330is_ui_sdo_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)1227 int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
1228 {
1229 ism330is_pin_ctrl_t pin_ctrl;
1230 int32_t ret;
1231
1232 ret = ism330is_read_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1233
1234 if (ret == 0)
1235 {
1236 pin_ctrl.sdo_pu_en = val;
1237 ret = ism330is_write_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1238 }
1239
1240 return ret;
1241 }
1242
1243 /**
1244 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
1245 *
1246 * @param ctx read / write interface definitions
1247 * @param val Enables pull-up on SDO pin of UI (User Interface).
1248 * @retval interface status (MANDATORY: return 0 -> no Error)
1249 *
1250 */
ism330is_ui_sdo_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)1251 int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
1252 {
1253 ism330is_pin_ctrl_t pin_ctrl;
1254 int32_t ret;
1255
1256 ret = ism330is_read_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1257
1258 *val = pin_ctrl.sdo_pu_en;
1259
1260 return ret;
1261 }
1262
1263 /**
1264 * @brief SPI Serial Interface Mode selection.[set]
1265 *
1266 * @param ctx read / write interface definitions
1267 * @param val SPI_4_WIRE, SPI_3_WIRE,
1268 * @retval interface status (MANDATORY: return 0 -> no Error)
1269 *
1270 */
ism330is_spi_mode_set(stmdev_ctx_t * ctx,ism330is_spi_mode_t val)1271 int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val)
1272 {
1273 ism330is_ctrl3_c_t ctrl3_c;
1274 int32_t ret;
1275
1276 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1277
1278 if (ret == 0)
1279 {
1280 ctrl3_c.sim = ((uint8_t)val & 0x1U);
1281 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1282 }
1283
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief SPI Serial Interface Mode selection.[get]
1289 *
1290 * @param ctx read / write interface definitions
1291 * @param val SPI_4_WIRE, SPI_3_WIRE,
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
ism330is_spi_mode_get(stmdev_ctx_t * ctx,ism330is_spi_mode_t * val)1295 int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val)
1296 {
1297 ism330is_ctrl3_c_t ctrl3_c;
1298 int32_t ret;
1299
1300 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1301
1302 switch ((ctrl3_c.sim))
1303 {
1304 case ISM330IS_SPI_4_WIRE:
1305 *val = ISM330IS_SPI_4_WIRE;
1306 break;
1307
1308 case ISM330IS_SPI_3_WIRE:
1309 *val = ISM330IS_SPI_3_WIRE;
1310 break;
1311
1312 default:
1313 *val = ISM330IS_SPI_4_WIRE;
1314 break;
1315 }
1316 return ret;
1317 }
1318
1319 /**
1320 * @brief Disables I2C on UI (User Interface).[set]
1321 *
1322 * @param ctx read / write interface definitions
1323 * @param val I2C_ENABLE, I2C_DISABLE,
1324 * @retval interface status (MANDATORY: return 0 -> no Error)
1325 *
1326 */
ism330is_ui_i2c_mode_set(stmdev_ctx_t * ctx,ism330is_ui_i2c_mode_t val)1327 int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val)
1328 {
1329 ism330is_ctrl4_c_t ctrl4_c;
1330 int32_t ret;
1331
1332 ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1333
1334 if (ret == 0)
1335 {
1336 ctrl4_c.i2c_disable = ((uint8_t)val & 0x1U);
1337 ret = ism330is_write_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1338 }
1339
1340 return ret;
1341 }
1342
1343 /**
1344 * @brief Disables I2C on UI (User Interface).[get]
1345 *
1346 * @param ctx read / write interface definitions
1347 * @param val I2C_ENABLE, I2C_DISABLE,
1348 * @retval interface status (MANDATORY: return 0 -> no Error)
1349 *
1350 */
ism330is_ui_i2c_mode_get(stmdev_ctx_t * ctx,ism330is_ui_i2c_mode_t * val)1351 int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val)
1352 {
1353 ism330is_ctrl4_c_t ctrl4_c;
1354 int32_t ret;
1355
1356 ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1357
1358 switch ((ctrl4_c.i2c_disable))
1359 {
1360 case ISM330IS_I2C_ENABLE:
1361 *val = ISM330IS_I2C_ENABLE;
1362 break;
1363
1364 case ISM330IS_I2C_DISABLE:
1365 *val = ISM330IS_I2C_DISABLE;
1366 break;
1367
1368 default:
1369 *val = ISM330IS_I2C_ENABLE;
1370 break;
1371 }
1372 return ret;
1373 }
1374
1375 /**
1376 * @}
1377 *
1378 */
1379
1380 /**
1381 * @defgroup Timestamp
1382 * @brief Timestamp
1383 * @{/
1384 *
1385 */
1386 /**
1387 * @brief Enables timestamp counter.[set]
1388 *
1389 * @param ctx read / write interface definitions
1390 * @param val Enables timestamp counter.
1391 * @retval interface status (MANDATORY: return 0 -> no Error)
1392 *
1393 */
ism330is_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1394 int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1395 {
1396 ism330is_ctrl10_c_t ctrl10_c;
1397 int32_t ret;
1398
1399 ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1400
1401 if (ret == 0)
1402 {
1403 ctrl10_c.timestamp_en = val;
1404 ret = ism330is_write_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1405 }
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Enables timestamp counter.[get]
1412 *
1413 * @param ctx read / write interface definitions
1414 * @param val Enables timestamp counter.
1415 * @retval interface status (MANDATORY: return 0 -> no Error)
1416 *
1417 */
ism330is_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1418 int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1419 {
1420 ism330is_ctrl10_c_t ctrl10_c;
1421 int32_t ret;
1422
1423 ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1424
1425 *val = ctrl10_c.timestamp_en;
1426
1427 return ret;
1428 }
1429
1430 /**
1431 * @brief Timestamp data output.[get]
1432 *
1433 * @param ctx read / write interface definitions
1434 * @param val Timestamp data output.
1435 * @retval interface status (MANDATORY: return 0 -> no Error)
1436 *
1437 */
ism330is_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1438 int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1439 {
1440 uint8_t buff[4];
1441 int32_t ret;
1442
1443 ret = ism330is_read_reg(ctx, ISM330IS_TIMESTAMP0, &buff[0], 4);
1444
1445 *val = (uint32_t)buff[3];
1446 *val = (*val * 256U) + (uint32_t)buff[2];
1447 *val = (*val * 256U) + (uint32_t)buff[1];
1448 *val = (*val * 256U) + (uint32_t)buff[0];
1449
1450 return ret;
1451 }
1452
1453 /**
1454 * @}
1455 *
1456 */
1457
1458 /**
1459 * @brief Get the status of all the interrupt sources.[get]
1460 *
1461 * @param ctx read / write interface definitions
1462 * @param val Get the status of all the interrupt sources.
1463 * @retval interface status (MANDATORY: return 0 -> no Error)
1464 *
1465 */
ism330is_all_sources_get(stmdev_ctx_t * ctx,ism330is_all_sources_t * val)1466 int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val)
1467 {
1468 ism330is_status_reg_t status_reg;
1469 ism330is_status_master_mainpage_t status_sh;
1470 uint32_t status_ispu;
1471 int32_t ret;
1472
1473 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1);
1474 if (ret != 0) { return ret; }
1475
1476 val->drdy_xl = status_reg.xlda;
1477 val->drdy_gy = status_reg.gda;
1478 val->drdy_temp = status_reg.tda;
1479
1480 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1);
1481 if (ret != 0) { return ret; }
1482
1483 val->sh_endop = status_sh.sens_hub_endop;
1484 val->sh_slave0_nack = status_sh.sens_hub_endop;
1485 val->sh_slave1_nack = status_sh.sens_hub_endop;
1486 val->sh_slave2_nack = status_sh.sens_hub_endop;
1487 val->sh_slave3_nack = status_sh.sens_hub_endop;
1488 val->sh_wr_once = status_sh.sens_hub_endop;
1489
1490 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4);
1491 if (ret != 0) { return ret; }
1492
1493 val->ispu = status_ispu;
1494
1495 return ret;
1496 }
1497
1498 /**
1499 * @brief The STATUS_REG register is read by the primary interface.[get]
1500 *
1501 * @param ctx Read / write interface definitions.(ptr)
1502 * @param val Get register STATUS_REG
1503 * @retval Interface status (MANDATORY: return 0 -> no Error).
1504 *
1505 */
ism330is_status_reg_get(stmdev_ctx_t * ctx,ism330is_status_reg_t * val)1506 int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx,
1507 ism330is_status_reg_t *val)
1508 {
1509 int32_t ret;
1510 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *) val, 1);
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief Accelerometer new data available.[get]
1517 *
1518 * @param ctx Read / write interface definitions.(ptr)
1519 * @param val Change the values of xlda in reg STATUS_REG
1520 * @retval Interface status (MANDATORY: return 0 -> no Error).
1521 *
1522 */
ism330is_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1523 int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
1524 uint8_t *val)
1525 {
1526 ism330is_status_reg_t status_reg;
1527 int32_t ret;
1528 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG,
1529 (uint8_t *)&status_reg, 1);
1530 *val = status_reg.xlda;
1531
1532 return ret;
1533 }
1534
1535 /**
1536 * @brief Gyroscope new data available.[get]
1537 *
1538 * @param ctx Read / write interface definitions.(ptr)
1539 * @param val Change the values of gda in reg STATUS_REG
1540 * @retval Interface status (MANDATORY: return 0 -> no Error).
1541 *
1542 */
ism330is_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1543 int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
1544 uint8_t *val)
1545 {
1546 ism330is_status_reg_t status_reg;
1547 int32_t ret;
1548 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG,
1549 (uint8_t *)&status_reg, 1);
1550 *val = status_reg.gda;
1551
1552 return ret;
1553 }
1554
1555 /**
1556 * @brief Temperature new data available.[get]
1557 *
1558 * @param ctx Read / write interface definitions.(ptr)
1559 * @param val Change the values of tda in reg STATUS_REG
1560 * @retval Interface status (MANDATORY: return 0 -> no Error).
1561 *
1562 */
ism330is_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1563 int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
1564 uint8_t *val)
1565 {
1566 ism330is_status_reg_t status_reg;
1567 int32_t ret;
1568 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG,
1569 (uint8_t *)&status_reg, 1);
1570 *val = status_reg.tda;
1571
1572 return ret;
1573 }
1574
1575 /**
1576 * @brief Temperature data output register[get]
1577 *
1578 * @param ctx read / write interface definitions
1579 * @param val Temperature data output register
1580 * @retval interface status (MANDATORY: return 0 -> no Error)
1581 *
1582 */
ism330is_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1583 int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1584 {
1585 uint8_t buff[2];
1586 int32_t ret;
1587
1588 ret = ism330is_read_reg(ctx, ISM330IS_OUT_TEMP_L, &buff[0], 2);
1589 *val = (int16_t)buff[1];
1590 *val = (*val * 256) + (int16_t)buff[0];
1591
1592 return ret;
1593 }
1594
1595 /**
1596 * @brief Angular rate sensor.[get]
1597 *
1598 * @param ctx read / write interface definitions
1599 * @param val Angular rate sensor.
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
ism330is_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1603 int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1604 {
1605 uint8_t buff[6];
1606 int32_t ret;
1607
1608 ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_G, buff, 6);
1609 val[0] = (int16_t)buff[1];
1610 val[0] = (val[0] * 256) + (int16_t)buff[0];
1611 val[1] = (int16_t)buff[3];
1612 val[1] = (val[1] * 256) + (int16_t)buff[2];
1613 val[2] = (int16_t)buff[5];
1614 val[2] = (val[2] * 256) + (int16_t)buff[4];
1615
1616 return ret;
1617 }
1618
1619 /**
1620 * @brief Linear acceleration sensor.[get]
1621 *
1622 * @param ctx read / write interface definitions
1623 * @param val Linear acceleration sensor.
1624 * @retval interface status (MANDATORY: return 0 -> no Error)
1625 *
1626 */
ism330is_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1627 int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1628 {
1629 uint8_t buff[6];
1630 int32_t ret;
1631
1632 ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_A, buff, 6);
1633 val[0] = (int16_t)buff[1];
1634 val[0] = (val[0] * 256) + (int16_t)buff[0];
1635 val[1] = (int16_t)buff[3];
1636 val[1] = (val[1] * 256) + (int16_t)buff[2];
1637 val[2] = (int16_t)buff[5];
1638 val[2] = (val[2] * 256) + (int16_t)buff[4];
1639
1640 return ret;
1641 }
1642
1643 /**
1644 * @}
1645 *
1646 */
1647
1648 /**
1649 * @defgroup Interrupt PINs
1650 * @brief Interrupt PINs
1651 * @{/
1652 *
1653 */
1654 /**
1655 * @brief It routes interrupt signals on INT 1 pin.[set]
1656 *
1657 * @param ctx read / write interface definitions
1658 * @param val It routes interrupt signals on INT 1 pin.
1659 * @retval interface status (MANDATORY: return 0 -> no Error)
1660 *
1661 */
ism330is_pin_int1_route_set(stmdev_ctx_t * ctx,ism330is_pin_int1_route_t val)1662 int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx,
1663 ism330is_pin_int1_route_t val)
1664 {
1665 ism330is_int1_ctrl_t int1_ctrl;
1666 ism330is_md1_cfg_t md1_cfg;
1667 int32_t ret;
1668
1669 ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1670 ret += ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1671 if (ret != 0) { return ret; }
1672
1673 int1_ctrl.int1_drdy_xl = val.drdy_xl;
1674 int1_ctrl.int1_drdy_g = val.drdy_gy;
1675 int1_ctrl.int1_boot = val.boot;
1676 ret += ism330is_write_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl,
1677 1);
1678
1679 md1_cfg.int1_shub = val.sh_endop;
1680 md1_cfg.int1_ispu = val.ispu;
1681 ret += ism330is_write_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1682
1683 return ret;
1684 }
1685
1686 /**
1687 * @brief It routes interrupt signals on INT 1 pin.[get]
1688 *
1689 * @param ctx read / write interface definitions
1690 * @param val It routes interrupt signals on INT 1 pin.
1691 * @retval interface status (MANDATORY: return 0 -> no Error)
1692 *
1693 */
ism330is_pin_int1_route_get(stmdev_ctx_t * ctx,ism330is_pin_int1_route_t * val)1694 int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx,
1695 ism330is_pin_int1_route_t *val)
1696 {
1697 ism330is_int1_ctrl_t int1_ctrl;
1698 ism330is_md1_cfg_t md1_cfg;
1699 int32_t ret;
1700
1701 ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1702 ret += ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1703 if (ret != 0) { return ret; }
1704
1705 val->drdy_xl = int1_ctrl.int1_drdy_xl;
1706 val->drdy_gy = int1_ctrl.int1_drdy_g;
1707 val->boot = int1_ctrl.int1_boot;
1708 val->sh_endop = md1_cfg.int1_shub;
1709 val->ispu = md1_cfg.int1_ispu;
1710
1711 return ret;
1712 }
1713
1714 /**
1715 * @brief It routes interrupt signals on INT 2 pin.[set]
1716 *
1717 * @param ctx read / write interface definitions
1718 * @param val It routes interrupt signals on INT 2 pin.
1719 * @retval interface status (MANDATORY: return 0 -> no Error)
1720 *
1721 */
ism330is_pin_int2_route_set(stmdev_ctx_t * ctx,ism330is_pin_int2_route_t val)1722 int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx,
1723 ism330is_pin_int2_route_t val)
1724 {
1725 ism330is_int2_ctrl_t int2_ctrl;
1726 ism330is_md2_cfg_t md2_cfg;
1727 int32_t ret;
1728
1729 ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1730 ret += ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1731 if (ret != 0) { return ret; }
1732
1733 int2_ctrl.int2_drdy_xl = val.drdy_xl;
1734 int2_ctrl.int2_drdy_g = val.drdy_gy;
1735 int2_ctrl.int2_drdy_temp = val.drdy_temp;
1736 int2_ctrl.int2_sleep_ispu = val.ispu_sleep;
1737 ret += ism330is_write_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1738
1739 md2_cfg.int2_ispu = val.ispu;
1740 md2_cfg.int2_timestamp = val.timestamp;
1741 ret += ism330is_write_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1742
1743 return ret;
1744 }
1745
1746 /**
1747 * @brief It routes interrupt signals on INT 2 pin.[get]
1748 *
1749 * @param ctx read / write interface definitions
1750 * @param val It routes interrupt signals on INT 2 pin.
1751 * @retval interface status (MANDATORY: return 0 -> no Error)
1752 *
1753 */
ism330is_pin_int2_route_get(stmdev_ctx_t * ctx,ism330is_pin_int2_route_t * val)1754 int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx,
1755 ism330is_pin_int2_route_t *val)
1756 {
1757 ism330is_int2_ctrl_t int2_ctrl;
1758 ism330is_md2_cfg_t md2_cfg;
1759 int32_t ret;
1760
1761 ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1762 ret += ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1763 if (ret != 0) { return ret; }
1764
1765 val->drdy_xl = int2_ctrl.int2_drdy_xl;
1766 val->drdy_gy = int2_ctrl.int2_drdy_g;
1767 val->drdy_temp = int2_ctrl.int2_drdy_temp;
1768 val->ispu_sleep = int2_ctrl.int2_sleep_ispu;
1769 val->ispu = md2_cfg.int2_ispu;
1770 val->timestamp = md2_cfg.int2_timestamp;
1771
1772 return ret;
1773 }
1774
1775 /**
1776 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
1777 *
1778 * @param ctx read / write interface definitions
1779 * @param val PUSH_PULL, OPEN_DRAIN,
1780 * @retval interface status (MANDATORY: return 0 -> no Error)
1781 *
1782 */
ism330is_int_pin_mode_set(stmdev_ctx_t * ctx,ism330is_int_pin_mode_t val)1783 int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx,
1784 ism330is_int_pin_mode_t val)
1785 {
1786 ism330is_ctrl3_c_t ctrl3_c;
1787 int32_t ret;
1788
1789 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1790
1791 if (ret == 0)
1792 {
1793 ctrl3_c.pp_od = ((uint8_t)val & 0x1U);
1794 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1795 }
1796
1797 return ret;
1798 }
1799
1800 /**
1801 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
1802 *
1803 * @param ctx read / write interface definitions
1804 * @param val PUSH_PULL, OPEN_DRAIN,
1805 * @retval interface status (MANDATORY: return 0 -> no Error)
1806 *
1807 */
ism330is_int_pin_mode_get(stmdev_ctx_t * ctx,ism330is_int_pin_mode_t * val)1808 int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx,
1809 ism330is_int_pin_mode_t *val)
1810 {
1811 ism330is_ctrl3_c_t ctrl3_c;
1812 int32_t ret;
1813
1814 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1815
1816 switch ((ctrl3_c.pp_od))
1817 {
1818 case ISM330IS_PUSH_PULL:
1819 *val = ISM330IS_PUSH_PULL;
1820 break;
1821
1822 case ISM330IS_OPEN_DRAIN:
1823 *val = ISM330IS_OPEN_DRAIN;
1824 break;
1825
1826 default:
1827 *val = ISM330IS_PUSH_PULL;
1828 break;
1829 }
1830 return ret;
1831 }
1832
1833 /**
1834 * @brief Interrupt activation level.[set]
1835 *
1836 * @param ctx read / write interface definitions
1837 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1838 * @retval interface status (MANDATORY: return 0 -> no Error)
1839 *
1840 */
ism330is_pin_polarity_set(stmdev_ctx_t * ctx,ism330is_pin_polarity_t val)1841 int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx,
1842 ism330is_pin_polarity_t val)
1843 {
1844 ism330is_ctrl3_c_t ctrl3_c;
1845 int32_t ret;
1846
1847 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1848
1849 if (ret == 0)
1850 {
1851 ctrl3_c.h_lactive = ((uint8_t)val & 0x1U);
1852 ret = ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1853 }
1854
1855 return ret;
1856 }
1857
1858 /**
1859 * @brief Interrupt activation level.[get]
1860 *
1861 * @param ctx read / write interface definitions
1862 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1863 * @retval interface status (MANDATORY: return 0 -> no Error)
1864 *
1865 */
ism330is_pin_polarity_get(stmdev_ctx_t * ctx,ism330is_pin_polarity_t * val)1866 int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx,
1867 ism330is_pin_polarity_t *val)
1868 {
1869 ism330is_ctrl3_c_t ctrl3_c;
1870 int32_t ret;
1871
1872 ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1873
1874 switch ((ctrl3_c.h_lactive))
1875 {
1876 case ISM330IS_ACTIVE_HIGH:
1877 *val = ISM330IS_ACTIVE_HIGH;
1878 break;
1879
1880 case ISM330IS_ACTIVE_LOW:
1881 *val = ISM330IS_ACTIVE_LOW;
1882 break;
1883
1884 default:
1885 *val = ISM330IS_ACTIVE_HIGH;
1886 break;
1887 }
1888 return ret;
1889 }
1890
1891 /**
1892 * @}
1893 *
1894 */
1895
1896 /**
1897 * @defgroup Sensor hub
1898 * @brief This section groups all the functions that manage the
1899 * sensor hub.
1900 * @{
1901 *
1902 */
1903
1904 /**
1905 * @brief Sensor hub output registers.[get]
1906 *
1907 * @param ctx read / write interface definitions
1908 * @param val Sensor hub output registers.
1909 * @retval interface status (MANDATORY: return 0 -> no Error)
1910 *
1911 */
ism330is_sh_read_data_raw_get(stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)1912 int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
1913 uint8_t len)
1914 {
1915 int32_t ret;
1916
1917 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
1918 ret += ism330is_read_reg(ctx, ISM330IS_SENSOR_HUB_1, val, len);
1919 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
1920
1921 return ret;
1922 }
1923
1924 /**
1925 * @brief Number of external sensors to be read by the sensor hub.[set]
1926 *
1927 * @param ctx read / write interface definitions
1928 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
1929 * @retval interface status (MANDATORY: return 0 -> no Error)
1930 *
1931 */
ism330is_sh_slave_connected_set(stmdev_ctx_t * ctx,ism330is_sh_slave_connected_t val)1932 int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx,
1933 ism330is_sh_slave_connected_t val)
1934 {
1935 ism330is_master_config_t master_config;
1936 int32_t ret;
1937
1938 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
1939 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1940 if (ret != 0) { goto exit; }
1941
1942 master_config.aux_sens_on = (uint8_t)val & 0x3U;
1943 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1944
1945 exit:
1946 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
1947
1948 return ret;
1949 }
1950
1951 /**
1952 * @brief Number of external sensors to be read by the sensor hub.[get]
1953 *
1954 * @param ctx read / write interface definitions
1955 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
1956 * @retval interface status (MANDATORY: return 0 -> no Error)
1957 *
1958 */
ism330is_sh_slave_connected_get(stmdev_ctx_t * ctx,ism330is_sh_slave_connected_t * val)1959 int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx,
1960 ism330is_sh_slave_connected_t *val)
1961 {
1962 ism330is_master_config_t master_config;
1963 int32_t ret;
1964
1965 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
1966 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1967 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
1968 if (ret != 0) { return ret; }
1969
1970 switch (master_config.aux_sens_on)
1971 {
1972 case ISM330IS_SLV_0:
1973 *val = ISM330IS_SLV_0;
1974 break;
1975
1976 case ISM330IS_SLV_0_1:
1977 *val = ISM330IS_SLV_0_1;
1978 break;
1979
1980 case ISM330IS_SLV_0_1_2:
1981 *val = ISM330IS_SLV_0_1_2;
1982 break;
1983
1984 case ISM330IS_SLV_0_1_2_3:
1985 *val = ISM330IS_SLV_0_1_2_3;
1986 break;
1987
1988 default:
1989 *val = ISM330IS_SLV_0;
1990 break;
1991 }
1992
1993 return ret;
1994 }
1995
1996 /**
1997 * @brief Sensor hub I2C master enable.[set]
1998 *
1999 * @param ctx read / write interface definitions
2000 * @param val Sensor hub I2C master enable.
2001 * @retval interface status (MANDATORY: return 0 -> no Error)
2002 *
2003 */
ism330is_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)2004 int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
2005 {
2006 ism330is_master_config_t master_config;
2007 int32_t ret;
2008
2009 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2010 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2011 if (ret != 0) { goto exit; }
2012
2013 master_config.master_on = val;
2014 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2015
2016 exit:
2017 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2018
2019 return ret;
2020 }
2021
2022 /**
2023 * @brief Sensor hub I2C master enable.[get]
2024 *
2025 * @param ctx read / write interface definitions
2026 * @param val Sensor hub I2C master enable.
2027 * @retval interface status (MANDATORY: return 0 -> no Error)
2028 *
2029 */
ism330is_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)2030 int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
2031 {
2032 ism330is_master_config_t master_config;
2033 int32_t ret;
2034
2035 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2036 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2037 if (ret != 0) { return ret; }
2038
2039 *val = master_config.master_on;
2040
2041 ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @brief Sensor Hub master I2C pull-up enable.[set]
2048 *
2049 * @param ctx read / write interface definitions
2050 * @param val Sensor Hub master I2C pull-up enable.
2051 * @retval interface status (MANDATORY: return 0 -> no Error)
2052 *
2053 */
ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)2054 int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
2055 {
2056 ism330is_master_config_t master_config;
2057 int32_t ret;
2058
2059 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2060 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2061 if (ret != 0) { goto exit; }
2062
2063 master_config.shub_pu_en = val;
2064 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2065
2066 exit:
2067 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2068
2069 return ret;
2070 }
2071
2072 /**
2073 * @brief Sensor Hub master I2C pull-up enable.[get]
2074 *
2075 * @param ctx read / write interface definitions
2076 * @param val Sensor Hub master I2C pull-up enable.
2077 * @retval interface status (MANDATORY: return 0 -> no Error)
2078 *
2079 */
ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)2080 int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx,
2081 uint8_t *val)
2082 {
2083 ism330is_master_config_t master_config;
2084 int32_t ret;
2085
2086 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2087 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2088 if (ret != 0) { return ret; }
2089
2090 *val = master_config.shub_pu_en;
2091
2092 ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2093
2094 return ret;
2095 }
2096
2097 /**
2098 * @brief I2C interface pass-through.[set]
2099 *
2100 * @param ctx Read / write interface definitions.(ptr)
2101 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2102 * @retval Interface status (MANDATORY: return 0 -> no Error).
2103 *
2104 */
ism330is_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)2105 int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
2106 {
2107 ism330is_master_config_t master_config;
2108 int32_t ret;
2109
2110 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2111 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2112 if (ret != 0) { goto exit; }
2113
2114 master_config.pass_through_mode = (uint8_t)val;
2115 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2116
2117 exit:
2118 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2119
2120 return ret;
2121 }
2122
2123 /**
2124 * @brief I2C interface pass-through.[get]
2125 *
2126 * @param ctx Read / write interface definitions.(ptr)
2127 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2128 * @retval Interface status (MANDATORY: return 0 -> no Error).
2129 *
2130 */
ism330is_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)2131 int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
2132 {
2133 ism330is_master_config_t master_config;
2134 int32_t ret;
2135
2136 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2137 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2138
2139 *val = master_config.pass_through_mode;
2140 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2141
2142 return ret;
2143 }
2144
2145 /**
2146 * @brief Sensor hub trigger signal selection.[set]
2147 *
2148 * @param ctx read / write interface definitions
2149 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2150 * @retval interface status (MANDATORY: return 0 -> no Error)
2151 *
2152 */
ism330is_sh_syncro_mode_set(stmdev_ctx_t * ctx,ism330is_sh_syncro_mode_t val)2153 int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx,
2154 ism330is_sh_syncro_mode_t val)
2155 {
2156 ism330is_master_config_t master_config;
2157 int32_t ret;
2158
2159 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2160 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2161 if (ret != 0) { goto exit; }
2162
2163 master_config.start_config = (uint8_t)val & 0x01U;
2164 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2165
2166 exit:
2167 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2168
2169 return ret;
2170 }
2171
2172 /**
2173 * @brief Sensor hub trigger signal selection.[get]
2174 *
2175 * @param ctx read / write interface definitions
2176 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2177 * @retval interface status (MANDATORY: return 0 -> no Error)
2178 *
2179 */
ism330is_sh_syncro_mode_get(stmdev_ctx_t * ctx,ism330is_sh_syncro_mode_t * val)2180 int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx,
2181 ism330is_sh_syncro_mode_t *val)
2182 {
2183 ism330is_master_config_t master_config;
2184 int32_t ret;
2185
2186 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2187 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2188 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2189 if (ret != 0) { return ret; }
2190
2191 switch (master_config.start_config)
2192 {
2193 case ISM330IS_SH_TRG_XL_GY_DRDY:
2194 *val = ISM330IS_SH_TRG_XL_GY_DRDY;
2195 break;
2196
2197 case ISM330IS_SH_TRIG_INT2:
2198 *val = ISM330IS_SH_TRIG_INT2;
2199 break;
2200
2201 default:
2202 *val = ISM330IS_SH_TRG_XL_GY_DRDY;
2203 break;
2204 }
2205
2206 return ret;
2207 }
2208
2209 /**
2210 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
2211 *
2212 * @param ctx read / write interface definitions
2213 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2214 * @retval interface status (MANDATORY: return 0 -> no Error)
2215 *
2216 */
ism330is_sh_write_mode_set(stmdev_ctx_t * ctx,ism330is_sh_write_mode_t val)2217 int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx,
2218 ism330is_sh_write_mode_t val)
2219 {
2220 ism330is_master_config_t master_config;
2221 int32_t ret;
2222
2223 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2224 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2225 if (ret != 0) { goto exit; }
2226
2227 master_config.write_once = (uint8_t)val & 0x01U;
2228 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2229
2230 exit:
2231 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2232
2233 return ret;
2234 }
2235
2236 /**
2237 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
2238 *
2239 * @param ctx read / write interface definitions
2240 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2241 * @retval interface status (MANDATORY: return 0 -> no Error)
2242 *
2243 */
ism330is_sh_write_mode_get(stmdev_ctx_t * ctx,ism330is_sh_write_mode_t * val)2244 int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx,
2245 ism330is_sh_write_mode_t *val)
2246 {
2247 ism330is_master_config_t master_config;
2248 int32_t ret;
2249
2250 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2251 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2252 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2253 if (ret != 0) { return ret; }
2254
2255 switch (master_config.write_once)
2256 {
2257 case ISM330IS_EACH_SH_CYCLE:
2258 *val = ISM330IS_EACH_SH_CYCLE;
2259 break;
2260
2261 case ISM330IS_ONLY_FIRST_CYCLE:
2262 *val = ISM330IS_ONLY_FIRST_CYCLE;
2263 break;
2264
2265 default:
2266 *val = ISM330IS_EACH_SH_CYCLE;
2267 break;
2268 }
2269
2270 return ret;
2271 }
2272
2273 /**
2274 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
2275 *
2276 * @param ctx read / write interface definitions
2277 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2278 * @retval interface status (MANDATORY: return 0 -> no Error)
2279 *
2280 */
ism330is_sh_reset_set(stmdev_ctx_t * ctx,uint8_t val)2281 int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2282 {
2283 ism330is_master_config_t master_config;
2284 int32_t ret;
2285
2286 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2287 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2288 if (ret != 0) { goto exit; }
2289
2290 master_config.rst_master_regs = val;
2291 ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2292
2293 exit:
2294 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2295
2296 return ret;
2297 }
2298
2299 /**
2300 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
2301 *
2302 * @param ctx read / write interface definitions
2303 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2304 * @retval interface status (MANDATORY: return 0 -> no Error)
2305 *
2306 */
ism330is_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2307 int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2308 {
2309 ism330is_master_config_t master_config;
2310 int32_t ret;
2311
2312 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2313 ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2314 if (ret != 0) { return ret; }
2315
2316 *val = master_config.rst_master_regs;
2317
2318 ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2319
2320 return ret;
2321 }
2322
2323 /**
2324 * @brief Configure slave 0 for perform a write.[set]
2325 *
2326 * @param ctx read / write interface definitions
2327 * @param val a structure that contain
2328 * - uint8_t slv1_add; 8 bit i2c device address
2329 * - uint8_t slv1_subadd; 8 bit register device address
2330 * - uint8_t slv1_data; 8 bit data to write
2331 * @retval interface status (MANDATORY: return 0 -> no Error)
2332 *
2333 */
ism330is_sh_cfg_write(stmdev_ctx_t * ctx,ism330is_sh_cfg_write_t * val)2334 int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx,
2335 ism330is_sh_cfg_write_t *val)
2336 {
2337 ism330is_slv0_add_t reg;
2338 int32_t ret;
2339
2340 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2341 if (ret != 0) { return ret; }
2342
2343 reg.slave0_add = val->slv0_add;
2344 reg.rw_0 = 0;
2345 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD, (uint8_t *)®, 1);
2346 if (ret != 0) { goto exit; }
2347
2348 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD,
2349 &(val->slv0_subadd), 1);
2350 if (ret != 0) { goto exit; }
2351
2352 ret = ism330is_write_reg(ctx, ISM330IS_DATAWRITE_SLV0,
2353 &(val->slv0_data), 1);
2354
2355 exit:
2356 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2357
2358 return ret;
2359 }
2360
2361 /**
2362 * @brief Rate at which the master communicates.[set]
2363 *
2364 * @param ctx read / write interface definitions
2365 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2366 * @retval interface status (MANDATORY: return 0 -> no Error)
2367 *
2368 */
ism330is_sh_data_rate_set(stmdev_ctx_t * ctx,ism330is_sh_data_rate_t val)2369 int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx,
2370 ism330is_sh_data_rate_t val)
2371 {
2372 ism330is_slv0_config_t slv0_config;
2373 int32_t ret;
2374
2375 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2376 ret += ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2377 if (ret != 0) { goto exit; }
2378
2379 slv0_config.shub_odr = (uint8_t)val & 0x07U;
2380 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2381
2382 exit:
2383 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * @brief Rate at which the master communicates.[get]
2390 *
2391 * @param ctx read / write interface definitions
2392 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2393 * @retval interface status (MANDATORY: return 0 -> no Error)
2394 *
2395 */
ism330is_sh_data_rate_get(stmdev_ctx_t * ctx,ism330is_sh_data_rate_t * val)2396 int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx,
2397 ism330is_sh_data_rate_t *val)
2398 {
2399 ism330is_slv0_config_t slv0_config;
2400 int32_t ret;
2401
2402 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2403 ret += ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2404 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2405 if (ret != 0) { return ret; }
2406
2407 switch (slv0_config.shub_odr)
2408 {
2409 case ISM330IS_SH_12_5Hz:
2410 *val = ISM330IS_SH_12_5Hz;
2411 break;
2412
2413 case ISM330IS_SH_26Hz:
2414 *val = ISM330IS_SH_26Hz;
2415 break;
2416
2417 case ISM330IS_SH_52Hz:
2418 *val = ISM330IS_SH_52Hz;
2419 break;
2420
2421 case ISM330IS_SH_104Hz:
2422 *val = ISM330IS_SH_104Hz;
2423 break;
2424
2425 default:
2426 *val = ISM330IS_SH_12_5Hz;
2427 break;
2428 }
2429
2430 return ret;
2431 }
2432
2433 /**
2434 * @brief Configure slave idx for perform a read.[set]
2435 *
2436 * @param ctx read / write interface definitions
2437 * @param val Structure that contain
2438 * - uint8_t slv_add; 8 bit i2c device address
2439 * - uint8_t slv_subadd; 8 bit register device address
2440 * - uint8_t slv_len; num of bit to read
2441 * @retval interface status (MANDATORY: return 0 -> no Error)
2442 *
2443 */
ism330is_sh_slv_cfg_read(stmdev_ctx_t * ctx,uint8_t idx,ism330is_sh_cfg_read_t * val)2444 int32_t ism330is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx,
2445 ism330is_sh_cfg_read_t *val)
2446 {
2447 ism330is_slv0_add_t slv_add;
2448 ism330is_slv0_config_t slv_config;
2449 int32_t ret;
2450
2451 ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK);
2452 if (ret != 0) { return ret; }
2453
2454 slv_add.slave0_add = val->slv_add;
2455 slv_add.rw_0 = 1;
2456 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD + idx*3U,
2457 (uint8_t *)&slv_add, 1);
2458 if (ret != 0) { goto exit; }
2459
2460 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD + idx*3U,
2461 &(val->slv_subadd), 1);
2462 if (ret != 0) { goto exit; }
2463
2464 ret = ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG + idx*3U,
2465 (uint8_t *)&slv_config, 1);
2466 if (ret != 0) { goto exit; }
2467
2468 slv_config.slave0_numop = val->slv_len;
2469 ret = ism330is_write_reg(ctx, ISM330IS_SLV0_CONFIG + idx*3U,
2470 (uint8_t *)&slv_config, 1);
2471
2472 exit:
2473 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2474
2475 return ret;
2476 }
2477
2478 /**
2479 * @brief Sensor hub source register.[get]
2480 *
2481 * @param ctx read / write interface definitions
2482 * @param val union of registers from STATUS_MASTER to
2483 * @retval interface status (MANDATORY: return 0 -> no Error)
2484 *
2485 */
ism330is_sh_status_get(stmdev_ctx_t * ctx,ism330is_status_master_t * val)2486 int32_t ism330is_sh_status_get(stmdev_ctx_t *ctx,
2487 ism330is_status_master_t *val)
2488 {
2489 int32_t ret;
2490
2491 ret = ism330is_read_reg(ctx, ISM330IS_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
2492
2493 return ret;
2494 }
2495
2496 /**
2497 * @}
2498 *
2499 */
2500
2501 /**
2502 * @defgroup ispu
2503 * @brief ispu
2504 * @{/
2505 *
2506 */
2507 /**
2508 * @brief Software reset of ISPU core.[set]
2509 *
2510 * @param ctx read / write interface definitions
2511 * @param val Software reset of ISPU core.
2512 * @retval interface status (MANDATORY: return 0 -> no Error)
2513 *
2514 */
ism330is_ispu_reset_set(stmdev_ctx_t * ctx,uint8_t val)2515 int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2516 {
2517 ism330is_func_cfg_access_t func_cfg_access;
2518 int32_t ret;
2519
2520 ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2521
2522 if (ret == 0)
2523 {
2524 func_cfg_access.sw_reset_ispu = val;
2525 ret = ism330is_write_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2526 }
2527
2528 return ret;
2529 }
2530
2531 /**
2532 * @brief Software reset of ISPU core.[get]
2533 *
2534 * @param ctx read / write interface definitions
2535 * @param val Software reset of ISPU core.
2536 * @retval interface status (MANDATORY: return 0 -> no Error)
2537 *
2538 */
ism330is_ispu_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2539 int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2540 {
2541 ism330is_func_cfg_access_t func_cfg_access;
2542 int32_t ret;
2543
2544 ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2545
2546 *val = func_cfg_access.sw_reset_ispu;
2547
2548
2549 return ret;
2550 }
2551
ism330is_ispu_clock_set(stmdev_ctx_t * ctx,ism330is_ispu_clock_sel_t val)2552 int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx,
2553 ism330is_ispu_clock_sel_t val)
2554 {
2555 ism330is_ctrl10_c_t ctrl10_c;
2556 int32_t ret;
2557
2558 ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2559
2560 if (ret == 0)
2561 {
2562 ctrl10_c.ispu_clk_sel = (uint8_t)val;
2563 ret += ism330is_write_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2564 }
2565
2566 return ret;
2567 }
2568
ism330is_ispu_clock_get(stmdev_ctx_t * ctx,ism330is_ispu_clock_sel_t * val)2569 int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx,
2570 ism330is_ispu_clock_sel_t *val)
2571 {
2572 ism330is_ctrl10_c_t ctrl10_c;
2573 int32_t ret;
2574
2575 ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2576
2577 switch (ctrl10_c.ispu_clk_sel)
2578 {
2579 default:
2580 case 0:
2581 *val = ISM330IS_ISPU_CLK_5MHz;
2582 break;
2583 case 1:
2584 *val = ISM330IS_ISPU_CLK_10MHz;
2585 break;
2586 }
2587
2588 return ret;
2589 }
2590
2591 /**
2592 * @brief ISPU irq rate selection.[set]
2593 *
2594 * @param ctx read / write interface definitions
2595 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2596 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2597 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2598 * @retval interface status (MANDATORY: return 0 -> no Error)
2599 *
2600 */
ism330is_ispu_data_rate_set(stmdev_ctx_t * ctx,ism330is_ispu_data_rate_t val)2601 int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx,
2602 ism330is_ispu_data_rate_t val)
2603 {
2604 ism330is_ctrl9_c_t ctrl9_c;
2605 int32_t ret;
2606
2607 ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2608
2609 if (ret == 0)
2610 {
2611 ctrl9_c.ispu_rate = ((uint8_t)val & 0xfU);
2612 ret = ism330is_write_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2613 }
2614
2615 return ret;
2616 }
2617
2618 /**
2619 * @brief ISPU irq rate selection.[get]
2620 *
2621 * @param ctx read / write interface definitions
2622 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2623 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2624 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2625 * @retval interface status (MANDATORY: return 0 -> no Error)
2626 *
2627 */
ism330is_ispu_data_rate_get(stmdev_ctx_t * ctx,ism330is_ispu_data_rate_t * val)2628 int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx,
2629 ism330is_ispu_data_rate_t *val)
2630 {
2631 ism330is_ctrl9_c_t ctrl9_c;
2632 int32_t ret;
2633
2634 ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2635
2636 switch ((ctrl9_c.ispu_rate))
2637 {
2638 case ISM330IS_ISPU_ODR_OFF:
2639 *val = ISM330IS_ISPU_ODR_OFF;
2640 break;
2641
2642 case ISM330IS_ISPU_ODR_AT_12Hz5:
2643 *val = ISM330IS_ISPU_ODR_AT_12Hz5;
2644 break;
2645
2646 case ISM330IS_ISPU_ODR_AT_26Hz:
2647 *val = ISM330IS_ISPU_ODR_AT_26Hz;
2648 break;
2649
2650 case ISM330IS_ISPU_ODR_AT_52Hz:
2651 *val = ISM330IS_ISPU_ODR_AT_52Hz;
2652 break;
2653
2654 case ISM330IS_ISPU_ODR_AT_104Hz:
2655 *val = ISM330IS_ISPU_ODR_AT_104Hz;
2656 break;
2657
2658 case ISM330IS_ISPU_ODR_AT_208Hz:
2659 *val = ISM330IS_ISPU_ODR_AT_208Hz;
2660 break;
2661
2662 case ISM330IS_ISPU_ODR_AT_416Hz:
2663 *val = ISM330IS_ISPU_ODR_AT_416Hz;
2664 break;
2665
2666 case ISM330IS_ISPU_ODR_AT_833Hz:
2667 *val = ISM330IS_ISPU_ODR_AT_833Hz;
2668 break;
2669
2670 case ISM330IS_ISPU_ODR_AT_1667Hz:
2671 *val = ISM330IS_ISPU_ODR_AT_1667Hz;
2672 break;
2673
2674 case ISM330IS_ISPU_ODR_AT_3333Hz:
2675 *val = ISM330IS_ISPU_ODR_AT_3333Hz;
2676 break;
2677
2678 case ISM330IS_ISPU_ODR_AT_6667Hz:
2679 *val = ISM330IS_ISPU_ODR_AT_6667Hz;
2680 break;
2681
2682 default:
2683 *val = ISM330IS_ISPU_ODR_OFF;
2684 break;
2685 }
2686 return ret;
2687 }
2688
2689 /**
2690 * @brief ISPU bdu selection.[set]
2691 *
2692 * @param ctx read / write interface definitions
2693 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
2694 * @retval interface status (MANDATORY: return 0 -> no Error)
2695 *
2696 */
ism330is_ispu_bdu_set(stmdev_ctx_t * ctx,ism330is_ispu_bdu_t val)2697 int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val)
2698 {
2699 ism330is_ctrl9_c_t ctrl9_c;
2700 int32_t ret;
2701
2702 ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2703
2704 if (ret == 0)
2705 {
2706 ctrl9_c.ispu_bdu = ((uint8_t)val & 0x3U);
2707 ret = ism330is_write_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2708 }
2709
2710 return ret;
2711 }
2712
2713 /**
2714 * @brief ISPU bdu selection.[get]
2715 *
2716 * @param ctx read / write interface definitions
2717 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
2718 * @retval interface status (MANDATORY: return 0 -> no Error)
2719 *
2720 */
ism330is_ispu_bdu_get(stmdev_ctx_t * ctx,ism330is_ispu_bdu_t * val)2721 int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val)
2722 {
2723 ism330is_ctrl9_c_t ctrl9_c;
2724 int32_t ret;
2725
2726 ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2727
2728 switch ((ctrl9_c.ispu_rate))
2729 {
2730 case ISM330IS_ISPU_BDU_OFF:
2731 *val = ISM330IS_ISPU_BDU_OFF;
2732 break;
2733
2734 case ISM330IS_ISPU_BDU_ON_2B_4B:
2735 *val = ISM330IS_ISPU_BDU_ON_2B_4B;
2736 break;
2737
2738 case ISM330IS_ISPU_BDU_ON_2B_2B:
2739 *val = ISM330IS_ISPU_BDU_ON_2B_2B;
2740 break;
2741
2742 case ISM330IS_ISPU_BDU_ON_4B_4B:
2743 *val = ISM330IS_ISPU_BDU_ON_4B_4B;
2744 break;
2745
2746 default:
2747 *val = ISM330IS_ISPU_BDU_OFF;
2748 break;
2749 }
2750 return ret;
2751 }
2752
2753 /**
2754 * @brief Generic Interrupt Flags from ISPU.[get]
2755 *
2756 * @param ctx read / write interface definitions
2757 * @param val Generic Interrupt Flags from ISPU.
2758 * @retval interface status (MANDATORY: return 0 -> no Error)
2759 *
2760 */
ism330is_ia_ispu_get(stmdev_ctx_t * ctx,uint32_t * val)2761 int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val)
2762 {
2763 uint8_t buff[4];
2764 int32_t ret;
2765
2766 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4);
2767
2768 *val = (uint32_t)buff[3];
2769 *val = (*val * 256U) + (uint32_t)buff[2];
2770 *val = (*val * 256U) + (uint32_t)buff[1];
2771 *val = (*val * 256U) + (uint32_t)buff[0];
2772
2773 return ret;
2774 }
2775
2776 /**
2777 * @brief General purpose input configuration register for ISPU[set]
2778 *
2779 * @param ctx read / write interface definitions
2780 * @param offset offset from ISPU_DUMMY_CFG_1 register
2781 * @param val General purpose input configuration register for ISPU
2782 * @param len number of bytes to write
2783 * @retval interface status (MANDATORY: return 0 -> no Error)
2784 *
2785 */
ism330is_ispu_write_dummy_cfg(stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)2786 int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset,
2787 uint8_t *val, uint8_t len)
2788 {
2789 int32_t ret;
2790
2791 /* check if we are writing outside of the range */
2792 if (ISM330IS_ISPU_DUMMY_CFG_1_L + offset + len > ISM330IS_ISPU_DUMMY_CFG_4_H)
2793 {
2794 return -1;
2795 }
2796
2797 ret = ism330is_write_reg(ctx, ISM330IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
2798
2799 return ret;
2800 }
2801
2802 /**
2803 * @brief General purpose input configuration register for ISPU[set]
2804 *
2805 * @param ctx read / write interface definitions
2806 * @param offset offset from ISPU_DUMMY_CFG_1 register
2807 * @param val General purpose input configuration register for ISPU
2808 * @param len number of bytes to write
2809 * @retval interface status (MANDATORY: return 0 -> no Error)
2810 *
2811 */
ism330is_ispu_read_dummy_cfg(stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)2812 int32_t ism330is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset,
2813 uint8_t *val, uint8_t len)
2814 {
2815 int32_t ret;
2816
2817 /* check if we are reading outside of the range */
2818 if (ISM330IS_ISPU_DUMMY_CFG_1_L + offset + len > ISM330IS_ISPU_DUMMY_CFG_4_H)
2819 {
2820 return -1;
2821 }
2822
2823 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
2824
2825 return ret;
2826 }
2827
2828 /**
2829 * @brief Boot ISPU core[set]
2830 *
2831 * @param ctx read / write interface definitions
2832 * @param val Boot ISPU core
2833 * @retval interface status (MANDATORY: return 0 -> no Error)
2834 *
2835 */
ism330is_ispu_boot_set(stmdev_ctx_t * ctx,ism330is_ispu_boot_latched_t val)2836 int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx,
2837 ism330is_ispu_boot_latched_t val)
2838 {
2839 ism330is_ispu_config_t ispu_config;
2840 int32_t ret;
2841
2842 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
2843 if (ret != 0) { return ret; }
2844
2845 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2846 if (ret != 0) { goto exit; }
2847
2848 ispu_config.ispu_rst_n = (uint8_t)val;
2849 ispu_config.clk_dis = (uint8_t)val;
2850 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2851
2852 exit:
2853 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2854
2855 return ret;
2856 }
2857
2858 /**
2859 * @brief Boot ISPU core[get]
2860 *
2861 * @param ctx read / write interface definitions
2862 * @param val Boot ISPU core
2863 * @retval interface status (MANDATORY: return 0 -> no Error)
2864 *
2865 */
ism330is_ispu_boot_get(stmdev_ctx_t * ctx,ism330is_ispu_boot_latched_t * val)2866 int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx,
2867 ism330is_ispu_boot_latched_t *val)
2868 {
2869 ism330is_ispu_config_t ispu_config;
2870 int32_t ret;
2871
2872 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
2873 if (ret != 0) { return ret; }
2874
2875 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2876 if (ret != 0) { goto exit; }
2877
2878 *val = ISM330IS_ISPU_TURN_OFF;
2879 if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U)
2880 {
2881 *val = ISM330IS_ISPU_TURN_ON;
2882 }
2883
2884 exit:
2885 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2886
2887 return ret;
2888 }
2889
2890 /**
2891 * @brief Enables latched ISPU interrupt.[set]
2892 *
2893 * @param ctx read / write interface definitions
2894 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
2895 * @retval interface status (MANDATORY: return 0 -> no Error)
2896 *
2897 */
ism330is_ispu_int_latched_set(stmdev_ctx_t * ctx,ism330is_ispu_int_latched_t val)2898 int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx,
2899 ism330is_ispu_int_latched_t val)
2900 {
2901 ism330is_ispu_config_t ispu_config;
2902 int32_t ret;
2903
2904 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
2905 if (ret != 0) { return ret; }
2906
2907 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2908 if (ret != 0) { goto exit; }
2909
2910 ispu_config.latched = ((uint8_t)val & 0x1U);
2911 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2912
2913 exit:
2914 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2915
2916 return ret;
2917 }
2918
2919 /**
2920 * @brief Enables latched ISPU interrupt.[get]
2921 *
2922 * @param ctx read / write interface definitions
2923 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
2924 * @retval interface status (MANDATORY: return 0 -> no Error)
2925 *
2926 */
ism330is_ispu_int_latched_get(stmdev_ctx_t * ctx,ism330is_ispu_int_latched_t * val)2927 int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx,
2928 ism330is_ispu_int_latched_t *val)
2929 {
2930 ism330is_ispu_config_t ispu_config;
2931 int32_t ret;
2932
2933 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
2934 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2935 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2936 if (ret != 0) { return ret; }
2937
2938 switch ((ispu_config.latched))
2939 {
2940 case ISM330IS_ISPU_INT_PULSED:
2941 *val = ISM330IS_ISPU_INT_PULSED;
2942 break;
2943
2944 case ISM330IS_ISPU_INT_LATCHED:
2945 *val = ISM330IS_ISPU_INT_LATCHED;
2946 break;
2947
2948 default:
2949 *val = ISM330IS_ISPU_INT_PULSED;
2950 break;
2951 }
2952
2953 return ret;
2954 }
2955
2956 /**
2957 * @brief returns ISPU boot status
2958 *
2959 * @param ctx read / write interface definitions
2960 * @param val ISM330IS_ISPU_BOOT_IN_PROGRESS, ISM330IS_ISPU_BOOT_ENDED
2961 * @retval interface status (MANDATORY: return 0 -> no Error)
2962 *
2963 */
ism330is_ispu_get_boot_status(stmdev_ctx_t * ctx,ism330is_ispu_boot_end_t * val)2964 int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx,
2965 ism330is_ispu_boot_end_t *val)
2966 {
2967 ism330is_ispu_status_t ispu_boot_status;
2968 int32_t ret;
2969
2970 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
2971 if (ret != 0) { return ret; }
2972
2973 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1);
2974 *val = (ism330is_ispu_boot_end_t)ispu_boot_status.boot_end;
2975 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
2976
2977 return ret;
2978 }
2979
ism330is_ispu_sel_memory_addr(stmdev_ctx_t * ctx,uint16_t mem_addr)2980 static int32_t ism330is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr)
2981 {
2982 uint8_t mem_addr_l, mem_addr_h;
2983 int32_t ret = 0;
2984
2985 mem_addr_l = (uint8_t)(mem_addr & 0xFFU);
2986 mem_addr_h = (uint8_t)(mem_addr / 256U);
2987 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_ADDR1,
2988 (uint8_t *)&mem_addr_h, 1);
2989 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_ADDR0,
2990 (uint8_t *)&mem_addr_l, 1);
2991
2992 return ret;
2993 }
2994
2995 /**
2996 * @brief ISPU write memory. ISPU clock is disabled inside the routine.
2997 *
2998 * @param ctx read / write interface definitions
2999 * @param mem_sel ISM330IS_ISPU_DATA_RAM_MEMORY, ISM330IS_ISPU_PROGRAM_RAM_MEMORY
3000 * @param mem_addr memory address
3001 * @param mem_data memory data
3002 * @param len data length
3003 * @retval interface status (MANDATORY: return 0 -> no Error)
3004 *
3005 */
ism330is_ispu_write_memory(stmdev_ctx_t * ctx,ism330is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3006 int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx,
3007 ism330is_ispu_memory_type_t mem_sel,
3008 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3009 {
3010 ism330is_ispu_mem_sel_t ispu_mem_sel;
3011 ism330is_ispu_config_t ispu_cfg;
3012 uint8_t clk_dis;
3013 int32_t ret;
3014 uint16_t i;
3015
3016 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3017 if (ret == 0)
3018 {
3019 /* disable ISPU clock */
3020 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3021 clk_dis = ispu_cfg.clk_dis;
3022 ispu_cfg.clk_dis = 1;
3023 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3024
3025 /* select memory to be written */
3026 ispu_mem_sel.read_mem_en = 0;
3027 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3028 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3029
3030 if (mem_sel == ISM330IS_ISPU_PROGRAM_RAM_MEMORY)
3031 {
3032 uint16_t addr_s[4] = {(uint16_t)0, (uint16_t)0, (uint16_t)0, (uint16_t)0};
3033 uint16_t len_s[4] = {(uint16_t)0, (uint16_t)0, (uint16_t)0, (uint16_t)0};
3034 uint8_t j = 0;
3035 uint16_t k;
3036
3037 addr_s[0] = mem_addr;
3038 k = 0U;
3039 for (i = 0U; i < len; i++)
3040 {
3041 if ((mem_addr + i == 0x2000U) || (mem_addr + i == 0x4000U) || (mem_addr + i == 0x6000U))
3042 {
3043 len_s[j++] = k;
3044 addr_s[j] = mem_addr + i;
3045 k = 0U;
3046 }
3047
3048 k++;
3049 }
3050 len_s[j++] = k;
3051
3052 k = 0U;
3053 for (i = 0U; i < j; i++)
3054 {
3055 ret += ism330is_ispu_sel_memory_addr(ctx, addr_s[i]);
3056 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]);
3057 k+=len_s[i];
3058 }
3059 } else {
3060 /* select memory address */
3061 ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr);
3062 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len);
3063 }
3064
3065 /* set ISPU clock back to previous value */
3066 ispu_cfg.clk_dis = clk_dis;
3067 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3068 }
3069
3070 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3071
3072 return ret;
3073 }
3074
3075 /**
3076 * @brief ISPU read memory. ISPU clock is disabled inside the routine.
3077 *
3078 * @param ctx read / write interface definitions
3079 * @param mem_sel ISM330IS_ISPU_DATA_RAM_MEMORY, ISM330IS_ISPU_PROGRAM_RAM_MEMORY
3080 * @param mem_addr memory address
3081 * @param mem_data memory data
3082 * @param len data length
3083 * @retval interface status (MANDATORY: return 0 -> no Error)
3084 *
3085 */
ism330is_ispu_read_memory(stmdev_ctx_t * ctx,ism330is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3086 int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx,
3087 ism330is_ispu_memory_type_t mem_sel,
3088 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3089 {
3090 ism330is_ispu_mem_sel_t ispu_mem_sel;
3091 ism330is_ispu_config_t ispu_cfg;
3092 uint8_t clk_dis;
3093 int32_t ret;
3094 uint8_t dummy;
3095
3096 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3097 if (ret == 0)
3098 {
3099 /* disable ISPU clock */
3100 ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3101 clk_dis = ispu_cfg.clk_dis;
3102 ispu_cfg.clk_dis = 1;
3103 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3104
3105 /* select memory to be read */
3106 ispu_mem_sel.read_mem_en = 1;
3107 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3108 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3109
3110 /* select memory address */
3111 ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr);
3112
3113 /* read data */
3114 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &dummy, 1);
3115 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len);
3116
3117 /* set ISPU clock back to previous value */
3118 ispu_cfg.clk_dis = clk_dis;
3119 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3120 }
3121
3122 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3123
3124 return ret;
3125 }
3126
3127 /**
3128 * @brief ISPU write flags (IF2S)
3129 *
3130 * @param ctx read / write interface definitions
3131 * @param data ISPU flags
3132 * @retval interface status (MANDATORY: return 0 -> no Error)
3133 *
3134 */
ism330is_ispu_write_flags(stmdev_ctx_t * ctx,uint16_t data)3135 int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data)
3136 {
3137 ism330is_ispu_if2s_flag_l_t flag_l;
3138 ism330is_ispu_if2s_flag_h_t flag_h;
3139 int32_t ret;
3140
3141 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3142 if (ret == 0)
3143 {
3144 /* write the flags */
3145 flag_h.if2s = (uint8_t)(data / 256U);
3146 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_IF2S_FLAG_H, (uint8_t *)&flag_h,
3147 1);
3148 flag_l.if2s = (uint8_t)(data & 0xffU);
3149 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_IF2S_FLAG_L, (uint8_t *)&flag_l,
3150 1);
3151 }
3152
3153 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3154
3155 return ret;
3156 }
3157
3158 /**
3159 * @brief ISPU read flags (S2IF)
3160 *
3161 * @param ctx read / write interface definitions
3162 * @param data ISPU flags
3163 * @retval interface status (MANDATORY: return 0 -> no Error)
3164 *
3165 */
ism330is_ispu_read_flags(stmdev_ctx_t * ctx,uint16_t * data)3166 int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data)
3167 {
3168 uint8_t buff[2];
3169 int32_t ret;
3170
3171 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3172 if (ret == 0)
3173 {
3174 /* read the flags */
3175 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_L, buff, 2);
3176 data[0] = (uint16_t)buff[1];
3177 data[0] = (data[0] * 256U) + (uint16_t)buff[0];
3178 }
3179
3180 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3181
3182 return ret;
3183 }
3184
3185 /**
3186 * @brief ISPU clear flags (S2IF)
3187 *
3188 * @param ctx read / write interface definitions
3189 * @retval interface status (MANDATORY: return 0 -> no Error)
3190 *
3191 */
ism330is_ispu_clear_flags(stmdev_ctx_t * ctx)3192 int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx)
3193 {
3194 uint8_t data = 1;
3195 int32_t ret;
3196
3197 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3198
3199 if (ret == 0)
3200 {
3201 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_H, &data, 1);
3202 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3203 }
3204
3205 return ret;
3206 }
3207
3208 /**
3209 * @brief ISPU DOUT registers.[get]
3210 *
3211 * @param ctx read / write interface definitions
3212 * @param val ISPU DOUT output registers.
3213 * @retval interface status (MANDATORY: return 0 -> no Error)
3214 *
3215 */
ism330is_ispu_read_data_raw_get(stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)3216 int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx,
3217 uint8_t *val,
3218 uint8_t len)
3219 {
3220 int32_t ret;
3221
3222 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3223 if (ret == 0)
3224 {
3225 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_DOUT_00_L, (uint8_t *) val,
3226 len);
3227 }
3228
3229 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3230
3231 return ret;
3232 }
3233
3234 /**
3235 * @brief ISPU int1_ctrl.[get]
3236 *
3237 * @param ctx read / write interface definitions
3238 * @param val ISPU int1_ctrl register value
3239 * @retval interface status (MANDATORY: return 0 -> no Error)
3240 *
3241 */
ism330is_ispu_int1_ctrl_get(stmdev_ctx_t * ctx,uint32_t * val)3242 int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val)
3243 {
3244 uint8_t buff[4];
3245 int32_t ret;
3246
3247 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3248 if (ret == 0)
3249 {
3250 /* read int1_ctrl reg */
3251 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT1_CTRL0, &buff[0], 4);
3252
3253 *val = (uint32_t)buff[3];
3254 *val = (*val * 256U) + (uint32_t)buff[2];
3255 *val = (*val * 256U) + (uint32_t)buff[1];
3256 *val = (*val * 256U) + (uint32_t)buff[0];
3257 }
3258
3259 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3260
3261 return ret;
3262 }
3263
3264 /**
3265 * @brief ISPU int1_ctrl.[set]
3266 *
3267 * @param ctx read / write interface definitions
3268 * @param val ISPU int1_ctrl register value
3269 * @retval interface status (MANDATORY: return 0 -> no Error)
3270 *
3271 */
ism330is_ispu_int1_ctrl_set(stmdev_ctx_t * ctx,uint32_t val)3272 int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val)
3273 {
3274 ism330is_ispu_int1_ctrl0_t int1_ctrl0;
3275 ism330is_ispu_int1_ctrl1_t int1_ctrl1;
3276 ism330is_ispu_int1_ctrl2_t int1_ctrl2;
3277 ism330is_ispu_int1_ctrl3_t int1_ctrl3;
3278 int32_t ret;
3279
3280 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3281 if (ret == 0)
3282 {
3283 /* write the int1_ctrl reg */
3284 int1_ctrl3.ispu_int1_ctrl = (uint8_t)((val >> 24) & 0xffU);
3285 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL3, (uint8_t *)&int1_ctrl3,
3286 1);
3287
3288 int1_ctrl2.ispu_int1_ctrl = (uint8_t)((val >> 16) & 0xffU);
3289 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL2, (uint8_t *)&int1_ctrl2,
3290 1);
3291
3292 int1_ctrl1.ispu_int1_ctrl = (uint8_t)((val >> 8) & 0xffU);
3293 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL1, (uint8_t *)&int1_ctrl1,
3294 1);
3295
3296 int1_ctrl0.ispu_int1_ctrl = (uint8_t)(val & 0xffU);
3297 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT1_CTRL0, (uint8_t *)&int1_ctrl0,
3298 1);
3299 }
3300
3301 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3302
3303 return ret;
3304 }
3305
3306 /**
3307 * @brief ISPU int2_ctrl.[get]
3308 *
3309 * @param ctx read / write interface definitions
3310 * @param val ISPU int2_ctrl register value
3311 * @retval interface status (MANDATORY: return 0 -> no Error)
3312 *
3313 */
ism330is_ispu_int2_ctrl_get(stmdev_ctx_t * ctx,uint32_t * val)3314 int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val)
3315 {
3316 uint8_t buff[4];
3317 int32_t ret;
3318
3319 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3320 if (ret == 0)
3321 {
3322 /* read int2_ctrl reg */
3323 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT2_CTRL0, &buff[0], 4);
3324
3325 *val = (uint32_t)buff[3];
3326 *val = (*val * 256U) + (uint32_t)buff[2];
3327 *val = (*val * 256U) + (uint32_t)buff[1];
3328 *val = (*val * 256U) + (uint32_t)buff[0];
3329 }
3330
3331 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3332
3333 return ret;
3334 }
3335
3336 /**
3337 * @brief ISPU int2_ctrl.[set]
3338 *
3339 * @param ctx read / write interface definitions
3340 * @param val ISPU int2_ctrl register value
3341 * @retval interface status (MANDATORY: return 0 -> no Error)
3342 *
3343 */
ism330is_ispu_int2_ctrl_set(stmdev_ctx_t * ctx,uint32_t val)3344 int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val)
3345 {
3346 ism330is_ispu_int2_ctrl0_t int2_ctrl0;
3347 ism330is_ispu_int2_ctrl1_t int2_ctrl1;
3348 ism330is_ispu_int2_ctrl2_t int2_ctrl2;
3349 ism330is_ispu_int2_ctrl3_t int2_ctrl3;
3350 int32_t ret;
3351
3352 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3353 if (ret == 0)
3354 {
3355 /* write the int2_ctrl reg */
3356 int2_ctrl3.ispu_int2_ctrl = (uint8_t)((val >> 24) & 0xffU);
3357 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL3, (uint8_t *)&int2_ctrl3,
3358 1);
3359
3360 int2_ctrl2.ispu_int2_ctrl = (uint8_t)((val >> 16) & 0xffU);
3361 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL2, (uint8_t *)&int2_ctrl2,
3362 1);
3363
3364 int2_ctrl1.ispu_int2_ctrl = (uint8_t)((val >> 8) & 0xffU);
3365 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL1, (uint8_t *)&int2_ctrl1,
3366 1);
3367
3368 int2_ctrl0.ispu_int2_ctrl = (uint8_t)(val & 0xffU);
3369 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_INT2_CTRL0, (uint8_t *)&int2_ctrl0,
3370 1);
3371 }
3372
3373 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3374
3375 return ret;
3376 }
3377
3378 /**
3379 * @brief ISPU int_status.[get]
3380 *
3381 * @param ctx read / write interface definitions
3382 * @param val ISPU int2_status register value
3383 * @retval interface status (MANDATORY: return 0 -> no Error)
3384 *
3385 */
ism330is_ispu_int_status_get(stmdev_ctx_t * ctx,uint32_t * val)3386 int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val)
3387 {
3388 uint8_t buff[4];
3389 int32_t ret;
3390
3391 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3392 if (ret == 0)
3393 {
3394 /* read int2_ctrl reg */
3395 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0, &buff[0], 4);
3396
3397 *val = (uint32_t)buff[3];
3398 *val = (*val * 256U) + (uint32_t)buff[2];
3399 *val = (*val * 256U) + (uint32_t)buff[1];
3400 *val = (*val * 256U) + (uint32_t)buff[0];
3401 }
3402
3403 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3404
3405 return ret;
3406 }
3407
3408 /**
3409 * @brief ISPU algo.[get]
3410 *
3411 * @param ctx read / write interface definitions
3412 * @param val ISPU algo register value
3413 * @retval interface status (MANDATORY: return 0 -> no Error)
3414 *
3415 */
ism330is_ispu_algo_get(stmdev_ctx_t * ctx,uint32_t * val)3416 int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val)
3417 {
3418 uint8_t buff[4];
3419 int32_t ret;
3420
3421 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3422 if (ret == 0)
3423 {
3424 /* read int2_ctrl reg */
3425 ret += ism330is_read_reg(ctx, ISM330IS_ISPU_ALGO0, &buff[0], 4);
3426
3427 *val = (uint32_t)buff[3];
3428 *val = (*val * 256U) + (uint32_t)buff[2];
3429 *val = (*val * 256U) + (uint32_t)buff[1];
3430 *val = (*val * 256U) + (uint32_t)buff[0];
3431 }
3432
3433 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3434
3435 return ret;
3436 }
3437
3438 /**
3439 * @brief ISPU algo.[set]
3440 *
3441 * @param ctx read / write interface definitions
3442 * @param val ISPU algo register value
3443 * @retval interface status (MANDATORY: return 0 -> no Error)
3444 *
3445 */
ism330is_ispu_algo_set(stmdev_ctx_t * ctx,uint32_t val)3446 int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val)
3447 {
3448 ism330is_ispu_algo0_t algo0;
3449 ism330is_ispu_algo1_t algo1;
3450 ism330is_ispu_algo2_t algo2;
3451 ism330is_ispu_algo3_t algo3;
3452 int32_t ret;
3453
3454 ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK);
3455 if (ret == 0)
3456 {
3457 /* write the algo reg */
3458 algo3.ispu_algo = (uint8_t)((val >> 24) & 0xffU);
3459 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO3, (uint8_t *)&algo3, 1);
3460
3461 algo2.ispu_algo = (uint8_t)((val >> 16) & 0xffU);
3462 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO2, (uint8_t *)&algo2, 1);
3463
3464 algo1.ispu_algo = (uint8_t)((val >> 8) & 0xffU);
3465 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO1, (uint8_t *)&algo1, 1);
3466
3467 algo0.ispu_algo = (uint8_t)(val & 0xffU);
3468 ret += ism330is_write_reg(ctx, ISM330IS_ISPU_ALGO0, (uint8_t *)&algo0, 1);
3469 }
3470
3471 ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK);
3472
3473 return ret;
3474 }
3475
3476 /**
3477 * @}
3478 *
3479 */
3480
