1 /**
2 ******************************************************************************
3 * @file ism330dlc_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ISM330DLC driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ism330dlc_reg.h"
21
22 /**
23 * @defgroup ISM330DLC
24 * @brief This file provides a set of functions needed to drive the
25 * ism330dlc enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ISM330DLC_interfaces_functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ism330dlc_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ism330dlc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
ism330dlc_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak ism330dlc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup ISM330DLC_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
ism330dlc_from_fs2g_to_mg(int16_t lsb)103 float_t ism330dlc_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
ism330dlc_from_fs4g_to_mg(int16_t lsb)108 float_t ism330dlc_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
ism330dlc_from_fs8g_to_mg(int16_t lsb)113 float_t ism330dlc_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
ism330dlc_from_fs16g_to_mg(int16_t lsb)118 float_t ism330dlc_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
ism330dlc_from_fs125dps_to_mdps(int16_t lsb)123 float_t ism330dlc_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
ism330dlc_from_fs250dps_to_mdps(int16_t lsb)128 float_t ism330dlc_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.750f);
131 }
132
ism330dlc_from_fs500dps_to_mdps(int16_t lsb)133 float_t ism330dlc_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
ism330dlc_from_fs1000dps_to_mdps(int16_t lsb)138 float_t ism330dlc_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
ism330dlc_from_fs2000dps_to_mdps(int16_t lsb)143 float_t ism330dlc_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
ism330dlc_from_lsb_to_celsius(int16_t lsb)148 float_t ism330dlc_from_lsb_to_celsius(int16_t lsb)
149 {
150 return (((float_t)lsb / 256.0f) + 25.0f);
151 }
152
153 /**
154 * @}
155 *
156 */
157
158 /**
159 * @defgroup ISM330DLC_data_generation
160 * @brief This section groups all the functions concerning data
161 * generation
162 * @{
163 *
164 */
165
166 /**
167 * @brief Accelerometer full-scale selection.[set]
168 *
169 * @param ctx Read / write interface definitions
170 * @param val Change the values of fs_xl in reg CTRL1_XL
171 * @retval Interface status (MANDATORY: return 0 -> no Error).
172 *
173 */
ism330dlc_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330dlc_fs_xl_t val)174 int32_t ism330dlc_xl_full_scale_set(const stmdev_ctx_t *ctx,
175 ism330dlc_fs_xl_t val)
176 {
177 ism330dlc_ctrl1_xl_t ctrl1_xl;
178 int32_t ret;
179 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
180 (uint8_t *)&ctrl1_xl, 1);
181
182 if (ret == 0)
183 {
184 ctrl1_xl.fs_xl = (uint8_t) val;
185 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
186 (uint8_t *)&ctrl1_xl, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Accelerometer full-scale selection.[get]
194 *
195 * @param ctx Read / write interface definitions
196 * @param val Get the values of fs_xl in reg CTRL1_XL
197 * @retval Interface status (MANDATORY: return 0 -> no Error).
198 *
199 */
ism330dlc_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330dlc_fs_xl_t * val)200 int32_t ism330dlc_xl_full_scale_get(const stmdev_ctx_t *ctx,
201 ism330dlc_fs_xl_t *val)
202 {
203 ism330dlc_ctrl1_xl_t ctrl1_xl;
204 int32_t ret;
205 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
206 (uint8_t *)&ctrl1_xl, 1);
207
208 switch (ctrl1_xl.fs_xl)
209 {
210 case ISM330DLC_2g:
211 *val = ISM330DLC_2g;
212 break;
213
214 case ISM330DLC_16g:
215 *val = ISM330DLC_16g;
216 break;
217
218 case ISM330DLC_4g:
219 *val = ISM330DLC_4g;
220 break;
221
222 case ISM330DLC_8g:
223 *val = ISM330DLC_8g;
224 break;
225
226 default:
227 *val = ISM330DLC_2g;
228 break;
229 }
230
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
ism330dlc_xl_data_rate_set(const stmdev_ctx_t * ctx,ism330dlc_odr_xl_t val)242 int32_t ism330dlc_xl_data_rate_set(const stmdev_ctx_t *ctx,
243 ism330dlc_odr_xl_t val)
244 {
245 ism330dlc_ctrl1_xl_t ctrl1_xl;
246 int32_t ret;
247 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
248 (uint8_t *)&ctrl1_xl, 1);
249
250 if (ret == 0)
251 {
252 ctrl1_xl.odr_xl = (uint8_t) val;
253 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
254 (uint8_t *)&ctrl1_xl, 1);
255 }
256
257 return ret;
258 }
259
260 /**
261 * @brief Accelerometer data rate selection.[get]
262 *
263 * @param ctx Read / write interface definitions
264 * @param val Get the values of odr_xl in reg CTRL1_XL
265 * @retval Interface status (MANDATORY: return 0 -> no Error).
266 *
267 */
ism330dlc_xl_data_rate_get(const stmdev_ctx_t * ctx,ism330dlc_odr_xl_t * val)268 int32_t ism330dlc_xl_data_rate_get(const stmdev_ctx_t *ctx,
269 ism330dlc_odr_xl_t *val)
270 {
271 ism330dlc_ctrl1_xl_t ctrl1_xl;
272 int32_t ret;
273 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
274 (uint8_t *)&ctrl1_xl, 1);
275
276 switch (ctrl1_xl.odr_xl)
277 {
278 case ISM330DLC_XL_ODR_OFF:
279 *val = ISM330DLC_XL_ODR_OFF;
280 break;
281
282 case ISM330DLC_XL_ODR_12Hz5:
283 *val = ISM330DLC_XL_ODR_12Hz5;
284 break;
285
286 case ISM330DLC_XL_ODR_26Hz:
287 *val = ISM330DLC_XL_ODR_26Hz;
288 break;
289
290 case ISM330DLC_XL_ODR_52Hz:
291 *val = ISM330DLC_XL_ODR_52Hz;
292 break;
293
294 case ISM330DLC_XL_ODR_104Hz:
295 *val = ISM330DLC_XL_ODR_104Hz;
296 break;
297
298 case ISM330DLC_XL_ODR_208Hz:
299 *val = ISM330DLC_XL_ODR_208Hz;
300 break;
301
302 case ISM330DLC_XL_ODR_416Hz:
303 *val = ISM330DLC_XL_ODR_416Hz;
304 break;
305
306 case ISM330DLC_XL_ODR_833Hz:
307 *val = ISM330DLC_XL_ODR_833Hz;
308 break;
309
310 case ISM330DLC_XL_ODR_1k66Hz:
311 *val = ISM330DLC_XL_ODR_1k66Hz;
312 break;
313
314 case ISM330DLC_XL_ODR_3k33Hz:
315 *val = ISM330DLC_XL_ODR_3k33Hz;
316 break;
317
318 case ISM330DLC_XL_ODR_6k66Hz:
319 *val = ISM330DLC_XL_ODR_6k66Hz;
320 break;
321
322 case ISM330DLC_XL_ODR_1Hz6:
323 *val = ISM330DLC_XL_ODR_1Hz6;
324 break;
325
326 default:
327 *val = ISM330DLC_XL_ODR_OFF;
328 break;
329 }
330
331 return ret;
332 }
333
334 /**
335 * @brief Gyroscope chain full-scale selection.[set]
336 *
337 * @param ctx Read / write interface definitions
338 * @param val Change the values of fs_g in reg CTRL2_G
339 * @retval Interface status (MANDATORY: return 0 -> no Error).
340 *
341 */
ism330dlc_gy_full_scale_set(const stmdev_ctx_t * ctx,ism330dlc_fs_g_t val)342 int32_t ism330dlc_gy_full_scale_set(const stmdev_ctx_t *ctx,
343 ism330dlc_fs_g_t val)
344 {
345 ism330dlc_ctrl2_g_t ctrl2_g;
346 int32_t ret;
347 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
348
349 if (ret == 0)
350 {
351 ctrl2_g.fs_g = (uint8_t) val;
352 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
353 }
354
355 return ret;
356 }
357
358 /**
359 * @brief Gyroscope chain full-scale selection.[get]
360 *
361 * @param ctx Read / write interface definitions
362 * @param val Get the values of fs_g in reg CTRL2_G
363 * @retval Interface status (MANDATORY: return 0 -> no Error).
364 *
365 */
ism330dlc_gy_full_scale_get(const stmdev_ctx_t * ctx,ism330dlc_fs_g_t * val)366 int32_t ism330dlc_gy_full_scale_get(const stmdev_ctx_t *ctx,
367 ism330dlc_fs_g_t *val)
368 {
369 ism330dlc_ctrl2_g_t ctrl2_g;
370 int32_t ret;
371 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
372
373 switch (ctrl2_g.fs_g)
374 {
375 case ISM330DLC_250dps:
376 *val = ISM330DLC_250dps;
377 break;
378
379 case ISM330DLC_125dps:
380 *val = ISM330DLC_125dps;
381 break;
382
383 case ISM330DLC_500dps:
384 *val = ISM330DLC_500dps;
385 break;
386
387 case ISM330DLC_1000dps:
388 *val = ISM330DLC_1000dps;
389 break;
390
391 case ISM330DLC_2000dps:
392 *val = ISM330DLC_2000dps;
393 break;
394
395 default:
396 *val = ISM330DLC_250dps;
397 break;
398 }
399
400 return ret;
401 }
402
403 /**
404 * @brief Gyroscope data rate selection.[set]
405 *
406 * @param ctx Read / write interface definitions
407 * @param val Change the values of odr_g in reg CTRL2_G
408 * @retval Interface status (MANDATORY: return 0 -> no Error).
409 *
410 */
ism330dlc_gy_data_rate_set(const stmdev_ctx_t * ctx,ism330dlc_odr_g_t val)411 int32_t ism330dlc_gy_data_rate_set(const stmdev_ctx_t *ctx,
412 ism330dlc_odr_g_t val)
413 {
414 ism330dlc_ctrl2_g_t ctrl2_g;
415 int32_t ret;
416 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
417
418 if (ret == 0)
419 {
420 ctrl2_g.odr_g = (uint8_t) val;
421 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
422 }
423
424 return ret;
425 }
426
427 /**
428 * @brief Gyroscope data rate selection.[get]
429 *
430 * @param ctx Read / write interface definitions
431 * @param val Get the values of odr_g in reg CTRL2_G
432 * @retval Interface status (MANDATORY: return 0 -> no Error).
433 *
434 */
ism330dlc_gy_data_rate_get(const stmdev_ctx_t * ctx,ism330dlc_odr_g_t * val)435 int32_t ism330dlc_gy_data_rate_get(const stmdev_ctx_t *ctx,
436 ism330dlc_odr_g_t *val)
437 {
438 ism330dlc_ctrl2_g_t ctrl2_g;
439 int32_t ret;
440 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
441
442 switch (ctrl2_g.odr_g)
443 {
444 case ISM330DLC_GY_ODR_OFF:
445 *val = ISM330DLC_GY_ODR_OFF;
446 break;
447
448 case ISM330DLC_GY_ODR_12Hz5:
449 *val = ISM330DLC_GY_ODR_12Hz5;
450 break;
451
452 case ISM330DLC_GY_ODR_26Hz:
453 *val = ISM330DLC_GY_ODR_26Hz;
454 break;
455
456 case ISM330DLC_GY_ODR_52Hz:
457 *val = ISM330DLC_GY_ODR_52Hz;
458 break;
459
460 case ISM330DLC_GY_ODR_104Hz:
461 *val = ISM330DLC_GY_ODR_104Hz;
462 break;
463
464 case ISM330DLC_GY_ODR_208Hz:
465 *val = ISM330DLC_GY_ODR_208Hz;
466 break;
467
468 case ISM330DLC_GY_ODR_416Hz:
469 *val = ISM330DLC_GY_ODR_416Hz;
470 break;
471
472 case ISM330DLC_GY_ODR_833Hz:
473 *val = ISM330DLC_GY_ODR_833Hz;
474 break;
475
476 case ISM330DLC_GY_ODR_1k66Hz:
477 *val = ISM330DLC_GY_ODR_1k66Hz;
478 break;
479
480 case ISM330DLC_GY_ODR_3k33Hz:
481 *val = ISM330DLC_GY_ODR_3k33Hz;
482 break;
483
484 case ISM330DLC_GY_ODR_6k66Hz:
485 *val = ISM330DLC_GY_ODR_6k66Hz;
486 break;
487
488 default:
489 *val = ISM330DLC_GY_ODR_OFF;
490 break;
491 }
492
493 return ret;
494 }
495
496 /**
497 * @brief Block data update.[set]
498 *
499 * @param ctx Read / write interface definitions
500 * @param val Change the values of bdu in reg CTRL3_C
501 * @retval Interface status (MANDATORY: return 0 -> no Error).
502 *
503 */
ism330dlc_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)504 int32_t ism330dlc_block_data_update_set(const stmdev_ctx_t *ctx,
505 uint8_t val)
506 {
507 ism330dlc_ctrl3_c_t ctrl3_c;
508 int32_t ret;
509 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
510
511 if (ret == 0)
512 {
513 ctrl3_c.bdu = val;
514 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
515 }
516
517 return ret;
518 }
519
520 /**
521 * @brief Block data update.[get]
522 *
523 * @param ctx Read / write interface definitions
524 * @param val Change the values of bdu in reg CTRL3_C
525 * @retval Interface status (MANDATORY: return 0 -> no Error).
526 *
527 */
ism330dlc_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)528 int32_t ism330dlc_block_data_update_get(const stmdev_ctx_t *ctx,
529 uint8_t *val)
530 {
531 ism330dlc_ctrl3_c_t ctrl3_c;
532 int32_t ret;
533 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
534 *val = ctrl3_c.bdu;
535
536 return ret;
537 }
538
539 /**
540 * @brief Weight of XL user offset bits of registers
541 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set]
542 *
543 * @param ctx Read / write interface definitions
544 * @param val Change the values of usr_off_w in reg CTRL6_C
545 * @retval Interface status (MANDATORY: return 0 -> no Error).
546 *
547 */
ism330dlc_xl_offset_weight_set(const stmdev_ctx_t * ctx,ism330dlc_usr_off_w_t val)548 int32_t ism330dlc_xl_offset_weight_set(const stmdev_ctx_t *ctx,
549 ism330dlc_usr_off_w_t val)
550 {
551 ism330dlc_ctrl6_c_t ctrl6_c;
552 int32_t ret;
553 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
554
555 if (ret == 0)
556 {
557 ctrl6_c.usr_off_w = (uint8_t) val;
558 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
559 }
560
561 return ret;
562 }
563
564 /**
565 * @brief Weight of XL user offset bits of registers
566 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get]
567 *
568 * @param ctx Read / write interface definitions
569 * @param val Get the values of usr_off_w in reg CTRL6_C
570 * @retval Interface status (MANDATORY: return 0 -> no Error).
571 *
572 */
ism330dlc_xl_offset_weight_get(const stmdev_ctx_t * ctx,ism330dlc_usr_off_w_t * val)573 int32_t ism330dlc_xl_offset_weight_get(const stmdev_ctx_t *ctx,
574 ism330dlc_usr_off_w_t *val)
575 {
576 ism330dlc_ctrl6_c_t ctrl6_c;
577 int32_t ret;
578 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
579
580 switch (ctrl6_c.usr_off_w)
581 {
582 case ISM330DLC_LSb_1mg:
583 *val = ISM330DLC_LSb_1mg;
584 break;
585
586 case ISM330DLC_LSb_16mg:
587 *val = ISM330DLC_LSb_16mg;
588 break;
589
590 default:
591 *val = ISM330DLC_LSb_1mg;
592 break;
593 }
594
595 return ret;
596 }
597
598 /**
599 * @brief High-performance operating mode for accelerometer[set]
600 *
601 * @param ctx Read / write interface definitions
602 * @param val Change the values of xl_hm_mode in reg CTRL6_C
603 * @retval Interface status (MANDATORY: return 0 -> no Error).
604 *
605 */
ism330dlc_xl_power_mode_set(const stmdev_ctx_t * ctx,ism330dlc_xl_hm_mode_t val)606 int32_t ism330dlc_xl_power_mode_set(const stmdev_ctx_t *ctx,
607 ism330dlc_xl_hm_mode_t val)
608 {
609 ism330dlc_ctrl6_c_t ctrl6_c;
610 int32_t ret;
611 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
612
613 if (ret == 0)
614 {
615 ctrl6_c.xl_hm_mode = (uint8_t) val;
616 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
617 }
618
619 return ret;
620 }
621
622 /**
623 * @brief High-performance operating mode for accelerometer.[get]
624 *
625 * @param ctx Read / write interface definitions
626 * @param val Get the values of xl_hm_mode in reg CTRL6_C
627 * @retval Interface status (MANDATORY: return 0 -> no Error).
628 *
629 */
ism330dlc_xl_power_mode_get(const stmdev_ctx_t * ctx,ism330dlc_xl_hm_mode_t * val)630 int32_t ism330dlc_xl_power_mode_get(const stmdev_ctx_t *ctx,
631 ism330dlc_xl_hm_mode_t *val)
632 {
633 ism330dlc_ctrl6_c_t ctrl6_c;
634 int32_t ret;
635 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
636
637 switch (ctrl6_c.xl_hm_mode)
638 {
639 case ISM330DLC_XL_HIGH_PERFORMANCE:
640 *val = ISM330DLC_XL_HIGH_PERFORMANCE;
641 break;
642
643 case ISM330DLC_XL_NORMAL:
644 *val = ISM330DLC_XL_NORMAL;
645 break;
646
647 default:
648 *val = ISM330DLC_XL_HIGH_PERFORMANCE;
649 break;
650 }
651
652 return ret;
653 }
654
655 /**
656 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
657 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
658 * FUNC_SRC1 (53h) registers in the primary interface.[set]
659 *
660 * @param ctx Read / write interface definitions
661 * @param val Change the values of rounding_status in reg CTRL7_G
662 * @retval Interface status (MANDATORY: return 0 -> no Error).
663 *
664 */
ism330dlc_rounding_on_status_set(const stmdev_ctx_t * ctx,ism330dlc_rounding_status_t val)665 int32_t ism330dlc_rounding_on_status_set(const stmdev_ctx_t *ctx,
666 ism330dlc_rounding_status_t val)
667 {
668 ism330dlc_ctrl7_g_t ctrl7_g;
669 int32_t ret;
670 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
671
672 if (ret == 0)
673 {
674 ctrl7_g.rounding_status = (uint8_t) val;
675 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
676 }
677
678 return ret;
679 }
680
681 /**
682 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
683 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
684 * FUNC_SRC1 (53h) registers in the primary interface.[get]
685 *
686 * @param ctx Read / write interface definitions
687 * @param val Get the values of rounding_status in reg CTRL7_G
688 * @retval Interface status (MANDATORY: return 0 -> no Error).
689 *
690 */
ism330dlc_rounding_on_status_get(const stmdev_ctx_t * ctx,ism330dlc_rounding_status_t * val)691 int32_t ism330dlc_rounding_on_status_get(const stmdev_ctx_t *ctx,
692 ism330dlc_rounding_status_t *val)
693 {
694 ism330dlc_ctrl7_g_t ctrl7_g;
695 int32_t ret;
696 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
697
698 switch (ctrl7_g.rounding_status)
699 {
700 case ISM330DLC_STAT_RND_DISABLE:
701 *val = ISM330DLC_STAT_RND_DISABLE;
702 break;
703
704 case ISM330DLC_STAT_RND_ENABLE:
705 *val = ISM330DLC_STAT_RND_ENABLE;
706 break;
707
708 default:
709 *val = ISM330DLC_STAT_RND_DISABLE;
710 break;
711 }
712
713 return ret;
714 }
715
716 /**
717 * @brief High-performance operating mode disable for gyroscope.[set]
718 *
719 * @param ctx Read / write interface definitions
720 * @param val Change the values of g_hm_mode in reg CTRL7_G
721 * @retval Interface status (MANDATORY: return 0 -> no Error).
722 *
723 */
ism330dlc_gy_power_mode_set(const stmdev_ctx_t * ctx,ism330dlc_g_hm_mode_t val)724 int32_t ism330dlc_gy_power_mode_set(const stmdev_ctx_t *ctx,
725 ism330dlc_g_hm_mode_t val)
726 {
727 ism330dlc_ctrl7_g_t ctrl7_g;
728 int32_t ret;
729 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
730
731 if (ret == 0)
732 {
733 ctrl7_g.g_hm_mode = (uint8_t) val;
734 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
735 }
736
737 return ret;
738 }
739
740 /**
741 * @brief High-performance operating mode disable for gyroscope.[get]
742 *
743 * @param ctx Read / write interface definitions
744 * @param val Get the values of g_hm_mode in reg CTRL7_G
745 * @retval Interface status (MANDATORY: return 0 -> no Error).
746 *
747 */
ism330dlc_gy_power_mode_get(const stmdev_ctx_t * ctx,ism330dlc_g_hm_mode_t * val)748 int32_t ism330dlc_gy_power_mode_get(const stmdev_ctx_t *ctx,
749 ism330dlc_g_hm_mode_t *val)
750 {
751 ism330dlc_ctrl7_g_t ctrl7_g;
752 int32_t ret;
753 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
754
755 switch (ctrl7_g.g_hm_mode)
756 {
757 case ISM330DLC_GY_HIGH_PERFORMANCE:
758 *val = ISM330DLC_GY_HIGH_PERFORMANCE;
759 break;
760
761 case ISM330DLC_GY_NORMAL:
762 *val = ISM330DLC_GY_NORMAL;
763 break;
764
765 default:
766 *val = ISM330DLC_GY_HIGH_PERFORMANCE;
767 break;
768 }
769
770 return ret;
771 }
772
773 /**
774 * @brief Read all the interrupt/status flag of the device.[get]
775 *
776 * @param ctx Read / write interface definitions
777 * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG,
778 * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask
779 * @retval Interface status (MANDATORY: return 0 -> no Error).
780 *
781 */
ism330dlc_all_sources_get(const stmdev_ctx_t * ctx,ism330dlc_all_sources_t * val)782 int32_t ism330dlc_all_sources_get(const stmdev_ctx_t *ctx,
783 ism330dlc_all_sources_t *val)
784 {
785 int32_t ret;
786 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_SRC,
787 (uint8_t *) & (val->wake_up_src), 1);
788
789 if (ret == 0)
790 {
791 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_SRC,
792 (uint8_t *) & (val->tap_src), 1);
793 }
794
795 if (ret == 0)
796 {
797 ret = ism330dlc_read_reg(ctx, ISM330DLC_D6D_SRC,
798 (uint8_t *) & (val->d6d_src), 1);
799 }
800
801 if (ret == 0)
802 {
803 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
804 (uint8_t *) & (val->status_reg), 1);
805 }
806
807 if (ret == 0)
808 {
809 ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_SRC1,
810 (uint8_t *) & (val->func_src1), 1);
811 }
812
813 if (ret == 0)
814 {
815 ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_SRC2,
816 (uint8_t *) & (val->func_src2), 1);
817 }
818
819 if (ret == 0)
820 {
821 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
822 }
823
824 return ret;
825 }
826 /**
827 * @brief The STATUS_REG register is read by the primary interface[get]
828 *
829 * @param ctx Read / write interface definitions
830 * @param val Registers STATUS_REG
831 * @retval Interface status (MANDATORY: return 0 -> no Error).
832 *
833 */
ism330dlc_status_reg_get(const stmdev_ctx_t * ctx,ism330dlc_status_reg_t * val)834 int32_t ism330dlc_status_reg_get(const stmdev_ctx_t *ctx,
835 ism330dlc_status_reg_t *val)
836 {
837 int32_t ret;
838 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t *) val, 1);
839
840 return ret;
841 }
842
843 /**
844 * @brief Accelerometer new data available.[get]
845 *
846 * @param ctx Read / write interface definitions
847 * @param val Change the values of xlda in reg STATUS_REG
848 * @retval Interface status (MANDATORY: return 0 -> no Error).
849 *
850 */
ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)851 int32_t ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
852 uint8_t *val)
853 {
854 ism330dlc_status_reg_t status_reg;
855 int32_t ret;
856 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
857 (uint8_t *)&status_reg, 1);
858 *val = status_reg.xlda;
859
860 return ret;
861 }
862
863 /**
864 * @brief Gyroscope new data available.[get]
865 *
866 * @param ctx Read / write interface definitions
867 * @param val Change the values of gda in reg STATUS_REG
868 * @retval Interface status (MANDATORY: return 0 -> no Error).
869 *
870 */
ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)871 int32_t ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
872 uint8_t *val)
873 {
874 ism330dlc_status_reg_t status_reg;
875 int32_t ret;
876 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
877 (uint8_t *)&status_reg, 1);
878 *val = status_reg.gda;
879
880 return ret;
881 }
882
883 /**
884 * @brief Temperature new data available.[get]
885 *
886 * @param ctx Read / write interface definitions
887 * @param val Change the values of tda in reg STATUS_REG
888 * @retval Interface status (MANDATORY: return 0 -> no Error).
889 *
890 */
ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)891 int32_t ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
892 uint8_t *val)
893 {
894 ism330dlc_status_reg_t status_reg;
895 int32_t ret;
896 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG,
897 (uint8_t *)&status_reg, 1);
898 *val = status_reg.tda;
899
900 return ret;
901 }
902
903 /**
904 * @brief Accelerometer axis user offset correction expressed in two’s
905 * complement, weight depends on USR_OFF_W in CTRL6_C.
906 * The value must be in the range [-127 127].[set]
907 *
908 * @param ctx Read / write interface definitions
909 * @param buff Buffer that contains data to write
910 * @retval Interface status (MANDATORY: return 0 -> no Error).
911 *
912 */
ism330dlc_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t * buff)913 int32_t ism330dlc_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff)
914 {
915 int32_t ret;
916 ret = ism330dlc_write_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3);
917
918 return ret;
919 }
920
921 /**
922 * @brief Accelerometer axis user offset correction xpressed in two’s
923 * complement, weight depends on USR_OFF_W in CTRL6_C.
924 * The value must be in the range [-127 127].[get]
925 *
926 * @param ctx Read / write interface definitions
927 * @param buff Buffer that stores data read
928 * @retval Interface status (MANDATORY: return 0 -> no Error).
929 *
930 */
ism330dlc_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * buff)931 int32_t ism330dlc_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff)
932 {
933 int32_t ret;
934 ret = ism330dlc_read_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3);
935
936 return ret;
937 }
938
939 /**
940 * @}
941 *
942 */
943
944 /**
945 * @defgroup ISM330DLC_Timestamp
946 * @brief This section groups all the functions that manage the
947 * timestamp generation.
948 * @{
949 *
950 */
951
952 /**
953 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
954 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set]
955 *
956 * @param ctx Read / write interface definitions
957 * @param val Change the values of timer_en in reg CTRL10_C
958 * @retval Interface status (MANDATORY: return 0 -> no Error).
959 *
960 */
ism330dlc_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)961 int32_t ism330dlc_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
962 {
963 ism330dlc_ctrl10_c_t ctrl10_c;
964 int32_t ret;
965 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
966 (uint8_t *)&ctrl10_c, 1);
967
968 if (ret == 0)
969 {
970 ctrl10_c.timer_en = val;
971
972 if (val != 0x00U)
973 {
974 ctrl10_c.func_en = val;
975 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL10_C,
976 (uint8_t *)&ctrl10_c, 1);
977 }
978 }
979
980 return ret;
981 }
982
983 /**
984 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
985 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get]
986 *
987 * @param ctx Read / write interface definitions
988 * @param val Change the values of timer_en in reg CTRL10_C
989 * @retval Interface status (MANDATORY: return 0 -> no Error).
990 *
991 */
ism330dlc_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)992 int32_t ism330dlc_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
993 {
994 ism330dlc_ctrl10_c_t ctrl10_c;
995 int32_t ret;
996 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
997 (uint8_t *)&ctrl10_c, 1);
998 *val = ctrl10_c.timer_en;
999
1000 return ret;
1001 }
1002
1003 /**
1004 * @brief Timestamp register resolution setting.
1005 * Configuration of this bit affects
1006 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1007 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1008 * STEP_TIMESTAMP_H(4Ah) and
1009 * STEP_COUNT_DELTA(15h) registers.[set]
1010 *
1011 * @param ctx Read / write interface definitions
1012 * @param val Change the values of timer_hr in reg WAKE_UP_DUR
1013 * @retval Interface status (MANDATORY: return 0 -> no Error).
1014 *
1015 */
ism330dlc_timestamp_res_set(const stmdev_ctx_t * ctx,ism330dlc_timer_hr_t val)1016 int32_t ism330dlc_timestamp_res_set(const stmdev_ctx_t *ctx,
1017 ism330dlc_timer_hr_t val)
1018 {
1019 ism330dlc_wake_up_dur_t wake_up_dur;
1020 int32_t ret;
1021 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
1022 (uint8_t *)&wake_up_dur, 1);
1023
1024 if (ret == 0)
1025 {
1026 wake_up_dur.timer_hr = (uint8_t) val;
1027 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
1028 (uint8_t *)&wake_up_dur, 1);
1029 }
1030
1031 return ret;
1032 }
1033
1034 /**
1035 * @brief Timestamp register resolution setting.
1036 * Configuration of this bit affects
1037 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1038 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1039 * STEP_TIMESTAMP_H(4Ah) and
1040 * STEP_COUNT_DELTA(15h) registers.[get]
1041 *
1042 * @param ctx Read / write interface definitions
1043 * @param val Get the values of timer_hr in reg WAKE_UP_DUR
1044 * @retval Interface status (MANDATORY: return 0 -> no Error).
1045 *
1046 */
ism330dlc_timestamp_res_get(const stmdev_ctx_t * ctx,ism330dlc_timer_hr_t * val)1047 int32_t ism330dlc_timestamp_res_get(const stmdev_ctx_t *ctx,
1048 ism330dlc_timer_hr_t *val)
1049 {
1050 ism330dlc_wake_up_dur_t wake_up_dur;
1051 int32_t ret;
1052 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
1053 (uint8_t *)&wake_up_dur, 1);
1054
1055 switch (wake_up_dur.timer_hr)
1056 {
1057 case ISM330DLC_LSB_6ms4:
1058 *val = ISM330DLC_LSB_6ms4;
1059 break;
1060
1061 case ISM330DLC_LSB_25us:
1062 *val = ISM330DLC_LSB_25us;
1063 break;
1064
1065 default:
1066 *val = ISM330DLC_LSB_6ms4;
1067 break;
1068 }
1069
1070 return ret;
1071 }
1072
1073 /**
1074 * @}
1075 *
1076 */
1077
1078 /**
1079 * @defgroup ISM330DLC_Dataoutput
1080 * @brief This section groups all the data output functions.
1081 * @{
1082 *
1083 */
1084
1085 /**
1086 * @brief Circular burst-mode (rounding) read from output registers
1087 * through the primary interface.[set]
1088 *
1089 * @param ctx Read / write interface definitions
1090 * @param val Change the values of rounding in reg CTRL5_C
1091 * @retval Interface status (MANDATORY: return 0 -> no Error).
1092 *
1093 */
ism330dlc_rounding_mode_set(const stmdev_ctx_t * ctx,ism330dlc_rounding_t val)1094 int32_t ism330dlc_rounding_mode_set(const stmdev_ctx_t *ctx,
1095 ism330dlc_rounding_t val)
1096 {
1097 ism330dlc_ctrl5_c_t ctrl5_c;
1098 int32_t ret;
1099 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1100
1101 if (ret == 0)
1102 {
1103 ctrl5_c.rounding = (uint8_t) val;
1104 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1105 }
1106
1107 return ret;
1108 }
1109
1110 /**
1111 * @brief Circular burst-mode (rounding) read from output registers
1112 * through the primary interface.[get]
1113 *
1114 * @param ctx Read / write interface definitions
1115 * @param val Get the values of rounding in reg CTRL5_C
1116 * @retval Interface status (MANDATORY: return 0 -> no Error).
1117 *
1118 */
ism330dlc_rounding_mode_get(const stmdev_ctx_t * ctx,ism330dlc_rounding_t * val)1119 int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx,
1120 ism330dlc_rounding_t *val)
1121 {
1122 ism330dlc_ctrl5_c_t ctrl5_c;
1123 int32_t ret;
1124 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1125
1126 switch (ctrl5_c.rounding)
1127 {
1128 case ISM330DLC_ROUND_DISABLE:
1129 *val = ISM330DLC_ROUND_DISABLE;
1130 break;
1131
1132 case ISM330DLC_ROUND_XL:
1133 *val = ISM330DLC_ROUND_XL;
1134 break;
1135
1136 case ISM330DLC_ROUND_GY:
1137 *val = ISM330DLC_ROUND_GY;
1138 break;
1139
1140 case ISM330DLC_ROUND_GY_XL:
1141 *val = ISM330DLC_ROUND_GY_XL;
1142 break;
1143
1144 case ISM330DLC_ROUND_SH1_TO_SH6:
1145 *val = ISM330DLC_ROUND_SH1_TO_SH6;
1146 break;
1147
1148 case ISM330DLC_ROUND_XL_SH1_TO_SH6:
1149 *val = ISM330DLC_ROUND_XL_SH1_TO_SH6;
1150 break;
1151
1152 case ISM330DLC_ROUND_GY_XL_SH1_TO_SH12:
1153 *val = ISM330DLC_ROUND_GY_XL_SH1_TO_SH12;
1154 break;
1155
1156 case ISM330DLC_ROUND_GY_XL_SH1_TO_SH6:
1157 *val = ISM330DLC_ROUND_GY_XL_SH1_TO_SH6;
1158 break;
1159
1160 default:
1161 *val = ISM330DLC_ROUND_DISABLE;
1162 break;
1163 }
1164
1165 return ret;
1166 }
1167
1168 /**
1169 * @brief Temperature data output register (r). L and H registers together
1170 * express a 16-bit word in two’s complement.[get]
1171 *
1172 * @param ctx Read / write interface definitions
1173 * @param buff Buffer that stores data read
1174 * @retval Interface status (MANDATORY: return 0 -> no Error).
1175 *
1176 */
ism330dlc_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1177 int32_t ism330dlc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1178 {
1179 uint8_t buff[2];
1180 int32_t ret;
1181 ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_TEMP_L, buff, 2);
1182 *val = (int16_t)buff[1];
1183 *val = (*val * 256) + (int16_t)buff[0];
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
1190 * two’s complement.[get]
1191 *
1192 * @param ctx Read / write interface definitions
1193 * @param buff Buffer that stores data read
1194 * @retval Interface status (MANDATORY: return 0 -> no Error).
1195 *
1196 */
ism330dlc_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1197 int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1198 int16_t *val)
1199 {
1200 uint8_t buff[6];
1201 int32_t ret;
1202 ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_G, buff, 6);
1203 val[0] = (int16_t)buff[1];
1204 val[0] = (val[0] * 256) + (int16_t)buff[0];
1205 val[1] = (int16_t)buff[3];
1206 val[1] = (val[1] * 256) + (int16_t)buff[2];
1207 val[2] = (int16_t)buff[5];
1208 val[2] = (val[2] * 256) + (int16_t)buff[4];
1209
1210 return ret;
1211 }
1212
1213 /**
1214 * @brief Linear acceleration output register. The value is expressed
1215 * as a 16-bit word in two’s complement.[get]
1216 *
1217 * @param ctx Read / write interface definitions
1218 * @param buff Buffer that stores data read
1219 * @retval Interface status (MANDATORY: return 0 -> no Error).
1220 *
1221 */
ism330dlc_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1222 int32_t ism330dlc_acceleration_raw_get(const stmdev_ctx_t *ctx,
1223 int16_t *val)
1224 {
1225 uint8_t buff[6];
1226 int32_t ret;
1227 ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_XL, buff, 6);
1228 val[0] = (int16_t)buff[1];
1229 val[0] = (val[0] * 256) + (int16_t)buff[0];
1230 val[1] = (int16_t)buff[3];
1231 val[1] = (val[1] * 256) + (int16_t)buff[2];
1232 val[2] = (int16_t)buff[5];
1233 val[2] = (val[2] * 256) + (int16_t)buff[4];
1234
1235 return ret;
1236 }
1237
1238 /**
1239 * @brief External magnetometer raw data.[get]
1240 *
1241 * @param ctx Read / write interface definitions
1242 * @param buff Buffer that stores data read
1243 * @retval Interface status (MANDATORY: return 0 -> no Error).
1244 *
1245 */
ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1246 int32_t ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t *ctx,
1247 int16_t *val)
1248 {
1249 uint8_t buff[6];
1250 int32_t ret;
1251 ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_MAG_RAW_X_L, buff, 6);
1252 val[0] = (int16_t)buff[1];
1253 val[0] = (val[0] * 256) + (int16_t)buff[0];
1254 val[1] = (int16_t)buff[3];
1255 val[1] = (val[1] * 256) + (int16_t)buff[2];
1256 val[2] = (int16_t)buff[5];
1257 val[2] = (val[2] * 256) + (int16_t)buff[4];
1258
1259 return ret;
1260 }
1261
1262 /**
1263 * @brief Read data in FIFO.[get]
1264 *
1265 * @param ctx Read / write interface definitions
1266 * @param buffer Data buffer to store FIFO data.
1267 * @param len Number of data to read from FIFO.
1268 * @retval Interface status (MANDATORY: return 0 -> no Error).
1269 *
1270 */
ism330dlc_fifo_raw_data_get(const stmdev_ctx_t * ctx,uint8_t * buffer,uint8_t len)1271 int32_t ism330dlc_fifo_raw_data_get(const stmdev_ctx_t *ctx,
1272 uint8_t *buffer,
1273 uint8_t len)
1274 {
1275 int32_t ret;
1276 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_DATA_OUT_L, buffer, len);
1277
1278 return ret;
1279 }
1280
1281 /**
1282 * @}
1283 *
1284 */
1285
1286 /**
1287 * @defgroup ISM330DLC_common
1288 * @brief This section groups common useful functions.
1289 * @{
1290 *
1291 */
1292
1293 /**
1294 * @brief Enable access to the embedded functions/sensor hub
1295 * configuration registers[set]
1296 *
1297 * @param ctx Read / write interface definitions
1298 * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS
1299 * @retval Interface status (MANDATORY: return 0 -> no Error).
1300 *
1301 */
ism330dlc_mem_bank_set(const stmdev_ctx_t * ctx,ism330dlc_func_cfg_en_t val)1302 int32_t ism330dlc_mem_bank_set(const stmdev_ctx_t *ctx,
1303 ism330dlc_func_cfg_en_t val)
1304 {
1305 ism330dlc_func_cfg_access_t func_cfg_access;
1306 int32_t ret;
1307 ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
1308 (uint8_t *)&func_cfg_access, 1);
1309
1310 if (ret == 0)
1311 {
1312 func_cfg_access.func_cfg_en = (uint8_t) val;
1313 ret = ism330dlc_write_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
1314 (uint8_t *)&func_cfg_access, 1);
1315 }
1316
1317 return ret;
1318 }
1319
1320 /**
1321 * @brief Enable access to the embedded functions/sensor hub configuration
1322 * registers[get]
1323 *
1324 * @param ctx Read / write interface definitions
1325 * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS
1326 * @retval Interface status (MANDATORY: return 0 -> no Error).
1327 *
1328 */
ism330dlc_mem_bank_get(const stmdev_ctx_t * ctx,ism330dlc_func_cfg_en_t * val)1329 int32_t ism330dlc_mem_bank_get(const stmdev_ctx_t *ctx,
1330 ism330dlc_func_cfg_en_t *val)
1331 {
1332 ism330dlc_func_cfg_access_t func_cfg_access;
1333 int32_t ret;
1334 ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS,
1335 (uint8_t *)&func_cfg_access, 1);
1336
1337 switch (func_cfg_access.func_cfg_en)
1338 {
1339 case ISM330DLC_USER_BANK:
1340 *val = ISM330DLC_USER_BANK;
1341 break;
1342
1343 default:
1344 *val = ISM330DLC_USER_BANK;
1345 break;
1346 }
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief Data-ready pulsed / letched mode[set]
1353 *
1354 * @param ctx Read / write interface definitions
1355 * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG
1356 * @retval Interface status (MANDATORY: return 0 -> no Error).
1357 *
1358 */
ism330dlc_data_ready_mode_set(const stmdev_ctx_t * ctx,ism330dlc_drdy_pulsed_t val)1359 int32_t ism330dlc_data_ready_mode_set(const stmdev_ctx_t *ctx,
1360 ism330dlc_drdy_pulsed_t val)
1361 {
1362 ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g;
1363 int32_t ret;
1364 ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
1365 (uint8_t *)&drdy_pulse_cfg_g, 1);
1366
1367 if (ret == 0)
1368 {
1369 drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
1370 ret = ism330dlc_write_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
1371 (uint8_t *)&drdy_pulse_cfg_g, 1);
1372 }
1373
1374 return ret;
1375 }
1376
1377 /**
1378 * @brief Data-ready pulsed / letched mode[get]
1379 *
1380 * @param ctx Read / write interface definitions
1381 * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG
1382 * @retval Interface status (MANDATORY: return 0 -> no Error).
1383 *
1384 */
ism330dlc_data_ready_mode_get(const stmdev_ctx_t * ctx,ism330dlc_drdy_pulsed_t * val)1385 int32_t ism330dlc_data_ready_mode_get(const stmdev_ctx_t *ctx,
1386 ism330dlc_drdy_pulsed_t *val)
1387 {
1388 ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g;
1389 int32_t ret;
1390 ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
1391 (uint8_t *)&drdy_pulse_cfg_g, 1);
1392
1393 switch (drdy_pulse_cfg_g.drdy_pulsed)
1394 {
1395 case ISM330DLC_DRDY_LATCHED:
1396 *val = ISM330DLC_DRDY_LATCHED;
1397 break;
1398
1399 case ISM330DLC_DRDY_PULSED:
1400 *val = ISM330DLC_DRDY_PULSED;
1401 break;
1402
1403 default:
1404 *val = ISM330DLC_DRDY_LATCHED;
1405 break;
1406 }
1407
1408 return ret;
1409 }
1410
1411 /**
1412 * @brief DeviceWhoamI.[get]
1413 *
1414 * @param ctx Read / write interface definitions
1415 * @param buff Buffer that stores data read
1416 * @retval Interface status (MANDATORY: return 0 -> no Error).
1417 *
1418 */
ism330dlc_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1419 int32_t ism330dlc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1420 {
1421 int32_t ret;
1422 ret = ism330dlc_read_reg(ctx, ISM330DLC_WHO_AM_I, buff, 1);
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief Software reset. Restore the default values in user registers[set]
1429 *
1430 * @param ctx Read / write interface definitions
1431 * @param val Change the values of sw_reset in reg CTRL3_C
1432 * @retval Interface status (MANDATORY: return 0 -> no Error).
1433 *
1434 */
ism330dlc_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1435 int32_t ism330dlc_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1436 {
1437 ism330dlc_ctrl3_c_t ctrl3_c;
1438 int32_t ret;
1439 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1440
1441 if (ret == 0)
1442 {
1443 ctrl3_c.sw_reset = val;
1444 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1445 }
1446
1447 return ret;
1448 }
1449
1450 /**
1451 * @brief Software reset. Restore the default values in user registers[get]
1452 *
1453 * @param ctx Read / write interface definitions
1454 * @param val Change the values of sw_reset in reg CTRL3_C
1455 * @retval Interface status (MANDATORY: return 0 -> no Error).
1456 *
1457 */
ism330dlc_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1458 int32_t ism330dlc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1459 {
1460 ism330dlc_ctrl3_c_t ctrl3_c;
1461 int32_t ret;
1462 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1463 *val = ctrl3_c.sw_reset;
1464
1465 return ret;
1466 }
1467
1468 /**
1469 * @brief Big/Little Endian Data selection.[set]
1470 *
1471 * @param ctx Read / write interface definitions
1472 * @param val Change the values of ble in reg CTRL3_C
1473 * @retval Interface status (MANDATORY: return 0 -> no Error).
1474 *
1475 */
ism330dlc_data_format_set(const stmdev_ctx_t * ctx,ism330dlc_ble_t val)1476 int32_t ism330dlc_data_format_set(const stmdev_ctx_t *ctx,
1477 ism330dlc_ble_t val)
1478 {
1479 ism330dlc_ctrl3_c_t ctrl3_c;
1480 int32_t ret;
1481 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1482
1483 if (ret == 0)
1484 {
1485 ctrl3_c.ble = (uint8_t) val;
1486 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1487 }
1488
1489 return ret;
1490 }
1491
1492 /**
1493 * @brief Big/Little Endian Data selection.[get]
1494 *
1495 * @param ctx Read / write interface definitions
1496 * @param val Get the values of ble in reg CTRL3_C
1497 * @retval Interface status (MANDATORY: return 0 -> no Error).
1498 *
1499 */
ism330dlc_data_format_get(const stmdev_ctx_t * ctx,ism330dlc_ble_t * val)1500 int32_t ism330dlc_data_format_get(const stmdev_ctx_t *ctx,
1501 ism330dlc_ble_t *val)
1502 {
1503 ism330dlc_ctrl3_c_t ctrl3_c;
1504 int32_t ret;
1505 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1506
1507 switch (ctrl3_c.ble)
1508 {
1509 case ISM330DLC_LSB_AT_LOW_ADD:
1510 *val = ISM330DLC_LSB_AT_LOW_ADD;
1511 break;
1512
1513 case ISM330DLC_MSB_AT_LOW_ADD:
1514 *val = ISM330DLC_MSB_AT_LOW_ADD;
1515 break;
1516
1517 default:
1518 *val = ISM330DLC_LSB_AT_LOW_ADD;
1519 break;
1520 }
1521
1522 return ret;
1523 }
1524
1525 /**
1526 * @brief Register address automatically incremented during a multiple byte
1527 * access with a serial interface.[set]
1528 *
1529 * @param ctx Read / write interface definitions
1530 * @param val Change the values of if_inc in reg CTRL3_C
1531 * @retval Interface status (MANDATORY: return 0 -> no Error).
1532 *
1533 */
ism330dlc_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1534 int32_t ism330dlc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1535 {
1536 ism330dlc_ctrl3_c_t ctrl3_c;
1537 int32_t ret;
1538 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1539
1540 if (ret == 0)
1541 {
1542 ctrl3_c.if_inc = val;
1543 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1544 }
1545
1546 return ret;
1547 }
1548
1549 /**
1550 * @brief Register address automatically incremented during a multiple byte
1551 * access with a serial interface.[get]
1552 *
1553 * @param ctx Read / write interface definitions
1554 * @param val Change the values of if_inc in reg CTRL3_C
1555 * @retval Interface status (MANDATORY: return 0 -> no Error).
1556 *
1557 */
ism330dlc_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1558 int32_t ism330dlc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1559 {
1560 ism330dlc_ctrl3_c_t ctrl3_c;
1561 int32_t ret;
1562 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1563 *val = ctrl3_c.if_inc;
1564
1565 return ret;
1566 }
1567
1568 /**
1569 * @brief Reboot memory content. Reload the calibration parameters.[set]
1570 *
1571 * @param ctx Read / write interface definitions
1572 * @param val Change the values of boot in reg CTRL3_C
1573 * @retval Interface status (MANDATORY: return 0 -> no Error).
1574 *
1575 */
ism330dlc_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1576 int32_t ism330dlc_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1577 {
1578 ism330dlc_ctrl3_c_t ctrl3_c;
1579 int32_t ret;
1580 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1581
1582 if (ret == 0)
1583 {
1584 ctrl3_c.boot = val;
1585 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1586 }
1587
1588 return ret;
1589 }
1590
1591 /**
1592 * @brief Reboot memory content. Reload the calibration parameters.[get]
1593 *
1594 * @param ctx Read / write interface definitions
1595 * @param val Change the values of boot in reg CTRL3_C
1596 * @retval Interface status (MANDATORY: return 0 -> no Error).
1597 *
1598 */
ism330dlc_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1599 int32_t ism330dlc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1600 {
1601 ism330dlc_ctrl3_c_t ctrl3_c;
1602 int32_t ret;
1603 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1604 *val = ctrl3_c.boot;
1605
1606 return ret;
1607 }
1608
1609 /**
1610 * @brief Linear acceleration sensor self-test enable.[set]
1611 *
1612 * @param ctx Read / write interface definitions
1613 * @param val Change the values of st_xl in reg CTRL5_C
1614 * @retval Interface status (MANDATORY: return 0 -> no Error).
1615 *
1616 */
ism330dlc_xl_self_test_set(const stmdev_ctx_t * ctx,ism330dlc_st_xl_t val)1617 int32_t ism330dlc_xl_self_test_set(const stmdev_ctx_t *ctx,
1618 ism330dlc_st_xl_t val)
1619 {
1620 ism330dlc_ctrl5_c_t ctrl5_c;
1621 int32_t ret;
1622 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1623
1624 if (ret == 0)
1625 {
1626 ctrl5_c.st_xl = (uint8_t) val;
1627 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1628 }
1629
1630 return ret;
1631 }
1632
1633 /**
1634 * @brief Linear acceleration sensor self-test enable.[get]
1635 *
1636 * @param ctx Read / write interface definitions
1637 * @param val Get the values of st_xl in reg CTRL5_C
1638 * @retval Interface status (MANDATORY: return 0 -> no Error).
1639 *
1640 */
ism330dlc_xl_self_test_get(const stmdev_ctx_t * ctx,ism330dlc_st_xl_t * val)1641 int32_t ism330dlc_xl_self_test_get(const stmdev_ctx_t *ctx,
1642 ism330dlc_st_xl_t *val)
1643 {
1644 ism330dlc_ctrl5_c_t ctrl5_c;
1645 int32_t ret;
1646 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1647
1648 switch (ctrl5_c.st_xl)
1649 {
1650 case ISM330DLC_XL_ST_DISABLE:
1651 *val = ISM330DLC_XL_ST_DISABLE;
1652 break;
1653
1654 case ISM330DLC_XL_ST_POSITIVE:
1655 *val = ISM330DLC_XL_ST_POSITIVE;
1656 break;
1657
1658 case ISM330DLC_XL_ST_NEGATIVE:
1659 *val = ISM330DLC_XL_ST_NEGATIVE;
1660 break;
1661
1662 default:
1663 *val = ISM330DLC_XL_ST_DISABLE;
1664 break;
1665 }
1666
1667 return ret;
1668 }
1669
1670 /**
1671 * @brief Angular rate sensor self-test enable.[set]
1672 *
1673 * @param ctx Read / write interface definitions
1674 * @param val Change the values of st_g in reg CTRL5_C
1675 * @retval Interface status (MANDATORY: return 0 -> no Error).
1676 *
1677 */
ism330dlc_gy_self_test_set(const stmdev_ctx_t * ctx,ism330dlc_st_g_t val)1678 int32_t ism330dlc_gy_self_test_set(const stmdev_ctx_t *ctx,
1679 ism330dlc_st_g_t val)
1680 {
1681 ism330dlc_ctrl5_c_t ctrl5_c;
1682 int32_t ret;
1683 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1684
1685 if (ret == 0)
1686 {
1687 ctrl5_c.st_g = (uint8_t) val;
1688 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1689 }
1690
1691 return ret;
1692 }
1693
1694 /**
1695 * @brief Angular rate sensor self-test enable.[get]
1696 *
1697 * @param ctx Read / write interface definitions
1698 * @param val Get the values of st_g in reg CTRL5_C
1699 * @retval Interface status (MANDATORY: return 0 -> no Error).
1700 *
1701 */
ism330dlc_gy_self_test_get(const stmdev_ctx_t * ctx,ism330dlc_st_g_t * val)1702 int32_t ism330dlc_gy_self_test_get(const stmdev_ctx_t *ctx,
1703 ism330dlc_st_g_t *val)
1704 {
1705 ism330dlc_ctrl5_c_t ctrl5_c;
1706 int32_t ret;
1707 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1708
1709 switch (ctrl5_c.st_g)
1710 {
1711 case ISM330DLC_GY_ST_DISABLE:
1712 *val = ISM330DLC_GY_ST_DISABLE;
1713 break;
1714
1715 case ISM330DLC_GY_ST_POSITIVE:
1716 *val = ISM330DLC_GY_ST_POSITIVE;
1717 break;
1718
1719 case ISM330DLC_GY_ST_NEGATIVE:
1720 *val = ISM330DLC_GY_ST_NEGATIVE;
1721 break;
1722
1723 default:
1724 *val = ISM330DLC_GY_ST_DISABLE;
1725 break;
1726 }
1727
1728 return ret;
1729 }
1730
1731 /**
1732 * @}
1733 *
1734 */
1735
1736 /**
1737 * @defgroup ISM330DLC_filters
1738 * @brief This section group all the functions concerning the filters
1739 * configuration that impact both accelerometer and gyro.
1740 * @{
1741 *
1742 */
1743
1744 /**
1745 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1746 * (XL and Gyro independently masked).[set]
1747 *
1748 * @param ctx Read / write interface definitions
1749 * @param val Change the values of drdy_mask in reg CTRL4_C
1750 * @retval Interface status (MANDATORY: return 0 -> no Error).
1751 *
1752 */
ism330dlc_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)1753 int32_t ism330dlc_filter_settling_mask_set(const stmdev_ctx_t *ctx,
1754 uint8_t val)
1755 {
1756 ism330dlc_ctrl4_c_t ctrl4_c;
1757 int32_t ret;
1758 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1759
1760 if (ret == 0)
1761 {
1762 ctrl4_c.drdy_mask = val;
1763 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1764 }
1765
1766 return ret;
1767 }
1768
1769 /**
1770 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1771 * (XL and Gyro independently masked).[get]
1772 *
1773 * @param ctx Read / write interface definitions
1774 * @param val Change the values of drdy_mask in reg CTRL4_C
1775 * @retval Interface status (MANDATORY: return 0 -> no Error).
1776 *
1777 */
ism330dlc_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)1778 int32_t ism330dlc_filter_settling_mask_get(const stmdev_ctx_t *ctx,
1779 uint8_t *val)
1780 {
1781 ism330dlc_ctrl4_c_t ctrl4_c;
1782 int32_t ret;
1783 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1784 *val = ctrl4_c.drdy_mask;
1785
1786 return ret;
1787 }
1788
1789 /**
1790 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1791 * functions.[set]
1792 *
1793 * @param ctx Read / write interface definitions
1794 * @param val Change the values of slope_fds in reg TAP_CFG
1795 * @retval Interface status (MANDATORY: return 0 -> no Error).
1796 *
1797 */
ism330dlc_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,ism330dlc_slope_fds_t val)1798 int32_t ism330dlc_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
1799 ism330dlc_slope_fds_t val)
1800 {
1801 ism330dlc_tap_cfg_t tap_cfg;
1802 int32_t ret;
1803 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1804
1805 if (ret == 0)
1806 {
1807 tap_cfg.slope_fds = (uint8_t) val;
1808 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1809 }
1810
1811 return ret;
1812 }
1813
1814 /**
1815 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1816 * functions.[get]
1817 *
1818 * @param ctx Read / write interface definitions
1819 * @param val Get the values of slope_fds in reg TAP_CFG
1820 * @retval Interface status (MANDATORY: return 0 -> no Error).
1821 *
1822 */
ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,ism330dlc_slope_fds_t * val)1823 int32_t ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
1824 ism330dlc_slope_fds_t *val)
1825 {
1826 ism330dlc_tap_cfg_t tap_cfg;
1827 int32_t ret;
1828 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1829
1830 switch (tap_cfg.slope_fds)
1831 {
1832 case ISM330DLC_USE_SLOPE:
1833 *val = ISM330DLC_USE_SLOPE;
1834 break;
1835
1836 case ISM330DLC_USE_HPF:
1837 *val = ISM330DLC_USE_HPF;
1838 break;
1839
1840 default:
1841 *val = ISM330DLC_USE_SLOPE;
1842 break;
1843 }
1844
1845 return ret;
1846 }
1847
1848 /**
1849 * @}
1850 *
1851 */
1852
1853 /**
1854 * @defgroup ISM330DLC_accelerometer_filters
1855 * @brief This section group all the functions concerning the filters
1856 * configuration that impact accelerometer in every mode.
1857 * @{
1858 *
1859 */
1860
1861 /**
1862 * @brief Accelerometer analog chain bandwidth selection (only for
1863 * accelerometer ODR ≥ 1.67 kHz).[set]
1864 *
1865 * @param ctx Read / write interface definitions
1866 * @param val Change the values of bw0_xl in reg CTRL1_XL
1867 * @retval Interface status (MANDATORY: return 0 -> no Error).
1868 *
1869 */
ism330dlc_xl_filter_analog_set(const stmdev_ctx_t * ctx,ism330dlc_bw0_xl_t val)1870 int32_t ism330dlc_xl_filter_analog_set(const stmdev_ctx_t *ctx,
1871 ism330dlc_bw0_xl_t val)
1872 {
1873 ism330dlc_ctrl1_xl_t ctrl1_xl;
1874 int32_t ret;
1875 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
1876 (uint8_t *)&ctrl1_xl, 1);
1877
1878 if (ret == 0)
1879 {
1880 ctrl1_xl.bw0_xl = (uint8_t) val;
1881 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
1882 (uint8_t *)&ctrl1_xl, 1);
1883 }
1884
1885 return ret;
1886 }
1887
1888 /**
1889 * @brief Accelerometer analog chain bandwidth selection (only for
1890 * accelerometer ODR ≥ 1.67 kHz).[get]
1891 *
1892 * @param ctx Read / write interface definitions
1893 * @param val Get the values of bw0_xl in reg CTRL1_XL
1894 * @retval Interface status (MANDATORY: return 0 -> no Error).
1895 *
1896 */
ism330dlc_xl_filter_analog_get(const stmdev_ctx_t * ctx,ism330dlc_bw0_xl_t * val)1897 int32_t ism330dlc_xl_filter_analog_get(const stmdev_ctx_t *ctx,
1898 ism330dlc_bw0_xl_t *val)
1899 {
1900 ism330dlc_ctrl1_xl_t ctrl1_xl;
1901 int32_t ret;
1902 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
1903 (uint8_t *)&ctrl1_xl, 1);
1904
1905 switch (ctrl1_xl.bw0_xl)
1906 {
1907 case ISM330DLC_XL_ANA_BW_1k5Hz:
1908 *val = ISM330DLC_XL_ANA_BW_1k5Hz;
1909 break;
1910
1911 case ISM330DLC_XL_ANA_BW_400Hz:
1912 *val = ISM330DLC_XL_ANA_BW_400Hz;
1913 break;
1914
1915 default:
1916 *val = ISM330DLC_XL_ANA_BW_1k5Hz;
1917 break;
1918 }
1919
1920 return ret;
1921 }
1922
1923 /**
1924 * @}
1925 *
1926 */
1927
1928 /**
1929 * @defgroup ISM330DLC_accelerometer_filters
1930 * @brief This section group all the functions concerning the filters
1931 * configuration that impact accelerometer.
1932 * @{
1933 *
1934 */
1935
1936 /**
1937 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is
1938 * not used.[set]
1939 *
1940 * @param ctx Read / write interface definitions
1941 * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL
1942 * @retval Interface status (MANDATORY: return 0 -> no Error).
1943 *
1944 */
ism330dlc_xl_lp1_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_lpf1_bw_sel_t val)1945 int32_t ism330dlc_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
1946 ism330dlc_lpf1_bw_sel_t val)
1947 {
1948 ism330dlc_ctrl1_xl_t ctrl1_xl;
1949 ism330dlc_ctrl8_xl_t ctrl8_xl;
1950 int32_t ret;
1951 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
1952 (uint8_t *)&ctrl1_xl, 1);
1953
1954 if (ret == 0)
1955 {
1956 ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
1957 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
1958 (uint8_t *)&ctrl1_xl, 1);
1959
1960 if (ret == 0)
1961 {
1962 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
1963 (uint8_t *)&ctrl8_xl, 1);
1964
1965 if (ret == 0)
1966 {
1967 ctrl8_xl.lpf2_xl_en = 0;
1968 ctrl8_xl.hp_slope_xl_en = 0;
1969 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
1970 (uint8_t *)&ctrl8_xl, 1);
1971 }
1972 }
1973 }
1974
1975 return ret;
1976 }
1977
1978 /**
1979 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2
1980 * is not used.[get]
1981 *
1982 * @param ctx Read / write interface definitions
1983 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
1984 * @retval Interface status (MANDATORY: return 0 -> no Error).
1985 *
1986 */
ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_lpf1_bw_sel_t * val)1987 int32_t ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
1988 ism330dlc_lpf1_bw_sel_t *val)
1989 {
1990 ism330dlc_ctrl1_xl_t ctrl1_xl;
1991 ism330dlc_ctrl8_xl_t ctrl8_xl;
1992 int32_t ret;
1993 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
1994 (uint8_t *)&ctrl8_xl, 1);
1995
1996 if (ret == 0)
1997 {
1998 if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
1999 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2000 {
2001 *val = ISM330DLC_XL_LP1_NA;
2002 }
2003
2004 else
2005 {
2006 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
2007 (uint8_t *)&ctrl1_xl, 1);
2008
2009 switch (ctrl1_xl.lpf1_bw_sel)
2010 {
2011 case ISM330DLC_XL_LP1_ODR_DIV_2:
2012 *val = ISM330DLC_XL_LP1_ODR_DIV_2;
2013 break;
2014
2015 case ISM330DLC_XL_LP1_ODR_DIV_4:
2016 *val = ISM330DLC_XL_LP1_ODR_DIV_4;
2017 break;
2018
2019 default:
2020 *val = ISM330DLC_XL_LP1_NA;
2021 break;
2022 }
2023 }
2024 }
2025
2026 return ret;
2027 }
2028
2029 /**
2030 * @brief LPF2 on outputs[set]
2031 *
2032 * @param ctx Read / write interface definitions
2033 * @param val Change the values of input_composite in reg CTRL8_XL
2034 * @retval Interface status (MANDATORY: return 0 -> no Error).
2035 *
2036 */
ism330dlc_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_input_composite_t val)2037 int32_t ism330dlc_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
2038 ism330dlc_input_composite_t val)
2039 {
2040 ism330dlc_ctrl8_xl_t ctrl8_xl;
2041 int32_t ret;
2042 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2043 (uint8_t *)&ctrl8_xl, 1);
2044
2045 if (ret == 0)
2046 {
2047 ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
2048 ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
2049 ctrl8_xl.lpf2_xl_en = 1;
2050 ctrl8_xl.hp_slope_xl_en = 0;
2051 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
2052 (uint8_t *)&ctrl8_xl, 1);
2053 }
2054
2055 return ret;
2056 }
2057
2058 /**
2059 * @brief LPF2 on outputs[get]
2060 *
2061 * @param ctx Read / write interface definitions
2062 * @param val Get the values of input_composite in reg CTRL8_XL
2063 * @retval Interface status (MANDATORY: return 0 -> no Error).
2064 *
2065 */
ism330dlc_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_input_composite_t * val)2066 int32_t ism330dlc_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
2067 ism330dlc_input_composite_t *val)
2068 {
2069 ism330dlc_ctrl8_xl_t ctrl8_xl;
2070 int32_t ret;
2071 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2072 (uint8_t *)&ctrl8_xl, 1);
2073
2074 if (ret == 0)
2075 {
2076 if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
2077 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2078 {
2079 *val = ISM330DLC_XL_LP_NA;
2080 }
2081
2082 else
2083 {
2084 switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
2085 {
2086 case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50:
2087 *val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50;
2088 break;
2089
2090 case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100:
2091 *val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100;
2092 break;
2093
2094 case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9:
2095 *val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9;
2096 break;
2097
2098 case ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_400:
2099 *val = ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_400;
2100 break;
2101
2102 case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_50:
2103 *val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_50;
2104 break;
2105
2106 case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_100:
2107 *val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_100;
2108 break;
2109
2110 case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_9:
2111 *val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_9;
2112 break;
2113
2114 case ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400:
2115 *val = ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400;
2116 break;
2117
2118 default:
2119 *val = ISM330DLC_XL_LP_NA;
2120 break;
2121 }
2122 }
2123 }
2124
2125 return ret;
2126 }
2127
2128 /**
2129 * @brief Enable HP filter reference mode.[set]
2130 *
2131 * @param ctx Read / write interface definitions
2132 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2133 * @retval Interface status (MANDATORY: return 0 -> no Error).
2134 *
2135 */
ism330dlc_xl_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2136 int32_t ism330dlc_xl_reference_mode_set(const stmdev_ctx_t *ctx,
2137 uint8_t val)
2138 {
2139 ism330dlc_ctrl8_xl_t ctrl8_xl;
2140 int32_t ret;
2141 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2142 (uint8_t *)&ctrl8_xl, 1);
2143
2144 if (ret == 0)
2145 {
2146 ctrl8_xl.hp_ref_mode = val;
2147 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
2148 (uint8_t *)&ctrl8_xl, 1);
2149 }
2150
2151 return ret;
2152 }
2153
2154 /**
2155 * @brief Enable HP filter reference mode.[get]
2156 *
2157 * @param ctx Read / write interface definitions
2158 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2159 * @retval Interface status (MANDATORY: return 0 -> no Error).
2160 *
2161 */
ism330dlc_xl_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2162 int32_t ism330dlc_xl_reference_mode_get(const stmdev_ctx_t *ctx,
2163 uint8_t *val)
2164 {
2165 ism330dlc_ctrl8_xl_t ctrl8_xl;
2166 int32_t ret;
2167 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2168 (uint8_t *)&ctrl8_xl, 1);
2169 *val = ctrl8_xl.hp_ref_mode;
2170
2171 return ret;
2172 }
2173
2174 /**
2175 * @brief High pass/Slope on outputs.[set]
2176 *
2177 * @param ctx Read / write interface definitions
2178 * @param val Change the values of hpcf_xl in reg CTRL8_XL
2179 * @retval Interface status (MANDATORY: return 0 -> no Error).
2180 *
2181 */
ism330dlc_xl_hp_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_hpcf_xl_t val)2182 int32_t ism330dlc_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx,
2183 ism330dlc_hpcf_xl_t val)
2184 {
2185 ism330dlc_ctrl8_xl_t ctrl8_xl;
2186 int32_t ret;
2187 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2188 (uint8_t *)&ctrl8_xl, 1);
2189
2190 if (ret == 0)
2191 {
2192 ctrl8_xl.input_composite = 0;
2193 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
2194 ctrl8_xl.hp_slope_xl_en = 1;
2195 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
2196 (uint8_t *)&ctrl8_xl, 1);
2197 }
2198
2199 return ret;
2200 }
2201
2202 /**
2203 * @brief High pass/Slope on outputs.[get]
2204 *
2205 * @param ctx Read / write interface definitions
2206 * @param val Get the values of hpcf_xl in reg CTRL8_XL
2207 * @retval Interface status (MANDATORY: return 0 -> no Error).
2208 *
2209 */
ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_hpcf_xl_t * val)2210 int32_t ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx,
2211 ism330dlc_hpcf_xl_t *val)
2212 {
2213 ism330dlc_ctrl8_xl_t ctrl8_xl;
2214 int32_t ret;
2215 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2216 (uint8_t *)&ctrl8_xl, 1);
2217
2218 if (ctrl8_xl.hp_slope_xl_en == 0x00U)
2219 {
2220 *val = ISM330DLC_XL_HP_NA;
2221 }
2222
2223 switch (ctrl8_xl.hpcf_xl)
2224 {
2225 case ISM330DLC_XL_HP_ODR_DIV_4:
2226 *val = ISM330DLC_XL_HP_ODR_DIV_4;
2227 break;
2228
2229 case ISM330DLC_XL_HP_ODR_DIV_100:
2230 *val = ISM330DLC_XL_HP_ODR_DIV_100;
2231 break;
2232
2233 case ISM330DLC_XL_HP_ODR_DIV_9:
2234 *val = ISM330DLC_XL_HP_ODR_DIV_9;
2235 break;
2236
2237 case ISM330DLC_XL_HP_ODR_DIV_400:
2238 *val = ISM330DLC_XL_HP_ODR_DIV_400;
2239 break;
2240
2241 default:
2242 *val = ISM330DLC_XL_HP_NA;
2243 break;
2244 }
2245
2246 return ret;
2247 }
2248
2249 /**
2250 * @}
2251 *
2252 */
2253
2254 /**
2255 * @defgroup ISM330DLC_accelerometer_filters_mode:4
2256 * @brief This section group all the functions concerning the filters
2257 * configuration that impact accelerometer when mode 4
2258 * (accelerometer on aux interface enable).
2259 * @{
2260 *
2261 */
2262
2263 /**
2264 * @brief Accelerometer digital LPF (LPF1) bandwidth selection. Only
2265 * for mode 4.[set]
2266 *
2267 * @param ctx Read / write interface definitions
2268 * @param val change the values of lpf1_bw_sel in reg CTRL1_XL
2269 * @retval Interface status (MANDATORY: return 0 -> no Error).
2270 *
2271 */
ism330dlc_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_ui_lpf1_bw_sel_t val)2272 int32_t ism330dlc_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2273 ism330dlc_ui_lpf1_bw_sel_t val)
2274 {
2275 ism330dlc_ctrl1_xl_t ctrl1_xl;
2276 ism330dlc_ctrl8_xl_t ctrl8_xl;
2277 int32_t ret;
2278 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
2279 (uint8_t *)&ctrl1_xl, 1);
2280
2281 if (ret == 0)
2282 {
2283 ctrl1_xl.lpf1_bw_sel = (uint8_t)val;
2284 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL,
2285 (uint8_t *)&ctrl1_xl, 1);
2286 }
2287
2288 if (ret == 0)
2289 {
2290 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2291 (uint8_t *)&ctrl8_xl, 1);
2292 }
2293
2294 if (ret == 0)
2295 {
2296 ctrl8_xl.hp_slope_xl_en = 0;
2297 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
2298 (uint8_t *)&ctrl8_xl, 1);
2299 }
2300
2301 return ret;
2302 }
2303
2304 /**
2305 * @brief Accelerometer digital LPF (LPF1) bandwidth selection. Only
2306 * for mode 4.[get]
2307 *
2308 * @param ctx Read / write interface definitions
2309 * @param val Get the values of lpf1_bw_sel in
2310 * reg CTRL1_XL
2311 * @retval Interface status (MANDATORY: return 0 -> no Error).
2312 *
2313 */
ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_ui_lpf1_bw_sel_t * val)2314 int32_t ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2315 ism330dlc_ui_lpf1_bw_sel_t *val)
2316 {
2317 ism330dlc_ctrl1_xl_t ctrl1_xl;
2318 ism330dlc_ctrl8_xl_t ctrl8_xl;
2319 int32_t ret;
2320 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
2321 (uint8_t *)&ctrl8_xl, 1);
2322
2323 if (ret == 0)
2324 {
2325 if (ctrl8_xl.hp_slope_xl_en == PROPERTY_DISABLE)
2326 {
2327 *val = ISM330DLC_XL_UI_LP1_NA;
2328 }
2329
2330 else
2331 {
2332 }
2333
2334 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL,
2335 (uint8_t *)&ctrl1_xl, 1);
2336
2337 switch (ctrl1_xl.lpf1_bw_sel)
2338 {
2339 case ISM330DLC_XL_UI_LP1_ODR_DIV_2:
2340 *val = ISM330DLC_XL_UI_LP1_ODR_DIV_2;
2341 break;
2342
2343 case ISM330DLC_XL_UI_LP1_ODR_DIV_4:
2344 *val = ISM330DLC_XL_UI_LP1_ODR_DIV_4;
2345 break;
2346
2347 default:
2348 *val = ISM330DLC_XL_UI_LP1_NA;
2349 break;
2350 }
2351 }
2352
2353 return ret;
2354 }
2355
2356 /**
2357 * @brief xl_ui_slope: Slope filter on outputs[set]
2358 *
2359 * @param ctx Read / write interface definitions
2360 * @param val change the values of hp_slope_xl_en in reg CTRL8_XL
2361 * @retval Interface status (MANDATORY: return 0 -> no Error).
2362 *
2363 */
ism330dlc_xl_ui_slope_set(const stmdev_ctx_t * ctx,uint8_t val)2364 int32_t ism330dlc_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val)
2365 {
2366 ism330dlc_ctrl8_xl_t reg;
2367 int32_t ret;
2368 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
2369
2370 if (ret == 0)
2371 {
2372 reg.hp_slope_xl_en = val;
2373 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
2374 }
2375
2376 return ret;
2377 }
2378
2379 /**
2380 * @brief xl_ui_slope: Slope filter on outputs[get]
2381 *
2382 * @param ctx Read / write interface definitions
2383 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2384 * @retval Interface status (MANDATORY: return 0 -> no Error).
2385 *
2386 */
ism330dlc_xl_ui_slope_get(const stmdev_ctx_t * ctx,uint8_t * val)2387 int32_t ism330dlc_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val)
2388 {
2389 ism330dlc_ctrl8_xl_t reg;
2390 int32_t ret;
2391 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1);
2392 *val = reg.hp_slope_xl_en;
2393
2394 return ret;
2395 }
2396
2397 /**
2398 * @brief xl_aux_lp_bandwidth: [set]
2399 *
2400 * @param ctx Read / write interface definitions
2401 * @param val change the values of filter_xl_conf_ois in reg CTRL3_OIS.
2402 *
2403 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2404 * LIGHT 636 Hz 2.96°
2405 * NORMAL 295 Hz 5.12°
2406 * STRONG 140 Hz 9.39°
2407 * AGGRESSIVE 68.2 Hz 17.6°
2408 *
2409 * Cut off feq [ODR UI ≤ 800 Hz ]
2410 * LIGHT 329 Hz 5.08°
2411 * NORMAL 222 Hz 7.23°
2412 * STRONG 128 Hz 11.5°
2413 * AGGRESSIVE 66.5 Hz 19.7°
2414 *
2415 * @retval Interface status (MANDATORY: return 0 -> no Error).
2416 *
2417 */
ism330dlc_xl_aux_lp_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_filter_xl_conf_ois_t val)2418 int32_t ism330dlc_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx,
2419 ism330dlc_filter_xl_conf_ois_t val)
2420 {
2421 ism330dlc_ctrl3_ois_t reg;
2422 int32_t ret;
2423 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
2424
2425 if (ret == 0)
2426 {
2427 reg.filter_xl_conf_ois = (uint8_t)val;
2428 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
2429 }
2430
2431 return ret;
2432 }
2433
2434 /**
2435 * @brief xl_aux_lp_bandwidth: [get]
2436 *
2437 * @param ctx Read / write interface definitions
2438 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
2439 *
2440 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2441 * LIGHT 636 Hz 2.96°
2442 * NORMAL 295 Hz 5.12°
2443 * STRONG 140 Hz 9.39°
2444 * AGGRESSIVE 68.2 Hz 17.6°
2445 *
2446 * Cut off feq [ODR UI ≤ 800 Hz ]
2447 * LIGHT 329 Hz 5.08°
2448 * NORMAL 222 Hz 7.23°
2449 * STRONG 128 Hz 11.5°
2450 * AGGRESSIVE 66.5 Hz 19.7°
2451 *
2452 * @retval Interface status (MANDATORY: return 0 -> no Error).
2453 *
2454 */
ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_filter_xl_conf_ois_t * val)2455 int32_t ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx,
2456 ism330dlc_filter_xl_conf_ois_t *val)
2457 {
2458 ism330dlc_ctrl3_ois_t reg;
2459 int32_t ret;
2460 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
2461
2462 switch (reg.filter_xl_conf_ois)
2463 {
2464 case ISM330DLC_AUX_LP_LIGHT:
2465 *val = ISM330DLC_AUX_LP_LIGHT;
2466 break;
2467
2468 case ISM330DLC_AUX_LP_NORMAL:
2469 *val = ISM330DLC_AUX_LP_NORMAL;
2470 break;
2471
2472 case ISM330DLC_AUX_LP_STRONG:
2473 *val = ISM330DLC_AUX_LP_STRONG;
2474 break;
2475
2476 case ISM330DLC_AUX_LP_AGGRESSIVE:
2477 *val = ISM330DLC_AUX_LP_AGGRESSIVE;
2478 break;
2479
2480 default:
2481 *val = ISM330DLC_AUX_LP_LIGHT;
2482 break;
2483 }
2484
2485 return ret;
2486 }
2487
2488 /**
2489 * @}
2490 *
2491 */
2492
2493 /**
2494 * @defgroup ISM330DLC_gyroscope_filters_mode:1,2
2495 * @brief This section group all the functions concerning the filters
2496 * configuration that impact gyroscope mode 1, 2
2497 * (gyroscope on aux interface disable).
2498 * @{
2499 *
2500 */
2501
2502 /**
2503 * @brief Gyroscope low pass path bandwidth.[set]
2504 *
2505 * @param ctx Read / write interface definitions
2506 * @param val gyroscope filtering chain configuration.
2507 * @retval Interface status (MANDATORY: return 0 -> no Error).
2508 *
2509 */
ism330dlc_gy_band_pass_set(const stmdev_ctx_t * ctx,ism330dlc_lpf1_sel_g_t val)2510 int32_t ism330dlc_gy_band_pass_set(const stmdev_ctx_t *ctx,
2511 ism330dlc_lpf1_sel_g_t val)
2512 {
2513 ism330dlc_ctrl4_c_t ctrl4_c;
2514 ism330dlc_ctrl6_c_t ctrl6_c;
2515 ism330dlc_ctrl7_g_t ctrl7_g;
2516 int32_t ret;
2517 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2518
2519 if (ret == 0)
2520 {
2521 ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
2522 ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2523 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2524
2525 if (ret == 0)
2526 {
2527 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2528
2529 if (ret == 0)
2530 {
2531 ctrl6_c.ftype = (uint8_t)val & 0x03U;
2532 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C,
2533 (uint8_t *)&ctrl6_c, 1);
2534
2535 if (ret == 0)
2536 {
2537 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C,
2538 (uint8_t *)&ctrl4_c, 1);
2539
2540 if (ret == 0)
2541 {
2542 ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
2543 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C,
2544 (uint8_t *)&ctrl4_c, 1);
2545 }
2546 }
2547 }
2548 }
2549 }
2550
2551 return ret;
2552 }
2553
2554 /**
2555 * @brief Gyroscope low pass path bandwidth.[get]
2556 *
2557 * @param ctx Read / write interface definitions
2558 * @param val gyroscope filtering chain
2559 * @retval Interface status (MANDATORY: return 0 -> no Error).
2560 *
2561 */
ism330dlc_gy_band_pass_get(const stmdev_ctx_t * ctx,ism330dlc_lpf1_sel_g_t * val)2562 int32_t ism330dlc_gy_band_pass_get(const stmdev_ctx_t *ctx,
2563 ism330dlc_lpf1_sel_g_t *val)
2564 {
2565 ism330dlc_ctrl4_c_t ctrl4_c;
2566 ism330dlc_ctrl6_c_t ctrl6_c;
2567 ism330dlc_ctrl7_g_t ctrl7_g;
2568 int32_t ret;
2569 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2570
2571 if (ret == 0)
2572 {
2573 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2574
2575 if (ret == 0)
2576 {
2577 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2578
2579 switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
2580 (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
2581 {
2582 case ISM330DLC_HP_16mHz_LP2:
2583 *val = ISM330DLC_HP_16mHz_LP2;
2584 break;
2585
2586 case ISM330DLC_HP_65mHz_LP2:
2587 *val = ISM330DLC_HP_65mHz_LP2;
2588 break;
2589
2590 case ISM330DLC_HP_260mHz_LP2:
2591 *val = ISM330DLC_HP_260mHz_LP2;
2592 break;
2593
2594 case ISM330DLC_HP_1Hz04_LP2:
2595 *val = ISM330DLC_HP_1Hz04_LP2;
2596 break;
2597
2598 case ISM330DLC_HP_DISABLE_LP1_LIGHT:
2599 *val = ISM330DLC_HP_DISABLE_LP1_LIGHT;
2600 break;
2601
2602 case ISM330DLC_HP_DISABLE_LP1_NORMAL:
2603 *val = ISM330DLC_HP_DISABLE_LP1_NORMAL;
2604 break;
2605
2606 case ISM330DLC_HP_DISABLE_LP_STRONG:
2607 *val = ISM330DLC_HP_DISABLE_LP_STRONG;
2608 break;
2609
2610 case ISM330DLC_HP_DISABLE_LP1_AGGRESSIVE:
2611 *val = ISM330DLC_HP_DISABLE_LP1_AGGRESSIVE;
2612 break;
2613
2614 case ISM330DLC_HP_16mHz_LP1_LIGHT:
2615 *val = ISM330DLC_HP_16mHz_LP1_LIGHT;
2616 break;
2617
2618 case ISM330DLC_HP_65mHz_LP1_NORMAL:
2619 *val = ISM330DLC_HP_65mHz_LP1_NORMAL;
2620 break;
2621
2622 case ISM330DLC_HP_260mHz_LP1_STRONG:
2623 *val = ISM330DLC_HP_260mHz_LP1_STRONG;
2624 break;
2625
2626 case ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE:
2627 *val = ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE;
2628 break;
2629
2630 default:
2631 *val = ISM330DLC_HP_16mHz_LP2;
2632 break;
2633 }
2634 }
2635 }
2636
2637 return ret;
2638 }
2639
2640 /**
2641 * @}
2642 *
2643 */
2644
2645 /**
2646 * @defgroup ISM330DLC_gyroscope_filters_mode:3,4
2647 * @brief This section group all the functions concerning the filters
2648 * configuration that impact gyroscope when mode 3, 4
2649 * (gyroscope on aux interface enable).
2650 * @{
2651 *
2652 */
2653
2654 /**
2655 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G in
2656 * CTRL7_G (16h) is set to '0'.[set]
2657 *
2658 * @param ctx Read / write interface definitions
2659 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2660 * @retval Interface status (MANDATORY: return 0 -> no Error).
2661 *
2662 */
ism330dlc_gy_ui_high_pass_set(const stmdev_ctx_t * ctx,uint8_t val)2663 int32_t ism330dlc_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val)
2664 {
2665 ism330dlc_ctrl7_g_t reg;
2666 int32_t ret;
2667 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
2668
2669 if (ret == 0)
2670 {
2671 reg.hp_en_g = val;
2672 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
2673 }
2674
2675 return ret;
2676 }
2677
2678 /**
2679 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G in
2680 * CTRL7_G (16h) is set to '0'.[get]
2681 *
2682 * @param ctx Read / write interface definitions
2683 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2684 * @retval Interface status (MANDATORY: return 0 -> no Error).
2685 *
2686 */
ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t * ctx,uint8_t * val)2687 int32_t ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val)
2688 {
2689 ism330dlc_ctrl7_g_t reg;
2690 int32_t ret;
2691 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1);
2692 *val = reg.hp_en_g;
2693
2694 return ret;
2695 }
2696
2697
2698 /**
2699 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G in
2700 * CTRL7_G (16h) is set to '0'.[set]
2701 *
2702 * @param ctx Read / write interface definitions
2703 * @param val gyroscope aux (ois) filtering chain configuration in
2704 * Mode: 3, 4.
2705 * @retval Interface status (MANDATORY: return 0 -> no Error).
2706 *
2707 */
ism330dlc_gy_aux_bandwidth_set(const stmdev_ctx_t * ctx,ism330dlc_hp_en_ois_t val)2708 int32_t ism330dlc_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx,
2709 ism330dlc_hp_en_ois_t val)
2710 {
2711 ism330dlc_ctrl7_g_t ctrl7_g;
2712 ism330dlc_ctrl2_ois_t ctrl2_ois;
2713 int32_t ret;
2714 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2715
2716 if (ret == 0)
2717 {
2718 ctrl7_g.hp_en_g = 0;
2719 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2720 }
2721
2722 if (ret == 0)
2723 {
2724 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS,
2725 (uint8_t *)&ctrl2_ois, 1);
2726 }
2727
2728 if (ret == 0)
2729 {
2730 ctrl2_ois.ftype_ois = (uint8_t)val & 0x03U;
2731 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x80U) >> 7;
2732 ctrl2_ois.hpm_ois = ((uint8_t)val & 0x30U) >> 4;
2733 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL2_OIS,
2734 (uint8_t *)&ctrl2_ois, 1);
2735 }
2736
2737 return ret;
2738 }
2739
2740 /**
2741 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G in
2742 * CTRL7_G (16h) is set to '0'.[get]
2743 *
2744 * @param ctx Read / write interface definitions
2745 * @param val gyroscope aux (ois) filtering chain configuration in
2746 * Mode: 3, 4.
2747 * @retval Interface status (MANDATORY: return 0 -> no Error).
2748 *
2749 */
ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t * ctx,ism330dlc_hp_en_ois_t * val)2750 int32_t ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx,
2751 ism330dlc_hp_en_ois_t *val)
2752 {
2753 ism330dlc_ctrl2_ois_t reg;
2754 int32_t ret;
2755 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS, (uint8_t *)®, 1);
2756
2757 switch ((reg.hp_en_ois << 7) + (reg.hpm_ois << 4) +
2758 reg.ftype_ois)
2759 {
2760 case ISM330DLC_HP_DISABLE_LP_173Hz:
2761 *val = ISM330DLC_HP_DISABLE_LP_173Hz;
2762 break;
2763
2764 case ISM330DLC_HP_DISABLE_LP_237Hz:
2765 *val = ISM330DLC_HP_DISABLE_LP_237Hz;
2766 break;
2767
2768 case ISM330DLC_HP_DISABLE_LP_351Hz:
2769 *val = ISM330DLC_HP_DISABLE_LP_351Hz;
2770 break;
2771
2772 case ISM330DLC_HP_DISABLE_LP_937Hz:
2773 *val = ISM330DLC_HP_DISABLE_LP_937Hz;
2774 break;
2775
2776 case ISM330DLC_HP_16mHz_LP_173Hz:
2777 *val = ISM330DLC_HP_16mHz_LP_173Hz;
2778 break;
2779
2780 case ISM330DLC_HP_65mHz_LP_237Hz:
2781 *val = ISM330DLC_HP_65mHz_LP_237Hz;
2782 break;
2783
2784 case ISM330DLC_HP_260mHz_LP_351Hz:
2785 *val = ISM330DLC_HP_260mHz_LP_351Hz;
2786 break;
2787
2788 case ISM330DLC_HP_1Hz04_LP_937Hz:
2789 *val = ISM330DLC_HP_1Hz04_LP_937Hz;
2790 break;
2791
2792 default:
2793 *val = ISM330DLC_HP_DISABLE_LP_173Hz;
2794 break;
2795 }
2796
2797 return ret;
2798 }
2799
2800 /**
2801 * @}
2802 *
2803 */
2804
2805 /**
2806 * @defgroup ISM330DLC_Auxiliary_interface
2807 * @brief This section groups all the functions concerning
2808 * auxiliary interface.
2809 * @{
2810 *
2811 */
2812
2813 /**
2814 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
2815 *
2816 * @param ctx Read / write interface definitions
2817 * @param val registers STATUS_SPIAUX.
2818 * @retval Interface status (MANDATORY: return 0 -> no Error).
2819 *
2820 */
ism330dlc_aux_status_reg_get(const stmdev_ctx_t * ctx,ism330dlc_status_spiaux_t * val)2821 int32_t ism330dlc_aux_status_reg_get(const stmdev_ctx_t *ctx,
2822 ism330dlc_status_spiaux_t *val)
2823 {
2824 int32_t ret;
2825 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
2826 (uint8_t *) val, 1);
2827
2828 return ret;
2829 }
2830
2831 /**
2832 * @brief AUX accelerometer data available.[get]
2833 *
2834 * @param ctx Read / write interface definitions
2835 * @param val change the values of xlda in reg STATUS_SPIAUX
2836 * @retval Interface status (MANDATORY: return 0 -> no Error).
2837 *
2838 */
ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)2839 int32_t ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
2840 uint8_t *val)
2841 {
2842 ism330dlc_status_spiaux_t reg;
2843 int32_t ret;
2844 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
2845 (uint8_t *)®, 1);
2846 *val = reg.xlda;
2847
2848 return ret;
2849 }
2850
2851 /**
2852 * @brief AUX gyroscope data available.[get]
2853 *
2854 * @param ctx Read / write interface definitions
2855 * @param val change the values of gda in reg STATUS_SPIAUX
2856 * @retval Interface status (MANDATORY: return 0 -> no Error).
2857 *
2858 */
ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)2859 int32_t ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
2860 uint8_t *val)
2861 {
2862 ism330dlc_status_spiaux_t reg;
2863 int32_t ret;
2864 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
2865 (uint8_t *)®, 1);
2866 *val = reg.gda;
2867
2868 return ret;
2869 }
2870
2871 /**
2872 * @brief High when the gyroscope output is in the settling phase.[get]
2873 *
2874 * @param ctx Read / write interface definitions
2875 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
2876 * @retval Interface status (MANDATORY: return 0 -> no Error).
2877 *
2878 */
ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2879 int32_t ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
2880 uint8_t *val)
2881 {
2882 ism330dlc_status_spiaux_t reg;
2883 int32_t ret;
2884 ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX,
2885 (uint8_t *)®, 1);
2886 *val = reg.gyro_settling;
2887
2888 return ret;
2889 }
2890
2891 /**
2892 * @brief Configure DEN mode on the OIS chain.[set]
2893 *
2894 * @param ctx Read / write interface definitions
2895 * @param val change the values of lvl2_ois in reg INT_OIS
2896 * @retval Interface status (MANDATORY: return 0 -> no Error).
2897 *
2898 */
ism330dlc_aux_den_mode_set(const stmdev_ctx_t * ctx,ism330dlc_lvl_ois_t val)2899 int32_t ism330dlc_aux_den_mode_set(const stmdev_ctx_t *ctx,
2900 ism330dlc_lvl_ois_t val)
2901 {
2902 ism330dlc_ctrl1_ois_t ctrl1_ois;
2903 ism330dlc_int_ois_t int_ois;
2904 int32_t ret;
2905 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)&int_ois, 1);
2906
2907 if (ret == 0)
2908 {
2909 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
2910 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_OIS,
2911 (uint8_t *)&int_ois, 1);
2912 }
2913
2914 if (ret == 0)
2915 {
2916 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS,
2917 (uint8_t *)&ctrl1_ois, 1);
2918 }
2919
2920 if (ret == 0)
2921 {
2922 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
2923 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS,
2924 (uint8_t *)&ctrl1_ois, 1);
2925 }
2926
2927 return ret;
2928 }
2929
2930 /**
2931 * @brief Configure DEN mode on the OIS chain.[get]
2932 *
2933 * @param ctx Read / write interface definitions
2934 * @param val Get the values of lvl2_ois in reg INT_OIS
2935 * @retval Interface status (MANDATORY: return 0 -> no Error).
2936 *
2937 */
ism330dlc_aux_den_mode_get(const stmdev_ctx_t * ctx,ism330dlc_lvl_ois_t * val)2938 int32_t ism330dlc_aux_den_mode_get(const stmdev_ctx_t *ctx,
2939 ism330dlc_lvl_ois_t *val)
2940 {
2941 ism330dlc_ctrl1_ois_t ctrl1_ois;
2942 ism330dlc_int_ois_t int_ois;
2943 int32_t ret;
2944 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)&int_ois, 1);
2945
2946 if (ret == 0)
2947 {
2948 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS,
2949 (uint8_t *)&ctrl1_ois, 1);
2950 }
2951
2952 switch ((ctrl1_ois.lvl1_ois << 1) | int_ois.lvl2_ois)
2953 {
2954 case ISM330DLC_AUX_DEN_DISABLE:
2955 *val = ISM330DLC_AUX_DEN_DISABLE;
2956 break;
2957
2958 case ISM330DLC_AUX_DEN_LEVEL_LATCH:
2959 *val = ISM330DLC_AUX_DEN_LEVEL_LATCH;
2960 break;
2961
2962 case ISM330DLC_AUX_DEN_LEVEL_TRIG:
2963 *val = ISM330DLC_AUX_DEN_LEVEL_TRIG;
2964 break;
2965
2966 default:
2967 *val = ISM330DLC_AUX_DEN_DISABLE;
2968 break;
2969 }
2970
2971 return ret;
2972 }
2973
2974 /**
2975 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
2976 * has priority over all other INT2 settings.[set]
2977 *
2978 * @param ctx Read / write interface definitions
2979 * @param val change the values of int2_drdy_ois in reg INT_OIS
2980 * @retval Interface status (MANDATORY: return 0 -> no Error).
2981 *
2982 */
ism330dlc_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)2983 int32_t ism330dlc_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
2984 {
2985 ism330dlc_int_ois_t reg;
2986 int32_t ret;
2987 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
2988
2989 if (ret == 0)
2990 {
2991 reg.int2_drdy_ois = val;
2992 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
2993 }
2994
2995 return ret;
2996 }
2997
2998 /**
2999 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
3000 * has priority over all other INT2 settings.[get]
3001 *
3002 * @param ctx Read / write interface definitions
3003 * @param val change the values of int2_drdy_ois in reg INT_OIS
3004 * @retval Interface status (MANDATORY: return 0 -> no Error).
3005 *
3006 */
ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3007 int32_t ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx,
3008 uint8_t *val)
3009 {
3010 ism330dlc_int_ois_t reg;
3011 int32_t ret;
3012 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1);
3013 *val = reg.int2_drdy_ois;
3014
3015 return ret;
3016 }
3017
3018 /**
3019 * @brief Enables OIS chain data processing for gyro
3020 * in Mode 3 and Mode 4 (mode4_en = 1) and
3021 * accelerometer data in and Mode 4 (mode4_en = 1).
3022 * When the OIS chain is enabled, the OIS outputs are
3023 * available through the SPI2 in registers
3024 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3025 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3026 * dedicated to this chain.[set]
3027 *
3028 * @param ctx Read / write interface definitions
3029 * @param val change the values of ois_en_spi2 in reg CTRL1_OIS
3030 * @retval Interface status (MANDATORY: return 0 -> no Error).
3031 *
3032 */
ism330dlc_aux_mode_set(const stmdev_ctx_t * ctx,ism330dlc_ois_en_spi2_t val)3033 int32_t ism330dlc_aux_mode_set(const stmdev_ctx_t *ctx,
3034 ism330dlc_ois_en_spi2_t val)
3035 {
3036 ism330dlc_ctrl1_ois_t reg;
3037 int32_t ret;
3038 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3039
3040 if (ret == 0)
3041 {
3042 reg.ois_en_spi2 = (uint8_t)val & 0x01U;
3043 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3044 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3045 }
3046
3047 return ret;
3048 }
3049
3050 /**
3051 * @brief Enables OIS chain data processing for gyro
3052 * in Mode 3 and Mode 4 (mode4_en = 1) and
3053 * accelerometer data in and Mode 4 (mode4_en = 1).
3054 * When the OIS chain is enabled, the OIS outputs
3055 * are available through the SPI2 in registers
3056 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3057 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3058 * dedicated to this chain.[get]
3059 *
3060 * @param ctx Read / write interface definitions
3061 * @param val Get the values of ois_en_spi2 in reg CTRL1_OIS
3062 * @retval Interface status (MANDATORY: return 0 -> no Error).
3063 *
3064 */
ism330dlc_aux_mode_get(const stmdev_ctx_t * ctx,ism330dlc_ois_en_spi2_t * val)3065 int32_t ism330dlc_aux_mode_get(const stmdev_ctx_t *ctx,
3066 ism330dlc_ois_en_spi2_t *val)
3067 {
3068 ism330dlc_ctrl1_ois_t reg;
3069 int32_t ret;
3070 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3071
3072 switch ((reg.mode4_en << 1) + reg.ois_en_spi2)
3073 {
3074 case ISM330DLC_AUX_DISABLE:
3075 *val = ISM330DLC_AUX_DISABLE;
3076 break;
3077
3078 case ISM330DLC_MODE_3_GY:
3079 *val = ISM330DLC_MODE_3_GY;
3080 break;
3081
3082 case ISM330DLC_MODE_4_GY_XL:
3083 *val = ISM330DLC_MODE_4_GY_XL;
3084 break;
3085
3086 default:
3087 *val = ISM330DLC_AUX_DISABLE;
3088 break;
3089 }
3090
3091 return ret;
3092 }
3093
3094 /**
3095 * @brief Selects gyroscope OIS chain full-scale.[set]
3096 *
3097 * @param ctx Read / write interface definitions
3098 * @param val change the values of fs_g_ois in reg CTRL1_OIS
3099 * @retval Interface status (MANDATORY: return 0 -> no Error).
3100 *
3101 */
ism330dlc_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,ism330dlc_fs_g_ois_t val)3102 int32_t ism330dlc_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3103 ism330dlc_fs_g_ois_t val)
3104 {
3105 ism330dlc_ctrl1_ois_t reg;
3106 int32_t ret;
3107 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3108
3109 if (ret == 0)
3110 {
3111 reg.fs_g_ois = (uint8_t)val;
3112 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3113 }
3114
3115 return ret;
3116 }
3117
3118 /**
3119 * @brief Selects gyroscope OIS chain full-scale.[get]
3120 *
3121 * @param ctx Read / write interface definitions
3122 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3123 * @retval Interface status (MANDATORY: return 0 -> no Error).
3124 *
3125 */
ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,ism330dlc_fs_g_ois_t * val)3126 int32_t ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3127 ism330dlc_fs_g_ois_t *val)
3128 {
3129 ism330dlc_ctrl1_ois_t reg;
3130 int32_t ret;
3131 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3132
3133 switch (reg.fs_g_ois)
3134 {
3135 case ISM330DLC_250dps_AUX:
3136 *val = ISM330DLC_250dps_AUX;
3137 break;
3138
3139 case ISM330DLC_125dps_AUX:
3140 *val = ISM330DLC_125dps_AUX;
3141 break;
3142
3143 case ISM330DLC_500dps_AUX:
3144 *val = ISM330DLC_500dps_AUX;
3145 break;
3146
3147 case ISM330DLC_1000dps_AUX:
3148 *val = ISM330DLC_1000dps_AUX;
3149 break;
3150
3151 case ISM330DLC_2000dps_AUX:
3152 *val = ISM330DLC_2000dps_AUX;
3153 break;
3154
3155 default:
3156 *val = ISM330DLC_250dps_AUX;
3157 break;
3158 }
3159
3160 return ret;
3161 }
3162
3163 /**
3164 * @brief SPI2 3- or 4-wire interface.[set]
3165 *
3166 * @param ctx Read / write interface definitions
3167 * @param val change the values of sim_ois in reg CTRL1_OIS
3168 * @retval Interface status (MANDATORY: return 0 -> no Error).
3169 *
3170 */
ism330dlc_aux_spi_mode_set(const stmdev_ctx_t * ctx,ism330dlc_sim_ois_t val)3171 int32_t ism330dlc_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3172 ism330dlc_sim_ois_t val)
3173 {
3174 ism330dlc_ctrl1_ois_t reg;
3175 int32_t ret;
3176 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3177
3178 if (ret == 0)
3179 {
3180 reg.sim_ois = (uint8_t)val;
3181 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3182 }
3183
3184 return ret;
3185 }
3186
3187 /**
3188 * @brief SPI2 3- or 4-wire interface.[get]
3189 *
3190 * @param ctx Read / write interface definitions
3191 * @param val Get the values of sim_ois in reg CTRL1_OIS
3192 * @retval Interface status (MANDATORY: return 0 -> no Error).
3193 *
3194 */
ism330dlc_aux_spi_mode_get(const stmdev_ctx_t * ctx,ism330dlc_sim_ois_t * val)3195 int32_t ism330dlc_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3196 ism330dlc_sim_ois_t *val)
3197 {
3198 ism330dlc_ctrl1_ois_t reg;
3199 int32_t ret;
3200 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3201
3202 switch (reg.sim_ois)
3203 {
3204 case ISM330DLC_AUX_SPI_4_WIRE:
3205 *val = ISM330DLC_AUX_SPI_4_WIRE;
3206 break;
3207
3208 case ISM330DLC_AUX_SPI_3_WIRE:
3209 *val = ISM330DLC_AUX_SPI_3_WIRE;
3210 break;
3211
3212 default:
3213 *val = ISM330DLC_AUX_SPI_4_WIRE;
3214 break;
3215 }
3216
3217 return ret;
3218 }
3219
3220 /**
3221 * @brief Big/Little Endian Data selection on aux interface.[set]
3222 *
3223 * @param ctx Read / write interface definitions
3224 * @param val change the values of ble_ois in reg CTRL1_OIS
3225 * @retval Interface status (MANDATORY: return 0 -> no Error).
3226 *
3227 */
ism330dlc_aux_data_format_set(const stmdev_ctx_t * ctx,ism330dlc_ble_ois_t val)3228 int32_t ism330dlc_aux_data_format_set(const stmdev_ctx_t *ctx,
3229 ism330dlc_ble_ois_t val)
3230 {
3231 ism330dlc_ctrl1_ois_t reg;
3232 int32_t ret;
3233 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3234
3235 if (ret == 0)
3236 {
3237 reg.ble_ois = (uint8_t)val;
3238 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3239 }
3240
3241 return ret;
3242 }
3243
3244 /**
3245 * @brief Big/Little Endian Data selection on aux interface.[get]
3246 *
3247 * @param ctx Read / write interface definitions
3248 * @param val Get the values of ble_ois in reg CTRL1_OIS
3249 * @retval Interface status (MANDATORY: return 0 -> no Error).
3250 *
3251 */
ism330dlc_aux_data_format_get(const stmdev_ctx_t * ctx,ism330dlc_ble_ois_t * val)3252 int32_t ism330dlc_aux_data_format_get(const stmdev_ctx_t *ctx,
3253 ism330dlc_ble_ois_t *val)
3254 {
3255 ism330dlc_ctrl1_ois_t reg;
3256 int32_t ret;
3257 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1);
3258
3259 switch (reg.ble_ois)
3260 {
3261 case ISM330DLC_AUX_LSB_AT_LOW_ADD:
3262 *val = ISM330DLC_AUX_LSB_AT_LOW_ADD;
3263 break;
3264
3265 case ISM330DLC_AUX_MSB_AT_LOW_ADD:
3266 *val = ISM330DLC_AUX_MSB_AT_LOW_ADD;
3267 break;
3268
3269 default:
3270 *val = ISM330DLC_AUX_LSB_AT_LOW_ADD;
3271 break;
3272 }
3273
3274 return ret;
3275 }
3276
3277 /**
3278 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3279 * outputs = 8000h during self-test; Disable: OIS chain
3280 * self-test outputs dependent from the aux gyro full scale
3281 * selected.[set]
3282 *
3283 * @param ctx Read / write interface definitions
3284 * @param val change the values of st_ois_clampdis in reg CTRL3_OIS
3285 * @retval Interface status (MANDATORY: return 0 -> no Error).
3286 *
3287 */
ism330dlc_aux_gy_clamp_set(const stmdev_ctx_t * ctx,ism330dlc_st_ois_clampdis_t val)3288 int32_t ism330dlc_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
3289 ism330dlc_st_ois_clampdis_t val)
3290 {
3291 ism330dlc_ctrl3_ois_t reg;
3292 int32_t ret;
3293 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3294
3295 if (ret == 0)
3296 {
3297 reg.st_ois_clampdis = (uint8_t)val;
3298 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3299 }
3300
3301 return ret;
3302 }
3303
3304 /**
3305 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3306 * outputs = 8000h during self-test; Disable: OIS chain
3307 * self-test outputs dependent from the aux gyro full scale
3308 * selected.[get]
3309 *
3310 * @param ctx Read / write interface definitions
3311 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
3312 * @retval Interface status (MANDATORY: return 0 -> no Error).
3313 *
3314 */
ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t * ctx,ism330dlc_st_ois_clampdis_t * val)3315 int32_t ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
3316 ism330dlc_st_ois_clampdis_t *val)
3317 {
3318 ism330dlc_ctrl3_ois_t reg;
3319 int32_t ret;
3320 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3321
3322 switch (reg.st_ois_clampdis)
3323 {
3324 case ISM330DLC_ENABLE_CLAMP:
3325 *val = ISM330DLC_ENABLE_CLAMP;
3326 break;
3327
3328 case ISM330DLC_DISABLE_CLAMP:
3329 *val = ISM330DLC_DISABLE_CLAMP;
3330 break;
3331
3332 default:
3333 *val = ISM330DLC_ENABLE_CLAMP;
3334 break;
3335 }
3336
3337 return ret;
3338 }
3339
3340 /**
3341 * @brief Selects gyroscope OIS chain self-test.[set]
3342 *
3343 * @param ctx Read / write interface definitions
3344 * @param val change the values of st_ois in reg CTRL3_OIS
3345 * @retval Interface status (MANDATORY: return 0 -> no Error).
3346 *
3347 */
ism330dlc_aux_gy_self_test_set(const stmdev_ctx_t * ctx,ism330dlc_st_ois_t val)3348 int32_t ism330dlc_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
3349 ism330dlc_st_ois_t val)
3350 {
3351 ism330dlc_ctrl3_ois_t reg;
3352 int32_t ret;
3353 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3354
3355 if (ret == 0)
3356 {
3357 reg.st_ois = (uint8_t)val;
3358 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3359 }
3360
3361 return ret;
3362 }
3363
3364 /**
3365 * @brief Selects gyroscope OIS chain self-test.[get]
3366 *
3367 * @param ctx Read / write interface definitions
3368 * @param val Get the values of st_ois in reg CTRL3_OIS
3369 * @retval Interface status (MANDATORY: return 0 -> no Error).
3370 *
3371 */
ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t * ctx,ism330dlc_st_ois_t * val)3372 int32_t ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
3373 ism330dlc_st_ois_t *val)
3374 {
3375 ism330dlc_ctrl3_ois_t reg;
3376 int32_t ret;
3377 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3378
3379 switch (reg.st_ois)
3380 {
3381 case ISM330DLC_AUX_GY_DISABLE:
3382 *val = ISM330DLC_AUX_GY_DISABLE;
3383 break;
3384
3385 case ISM330DLC_AUX_GY_POS:
3386 *val = ISM330DLC_AUX_GY_POS;
3387 break;
3388
3389 case ISM330DLC_AUX_GY_NEG:
3390 *val = ISM330DLC_AUX_GY_NEG;
3391 break;
3392
3393 default:
3394 *val = ISM330DLC_AUX_GY_DISABLE;
3395 break;
3396 }
3397
3398 return ret;
3399 }
3400
3401 /**
3402 * @brief Selects accelerometer OIS channel full-scale.[set]
3403 *
3404 * @param ctx Read / write interface definitions
3405 * @param val change the values of fs_xl_ois in reg CTRL3_OIS
3406 * @retval Interface status (MANDATORY: return 0 -> no Error).
3407 *
3408 */
ism330dlc_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330dlc_fs_xl_ois_t val)3409 int32_t ism330dlc_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
3410 ism330dlc_fs_xl_ois_t val)
3411 {
3412 ism330dlc_ctrl3_ois_t reg;
3413 int32_t ret;
3414 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3415
3416 if (ret == 0)
3417 {
3418 reg.fs_xl_ois = (uint8_t)val;
3419 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3420 }
3421
3422 return ret;
3423 }
3424
3425 /**
3426 * @brief Selects accelerometer OIS channel full-scale.[get]
3427 *
3428 * @param ctx Read / write interface definitions
3429 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
3430 * @retval Interface status (MANDATORY: return 0 -> no Error).
3431 *
3432 */
ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330dlc_fs_xl_ois_t * val)3433 int32_t ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
3434 ism330dlc_fs_xl_ois_t *val)
3435 {
3436 ism330dlc_ctrl3_ois_t reg;
3437 int32_t ret;
3438 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3439
3440 switch (reg.fs_xl_ois)
3441 {
3442 case ISM330DLC_AUX_2g:
3443 *val = ISM330DLC_AUX_2g;
3444 break;
3445
3446 case ISM330DLC_AUX_16g:
3447 *val = ISM330DLC_AUX_16g;
3448 break;
3449
3450 case ISM330DLC_AUX_4g:
3451 *val = ISM330DLC_AUX_4g;
3452 break;
3453
3454 case ISM330DLC_AUX_8g:
3455 *val = ISM330DLC_AUX_8g;
3456 break;
3457
3458 default:
3459 *val = ISM330DLC_AUX_2g;
3460 break;
3461 }
3462
3463 return ret;
3464 }
3465
3466 /**
3467 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3468 *
3469 * @param ctx Read / write interface definitions
3470 * @param val change the values of den_lh_ois in reg CTRL3_OIS
3471 * @retval Interface status (MANDATORY: return 0 -> no Error).
3472 *
3473 */
ism330dlc_aux_den_polarity_set(const stmdev_ctx_t * ctx,ism330dlc_den_lh_ois_t val)3474 int32_t ism330dlc_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3475 ism330dlc_den_lh_ois_t val)
3476 {
3477 ism330dlc_ctrl3_ois_t reg;
3478 int32_t ret;
3479 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3480
3481 if (ret == 0)
3482 {
3483 reg.den_lh_ois = (uint8_t)val;
3484 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3485 }
3486
3487 return ret;
3488 }
3489
3490 /**
3491 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3492 *
3493 * @param ctx Read / write interface definitions
3494 * @param val Get the values of den_lh_ois in reg CTRL3_OIS
3495 * @retval Interface status (MANDATORY: return 0 -> no Error).
3496 *
3497 */
ism330dlc_aux_den_polarity_get(const stmdev_ctx_t * ctx,ism330dlc_den_lh_ois_t * val)3498 int32_t ism330dlc_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3499 ism330dlc_den_lh_ois_t *val)
3500 {
3501 ism330dlc_ctrl3_ois_t reg;
3502 int32_t ret;
3503 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1);
3504
3505 switch (reg.den_lh_ois)
3506 {
3507 case ISM330DLC_AUX_DEN_ACTIVE_LOW:
3508 *val = ISM330DLC_AUX_DEN_ACTIVE_LOW;
3509 break;
3510
3511 case ISM330DLC_AUX_DEN_ACTIVE_HIGH:
3512 *val = ISM330DLC_AUX_DEN_ACTIVE_HIGH;
3513 break;
3514
3515 default:
3516 *val = ISM330DLC_AUX_DEN_ACTIVE_LOW;
3517 break;
3518 }
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @}
3525 *
3526 */
3527
3528 /**
3529 * @defgroup ISM330DLC_main_serial_interface
3530 * @brief This section groups all the functions concerning serial
3531 * interface management
3532 * @{
3533 *
3534 */
3535
3536 /**
3537 * @brief SPI Serial Interface Mode selection.[set]
3538 *
3539 * @param ctx Read / write interface definitions
3540 * @param val Change the values of sim in reg CTRL3_C
3541 * @retval Interface status (MANDATORY: return 0 -> no Error).
3542 *
3543 */
ism330dlc_spi_mode_set(const stmdev_ctx_t * ctx,ism330dlc_sim_t val)3544 int32_t ism330dlc_spi_mode_set(const stmdev_ctx_t *ctx, ism330dlc_sim_t val)
3545 {
3546 ism330dlc_ctrl3_c_t ctrl3_c;
3547 int32_t ret;
3548 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3549
3550 if (ret == 0)
3551 {
3552 ctrl3_c.sim = (uint8_t) val;
3553 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3554 }
3555
3556 return ret;
3557 }
3558
3559 /**
3560 * @brief SPI Serial Interface Mode selection.[get]
3561 *
3562 * @param ctx Read / write interface definitions
3563 * @param val Get the values of sim in reg CTRL3_C
3564 * @retval Interface status (MANDATORY: return 0 -> no Error).
3565 *
3566 */
ism330dlc_spi_mode_get(const stmdev_ctx_t * ctx,ism330dlc_sim_t * val)3567 int32_t ism330dlc_spi_mode_get(const stmdev_ctx_t *ctx,
3568 ism330dlc_sim_t *val)
3569 {
3570 ism330dlc_ctrl3_c_t ctrl3_c;
3571 int32_t ret;
3572 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3573
3574 switch (ctrl3_c.sim)
3575 {
3576 case ISM330DLC_SPI_4_WIRE:
3577 *val = ISM330DLC_SPI_4_WIRE;
3578 break;
3579
3580 case ISM330DLC_SPI_3_WIRE:
3581 *val = ISM330DLC_SPI_3_WIRE;
3582 break;
3583
3584 default:
3585 *val = ISM330DLC_SPI_4_WIRE;
3586 break;
3587 }
3588
3589 return ret;
3590 }
3591
3592 /**
3593 * @brief Disable / Enable I2C interface.[set]
3594 *
3595 * @param ctx Read / write interface definitions
3596 * @param val Change the values of i2c_disable in reg CTRL4_C
3597 * @retval Interface status (MANDATORY: return 0 -> no Error).
3598 *
3599 */
ism330dlc_i2c_interface_set(const stmdev_ctx_t * ctx,ism330dlc_i2c_disable_t val)3600 int32_t ism330dlc_i2c_interface_set(const stmdev_ctx_t *ctx,
3601 ism330dlc_i2c_disable_t val)
3602 {
3603 ism330dlc_ctrl4_c_t ctrl4_c;
3604 int32_t ret;
3605 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3606
3607 if (ret == 0)
3608 {
3609 ctrl4_c.i2c_disable = (uint8_t)val;
3610 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3611 }
3612
3613 return ret;
3614 }
3615
3616 /**
3617 * @brief Disable / Enable I2C interface.[get]
3618 *
3619 * @param ctx Read / write interface definitions
3620 * @param val Get the values of i2c_disable in reg CTRL4_C
3621 * @retval Interface status (MANDATORY: return 0 -> no Error).
3622 *
3623 */
ism330dlc_i2c_interface_get(const stmdev_ctx_t * ctx,ism330dlc_i2c_disable_t * val)3624 int32_t ism330dlc_i2c_interface_get(const stmdev_ctx_t *ctx,
3625 ism330dlc_i2c_disable_t *val)
3626 {
3627 ism330dlc_ctrl4_c_t ctrl4_c;
3628 int32_t ret;
3629 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3630
3631 switch (ctrl4_c.i2c_disable)
3632 {
3633 case ISM330DLC_I2C_ENABLE:
3634 *val = ISM330DLC_I2C_ENABLE;
3635 break;
3636
3637 case ISM330DLC_I2C_DISABLE:
3638 *val = ISM330DLC_I2C_DISABLE;
3639 break;
3640
3641 default:
3642 *val = ISM330DLC_I2C_ENABLE;
3643 break;
3644 }
3645
3646 return ret;
3647 }
3648
3649 /**
3650 * @}
3651 *
3652 */
3653
3654 /**
3655 * @defgroup ISM330DLC_interrupt_pins
3656 * @brief This section groups all the functions that manage
3657 * interrupt pins
3658 * @{
3659 *
3660 */
3661
3662 /**
3663 * @brief Select the signal that need to route on int1 pad[set]
3664 *
3665 * @param ctx Read / write interface definitions
3666 * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3667 * MASTER_CONFIG(drdy_on_int1)
3668 * @retval Interface status (MANDATORY: return 0 -> no Error).
3669 *
3670 */
ism330dlc_pin_int1_route_set(const stmdev_ctx_t * ctx,ism330dlc_int1_route_t val)3671 int32_t ism330dlc_pin_int1_route_set(const stmdev_ctx_t *ctx,
3672 ism330dlc_int1_route_t val)
3673 {
3674 ism330dlc_master_config_t master_config;
3675 ism330dlc_int1_ctrl_t int1_ctrl;
3676 ism330dlc_md1_cfg_t md1_cfg;
3677 ism330dlc_md2_cfg_t md2_cfg;
3678 ism330dlc_ctrl4_c_t ctrl4_c;
3679 ism330dlc_tap_cfg_t tap_cfg;
3680 int32_t ret;
3681 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT1_CTRL,
3682 (uint8_t *)&int1_ctrl, 1);
3683
3684 if (ret == 0)
3685 {
3686 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
3687 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
3688 int1_ctrl.int1_boot = val.int1_boot;
3689 int1_ctrl.int1_fth = val.int1_fth;
3690 int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
3691 int1_ctrl.int1_full_flag = val.int1_full_flag;
3692 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT1_CTRL,
3693 (uint8_t *)&int1_ctrl, 1);
3694 }
3695
3696 if (ret == 0)
3697 {
3698 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3699 }
3700
3701 if (ret == 0)
3702 {
3703 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3704 }
3705
3706 if (ret == 0)
3707 {
3708 md1_cfg.int1_tilt = val.int1_tilt;
3709 md1_cfg.int1_6d = val.int1_6d;
3710 md1_cfg.int1_double_tap = val.int1_double_tap;
3711 md1_cfg.int1_ff = val.int1_ff;
3712 md1_cfg.int1_wu = val.int1_wu;
3713 md1_cfg.int1_single_tap = val.int1_single_tap;
3714 md1_cfg.int1_inact_state = val.int1_inact_state;
3715 ret = ism330dlc_write_reg(ctx, ISM330DLC_MD1_CFG,
3716 (uint8_t *)&md1_cfg, 1);
3717 }
3718
3719 if (ret == 0)
3720 {
3721 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3722 }
3723
3724 if (ret == 0)
3725 {
3726 ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
3727 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3728 }
3729
3730 if (ret == 0)
3731 {
3732 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
3733 (uint8_t *)&master_config, 1);
3734 }
3735
3736 if (ret == 0)
3737 {
3738 master_config.drdy_on_int1 = val.den_drdy_int1;
3739 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
3740 (uint8_t *)&master_config, 1);
3741 }
3742
3743 if (ret == 0)
3744 {
3745 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3746
3747 if ((val.int1_6d != 0x00U) ||
3748 (val.int1_ff != 0x00U) ||
3749 (val.int1_wu != 0x00U) ||
3750 (val.int1_single_tap != 0x00U) ||
3751 (val.int1_double_tap != 0x00U) ||
3752 (val.int1_inact_state != 0x00U) ||
3753 (md2_cfg.int2_6d != 0x00U) ||
3754 (md2_cfg.int2_ff != 0x00U) ||
3755 (md2_cfg.int2_wu != 0x00U) ||
3756 (md2_cfg.int2_single_tap != 0x00U) ||
3757 (md2_cfg.int2_double_tap != 0x00U) ||
3758 (md2_cfg.int2_inact_state != 0x00U))
3759 {
3760 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
3761 }
3762
3763 else
3764 {
3765 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
3766 }
3767 }
3768
3769 if (ret == 0)
3770 {
3771 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3772 }
3773
3774 return ret;
3775 }
3776
3777 /**
3778 * @brief Select the signal that need to route on int1 pad[get]
3779 *
3780 * @param ctx Read / write interface definitions
3781 * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3782 * MASTER_CONFIG(drdy_on_int1)
3783 * @retval Interface status (MANDATORY: return 0 -> no Error).
3784 *
3785 */
ism330dlc_pin_int1_route_get(const stmdev_ctx_t * ctx,ism330dlc_int1_route_t * val)3786 int32_t ism330dlc_pin_int1_route_get(const stmdev_ctx_t *ctx,
3787 ism330dlc_int1_route_t *val)
3788 {
3789 ism330dlc_master_config_t master_config;
3790 ism330dlc_int1_ctrl_t int1_ctrl;
3791 ism330dlc_md1_cfg_t md1_cfg;
3792 ism330dlc_ctrl4_c_t ctrl4_c;
3793 int32_t ret;
3794 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT1_CTRL,
3795 (uint8_t *)&int1_ctrl, 1);
3796
3797 if (ret == 0)
3798 {
3799 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
3800 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
3801 val->int1_boot = int1_ctrl.int1_boot;
3802 val->int1_fth = int1_ctrl.int1_fth;
3803 val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
3804 val->int1_full_flag = int1_ctrl.int1_full_flag;
3805 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3806
3807 if (ret == 0)
3808 {
3809 val->int1_tilt = md1_cfg.int1_tilt;
3810 val->int1_6d = md1_cfg.int1_6d;
3811 val->int1_double_tap = md1_cfg.int1_double_tap;
3812 val->int1_ff = md1_cfg.int1_ff;
3813 val->int1_wu = md1_cfg.int1_wu;
3814 val->int1_single_tap = md1_cfg.int1_single_tap;
3815 val->int1_inact_state = md1_cfg.int1_inact_state;
3816 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3817
3818 if (ret == 0)
3819 {
3820 val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
3821 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
3822 (uint8_t *)&master_config, 1);
3823 val->den_drdy_int1 = master_config.drdy_on_int1;
3824 }
3825 }
3826 }
3827
3828 return ret;
3829 }
3830
3831 /**
3832 * @brief Select the signal that need to route on int2 pad[set]
3833 *
3834 * @param ctx Read / write interface definitions
3835 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
3836 * @retval Interface status (MANDATORY: return 0 -> no Error).
3837 *
3838 */
ism330dlc_pin_int2_route_set(const stmdev_ctx_t * ctx,ism330dlc_int2_route_t val)3839 int32_t ism330dlc_pin_int2_route_set(const stmdev_ctx_t *ctx,
3840 ism330dlc_int2_route_t val)
3841 {
3842 ism330dlc_int2_ctrl_t int2_ctrl;
3843 ism330dlc_md1_cfg_t md1_cfg;
3844 ism330dlc_md2_cfg_t md2_cfg;
3845 ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg;
3846 ism330dlc_tap_cfg_t tap_cfg;
3847 int32_t ret;
3848 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT2_CTRL,
3849 (uint8_t *)&int2_ctrl, 1);
3850
3851 if (ret == 0)
3852 {
3853 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
3854 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
3855 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
3856 int2_ctrl.int2_fth = val.int2_fth;
3857 int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
3858 int2_ctrl.int2_full_flag = val.int2_full_flag;
3859 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT2_CTRL,
3860 (uint8_t *)&int2_ctrl, 1);
3861 }
3862
3863 if (ret == 0)
3864 {
3865 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD1_CFG,
3866 (uint8_t *)&md1_cfg, 1);
3867 }
3868
3869 if (ret == 0)
3870 {
3871 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG,
3872 (uint8_t *)&md2_cfg, 1);
3873 }
3874
3875 if (ret == 0)
3876 {
3877 md2_cfg.int2_iron = val.int2_iron;
3878 md2_cfg.int2_tilt = val.int2_tilt;
3879 md2_cfg.int2_6d = val.int2_6d;
3880 md2_cfg.int2_double_tap = val.int2_double_tap;
3881 md2_cfg.int2_ff = val.int2_ff;
3882 md2_cfg.int2_wu = val.int2_wu;
3883 md2_cfg.int2_single_tap = val.int2_single_tap;
3884 md2_cfg.int2_inact_state = val.int2_inact_state;
3885 ret = ism330dlc_write_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3886 }
3887
3888 if (ret == 0)
3889 {
3890 ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
3891 (uint8_t *)&drdy_pulse_cfg, 1);
3892 }
3893
3894 if (ret == 0)
3895 {
3896 ret = ism330dlc_write_reg(ctx, ISM330DLC_DRDY_PULSE_CFG,
3897 (uint8_t *)&drdy_pulse_cfg, 1);
3898 }
3899
3900 if (ret == 0)
3901 {
3902 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3903
3904 if ((md1_cfg.int1_6d != 0x00U) ||
3905 (md1_cfg.int1_ff != 0x00U) ||
3906 (md1_cfg.int1_wu != 0x00U) ||
3907 (md1_cfg.int1_single_tap != 0x00U) ||
3908 (md1_cfg.int1_double_tap != 0x00U) ||
3909 (md1_cfg.int1_inact_state != 0x00U) ||
3910 (val.int2_6d != 0x00U) ||
3911 (val.int2_ff != 0x00U) ||
3912 (val.int2_wu != 0x00U) ||
3913 (val.int2_single_tap != 0x00U) ||
3914 (val.int2_double_tap != 0x00U) ||
3915 (val.int2_inact_state != 0x00U))
3916 {
3917 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
3918 }
3919
3920 else
3921 {
3922 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
3923 }
3924 }
3925
3926 if (ret == 0)
3927 {
3928 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3929 }
3930
3931 return ret;
3932 }
3933
3934 /**
3935 * @brief Select the signal that need to route on int2 pad[get]
3936 *
3937 * @param ctx Read / write interface definitions
3938 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
3939 * @retval Interface status (MANDATORY: return 0 -> no Error).
3940 *
3941 */
ism330dlc_pin_int2_route_get(const stmdev_ctx_t * ctx,ism330dlc_int2_route_t * val)3942 int32_t ism330dlc_pin_int2_route_get(const stmdev_ctx_t *ctx,
3943 ism330dlc_int2_route_t *val)
3944 {
3945 ism330dlc_int2_ctrl_t int2_ctrl;
3946 ism330dlc_md2_cfg_t md2_cfg;
3947 int32_t ret;
3948 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT2_CTRL,
3949 (uint8_t *)&int2_ctrl, 1);
3950
3951 if (ret == 0)
3952 {
3953 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
3954 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
3955 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
3956 val->int2_fth = int2_ctrl.int2_fth;
3957 val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
3958 val->int2_full_flag = int2_ctrl.int2_full_flag;
3959 ret = ism330dlc_read_reg(ctx, ISM330DLC_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3960
3961 if (ret == 0)
3962 {
3963 val->int2_iron = md2_cfg.int2_iron;
3964 val->int2_tilt = md2_cfg.int2_tilt;
3965 val->int2_6d = md2_cfg.int2_6d;
3966 val->int2_double_tap = md2_cfg.int2_double_tap;
3967 val->int2_ff = md2_cfg.int2_ff;
3968 val->int2_wu = md2_cfg.int2_wu;
3969 val->int2_single_tap = md2_cfg.int2_single_tap;
3970 val->int2_inact_state = md2_cfg.int2_inact_state;
3971 }
3972 }
3973
3974 return ret;
3975 }
3976
3977 /**
3978 * @brief Push-pull/open drain selection on interrupt pads.[set]
3979 *
3980 * @param ctx Read / write interface definitions
3981 * @param val Change the values of pp_od in reg CTRL3_C
3982 * @retval Interface status (MANDATORY: return 0 -> no Error).
3983 *
3984 */
ism330dlc_pin_mode_set(const stmdev_ctx_t * ctx,ism330dlc_pp_od_t val)3985 int32_t ism330dlc_pin_mode_set(const stmdev_ctx_t *ctx,
3986 ism330dlc_pp_od_t val)
3987 {
3988 ism330dlc_ctrl3_c_t ctrl3_c;
3989 int32_t ret;
3990 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3991
3992 if (ret == 0)
3993 {
3994 ctrl3_c.pp_od = (uint8_t) val;
3995 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3996 }
3997
3998 return ret;
3999 }
4000
4001 /**
4002 * @brief Push-pull/open drain selection on interrupt pads.[get]
4003 *
4004 * @param ctx Read / write interface definitions
4005 * @param val Get the values of pp_od in reg CTRL3_C
4006 * @retval Interface status (MANDATORY: return 0 -> no Error).
4007 *
4008 */
ism330dlc_pin_mode_get(const stmdev_ctx_t * ctx,ism330dlc_pp_od_t * val)4009 int32_t ism330dlc_pin_mode_get(const stmdev_ctx_t *ctx,
4010 ism330dlc_pp_od_t *val)
4011 {
4012 ism330dlc_ctrl3_c_t ctrl3_c;
4013 int32_t ret;
4014 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4015
4016 switch (ctrl3_c.pp_od)
4017 {
4018 case ISM330DLC_PUSH_PULL:
4019 *val = ISM330DLC_PUSH_PULL;
4020 break;
4021
4022 case ISM330DLC_OPEN_DRAIN:
4023 *val = ISM330DLC_OPEN_DRAIN;
4024 break;
4025
4026 default:
4027 *val = ISM330DLC_PUSH_PULL;
4028 break;
4029 }
4030
4031 return ret;
4032 }
4033
4034 /**
4035 * @brief Interrupt active-high/low.[set]
4036 *
4037 * @param ctx Read / write interface definitions
4038 * @param val Change the values of h_lactive in reg CTRL3_C
4039 * @retval Interface status (MANDATORY: return 0 -> no Error).
4040 *
4041 */
ism330dlc_pin_polarity_set(const stmdev_ctx_t * ctx,ism330dlc_h_lactive_t val)4042 int32_t ism330dlc_pin_polarity_set(const stmdev_ctx_t *ctx,
4043 ism330dlc_h_lactive_t val)
4044 {
4045 ism330dlc_ctrl3_c_t ctrl3_c;
4046 int32_t ret;
4047 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4048
4049 if (ret == 0)
4050 {
4051 ctrl3_c.h_lactive = (uint8_t) val;
4052 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4053 }
4054
4055 return ret;
4056 }
4057
4058 /**
4059 * @brief Interrupt active-high/low.[get]
4060 *
4061 * @param ctx Read / write interface definitions
4062 * @param val Get the values of h_lactive in reg CTRL3_C
4063 * @retval Interface status (MANDATORY: return 0 -> no Error).
4064 *
4065 */
ism330dlc_pin_polarity_get(const stmdev_ctx_t * ctx,ism330dlc_h_lactive_t * val)4066 int32_t ism330dlc_pin_polarity_get(const stmdev_ctx_t *ctx,
4067 ism330dlc_h_lactive_t *val)
4068 {
4069 ism330dlc_ctrl3_c_t ctrl3_c;
4070 int32_t ret;
4071 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4072
4073 switch (ctrl3_c.h_lactive)
4074 {
4075 case ISM330DLC_ACTIVE_HIGH:
4076 *val = ISM330DLC_ACTIVE_HIGH;
4077 break;
4078
4079 case ISM330DLC_ACTIVE_LOW:
4080 *val = ISM330DLC_ACTIVE_LOW;
4081 break;
4082
4083 default:
4084 *val = ISM330DLC_ACTIVE_HIGH;
4085 break;
4086 }
4087
4088 return ret;
4089 }
4090
4091 /**
4092 * @brief All interrupt signals become available on INT1 pin.[set]
4093 *
4094 * @param ctx Read / write interface definitions
4095 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4096 * @retval Interface status (MANDATORY: return 0 -> no Error).
4097 *
4098 */
ism330dlc_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)4099 int32_t ism330dlc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
4100 {
4101 ism330dlc_ctrl4_c_t ctrl4_c;
4102 int32_t ret;
4103 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4104
4105 if (ret == 0)
4106 {
4107 ctrl4_c.int2_on_int1 = val;
4108 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4109 }
4110
4111 return ret;
4112 }
4113
4114 /**
4115 * @brief All interrupt signals become available on INT1 pin.[get]
4116 *
4117 * @param ctx Read / write interface definitions
4118 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4119 * @retval Interface status (MANDATORY: return 0 -> no Error).
4120 *
4121 */
ism330dlc_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)4122 int32_t ism330dlc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
4123 {
4124 ism330dlc_ctrl4_c_t ctrl4_c;
4125 int32_t ret;
4126 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4127 *val = ctrl4_c.int2_on_int1;
4128
4129 return ret;
4130 }
4131
4132 /**
4133 * @brief Latched/pulsed interrupt.[set]
4134 *
4135 * @param ctx Read / write interface definitions
4136 * @param val Change the values of lir in reg TAP_CFG
4137 * @retval Interface status (MANDATORY: return 0 -> no Error).
4138 *
4139 */
ism330dlc_int_notification_set(const stmdev_ctx_t * ctx,ism330dlc_lir_t val)4140 int32_t ism330dlc_int_notification_set(const stmdev_ctx_t *ctx,
4141 ism330dlc_lir_t val)
4142 {
4143 ism330dlc_tap_cfg_t tap_cfg;
4144 int32_t ret;
4145 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4146
4147 if (ret == 0)
4148 {
4149 tap_cfg.lir = (uint8_t) val;
4150 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4151 }
4152
4153 return ret;
4154 }
4155
4156 /**
4157 * @brief Latched/pulsed interrupt.[get]
4158 *
4159 * @param ctx Read / write interface definitions
4160 * @param val Get the values of lir in reg TAP_CFG
4161 * @retval Interface status (MANDATORY: return 0 -> no Error).
4162 *
4163 */
ism330dlc_int_notification_get(const stmdev_ctx_t * ctx,ism330dlc_lir_t * val)4164 int32_t ism330dlc_int_notification_get(const stmdev_ctx_t *ctx,
4165 ism330dlc_lir_t *val)
4166 {
4167 ism330dlc_tap_cfg_t tap_cfg;
4168 int32_t ret;
4169 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4170
4171 switch (tap_cfg.lir)
4172 {
4173 case ISM330DLC_INT_PULSED:
4174 *val = ISM330DLC_INT_PULSED;
4175 break;
4176
4177 case ISM330DLC_INT_LATCHED:
4178 *val = ISM330DLC_INT_LATCHED;
4179 break;
4180
4181 default:
4182 *val = ISM330DLC_INT_PULSED;
4183 break;
4184 }
4185
4186 return ret;
4187 }
4188
4189 /**
4190 * @}
4191 *
4192 */
4193
4194 /**
4195 * @defgroup ISM330DLC_Wake_Up_event
4196 * @brief This section groups all the functions that manage the
4197 * Wake Up event generation.
4198 * @{
4199 *
4200 */
4201
4202 /**
4203 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
4204 *
4205 * @param ctx Read / write interface definitions
4206 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4207 * @retval Interface status (MANDATORY: return 0 -> no Error).
4208 *
4209 */
ism330dlc_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)4210 int32_t ism330dlc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
4211 {
4212 ism330dlc_wake_up_ths_t wake_up_ths;
4213 int32_t ret;
4214 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
4215 (uint8_t *)&wake_up_ths, 1);
4216
4217 if (ret == 0)
4218 {
4219 wake_up_ths.wk_ths = val;
4220 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_THS,
4221 (uint8_t *)&wake_up_ths, 1);
4222 }
4223
4224 return ret;
4225 }
4226
4227 /**
4228 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
4229 *
4230 * @param ctx Read / write interface definitions
4231 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4232 * @retval Interface status (MANDATORY: return 0 -> no Error).
4233 *
4234 */
ism330dlc_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)4235 int32_t ism330dlc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
4236 {
4237 ism330dlc_wake_up_ths_t wake_up_ths;
4238 int32_t ret;
4239 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
4240 (uint8_t *)&wake_up_ths, 1);
4241 *val = wake_up_ths.wk_ths;
4242
4243 return ret;
4244 }
4245
4246 /**
4247 * @brief Wake up duration event.1LSb = 1 / ODR[set]
4248 *
4249 * @param ctx Read / write interface definitions
4250 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4251 * @retval Interface status (MANDATORY: return 0 -> no Error).
4252 *
4253 */
ism330dlc_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4254 int32_t ism330dlc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4255 {
4256 ism330dlc_wake_up_dur_t wake_up_dur;
4257 int32_t ret;
4258 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4259 (uint8_t *)&wake_up_dur, 1);
4260
4261 if (ret == 0)
4262 {
4263 wake_up_dur.wake_dur = val;
4264 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4265 (uint8_t *)&wake_up_dur, 1);
4266 }
4267
4268 return ret;
4269 }
4270
4271 /**
4272 * @brief Wake up duration event.1LSb = 1 / ODR[get]
4273 *
4274 * @param ctx Read / write interface definitions
4275 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4276 * @retval Interface status (MANDATORY: return 0 -> no Error).
4277 *
4278 */
ism330dlc_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4279 int32_t ism330dlc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4280 {
4281 ism330dlc_wake_up_dur_t wake_up_dur;
4282 int32_t ret;
4283 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4284 (uint8_t *)&wake_up_dur, 1);
4285 *val = wake_up_dur.wake_dur;
4286
4287 return ret;
4288 }
4289
4290 /**
4291 * @}
4292 *
4293 */
4294
4295 /**
4296 * @defgroup ISM330DLC_Activity/Inactivity_detection
4297 * @brief This section groups all the functions concerning
4298 * activity/inactivity detection.
4299 * @{
4300 *
4301 */
4302
4303 /**
4304 * @brief Enables gyroscope Sleep mode.[set]
4305 *
4306 * @param ctx Read / write interface definitions
4307 * @param val Change the values of sleep in reg CTRL4_C
4308 * @retval Interface status (MANDATORY: return 0 -> no Error).
4309 *
4310 */
ism330dlc_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4311 int32_t ism330dlc_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4312 {
4313 ism330dlc_ctrl4_c_t ctrl4_c;
4314 int32_t ret;
4315 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4316
4317 if (ret == 0)
4318 {
4319 ctrl4_c.sleep = val;
4320 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4321 }
4322
4323 return ret;
4324 }
4325
4326 /**
4327 * @brief Enables gyroscope Sleep mode.[get]
4328 *
4329 * @param ctx Read / write interface definitions
4330 * @param val Change the values of sleep in reg CTRL4_C
4331 * @retval Interface status (MANDATORY: return 0 -> no Error).
4332 *
4333 */
ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4334 int32_t ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4335 {
4336 ism330dlc_ctrl4_c_t ctrl4_c;
4337 int32_t ret;
4338 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4339 *val = ctrl4_c.sleep;
4340
4341 return ret;
4342 }
4343
4344 /**
4345 * @brief Enable inactivity function.[set]
4346 *
4347 * @param ctx Read / write interface definitions
4348 * @param val Change the values of inact_en in reg TAP_CFG
4349 * @retval Interface status (MANDATORY: return 0 -> no Error).
4350 *
4351 */
ism330dlc_act_mode_set(const stmdev_ctx_t * ctx,ism330dlc_inact_en_t val)4352 int32_t ism330dlc_act_mode_set(const stmdev_ctx_t *ctx,
4353 ism330dlc_inact_en_t val)
4354 {
4355 ism330dlc_tap_cfg_t tap_cfg;
4356 int32_t ret;
4357 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4358
4359 if (ret == 0)
4360 {
4361 tap_cfg.inact_en = (uint8_t) val;
4362 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4363 }
4364
4365 return ret;
4366 }
4367
4368 /**
4369 * @brief Enable inactivity function.[get]
4370 *
4371 * @param ctx Read / write interface definitions
4372 * @param val Get the values of inact_en in reg TAP_CFG
4373 * @retval Interface status (MANDATORY: return 0 -> no Error).
4374 *
4375 */
ism330dlc_act_mode_get(const stmdev_ctx_t * ctx,ism330dlc_inact_en_t * val)4376 int32_t ism330dlc_act_mode_get(const stmdev_ctx_t *ctx,
4377 ism330dlc_inact_en_t *val)
4378 {
4379 ism330dlc_tap_cfg_t tap_cfg;
4380 int32_t ret;
4381 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4382
4383 switch (tap_cfg.inact_en)
4384 {
4385 case ISM330DLC_PROPERTY_DISABLE:
4386 *val = ISM330DLC_PROPERTY_DISABLE;
4387 break;
4388
4389 case ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED:
4390 *val = ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED;
4391 break;
4392
4393 case ISM330DLC_XL_12Hz5_GY_SLEEP:
4394 *val = ISM330DLC_XL_12Hz5_GY_SLEEP;
4395 break;
4396
4397 case ISM330DLC_XL_12Hz5_GY_PD:
4398 *val = ISM330DLC_XL_12Hz5_GY_PD;
4399 break;
4400
4401 default:
4402 *val = ISM330DLC_PROPERTY_DISABLE;
4403 break;
4404 }
4405
4406 return ret;
4407 }
4408
4409 /**
4410 * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set]
4411 *
4412 * @param ctx Read / write interface definitions
4413 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4414 * @retval Interface status (MANDATORY: return 0 -> no Error).
4415 *
4416 */
ism330dlc_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4417 int32_t ism330dlc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4418 {
4419 ism330dlc_wake_up_dur_t wake_up_dur;
4420 int32_t ret;
4421 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4422 (uint8_t *)&wake_up_dur, 1);
4423
4424 if (ret == 0)
4425 {
4426 wake_up_dur.sleep_dur = val;
4427 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4428 (uint8_t *)&wake_up_dur, 1);
4429 }
4430
4431 return ret;
4432 }
4433
4434 /**
4435 * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get]
4436 *
4437 * @param ctx Read / write interface definitions
4438 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4439 * @retval Interface status (MANDATORY: return 0 -> no Error).
4440 *
4441 */
ism330dlc_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4442 int32_t ism330dlc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4443 {
4444 ism330dlc_wake_up_dur_t wake_up_dur;
4445 int32_t ret;
4446 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
4447 (uint8_t *)&wake_up_dur, 1);
4448 *val = wake_up_dur.sleep_dur;
4449
4450 return ret;
4451 }
4452
4453 /**
4454 * @}
4455 *
4456 */
4457
4458 /**
4459 * @defgroup ISM330DLC_tap_generator
4460 * @brief This section groups all the functions that manage the
4461 * tap and double tap event generation.
4462 * @{
4463 *
4464 */
4465
4466 /**
4467 * @brief Read the tap / double tap source register.[get]
4468 *
4469 * @param ctx Read / write interface definitions
4470 * @param val Structure of registers from TAP_SRC
4471 * @retval Interface status (MANDATORY: return 0 -> no Error).
4472 *
4473 */
ism330dlc_tap_src_get(const stmdev_ctx_t * ctx,ism330dlc_tap_src_t * val)4474 int32_t ism330dlc_tap_src_get(const stmdev_ctx_t *ctx,
4475 ism330dlc_tap_src_t *val)
4476 {
4477 int32_t ret;
4478 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_SRC, (uint8_t *) val, 1);
4479
4480 return ret;
4481 }
4482
4483 /**
4484 * @brief Enable Z direction in tap recognition.[set]
4485 *
4486 * @param ctx Read / write interface definitions
4487 * @param val Change the values of tap_z_en in reg TAP_CFG
4488 *
4489 */
ism330dlc_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)4490 int32_t ism330dlc_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
4491 uint8_t val)
4492 {
4493 ism330dlc_tap_cfg_t tap_cfg;
4494 int32_t ret;
4495 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4496
4497 if (ret == 0)
4498 {
4499 tap_cfg.tap_z_en = val;
4500 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4501 }
4502
4503 return ret;
4504 }
4505
4506 /**
4507 * @brief Enable Z direction in tap recognition.[get]
4508 *
4509 * @param ctx Read / write interface definitions
4510 * @param val Change the values of tap_z_en in reg TAP_CFG
4511 * @retval Interface status (MANDATORY: return 0 -> no Error).
4512 *
4513 */
ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4514 int32_t ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
4515 uint8_t *val)
4516 {
4517 ism330dlc_tap_cfg_t tap_cfg;
4518 int32_t ret;
4519 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4520 *val = tap_cfg.tap_z_en;
4521
4522 return ret;
4523 }
4524
4525 /**
4526 * @brief Enable Y direction in tap recognition.[set]
4527 *
4528 * @param ctx Read / write interface definitions
4529 * @param val Change the values of tap_y_en in reg TAP_CFG
4530 * @retval Interface status (MANDATORY: return 0 -> no Error).
4531 *
4532 */
ism330dlc_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)4533 int32_t ism330dlc_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
4534 uint8_t val)
4535 {
4536 ism330dlc_tap_cfg_t tap_cfg;
4537 int32_t ret;
4538 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4539
4540 if (ret == 0)
4541 {
4542 tap_cfg.tap_y_en = val;
4543 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4544 }
4545
4546 return ret;
4547 }
4548
4549 /**
4550 * @brief Enable Y direction in tap recognition.[get]
4551 *
4552 * @param ctx Read / write interface definitions
4553 * @param val Change the values of tap_y_en in reg TAP_CFG
4554 * @retval Interface status (MANDATORY: return 0 -> no Error).
4555 *
4556 */
ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4557 int32_t ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
4558 uint8_t *val)
4559 {
4560 ism330dlc_tap_cfg_t tap_cfg;
4561 int32_t ret;
4562 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4563 *val = tap_cfg.tap_y_en;
4564
4565 return ret;
4566 }
4567
4568 /**
4569 * @brief Enable X direction in tap recognition.[set]
4570 *
4571 * @param ctx Read / write interface definitions
4572 * @param val Change the values of tap_x_en in reg TAP_CFG
4573 * @retval Interface status (MANDATORY: return 0 -> no Error).
4574 *
4575 */
ism330dlc_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)4576 int32_t ism330dlc_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
4577 uint8_t val)
4578 {
4579 ism330dlc_tap_cfg_t tap_cfg;
4580 int32_t ret;
4581 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4582
4583 if (ret == 0)
4584 {
4585 tap_cfg.tap_x_en = val;
4586 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4587 }
4588
4589 return ret;
4590 }
4591
4592 /**
4593 * @brief Enable X direction in tap recognition.[get]
4594 *
4595 * @param ctx Read / write interface definitions
4596 * @param val Change the values of tap_x_en in reg TAP_CFG
4597 * @retval Interface status (MANDATORY: return 0 -> no Error).
4598 *
4599 */
ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4600 int32_t ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
4601 uint8_t *val)
4602 {
4603 ism330dlc_tap_cfg_t tap_cfg;
4604 int32_t ret;
4605 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4606 *val = tap_cfg.tap_x_en;
4607
4608 return ret;
4609 }
4610
4611 /**
4612 * @brief Threshold for tap recognition.[set]
4613 *
4614 * @param ctx Read / write interface definitions
4615 * @param val Change the values of tap_ths in reg TAP_THS_6D
4616 * @retval Interface status (MANDATORY: return 0 -> no Error).
4617 *
4618 */
ism330dlc_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)4619 int32_t ism330dlc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
4620 {
4621 ism330dlc_tap_ths_6d_t tap_ths_6d;
4622 int32_t ret;
4623 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
4624 (uint8_t *)&tap_ths_6d, 1);
4625
4626 if (ret == 0)
4627 {
4628 tap_ths_6d.tap_ths = val;
4629 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
4630 (uint8_t *)&tap_ths_6d, 1);
4631 }
4632
4633 return ret;
4634 }
4635
4636 /**
4637 * @brief Threshold for tap recognition.[get]
4638 *
4639 * @param ctx Read / write interface definitions
4640 * @param val Change the values of tap_ths in reg TAP_THS_6D
4641 * @retval Interface status (MANDATORY: return 0 -> no Error).
4642 *
4643 */
ism330dlc_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4644 int32_t ism330dlc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
4645 {
4646 ism330dlc_tap_ths_6d_t tap_ths_6d;
4647 int32_t ret;
4648 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
4649 (uint8_t *)&tap_ths_6d, 1);
4650 *val = tap_ths_6d.tap_ths;
4651
4652 return ret;
4653 }
4654
4655 /**
4656 * @brief Maximum duration is the maximum time of an overthreshold signal
4657 * detection to be recognized as a tap event.
4658 * The default value of these bits is 00b which corresponds to
4659 * 4*ODR_XL time.
4660 * If the SHOCK[1:0] bits are set to a different
4661 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4662 *
4663 * @param ctx Read / write interface definitions
4664 * @param val Change the values of shock in reg INT_DUR2
4665 * @retval Interface status (MANDATORY: return 0 -> no Error).
4666 *
4667 */
ism330dlc_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)4668 int32_t ism330dlc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
4669 {
4670 ism330dlc_int_dur2_t int_dur2;
4671 int32_t ret;
4672 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4673 (uint8_t *)&int_dur2, 1);
4674
4675 if (ret == 0)
4676 {
4677 int_dur2.shock = val;
4678 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
4679 (uint8_t *)&int_dur2, 1);
4680 }
4681
4682 return ret;
4683 }
4684
4685 /**
4686 * @brief Maximum duration is the maximum time of an overthreshold signal
4687 * detection to be recognized as a tap event.
4688 * The default value of these bits is 00b which corresponds to
4689 * 4*ODR_XL time.
4690 * If the SHOCK[1:0] bits are set to a different value, 1LSB
4691 * corresponds to 8*ODR_XL time.[get]
4692 *
4693 * @param ctx Read / write interface definitions
4694 * @param val Change the values of shock in reg INT_DUR2
4695 * @retval Interface status (MANDATORY: return 0 -> no Error).
4696 *
4697 */
ism330dlc_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)4698 int32_t ism330dlc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
4699 {
4700 ism330dlc_int_dur2_t int_dur2;
4701 int32_t ret;
4702 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4703 (uint8_t *)&int_dur2, 1);
4704 *val = int_dur2.shock;
4705
4706 return ret;
4707 }
4708
4709 /**
4710 * @brief Quiet time is the time after the first detected tap in which there
4711 * must not be any overthreshold event.
4712 * The default value of these bits is 00b which corresponds to
4713 * 2*ODR_XL time.
4714 * If the QUIET[1:0] bits are set to a different value, 1LSB
4715 * corresponds to 4*ODR_XL time.[set]
4716 *
4717 * @param ctx Read / write interface definitions
4718 * @param val Change the values of quiet in reg INT_DUR2
4719 * @retval Interface status (MANDATORY: return 0 -> no Error).
4720 *
4721 */
ism330dlc_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)4722 int32_t ism330dlc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
4723 {
4724 ism330dlc_int_dur2_t int_dur2;
4725 int32_t ret;
4726 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4727 (uint8_t *)&int_dur2, 1);
4728
4729 if (ret == 0)
4730 {
4731 int_dur2.quiet = val;
4732 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
4733 (uint8_t *)&int_dur2, 1);
4734 }
4735
4736 return ret;
4737 }
4738
4739 /**
4740 * @brief Quiet time is the time after the first detected tap in which there
4741 * must not be any overthreshold event.
4742 * The default value of these bits is 00b which corresponds to
4743 * 2*ODR_XL time.
4744 * If the QUIET[1:0] bits are set to a different value, 1LSB
4745 * corresponds to 4*ODR_XL time.[get]
4746 *
4747 * @param ctx Read / write interface definitions
4748 * @param val Change the values of quiet in reg INT_DUR2
4749 * @retval Interface status (MANDATORY: return 0 -> no Error).
4750 *
4751 */
ism330dlc_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)4752 int32_t ism330dlc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
4753 {
4754 ism330dlc_int_dur2_t int_dur2;
4755 int32_t ret;
4756 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4757 (uint8_t *)&int_dur2, 1);
4758 *val = int_dur2.quiet;
4759
4760 return ret;
4761 }
4762
4763 /**
4764 * @brief When double tap recognition is enabled, this register expresses the
4765 * maximum time between two consecutive detected taps to determine a
4766 * double tap event.
4767 * The default value of these bits is 0000b which corresponds to
4768 * 16*ODR_XL time.
4769 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4770 * to 32*ODR_XL time.[set]
4771 *
4772 * @param ctx Read / write interface definitions
4773 * @param val Change the values of dur in reg INT_DUR2
4774 * @retval Interface status (MANDATORY: return 0 -> no Error).
4775 *
4776 */
ism330dlc_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4777 int32_t ism330dlc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4778 {
4779 ism330dlc_int_dur2_t int_dur2;
4780 int32_t ret;
4781 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4782 (uint8_t *)&int_dur2, 1);
4783
4784 if (ret == 0)
4785 {
4786 int_dur2.dur = val;
4787 ret = ism330dlc_write_reg(ctx, ISM330DLC_INT_DUR2,
4788 (uint8_t *)&int_dur2, 1);
4789 }
4790
4791 return ret;
4792 }
4793
4794 /**
4795 * @brief When double tap recognition is enabled, this register expresses the
4796 * maximum time between two consecutive detected taps to determine a
4797 * double tap event.
4798 * The default value of these bits is 0000b which corresponds to
4799 * 16*ODR_XL time.
4800 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4801 * to 32*ODR_XL time.[get]
4802 *
4803 * @param ctx Read / write interface definitions
4804 * @param val Change the values of dur in reg INT_DUR2
4805 * @retval Interface status (MANDATORY: return 0 -> no Error).
4806 *
4807 */
ism330dlc_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4808 int32_t ism330dlc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4809 {
4810 ism330dlc_int_dur2_t int_dur2;
4811 int32_t ret;
4812 ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2,
4813 (uint8_t *)&int_dur2, 1);
4814 *val = int_dur2.dur;
4815
4816 return ret;
4817 }
4818
4819 /**
4820 * @brief Single/double-tap event enable/disable.[set]
4821 *
4822 * @param ctx Read / write interface definitions
4823 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
4824 * @retval Interface status (MANDATORY: return 0 -> no Error).
4825 *
4826 */
ism330dlc_tap_mode_set(const stmdev_ctx_t * ctx,ism330dlc_single_double_tap_t val)4827 int32_t ism330dlc_tap_mode_set(const stmdev_ctx_t *ctx,
4828 ism330dlc_single_double_tap_t val)
4829 {
4830 ism330dlc_wake_up_ths_t wake_up_ths;
4831 int32_t ret;
4832 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
4833 (uint8_t *)&wake_up_ths, 1);
4834
4835 if (ret == 0)
4836 {
4837 wake_up_ths.single_double_tap = (uint8_t) val;
4838 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_THS,
4839 (uint8_t *)&wake_up_ths, 1);
4840 }
4841
4842 return ret;
4843 }
4844
4845 /**
4846 * @brief Single/double-tap event enable/disable.[get]
4847 *
4848 * @param ctx Read / write interface definitions
4849 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
4850 * @retval Interface status (MANDATORY: return 0 -> no Error).
4851 *
4852 */
ism330dlc_tap_mode_get(const stmdev_ctx_t * ctx,ism330dlc_single_double_tap_t * val)4853 int32_t ism330dlc_tap_mode_get(const stmdev_ctx_t *ctx,
4854 ism330dlc_single_double_tap_t *val)
4855 {
4856 ism330dlc_wake_up_ths_t wake_up_ths;
4857 int32_t ret;
4858 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS,
4859 (uint8_t *)&wake_up_ths, 1);
4860
4861 switch (wake_up_ths.single_double_tap)
4862 {
4863 case ISM330DLC_ONLY_SINGLE:
4864 *val = ISM330DLC_ONLY_SINGLE;
4865 break;
4866
4867 case ISM330DLC_BOTH_SINGLE_DOUBLE:
4868 *val = ISM330DLC_BOTH_SINGLE_DOUBLE;
4869 break;
4870
4871 default:
4872 *val = ISM330DLC_ONLY_SINGLE;
4873 break;
4874 }
4875
4876 return ret;
4877 }
4878
4879 /**
4880 * @}
4881 *
4882 */
4883
4884 /**
4885 * @defgroup ISM330DLC_ Six_position_detection(6D/4D)
4886 * @brief This section groups all the functions concerning six
4887 * position detection (6D).
4888 * @{
4889 *
4890 */
4891
4892 /**
4893 * @brief LPF2 feed 6D function selection.[set]
4894 *
4895 * @param ctx Read / write interface definitions
4896 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
4897 * @retval Interface status (MANDATORY: return 0 -> no Error).
4898 *
4899 */
ism330dlc_6d_feed_data_set(const stmdev_ctx_t * ctx,ism330dlc_low_pass_on_6d_t val)4900 int32_t ism330dlc_6d_feed_data_set(const stmdev_ctx_t *ctx,
4901 ism330dlc_low_pass_on_6d_t val)
4902 {
4903 ism330dlc_ctrl8_xl_t ctrl8_xl;
4904 int32_t ret;
4905 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
4906 (uint8_t *)&ctrl8_xl, 1);
4907
4908 if (ret == 0)
4909 {
4910 ctrl8_xl.low_pass_on_6d = (uint8_t) val;
4911 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL8_XL,
4912 (uint8_t *)&ctrl8_xl, 1);
4913 }
4914
4915 return ret;
4916 }
4917
4918 /**
4919 * @brief LPF2 feed 6D function selection.[get]
4920 *
4921 * @param ctx Read / write interface definitions
4922 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
4923 * @retval Interface status (MANDATORY: return 0 -> no Error).
4924 *
4925 */
ism330dlc_6d_feed_data_get(const stmdev_ctx_t * ctx,ism330dlc_low_pass_on_6d_t * val)4926 int32_t ism330dlc_6d_feed_data_get(const stmdev_ctx_t *ctx,
4927 ism330dlc_low_pass_on_6d_t *val)
4928 {
4929 ism330dlc_ctrl8_xl_t ctrl8_xl;
4930 int32_t ret;
4931 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL,
4932 (uint8_t *)&ctrl8_xl, 1);
4933
4934 switch (ctrl8_xl.low_pass_on_6d)
4935 {
4936 case ISM330DLC_ODR_DIV_2_FEED:
4937 *val = ISM330DLC_ODR_DIV_2_FEED;
4938 break;
4939
4940 case ISM330DLC_LPF2_FEED:
4941 *val = ISM330DLC_LPF2_FEED;
4942 break;
4943
4944 default:
4945 *val = ISM330DLC_ODR_DIV_2_FEED;
4946 break;
4947 }
4948
4949 return ret;
4950 }
4951
4952 /**
4953 * @brief Threshold for 4D/6D function.[set]
4954 *
4955 * @param ctx Read / write interface definitions
4956 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4957 * @retval Interface status (MANDATORY: return 0 -> no Error).
4958 *
4959 */
ism330dlc_6d_threshold_set(const stmdev_ctx_t * ctx,ism330dlc_sixd_ths_t val)4960 int32_t ism330dlc_6d_threshold_set(const stmdev_ctx_t *ctx,
4961 ism330dlc_sixd_ths_t val)
4962 {
4963 ism330dlc_tap_ths_6d_t tap_ths_6d;
4964 int32_t ret;
4965 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
4966 (uint8_t *)&tap_ths_6d, 1);
4967
4968 if (ret == 0)
4969 {
4970 tap_ths_6d.sixd_ths = (uint8_t) val;
4971 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
4972 (uint8_t *)&tap_ths_6d, 1);
4973 }
4974
4975 return ret;
4976 }
4977
4978 /**
4979 * @brief Threshold for 4D/6D function.[get]
4980 *
4981 * @param ctx Read / write interface definitions
4982 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4983 * @retval Interface status (MANDATORY: return 0 -> no Error).
4984 *
4985 */
ism330dlc_6d_threshold_get(const stmdev_ctx_t * ctx,ism330dlc_sixd_ths_t * val)4986 int32_t ism330dlc_6d_threshold_get(const stmdev_ctx_t *ctx,
4987 ism330dlc_sixd_ths_t *val)
4988 {
4989 ism330dlc_tap_ths_6d_t tap_ths_6d;
4990 int32_t ret;
4991 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
4992 (uint8_t *)&tap_ths_6d, 1);
4993
4994 switch (tap_ths_6d.sixd_ths)
4995 {
4996 case ISM330DLC_DEG_80:
4997 *val = ISM330DLC_DEG_80;
4998 break;
4999
5000 case ISM330DLC_DEG_70:
5001 *val = ISM330DLC_DEG_70;
5002 break;
5003
5004 case ISM330DLC_DEG_60:
5005 *val = ISM330DLC_DEG_60;
5006 break;
5007
5008 case ISM330DLC_DEG_50:
5009 *val = ISM330DLC_DEG_50;
5010 break;
5011
5012 default:
5013 *val = ISM330DLC_DEG_80;
5014 break;
5015 }
5016
5017 return ret;
5018 }
5019
5020 /**
5021 * @brief 4D orientation detection enable.[set]
5022 *
5023 * @param ctx Read / write interface definitions
5024 * @param val Change the values of d4d_en in reg TAP_THS_6D
5025 * @retval Interface status (MANDATORY: return 0 -> no Error).
5026 *
5027 */
ism330dlc_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5028 int32_t ism330dlc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5029 {
5030 ism330dlc_tap_ths_6d_t tap_ths_6d;
5031 int32_t ret;
5032 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
5033 (uint8_t *)&tap_ths_6d, 1);
5034
5035 if (ret == 0)
5036 {
5037 tap_ths_6d.d4d_en = val;
5038 ret = ism330dlc_write_reg(ctx, ISM330DLC_TAP_THS_6D,
5039 (uint8_t *)&tap_ths_6d, 1);
5040 }
5041
5042 return ret;
5043 }
5044
5045 /**
5046 * @brief 4D orientation detection enable.[get]
5047 *
5048 * @param ctx Read / write interface definitions
5049 * @param val Change the values of d4d_en in reg TAP_THS_6D
5050 * @retval Interface status (MANDATORY: return 0 -> no Error).
5051 *
5052 */
ism330dlc_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5053 int32_t ism330dlc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5054 {
5055 ism330dlc_tap_ths_6d_t tap_ths_6d;
5056 int32_t ret;
5057 ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D,
5058 (uint8_t *)&tap_ths_6d, 1);
5059 *val = tap_ths_6d.d4d_en;
5060
5061 return ret;
5062 }
5063
5064 /**
5065 * @}
5066 *
5067 */
5068
5069 /**
5070 * @defgroup ISM330DLC_free_fall
5071 * @brief This section group all the functions concerning the free
5072 * fall detection.
5073 * @{
5074 *
5075 */
5076
5077 /**
5078 * @brief Free-fall duration event. 1LSb = 1 / ODR[set]
5079 *
5080 * @param ctx Read / write interface definitions
5081 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5082 * @retval Interface status (MANDATORY: return 0 -> no Error).
5083 *
5084 */
ism330dlc_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5085 int32_t ism330dlc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5086 {
5087 ism330dlc_wake_up_dur_t wake_up_dur;
5088 ism330dlc_free_fall_t free_fall;
5089 int32_t ret;
5090 ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
5091 (uint8_t *)&free_fall, 1);
5092
5093 if (ret == 0)
5094 {
5095 free_fall.ff_dur = (val & 0x1FU);
5096 ret = ism330dlc_write_reg(ctx, ISM330DLC_FREE_FALL,
5097 (uint8_t *)&free_fall, 1);
5098
5099 if (ret == 0)
5100 {
5101 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
5102 (uint8_t *)&wake_up_dur, 1);
5103
5104 if (ret == 0)
5105 {
5106 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
5107 ret = ism330dlc_write_reg(ctx, ISM330DLC_WAKE_UP_DUR,
5108 (uint8_t *)&wake_up_dur, 1);
5109 }
5110 }
5111 }
5112
5113 return ret;
5114 }
5115
5116 /**
5117 * @brief Free-fall duration event. 1LSb = 1 / ODR[get]
5118 *
5119 * @param ctx Read / write interface definitions
5120 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5121 * @retval Interface status (MANDATORY: return 0 -> no Error).
5122 *
5123 */
ism330dlc_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5124 int32_t ism330dlc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5125 {
5126 ism330dlc_wake_up_dur_t wake_up_dur;
5127 ism330dlc_free_fall_t free_fall;
5128 int32_t ret;
5129 ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR,
5130 (uint8_t *)&wake_up_dur, 1);
5131
5132 if (ret == 0)
5133 {
5134 ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
5135 (uint8_t *)&free_fall, 1);
5136 }
5137
5138 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5139
5140 return ret;
5141 }
5142
5143 /**
5144 * @brief Free fall threshold setting.[set]
5145 *
5146 * @param ctx Read / write interface definitions
5147 * @param val Change the values of ff_ths in reg FREE_FALL
5148 * @retval Interface status (MANDATORY: return 0 -> no Error).
5149 *
5150 */
ism330dlc_ff_threshold_set(const stmdev_ctx_t * ctx,ism330dlc_ff_ths_t val)5151 int32_t ism330dlc_ff_threshold_set(const stmdev_ctx_t *ctx,
5152 ism330dlc_ff_ths_t val)
5153 {
5154 ism330dlc_free_fall_t free_fall;
5155 int32_t ret;
5156 ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
5157 (uint8_t *)&free_fall, 1);
5158
5159 if (ret == 0)
5160 {
5161 free_fall.ff_ths = (uint8_t) val;
5162 ret = ism330dlc_write_reg(ctx, ISM330DLC_FREE_FALL,
5163 (uint8_t *)&free_fall, 1);
5164 }
5165
5166 return ret;
5167 }
5168
5169 /**
5170 * @brief Free fall threshold setting.[get]
5171 *
5172 * @param ctx Read / write interface definitions
5173 * @param val Get the values of ff_ths in reg FREE_FALL
5174 * @retval Interface status (MANDATORY: return 0 -> no Error).
5175 *
5176 */
ism330dlc_ff_threshold_get(const stmdev_ctx_t * ctx,ism330dlc_ff_ths_t * val)5177 int32_t ism330dlc_ff_threshold_get(const stmdev_ctx_t *ctx,
5178 ism330dlc_ff_ths_t *val)
5179 {
5180 ism330dlc_free_fall_t free_fall;
5181 int32_t ret;
5182 ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL,
5183 (uint8_t *)&free_fall, 1);
5184
5185 switch (free_fall.ff_ths)
5186 {
5187 case ISM330DLC_FF_TSH_156mg:
5188 *val = ISM330DLC_FF_TSH_156mg;
5189 break;
5190
5191 case ISM330DLC_FF_TSH_219mg:
5192 *val = ISM330DLC_FF_TSH_219mg;
5193 break;
5194
5195 case ISM330DLC_FF_TSH_250mg:
5196 *val = ISM330DLC_FF_TSH_250mg;
5197 break;
5198
5199 case ISM330DLC_FF_TSH_312mg:
5200 *val = ISM330DLC_FF_TSH_312mg;
5201 break;
5202
5203 case ISM330DLC_FF_TSH_344mg:
5204 *val = ISM330DLC_FF_TSH_344mg;
5205 break;
5206
5207 case ISM330DLC_FF_TSH_406mg:
5208 *val = ISM330DLC_FF_TSH_406mg;
5209 break;
5210
5211 case ISM330DLC_FF_TSH_469mg:
5212 *val = ISM330DLC_FF_TSH_469mg;
5213 break;
5214
5215 case ISM330DLC_FF_TSH_500mg:
5216 *val = ISM330DLC_FF_TSH_500mg;
5217 break;
5218
5219 default:
5220 *val = ISM330DLC_FF_TSH_156mg;
5221 break;
5222 }
5223
5224 return ret;
5225 }
5226
5227 /**
5228 * @}
5229 *
5230 */
5231
5232 /**
5233 * @defgroup ISM330DLC_fifo
5234 * @brief This section group all the functions concerning the
5235 * fifo usage
5236 * @{
5237 *
5238 */
5239
5240 /**
5241 * @brief FIFO watermark level selection.[set]
5242 *
5243 * @param ctx Read / write interface definitions
5244 * @param val Change the values of fth in reg FIFO_CTRL1
5245 * @retval Interface status (MANDATORY: return 0 -> no Error).
5246 *
5247 */
ism330dlc_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)5248 int32_t ism330dlc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
5249 {
5250 ism330dlc_fifo_ctrl1_t fifo_ctrl1;
5251 ism330dlc_fifo_ctrl2_t fifo_ctrl2;
5252 int32_t ret;
5253 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
5254 (uint8_t *)&fifo_ctrl2, 1);
5255
5256 if (ret == 0)
5257 {
5258 fifo_ctrl2.fth = (uint8_t)(uint8_t)(val / 256U);
5259 fifo_ctrl1.fth = (uint8_t)(uint8_t)(val - (fifo_ctrl2.fth * 256U));
5260 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL1,
5261 (uint8_t *)&fifo_ctrl1, 1);
5262
5263 if (ret == 0)
5264 {
5265 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL2,
5266 (uint8_t *)&fifo_ctrl2, 1);
5267 }
5268 }
5269
5270 return ret;
5271 }
5272
5273 /**
5274 * @brief FIFO watermark level selection.[get]
5275 *
5276 * @param ctx Read / write interface definitions
5277 * @param val Change the values of fth in reg FIFO_CTRL1
5278 * @retval Interface status (MANDATORY: return 0 -> no Error).
5279 *
5280 */
ism330dlc_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)5281 int32_t ism330dlc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
5282 {
5283 ism330dlc_fifo_ctrl1_t fifo_ctrl1;
5284 ism330dlc_fifo_ctrl2_t fifo_ctrl2;
5285 int32_t ret;
5286 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL1,
5287 (uint8_t *)&fifo_ctrl1, 1);
5288
5289 if (ret == 0)
5290 {
5291 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
5292 (uint8_t *)&fifo_ctrl2, 1);
5293 }
5294
5295 *val = fifo_ctrl2.fth;
5296 *val = (*val * 256U) + fifo_ctrl1.fth;
5297
5298 return ret;
5299 }
5300
5301 /**
5302 * @brief FIFO data level.[get]
5303 *
5304 * @param ctx Read / write interface definitions
5305 * @param val get the values of diff_fifo in reg FIFO_STATUS1 and
5306 * FIFO_STATUS2(diff_fifo), it is recommended to set the
5307 * BDU bit.
5308 * @retval Interface status (MANDATORY: return 0 -> no Error).
5309 *
5310 */
ism330dlc_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5311 int32_t ism330dlc_fifo_data_level_get(const stmdev_ctx_t *ctx,
5312 uint16_t *val)
5313 {
5314 ism330dlc_fifo_status1_t fifo_status1;
5315 ism330dlc_fifo_status2_t fifo_status2;
5316 int32_t ret;
5317 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS1,
5318 (uint8_t *)&fifo_status1, 1);
5319
5320 if (ret == 0)
5321 {
5322 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2,
5323 (uint8_t *)&fifo_status2, 1);
5324 *val = fifo_status2.diff_fifo;
5325 *val = (*val * 256U) + fifo_status1.diff_fifo;
5326 }
5327
5328 return ret;
5329 }
5330
5331 /**
5332 * @brief FIFO watermark.[get]
5333 *
5334 * @param ctx Read / write interface definitions
5335 * @param val get the values of watermark in reg FIFO_STATUS2 and
5336 * @retval Interface status (MANDATORY: return 0 -> no Error).
5337 *
5338 */
ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5339 int32_t ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5340 {
5341 ism330dlc_fifo_status2_t fifo_status2;
5342 int32_t ret;
5343 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2,
5344 (uint8_t *)&fifo_status2, 1);
5345 *val = fifo_status2.waterm;
5346
5347 return ret;
5348 }
5349
5350 /**
5351 * @brief FIFO pattern.[get]
5352 *
5353 * @param ctx Read / write interface definitions
5354 * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and
5355 * FIFO_STATUS4, it is recommended to set the BDU bit
5356 * @retval Interface status (MANDATORY: return 0 -> no Error).
5357 *
5358 */
ism330dlc_fifo_pattern_get(const stmdev_ctx_t * ctx,uint16_t * val)5359 int32_t ism330dlc_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val)
5360 {
5361 ism330dlc_fifo_status3_t fifo_status3;
5362 ism330dlc_fifo_status4_t fifo_status4;
5363 int32_t ret;
5364 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS3,
5365 (uint8_t *)&fifo_status3, 1);
5366
5367 if (ret == 0)
5368 {
5369 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS4,
5370 (uint8_t *)&fifo_status4, 1);
5371 *val = fifo_status4.fifo_pattern;
5372 *val = (*val * 256U) + fifo_status3.fifo_pattern;
5373 }
5374
5375 return ret;
5376 }
5377
5378 /**
5379 * @brief Batching of temperature data[set]
5380 *
5381 * @param ctx Read / write interface definitions
5382 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5383 * @retval Interface status (MANDATORY: return 0 -> no Error).
5384 *
5385 */
ism330dlc_fifo_temp_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5386 int32_t ism330dlc_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5387 {
5388 ism330dlc_fifo_ctrl2_t fifo_ctrl2;
5389 int32_t ret;
5390 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
5391 (uint8_t *)&fifo_ctrl2, 1);
5392
5393 if (ret == 0)
5394 {
5395 fifo_ctrl2.fifo_temp_en = val;
5396 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL2,
5397 (uint8_t *)&fifo_ctrl2, 1);
5398 }
5399
5400 return ret;
5401 }
5402
5403 /**
5404 * @brief Batching of temperature data[get]
5405 *
5406 * @param ctx Read / write interface definitions
5407 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5408 * @retval Interface status (MANDATORY: return 0 -> no Error).
5409 *
5410 */
ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5411 int32_t ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5412 {
5413 ism330dlc_fifo_ctrl2_t fifo_ctrl2;
5414 int32_t ret;
5415 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2,
5416 (uint8_t *)&fifo_ctrl2, 1);
5417 *val = fifo_ctrl2.fifo_temp_en;
5418
5419 return ret;
5420 }
5421
5422 /**
5423 * @brief Trigger signal for FIFO write operation.[set]
5424 *
5425 * @param ctx Read / write interface definitions
5426 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
5427 * and MASTER_CONFIG(data_valid_sel_fifo)
5428 * @retval Interface status (MANDATORY: return 0 -> no Error).
5429 *
5430 */
ism330dlc_fifo_write_trigger_set(const stmdev_ctx_t * ctx,ism330dlc_trigger_fifo_t val)5431 int32_t ism330dlc_fifo_write_trigger_set(const stmdev_ctx_t *ctx,
5432 ism330dlc_trigger_fifo_t val)
5433 {
5434 ism330dlc_master_config_t master_config;
5435 int32_t ret;
5436 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
5437 (uint8_t *)&master_config, 1);
5438
5439 if (ret == 0)
5440 {
5441 master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
5442 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
5443 (uint8_t *)&master_config, 1);
5444 }
5445
5446 return ret;
5447 }
5448
5449 /**
5450 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5451 * accelerometer data.[set]
5452 *
5453 * @param ctx Read / write interface definitions
5454 * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3
5455 * @retval Interface status (MANDATORY: return 0 -> no Error).
5456 *
5457 */
ism330dlc_fifo_xl_batch_set(const stmdev_ctx_t * ctx,ism330dlc_dec_fifo_xl_t val)5458 int32_t ism330dlc_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5459 ism330dlc_dec_fifo_xl_t val)
5460 {
5461 ism330dlc_fifo_ctrl3_t fifo_ctrl3;
5462 int32_t ret;
5463 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
5464 (uint8_t *)&fifo_ctrl3, 1);
5465
5466 if (ret == 0)
5467 {
5468 fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
5469 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL3,
5470 (uint8_t *)&fifo_ctrl3, 1);
5471 }
5472
5473 return ret;
5474 }
5475
5476 /**
5477 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5478 * accelerometer data.[get]
5479 *
5480 * @param ctx Read / write interface definitions
5481 * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3
5482 * @retval Interface status (MANDATORY: return 0 -> no Error).
5483 *
5484 */
ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t * ctx,ism330dlc_dec_fifo_xl_t * val)5485 int32_t ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5486 ism330dlc_dec_fifo_xl_t *val)
5487 {
5488 ism330dlc_fifo_ctrl3_t fifo_ctrl3;
5489 int32_t ret;
5490 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
5491 (uint8_t *)&fifo_ctrl3, 1);
5492
5493 switch (fifo_ctrl3.dec_fifo_xl)
5494 {
5495 case ISM330DLC_FIFO_XL_DISABLE:
5496 *val = ISM330DLC_FIFO_XL_DISABLE;
5497 break;
5498
5499 case ISM330DLC_FIFO_XL_NO_DEC:
5500 *val = ISM330DLC_FIFO_XL_NO_DEC;
5501 break;
5502
5503 case ISM330DLC_FIFO_XL_DEC_2:
5504 *val = ISM330DLC_FIFO_XL_DEC_2;
5505 break;
5506
5507 case ISM330DLC_FIFO_XL_DEC_3:
5508 *val = ISM330DLC_FIFO_XL_DEC_3;
5509 break;
5510
5511 case ISM330DLC_FIFO_XL_DEC_4:
5512 *val = ISM330DLC_FIFO_XL_DEC_4;
5513 break;
5514
5515 case ISM330DLC_FIFO_XL_DEC_8:
5516 *val = ISM330DLC_FIFO_XL_DEC_8;
5517 break;
5518
5519 case ISM330DLC_FIFO_XL_DEC_16:
5520 *val = ISM330DLC_FIFO_XL_DEC_16;
5521 break;
5522
5523 case ISM330DLC_FIFO_XL_DEC_32:
5524 *val = ISM330DLC_FIFO_XL_DEC_32;
5525 break;
5526
5527 default:
5528 *val = ISM330DLC_FIFO_XL_DISABLE;
5529 break;
5530 }
5531
5532 return ret;
5533 }
5534
5535 /**
5536 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5537 * for gyroscope data.[set]
5538 *
5539 * @param ctx Read / write interface definitions
5540 * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3
5541 * @retval Interface status (MANDATORY: return 0 -> no Error).
5542 *
5543 */
ism330dlc_fifo_gy_batch_set(const stmdev_ctx_t * ctx,ism330dlc_dec_fifo_gyro_t val)5544 int32_t ism330dlc_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5545 ism330dlc_dec_fifo_gyro_t val)
5546 {
5547 ism330dlc_fifo_ctrl3_t fifo_ctrl3;
5548 int32_t ret;
5549 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
5550 (uint8_t *)&fifo_ctrl3, 1);
5551
5552 if (ret == 0)
5553 {
5554 fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
5555 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL3,
5556 (uint8_t *)&fifo_ctrl3, 1);
5557 }
5558
5559 return ret;
5560 }
5561
5562 /**
5563 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5564 * for gyroscope data.[get]
5565 *
5566 * @param ctx Read / write interface definitions
5567 * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3
5568 * @retval Interface status (MANDATORY: return 0 -> no Error).
5569 *
5570 */
ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t * ctx,ism330dlc_dec_fifo_gyro_t * val)5571 int32_t ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5572 ism330dlc_dec_fifo_gyro_t *val)
5573 {
5574 ism330dlc_fifo_ctrl3_t fifo_ctrl3;
5575 int32_t ret;
5576 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3,
5577 (uint8_t *)&fifo_ctrl3, 1);
5578
5579 switch (fifo_ctrl3.dec_fifo_gyro)
5580 {
5581 case ISM330DLC_FIFO_GY_DISABLE:
5582 *val = ISM330DLC_FIFO_GY_DISABLE;
5583 break;
5584
5585 case ISM330DLC_FIFO_GY_NO_DEC:
5586 *val = ISM330DLC_FIFO_GY_NO_DEC;
5587 break;
5588
5589 case ISM330DLC_FIFO_GY_DEC_2:
5590 *val = ISM330DLC_FIFO_GY_DEC_2;
5591 break;
5592
5593 case ISM330DLC_FIFO_GY_DEC_3:
5594 *val = ISM330DLC_FIFO_GY_DEC_3;
5595 break;
5596
5597 case ISM330DLC_FIFO_GY_DEC_4:
5598 *val = ISM330DLC_FIFO_GY_DEC_4;
5599 break;
5600
5601 case ISM330DLC_FIFO_GY_DEC_8:
5602 *val = ISM330DLC_FIFO_GY_DEC_8;
5603 break;
5604
5605 case ISM330DLC_FIFO_GY_DEC_16:
5606 *val = ISM330DLC_FIFO_GY_DEC_16;
5607 break;
5608
5609 case ISM330DLC_FIFO_GY_DEC_32:
5610 *val = ISM330DLC_FIFO_GY_DEC_32;
5611 break;
5612
5613 default:
5614 *val = ISM330DLC_FIFO_GY_DISABLE;
5615 break;
5616 }
5617
5618 return ret;
5619 }
5620
5621 /**
5622 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5623 * for third data set.[set]
5624 *
5625 * @param ctx Read / write interface definitions
5626 * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4
5627 * @retval Interface status (MANDATORY: return 0 -> no Error).
5628 *
5629 */
ism330dlc_fifo_dataset_3_batch_set(const stmdev_ctx_t * ctx,ism330dlc_dec_ds3_fifo_t val)5630 int32_t ism330dlc_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx,
5631 ism330dlc_dec_ds3_fifo_t val)
5632 {
5633 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5634 int32_t ret;
5635 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5636 (uint8_t *)&fifo_ctrl4, 1);
5637
5638 if (ret == 0)
5639 {
5640 fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
5641 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
5642 (uint8_t *)&fifo_ctrl4, 1);
5643 }
5644
5645 return ret;
5646 }
5647
5648 /**
5649 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5650 * for third data set.[get]
5651 *
5652 * @param ctx Read / write interface definitions
5653 * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4
5654 * @retval Interface status (MANDATORY: return 0 -> no Error).
5655 *
5656 */
ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t * ctx,ism330dlc_dec_ds3_fifo_t * val)5657 int32_t ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx,
5658 ism330dlc_dec_ds3_fifo_t *val)
5659 {
5660 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5661 int32_t ret;
5662 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5663 (uint8_t *)&fifo_ctrl4, 1);
5664
5665 switch (fifo_ctrl4.dec_ds3_fifo)
5666 {
5667 case ISM330DLC_FIFO_DS3_DISABLE:
5668 *val = ISM330DLC_FIFO_DS3_DISABLE;
5669 break;
5670
5671 case ISM330DLC_FIFO_DS3_NO_DEC:
5672 *val = ISM330DLC_FIFO_DS3_NO_DEC;
5673 break;
5674
5675 case ISM330DLC_FIFO_DS3_DEC_2:
5676 *val = ISM330DLC_FIFO_DS3_DEC_2;
5677 break;
5678
5679 case ISM330DLC_FIFO_DS3_DEC_3:
5680 *val = ISM330DLC_FIFO_DS3_DEC_3;
5681 break;
5682
5683 case ISM330DLC_FIFO_DS3_DEC_4:
5684 *val = ISM330DLC_FIFO_DS3_DEC_4;
5685 break;
5686
5687 case ISM330DLC_FIFO_DS3_DEC_8:
5688 *val = ISM330DLC_FIFO_DS3_DEC_8;
5689 break;
5690
5691 case ISM330DLC_FIFO_DS3_DEC_16:
5692 *val = ISM330DLC_FIFO_DS3_DEC_16;
5693 break;
5694
5695 case ISM330DLC_FIFO_DS3_DEC_32:
5696 *val = ISM330DLC_FIFO_DS3_DEC_32;
5697 break;
5698
5699 default:
5700 *val = ISM330DLC_FIFO_DS3_DISABLE;
5701 break;
5702 }
5703
5704 return ret;
5705 }
5706
5707 /**
5708 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5709 * for fourth data set.[set]
5710 *
5711 * @param ctx Read / write interface definitions
5712 * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4
5713 * @retval Interface status (MANDATORY: return 0 -> no Error).
5714 *
5715 */
ism330dlc_fifo_dataset_4_batch_set(const stmdev_ctx_t * ctx,ism330dlc_dec_ds4_fifo_t val)5716 int32_t ism330dlc_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx,
5717 ism330dlc_dec_ds4_fifo_t val)
5718 {
5719 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5720 int32_t ret;
5721 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5722 (uint8_t *)&fifo_ctrl4, 1);
5723
5724 if (ret == 0)
5725 {
5726 fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
5727 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
5728 (uint8_t *)&fifo_ctrl4, 1);
5729 }
5730
5731 return ret;
5732 }
5733
5734 /**
5735 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5736 * fourth data set.[get]
5737 *
5738 * @param ctx Read / write interface definitions
5739 * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4
5740 * @retval Interface status (MANDATORY: return 0 -> no Error).
5741 *
5742 */
ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t * ctx,ism330dlc_dec_ds4_fifo_t * val)5743 int32_t ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx,
5744 ism330dlc_dec_ds4_fifo_t *val)
5745 {
5746 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5747 int32_t ret;
5748 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5749 (uint8_t *)&fifo_ctrl4, 1);
5750
5751 switch (fifo_ctrl4.dec_ds4_fifo)
5752 {
5753 case ISM330DLC_FIFO_DS4_DISABLE:
5754 *val = ISM330DLC_FIFO_DS4_DISABLE;
5755 break;
5756
5757 case ISM330DLC_FIFO_DS4_NO_DEC:
5758 *val = ISM330DLC_FIFO_DS4_NO_DEC;
5759 break;
5760
5761 case ISM330DLC_FIFO_DS4_DEC_2:
5762 *val = ISM330DLC_FIFO_DS4_DEC_2;
5763 break;
5764
5765 case ISM330DLC_FIFO_DS4_DEC_3:
5766 *val = ISM330DLC_FIFO_DS4_DEC_3;
5767 break;
5768
5769 case ISM330DLC_FIFO_DS4_DEC_4:
5770 *val = ISM330DLC_FIFO_DS4_DEC_4;
5771 break;
5772
5773 case ISM330DLC_FIFO_DS4_DEC_8:
5774 *val = ISM330DLC_FIFO_DS4_DEC_8;
5775 break;
5776
5777 case ISM330DLC_FIFO_DS4_DEC_16:
5778 *val = ISM330DLC_FIFO_DS4_DEC_16;
5779 break;
5780
5781 case ISM330DLC_FIFO_DS4_DEC_32:
5782 *val = ISM330DLC_FIFO_DS4_DEC_32;
5783 break;
5784
5785 default:
5786 *val = ISM330DLC_FIFO_DS4_DISABLE;
5787 break;
5788 }
5789
5790 return ret;
5791 }
5792
5793 /**
5794 * @brief 8-bit data storage in FIFO.[set]
5795 *
5796 * @param ctx Read / write interface definitions
5797 * @param val Change the values of only_high_data in reg FIFO_CTRL4
5798 * @retval Interface status (MANDATORY: return 0 -> no Error).
5799 *
5800 */
ism330dlc_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t * ctx,uint8_t val)5801 int32_t ism330dlc_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx,
5802 uint8_t val)
5803 {
5804 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5805 int32_t ret;
5806 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5807 (uint8_t *)&fifo_ctrl4, 1);
5808
5809 if (ret == 0)
5810 {
5811 fifo_ctrl4.only_high_data = val;
5812 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
5813 (uint8_t *)&fifo_ctrl4, 1);
5814 }
5815
5816 return ret;
5817 }
5818
5819 /**
5820 * @brief 8-bit data storage in FIFO.[get]
5821 *
5822 * @param ctx Read / write interface definitions
5823 * @param val Change the values of only_high_data in reg FIFO_CTRL4
5824 * @retval Interface status (MANDATORY: return 0 -> no Error).
5825 *
5826 */
ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t * ctx,uint8_t * val)5827 int32_t ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx,
5828 uint8_t *val)
5829 {
5830 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5831 int32_t ret;
5832 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5833 (uint8_t *)&fifo_ctrl4, 1);
5834 *val = fifo_ctrl4.only_high_data;
5835
5836 return ret;
5837 }
5838
5839 /**
5840 * @brief Sensing chain FIFO stop values memorization at threshold
5841 * level.[set]
5842 *
5843 * @param ctx Read / write interface definitions
5844 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
5845 * @retval Interface status (MANDATORY: return 0 -> no Error).
5846 *
5847 */
ism330dlc_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)5848 int32_t ism330dlc_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
5849 {
5850 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5851 int32_t ret;
5852 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5853 (uint8_t *)&fifo_ctrl4, 1);
5854
5855 if (ret == 0)
5856 {
5857 fifo_ctrl4.stop_on_fth = val;
5858 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL4,
5859 (uint8_t *)&fifo_ctrl4, 1);
5860 }
5861
5862 return ret;
5863 }
5864
5865 /**
5866 * @brief Sensing chain FIFO stop values memorization at threshold
5867 * level.[get]
5868 *
5869 * @param ctx Read / write interface definitions
5870 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
5871 * @retval Interface status (MANDATORY: return 0 -> no Error).
5872 *
5873 */
ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)5874 int32_t ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
5875 uint8_t *val)
5876 {
5877 ism330dlc_fifo_ctrl4_t fifo_ctrl4;
5878 int32_t ret;
5879 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4,
5880 (uint8_t *)&fifo_ctrl4, 1);
5881 *val = fifo_ctrl4.stop_on_fth;
5882
5883 return ret;
5884 }
5885
5886 /**
5887 * @brief FIFO mode selection.[set]
5888 *
5889 * @param ctx Read / write interface definitions
5890 * @param val Change the values of fifo_mode in reg FIFO_CTRL5
5891 * @retval Interface status (MANDATORY: return 0 -> no Error).
5892 *
5893 */
ism330dlc_fifo_mode_set(const stmdev_ctx_t * ctx,ism330dlc_fifo_mode_t val)5894 int32_t ism330dlc_fifo_mode_set(const stmdev_ctx_t *ctx,
5895 ism330dlc_fifo_mode_t val)
5896 {
5897 ism330dlc_fifo_ctrl5_t fifo_ctrl5;
5898 int32_t ret;
5899 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
5900 (uint8_t *)&fifo_ctrl5, 1);
5901
5902 if (ret == 0)
5903 {
5904 fifo_ctrl5.fifo_mode = (uint8_t)val;
5905 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL5,
5906 (uint8_t *)&fifo_ctrl5, 1);
5907 }
5908
5909 return ret;
5910 }
5911
5912 /**
5913 * @brief FIFO mode selection.[get]
5914 *
5915 * @param ctx Read / write interface definitions
5916 * @param val Get the values of fifo_mode in reg FIFO_CTRL5
5917 * @retval Interface status (MANDATORY: return 0 -> no Error).
5918 *
5919 */
ism330dlc_fifo_mode_get(const stmdev_ctx_t * ctx,ism330dlc_fifo_mode_t * val)5920 int32_t ism330dlc_fifo_mode_get(const stmdev_ctx_t *ctx,
5921 ism330dlc_fifo_mode_t *val)
5922 {
5923 ism330dlc_fifo_ctrl5_t fifo_ctrl5;
5924 int32_t ret;
5925 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
5926 (uint8_t *)&fifo_ctrl5, 1);
5927
5928 switch (fifo_ctrl5.fifo_mode)
5929 {
5930 case ISM330DLC_BYPASS_MODE:
5931 *val = ISM330DLC_BYPASS_MODE;
5932 break;
5933
5934 case ISM330DLC_FIFO_MODE:
5935 *val = ISM330DLC_FIFO_MODE;
5936 break;
5937
5938 case ISM330DLC_STREAM_TO_FIFO_MODE:
5939 *val = ISM330DLC_STREAM_TO_FIFO_MODE;
5940 break;
5941
5942 case ISM330DLC_BYPASS_TO_STREAM_MODE:
5943 *val = ISM330DLC_BYPASS_TO_STREAM_MODE;
5944 break;
5945
5946 case ISM330DLC_STREAM_MODE:
5947 *val = ISM330DLC_STREAM_MODE;
5948 break;
5949
5950 default:
5951 *val = ISM330DLC_BYPASS_MODE;
5952 break;
5953 }
5954
5955 return ret;
5956 }
5957
5958 /**
5959 * @brief FIFO ODR selection, setting FIFO_MODE also.[set]
5960 *
5961 * @param ctx Read / write interface definitions
5962 * @param val Change the values of odr_fifo in reg FIFO_CTRL5
5963 * @retval Interface status (MANDATORY: return 0 -> no Error).
5964 *
5965 */
ism330dlc_fifo_data_rate_set(const stmdev_ctx_t * ctx,ism330dlc_odr_fifo_t val)5966 int32_t ism330dlc_fifo_data_rate_set(const stmdev_ctx_t *ctx,
5967 ism330dlc_odr_fifo_t val)
5968 {
5969 ism330dlc_fifo_ctrl5_t fifo_ctrl5;
5970 int32_t ret;
5971 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
5972 (uint8_t *)&fifo_ctrl5, 1);
5973
5974 if (ret == 0)
5975 {
5976 fifo_ctrl5.odr_fifo = (uint8_t)val;
5977 ret = ism330dlc_write_reg(ctx, ISM330DLC_FIFO_CTRL5,
5978 (uint8_t *)&fifo_ctrl5, 1);
5979 }
5980
5981 return ret;
5982 }
5983
5984 /**
5985 * @brief FIFO ODR selection, setting FIFO_MODE also.[get]
5986 *
5987 * @param ctx Read / write interface definitions
5988 * @param val Get the values of odr_fifo in reg FIFO_CTRL5
5989 * @retval Interface status (MANDATORY: return 0 -> no Error).
5990 *
5991 */
ism330dlc_fifo_data_rate_get(const stmdev_ctx_t * ctx,ism330dlc_odr_fifo_t * val)5992 int32_t ism330dlc_fifo_data_rate_get(const stmdev_ctx_t *ctx,
5993 ism330dlc_odr_fifo_t *val)
5994 {
5995 ism330dlc_fifo_ctrl5_t fifo_ctrl5;
5996 int32_t ret;
5997 ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5,
5998 (uint8_t *)&fifo_ctrl5, 1);
5999
6000 switch (fifo_ctrl5.odr_fifo)
6001 {
6002 case ISM330DLC_FIFO_DISABLE:
6003 *val = ISM330DLC_FIFO_DISABLE;
6004 break;
6005
6006 case ISM330DLC_FIFO_12Hz5:
6007 *val = ISM330DLC_FIFO_12Hz5;
6008 break;
6009
6010 case ISM330DLC_FIFO_26Hz:
6011 *val = ISM330DLC_FIFO_26Hz;
6012 break;
6013
6014 case ISM330DLC_FIFO_52Hz:
6015 *val = ISM330DLC_FIFO_52Hz;
6016 break;
6017
6018 case ISM330DLC_FIFO_104Hz:
6019 *val = ISM330DLC_FIFO_104Hz;
6020 break;
6021
6022 case ISM330DLC_FIFO_208Hz:
6023 *val = ISM330DLC_FIFO_208Hz;
6024 break;
6025
6026 case ISM330DLC_FIFO_416Hz:
6027 *val = ISM330DLC_FIFO_416Hz;
6028 break;
6029
6030 case ISM330DLC_FIFO_833Hz:
6031 *val = ISM330DLC_FIFO_833Hz;
6032 break;
6033
6034 case ISM330DLC_FIFO_1k66Hz:
6035 *val = ISM330DLC_FIFO_1k66Hz;
6036 break;
6037
6038 case ISM330DLC_FIFO_3k33Hz:
6039 *val = ISM330DLC_FIFO_3k33Hz;
6040 break;
6041
6042 case ISM330DLC_FIFO_6k66Hz:
6043 *val = ISM330DLC_FIFO_6k66Hz;
6044 break;
6045
6046 default:
6047 *val = ISM330DLC_FIFO_DISABLE;
6048 break;
6049 }
6050
6051 return ret;
6052 }
6053
6054 /**
6055 * @}
6056 *
6057 */
6058
6059 /**
6060 * @defgroup ISM330DLC_DEN_functionality
6061 * @brief This section groups all the functions concerning DEN
6062 * functionality.
6063 * @{
6064 *
6065 */
6066
6067 /**
6068 * @brief DEN active level configuration.[set]
6069 *
6070 * @param ctx Read / write interface definitions
6071 * @param val Change the values of den_lh in reg CTRL5_C
6072 * @retval Interface status (MANDATORY: return 0 -> no Error).
6073 *
6074 */
ism330dlc_den_polarity_set(const stmdev_ctx_t * ctx,ism330dlc_den_lh_t val)6075 int32_t ism330dlc_den_polarity_set(const stmdev_ctx_t *ctx,
6076 ism330dlc_den_lh_t val)
6077 {
6078 ism330dlc_ctrl5_c_t ctrl5_c;
6079 int32_t ret;
6080 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6081
6082 if (ret == 0)
6083 {
6084 ctrl5_c.den_lh = (uint8_t)val;
6085 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6086 }
6087
6088 return ret;
6089 }
6090
6091 /**
6092 * @brief DEN active level configuration.[get]
6093 *
6094 * @param ctx Read / write interface definitions
6095 * @param val Get the values of den_lh in reg CTRL5_C
6096 * @retval Interface status (MANDATORY: return 0 -> no Error).
6097 *
6098 */
ism330dlc_den_polarity_get(const stmdev_ctx_t * ctx,ism330dlc_den_lh_t * val)6099 int32_t ism330dlc_den_polarity_get(const stmdev_ctx_t *ctx,
6100 ism330dlc_den_lh_t *val)
6101 {
6102 ism330dlc_ctrl5_c_t ctrl5_c;
6103 int32_t ret;
6104 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6105
6106 switch (ctrl5_c.den_lh)
6107 {
6108 case ISM330DLC_DEN_ACT_LOW:
6109 *val = ISM330DLC_DEN_ACT_LOW;
6110 break;
6111
6112 case ISM330DLC_DEN_ACT_HIGH:
6113 *val = ISM330DLC_DEN_ACT_HIGH;
6114 break;
6115
6116 default:
6117 *val = ISM330DLC_DEN_ACT_LOW;
6118 break;
6119 }
6120
6121 return ret;
6122 }
6123
6124 /**
6125 * @brief DEN functionality marking mode[set]
6126 *
6127 * @param ctx Read / write interface definitions
6128 * @param val Change the values of den_mode in reg CTRL6_C
6129 * @retval Interface status (MANDATORY: return 0 -> no Error).
6130 *
6131 */
ism330dlc_den_mode_set(const stmdev_ctx_t * ctx,ism330dlc_den_mode_t val)6132 int32_t ism330dlc_den_mode_set(const stmdev_ctx_t *ctx,
6133 ism330dlc_den_mode_t val)
6134 {
6135 ism330dlc_ctrl6_c_t ctrl6_c;
6136 int32_t ret;
6137 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6138
6139 if (ret == 0)
6140 {
6141 ctrl6_c.den_mode = (uint8_t)val;
6142 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6143 }
6144
6145 return ret;
6146 }
6147
6148 /**
6149 * @brief DEN functionality marking mode[get]
6150 *
6151 * @param ctx Read / write interface definitions
6152 * @param val Change the values of den_mode in reg CTRL6_C
6153 * @retval Interface status (MANDATORY: return 0 -> no Error).
6154 *
6155 */
ism330dlc_den_mode_get(const stmdev_ctx_t * ctx,ism330dlc_den_mode_t * val)6156 int32_t ism330dlc_den_mode_get(const stmdev_ctx_t *ctx,
6157 ism330dlc_den_mode_t *val)
6158 {
6159 ism330dlc_ctrl6_c_t ctrl6_c;
6160 int32_t ret;
6161 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6162
6163 switch (ctrl6_c.den_mode)
6164 {
6165 case ISM330DLC_DEN_DISABLE:
6166 *val = ISM330DLC_DEN_DISABLE;
6167 break;
6168
6169 case ISM330DLC_LEVEL_LETCHED:
6170 *val = ISM330DLC_LEVEL_LETCHED;
6171 break;
6172
6173 case ISM330DLC_LEVEL_TRIGGER:
6174 *val = ISM330DLC_LEVEL_TRIGGER;
6175 break;
6176
6177 case ISM330DLC_EDGE_TRIGGER:
6178 *val = ISM330DLC_EDGE_TRIGGER;
6179 break;
6180
6181 default:
6182 *val = ISM330DLC_DEN_DISABLE;
6183 break;
6184 }
6185
6186 return ret;
6187 }
6188
6189 /**
6190 * @brief Extend DEN functionality to accelerometer sensor.[set]
6191 *
6192 * @param ctx Read / write interface definitions
6193 * @param val Change the values of den_xl_g in reg CTRL9_XL
6194 * and den_xl_en in CTRL4_C.
6195 * @retval Interface status (MANDATORY: return 0 -> no Error).
6196 *
6197 */
ism330dlc_den_enable_set(const stmdev_ctx_t * ctx,ism330dlc_den_xl_en_t val)6198 int32_t ism330dlc_den_enable_set(const stmdev_ctx_t *ctx,
6199 ism330dlc_den_xl_en_t val)
6200 {
6201 ism330dlc_ctrl4_c_t ctrl4_c;
6202 ism330dlc_ctrl9_xl_t ctrl9_xl;
6203 int32_t ret;
6204 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6205 (uint8_t *)&ctrl9_xl, 1);
6206
6207 if (ret == 0)
6208 {
6209 ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
6210 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
6211 (uint8_t *)&ctrl9_xl, 1);
6212
6213 if (ret == 0)
6214 {
6215 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C,
6216 (uint8_t *)&ctrl4_c, 1);
6217
6218 if (ret == 0)
6219 {
6220 ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
6221 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL4_C,
6222 (uint8_t *)&ctrl4_c, 1);
6223 }
6224 }
6225 }
6226
6227 return ret;
6228 }
6229
6230 /**
6231 * @brief Extend DEN functionality to accelerometer sensor. [get]
6232 *
6233 * @param ctx Read / write interface definitions
6234 * @param val Get the values of den_xl_g in reg CTRL9_XL
6235 * and den_xl_en in CTRL4_C.
6236 * @retval Interface status (MANDATORY: return 0 -> no Error).
6237 *
6238 */
ism330dlc_den_enable_get(const stmdev_ctx_t * ctx,ism330dlc_den_xl_en_t * val)6239 int32_t ism330dlc_den_enable_get(const stmdev_ctx_t *ctx,
6240 ism330dlc_den_xl_en_t *val)
6241 {
6242 ism330dlc_ctrl4_c_t ctrl4_c;
6243 ism330dlc_ctrl9_xl_t ctrl9_xl;
6244 int32_t ret;
6245 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6246
6247 if (ret == 0)
6248 {
6249 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6250 (uint8_t *)&ctrl9_xl, 1);
6251
6252 switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
6253 {
6254 case ISM330DLC_STAMP_IN_GY_DATA:
6255 *val = ISM330DLC_STAMP_IN_GY_DATA;
6256 break;
6257
6258 case ISM330DLC_STAMP_IN_XL_DATA:
6259 *val = ISM330DLC_STAMP_IN_XL_DATA;
6260 break;
6261
6262 case ISM330DLC_STAMP_IN_GY_XL_DATA:
6263 *val = ISM330DLC_STAMP_IN_GY_XL_DATA;
6264 break;
6265
6266 default:
6267 *val = ISM330DLC_STAMP_IN_GY_DATA;
6268 break;
6269 }
6270 }
6271
6272 return ret;
6273 }
6274
6275 /**
6276 * @brief DEN value stored in LSB of Z-axis.[set]
6277 *
6278 * @param ctx Read / write interface definitions
6279 * @param val Change the values of den_z in reg CTRL9_XL
6280 * @retval Interface status (MANDATORY: return 0 -> no Error).
6281 *
6282 */
ism330dlc_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)6283 int32_t ism330dlc_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6284 {
6285 ism330dlc_ctrl9_xl_t ctrl9_xl;
6286 int32_t ret;
6287 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6288 (uint8_t *)&ctrl9_xl, 1);
6289
6290 if (ret == 0)
6291 {
6292 ctrl9_xl.den_z = val;
6293 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
6294 (uint8_t *)&ctrl9_xl, 1);
6295 }
6296
6297 return ret;
6298 }
6299
6300 /**
6301 * @brief DEN value stored in LSB of Z-axis.[get]
6302 *
6303 * @param ctx Read / write interface definitions
6304 * @param val Change the values of den_z in reg CTRL9_XL
6305 * @retval Interface status (MANDATORY: return 0 -> no Error).
6306 *
6307 */
ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6308 int32_t ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
6309 {
6310 ism330dlc_ctrl9_xl_t ctrl9_xl;
6311 int32_t ret;
6312 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6313 (uint8_t *)&ctrl9_xl, 1);
6314 *val = ctrl9_xl.den_z;
6315
6316 return ret;
6317 }
6318
6319 /**
6320 * @brief DEN value stored in LSB of Y-axis.[set]
6321 *
6322 * @param ctx Read / write interface definitions
6323 * @param val Change the values of den_y in reg CTRL9_XL
6324 * @retval Interface status (MANDATORY: return 0 -> no Error).
6325 *
6326 */
ism330dlc_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)6327 int32_t ism330dlc_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6328 {
6329 ism330dlc_ctrl9_xl_t ctrl9_xl;
6330 int32_t ret;
6331 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6332 (uint8_t *)&ctrl9_xl, 1);
6333
6334 if (ret == 0)
6335 {
6336 ctrl9_xl.den_y = val;
6337 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
6338 (uint8_t *)&ctrl9_xl, 1);
6339 }
6340
6341 return ret;
6342 }
6343
6344 /**
6345 * @brief DEN value stored in LSB of Y-axis.[get]
6346 *
6347 * @param ctx Read / write interface definitions
6348 * @param val Change the values of den_y in reg CTRL9_XL
6349 * @retval Interface status (MANDATORY: return 0 -> no Error).
6350 *
6351 */
ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6352 int32_t ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
6353 {
6354 ism330dlc_ctrl9_xl_t ctrl9_xl;
6355 int32_t ret;
6356 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6357 (uint8_t *)&ctrl9_xl, 1);
6358 *val = ctrl9_xl.den_y;
6359
6360 return ret;
6361 }
6362
6363 /**
6364 * @brief DEN value stored in LSB of X-axis.[set]
6365 *
6366 * @param ctx Read / write interface definitions
6367 * @param val Change the values of den_x in reg CTRL9_XL
6368 * @retval Interface status (MANDATORY: return 0 -> no Error).
6369 *
6370 */
ism330dlc_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)6371 int32_t ism330dlc_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
6372 {
6373 ism330dlc_ctrl9_xl_t ctrl9_xl;
6374 int32_t ret;
6375 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6376 (uint8_t *)&ctrl9_xl, 1);
6377
6378 if (ret == 0)
6379 {
6380 ctrl9_xl.den_x = val;
6381 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
6382 (uint8_t *)&ctrl9_xl, 1);
6383 }
6384
6385 return ret;
6386 }
6387
6388 /**
6389 * @brief DEN value stored in LSB of X-axis.[get]
6390 *
6391 * @param ctx Read / write interface definitions
6392 * @param val Change the values of den_x in reg CTRL9_XL
6393 * @retval Interface status (MANDATORY: return 0 -> no Error).
6394 *
6395 */
ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6396 int32_t ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
6397 {
6398 ism330dlc_ctrl9_xl_t ctrl9_xl;
6399 int32_t ret;
6400 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6401 (uint8_t *)&ctrl9_xl, 1);
6402 *val = ctrl9_xl.den_x;
6403
6404 return ret;
6405 }
6406
6407 /**
6408 * @}
6409 *
6410 */
6411
6412 /**
6413 * @defgroup ISM330DLC_ magnetometer_sensor
6414 * @brief This section groups all the functions that manage additional
6415 * magnetometer sensor.
6416 * @{
6417 *
6418 */
6419
6420 /**
6421 * @brief Enable soft-iron correction algorithm for magnetometer.[set]
6422 *
6423 * @param ctx Read / write interface definitions
6424 * @param val Change the values of soft_en in reg CTRL9_XL
6425 * @retval Interface status (MANDATORY: return 0 -> no Error).
6426 *
6427 */
ism330dlc_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint8_t val)6428 int32_t ism330dlc_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
6429 {
6430 ism330dlc_ctrl9_xl_t ctrl9_xl;
6431 int32_t ret;
6432 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6433 (uint8_t *)&ctrl9_xl, 1);
6434
6435 if (ret == 0)
6436 {
6437 ctrl9_xl.soft_en = val;
6438 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL9_XL,
6439 (uint8_t *)&ctrl9_xl, 1);
6440 }
6441
6442 return ret;
6443 }
6444
6445 /**
6446 * @brief Enable soft-iron correction algorithm for magnetometer.[get]
6447 *
6448 * @param ctx Read / write interface definitions
6449 * @param val Change the values of soft_en in reg CTRL9_XL
6450 * @retval Interface status (MANDATORY: return 0 -> no Error).
6451 *
6452 */
ism330dlc_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)6453 int32_t ism330dlc_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
6454 {
6455 ism330dlc_ctrl9_xl_t ctrl9_xl;
6456 int32_t ret;
6457 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL,
6458 (uint8_t *)&ctrl9_xl, 1);
6459 *val = ctrl9_xl.soft_en;
6460
6461 return ret;
6462 }
6463
6464 /**
6465 * @brief Enable hard-iron correction algorithm for magnetometer.[set]
6466 *
6467 * @param ctx Read / write interface definitions
6468 * @param val Change the values of iron_en in reg MASTER_CONFIG
6469 * @retval Interface status (MANDATORY: return 0 -> no Error).
6470 *
6471 */
ism330dlc_mag_hard_iron_set(const stmdev_ctx_t * ctx,uint8_t val)6472 int32_t ism330dlc_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
6473 {
6474 ism330dlc_master_config_t master_config;
6475 ism330dlc_ctrl10_c_t ctrl10_c;
6476 int32_t ret;
6477 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6478 (uint8_t *)&master_config, 1);
6479
6480 if (ret == 0)
6481 {
6482 master_config.iron_en = val;
6483 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
6484 (uint8_t *)&master_config, 1);
6485
6486 if (ret == 0)
6487 {
6488 ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C,
6489 (uint8_t *)&ctrl10_c, 1);
6490
6491 if (ret == 0)
6492 {
6493 if (val != 0x00U)
6494 {
6495 ctrl10_c.func_en = val;
6496 }
6497
6498 ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL10_C,
6499 (uint8_t *)&ctrl10_c, 1);
6500 }
6501 }
6502 }
6503
6504 return ret;
6505 }
6506
6507 /**
6508 * @brief Enable hard-iron correction algorithm for magnetometer.[get]
6509 *
6510 * @param ctx Read / write interface definitions
6511 * @param val Change the values of iron_en in reg MASTER_CONFIG
6512 * @retval Interface status (MANDATORY: return 0 -> no Error).
6513 *
6514 */
ism330dlc_mag_hard_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)6515 int32_t ism330dlc_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
6516 {
6517 ism330dlc_master_config_t master_config;
6518 int32_t ret;
6519 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6520 (uint8_t *)&master_config, 1);
6521 *val = master_config.iron_en;
6522
6523 return ret;
6524 }
6525
6526 /**
6527 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6528 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set]
6529 *
6530 * @param ctx Read / write interface definitions
6531 * @param buff Buffer that contains data to write
6532 * @retval Interface status (MANDATORY: return 0 -> no Error).
6533 *
6534 */
ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t * ctx,uint8_t * buff)6535 int32_t ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx,
6536 uint8_t *buff)
6537 {
6538 int32_t ret;
6539 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
6540
6541 if (ret == 0)
6542 {
6543 ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9);
6544
6545 if (ret == 0)
6546 {
6547 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
6548 }
6549 }
6550
6551 return ret;
6552 }
6553
6554 /**
6555 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6556 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get]
6557 *
6558 * @param ctx Read / write interface definitions
6559 * @param buff Buffer that stores data read
6560 * @retval Interface status (MANDATORY: return 0 -> no Error).
6561 *
6562 */
ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t * ctx,uint8_t * buff)6563 int32_t ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx,
6564 uint8_t *buff)
6565 {
6566 int32_t ret;
6567 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
6568
6569 if (ret == 0)
6570 {
6571 ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9);
6572
6573 if (ret == 0)
6574 {
6575 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
6576 }
6577 }
6578
6579 return ret;
6580 }
6581
6582 /**
6583 * @brief Offset for hard-iron compensation register (r/w). The value is
6584 * expressed as a 16-bit word in two’s complement.[set]
6585 *
6586 * @param ctx Read / write interface definitions
6587 * @param buff Buffer that contains data to write
6588 * @retval Interface status (MANDATORY: return 0 -> no Error).
6589 *
6590 */
ism330dlc_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)6591 int32_t ism330dlc_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
6592 {
6593 uint8_t buff[6];
6594 int32_t ret;
6595 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
6596
6597 if (ret == 0)
6598 {
6599 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
6600 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
6601 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
6602 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
6603 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
6604 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
6605 ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6);
6606
6607 if (ret == 0)
6608 {
6609 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
6610 }
6611 }
6612
6613 return ret;
6614 }
6615
6616 /**
6617 * @brief Offset for hard-iron compensation register(r/w).
6618 * The value is expressed as a 16-bit word in two’s complement.[get]
6619 *
6620 * @param ctx Read / write interface definitions
6621 * @param buff Buffer that stores data read
6622 * @retval Interface status (MANDATORY: return 0 -> no Error).
6623 *
6624 */
ism330dlc_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)6625 int32_t ism330dlc_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
6626 {
6627 uint8_t buff[6];
6628 int32_t ret;
6629 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
6630
6631 if (ret == 0)
6632 {
6633 ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6);
6634 val[0] = (int16_t)buff[1];
6635 val[0] = (val[0] * 256) + (int16_t)buff[0];
6636 val[1] = (int16_t)buff[3];
6637 val[1] = (val[1] * 256) + (int16_t)buff[2];
6638 val[2] = (int16_t)buff[5];
6639 val[2] = (val[2] * 256) + (int16_t)buff[4];
6640
6641 if (ret == 0)
6642 {
6643 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
6644 }
6645 }
6646
6647 return ret;
6648 }
6649
6650 /**
6651 * @}
6652 *
6653 */
6654
6655 /**
6656 * @defgroup ISM330DLC_Sensor_hub
6657 * @brief This section groups all the functions that manage the sensor
6658 * hub functionality.
6659 * @{
6660 *
6661 */
6662
6663 /**
6664 * @brief Sensor synchronization time frame with the step of 500 ms and
6665 * full range of 5s. Unsigned 8-bit.[set]
6666 *
6667 * @param ctx Read / write interface definitions
6668 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6669 * @retval Interface status (MANDATORY: return 0 -> no Error).
6670 *
6671 */
ism330dlc_sh_sync_sens_frame_set(const stmdev_ctx_t * ctx,uint8_t val)6672 int32_t ism330dlc_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx,
6673 uint8_t val)
6674 {
6675 ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame;
6676 int32_t ret;
6677 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
6678 (uint8_t *)&sensor_sync_time_frame, 1);
6679
6680 if (ret == 0)
6681 {
6682 sensor_sync_time_frame.tph = val;
6683 ret = ism330dlc_write_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
6684 (uint8_t *)&sensor_sync_time_frame, 1);
6685 }
6686
6687 return ret;
6688 }
6689
6690 /**
6691 * @brief Sensor synchronization time frame with the step of 500 ms and
6692 * full range of 5s. Unsigned 8-bit.[get]
6693 *
6694 * @param ctx Read / write interface definitions
6695 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6696 * @retval Interface status (MANDATORY: return 0 -> no Error).
6697 *
6698 */
ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t * ctx,uint8_t * val)6699 int32_t ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx,
6700 uint8_t *val)
6701 {
6702 ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame;
6703 int32_t ret;
6704 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME,
6705 (uint8_t *)&sensor_sync_time_frame, 1);
6706 *val = sensor_sync_time_frame.tph;
6707
6708 return ret;
6709 }
6710
6711 /**
6712 * @brief Resolution ratio of error code for sensor synchronization.[set]
6713 *
6714 * @param ctx Read / write interface definitions
6715 * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO
6716 * @retval Interface status (MANDATORY: return 0 -> no Error).
6717 *
6718 */
ism330dlc_sh_sync_sens_ratio_set(const stmdev_ctx_t * ctx,ism330dlc_rr_t val)6719 int32_t ism330dlc_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx,
6720 ism330dlc_rr_t val)
6721 {
6722 ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6723 int32_t ret;
6724 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
6725 (uint8_t *)&sensor_sync_res_ratio, 1);
6726
6727 if (ret == 0)
6728 {
6729 sensor_sync_res_ratio.rr = (uint8_t) val;
6730 ret = ism330dlc_write_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
6731 (uint8_t *)&sensor_sync_res_ratio, 1);
6732 }
6733
6734 return ret;
6735 }
6736
6737 /**
6738 * @brief Resolution ratio of error code for sensor synchronization.[get]
6739 *
6740 * @param ctx Read / write interface definitions
6741 * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO
6742 * @retval Interface status (MANDATORY: return 0 -> no Error).
6743 *
6744 */
ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t * ctx,ism330dlc_rr_t * val)6745 int32_t ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx,
6746 ism330dlc_rr_t *val)
6747 {
6748 ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6749 int32_t ret;
6750 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO,
6751 (uint8_t *)&sensor_sync_res_ratio, 1);
6752
6753 switch (sensor_sync_res_ratio.rr)
6754 {
6755 case ISM330DLC_RES_RATIO_2_11:
6756 *val = ISM330DLC_RES_RATIO_2_11;
6757 break;
6758
6759 case ISM330DLC_RES_RATIO_2_12:
6760 *val = ISM330DLC_RES_RATIO_2_12;
6761 break;
6762
6763 case ISM330DLC_RES_RATIO_2_13:
6764 *val = ISM330DLC_RES_RATIO_2_13;
6765 break;
6766
6767 case ISM330DLC_RES_RATIO_2_14:
6768 *val = ISM330DLC_RES_RATIO_2_14;
6769 break;
6770
6771 default:
6772 *val = ISM330DLC_RES_RATIO_2_11;
6773 break;
6774 }
6775
6776 return ret;
6777 }
6778
6779 /**
6780 * @brief Sensor hub I2C master enable.[set]
6781 *
6782 * @param ctx Read / write interface definitions
6783 * @param val Change the values of master_on in reg MASTER_CONFIG
6784 * @retval Interface status (MANDATORY: return 0 -> no Error).
6785 *
6786 */
ism330dlc_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)6787 int32_t ism330dlc_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
6788 {
6789 ism330dlc_master_config_t master_config;
6790 int32_t ret;
6791 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6792 (uint8_t *)&master_config, 1);
6793
6794 if (ret == 0)
6795 {
6796 master_config.master_on = val;
6797 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
6798 (uint8_t *)&master_config, 1);
6799 }
6800
6801 return ret;
6802 }
6803
6804 /**
6805 * @brief Sensor hub I2C master enable.[get]
6806 *
6807 * @param ctx Read / write interface definitions
6808 * @param val Change the values of master_on in reg MASTER_CONFIG
6809 * @retval Interface status (MANDATORY: return 0 -> no Error).
6810 *
6811 */
ism330dlc_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)6812 int32_t ism330dlc_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
6813 {
6814 ism330dlc_master_config_t master_config;
6815 int32_t ret;
6816 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6817 (uint8_t *)&master_config, 1);
6818 *val = master_config.master_on;
6819
6820 return ret;
6821 }
6822
6823 /**
6824 * @brief I2C interface pass-through.[set]
6825 *
6826 * @param ctx Read / write interface definitions
6827 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6828 * @retval Interface status (MANDATORY: return 0 -> no Error).
6829 *
6830 */
ism330dlc_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)6831 int32_t ism330dlc_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
6832 {
6833 ism330dlc_master_config_t master_config;
6834 int32_t ret;
6835 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6836 (uint8_t *)&master_config, 1);
6837
6838 if (ret == 0)
6839 {
6840 master_config.pass_through_mode = val;
6841 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
6842 (uint8_t *)&master_config, 1);
6843 }
6844
6845 return ret;
6846 }
6847
6848 /**
6849 * @brief I2C interface pass-through.[get]
6850 *
6851 * @param ctx Read / write interface definitions
6852 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6853 * @retval Interface status (MANDATORY: return 0 -> no Error).
6854 *
6855 */
ism330dlc_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)6856 int32_t ism330dlc_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
6857 {
6858 ism330dlc_master_config_t master_config;
6859 int32_t ret;
6860 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6861 (uint8_t *)&master_config, 1);
6862 *val = master_config.pass_through_mode;
6863
6864 return ret;
6865 }
6866
6867 /**
6868 * @brief Master I2C pull-up enable/disable.[set]
6869 *
6870 * @param ctx Read / write interface definitions
6871 * @param val Change the values of pull_up_en in reg MASTER_CONFIG
6872 * @retval Interface status (MANDATORY: return 0 -> no Error).
6873 *
6874 */
ism330dlc_sh_pin_mode_set(const stmdev_ctx_t * ctx,ism330dlc_pull_up_en_t val)6875 int32_t ism330dlc_sh_pin_mode_set(const stmdev_ctx_t *ctx,
6876 ism330dlc_pull_up_en_t val)
6877 {
6878 ism330dlc_master_config_t master_config;
6879 int32_t ret;
6880 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6881 (uint8_t *)&master_config, 1);
6882
6883 if (ret == 0)
6884 {
6885 master_config.pull_up_en = (uint8_t) val;
6886 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
6887 (uint8_t *)&master_config, 1);
6888 }
6889
6890 return ret;
6891 }
6892
6893 /**
6894 * @brief Master I2C pull-up enable/disable.[get]
6895 *
6896 * @param ctx Read / write interface definitions
6897 * @param val Get the values of pull_up_en in reg MASTER_CONFIG
6898 * @retval Interface status (MANDATORY: return 0 -> no Error).
6899 *
6900 */
ism330dlc_sh_pin_mode_get(const stmdev_ctx_t * ctx,ism330dlc_pull_up_en_t * val)6901 int32_t ism330dlc_sh_pin_mode_get(const stmdev_ctx_t *ctx,
6902 ism330dlc_pull_up_en_t *val)
6903 {
6904 ism330dlc_master_config_t master_config;
6905 int32_t ret;
6906 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6907 (uint8_t *)&master_config, 1);
6908
6909 switch (master_config.pull_up_en)
6910 {
6911 case ISM330DLC_EXT_PULL_UP:
6912 *val = ISM330DLC_EXT_PULL_UP;
6913 break;
6914
6915 case ISM330DLC_INTERNAL_PULL_UP:
6916 *val = ISM330DLC_INTERNAL_PULL_UP;
6917 break;
6918
6919 default:
6920 *val = ISM330DLC_EXT_PULL_UP;
6921 break;
6922 }
6923
6924 return ret;
6925 }
6926
6927 /**
6928 * @brief Sensor hub trigger signal selection.[set]
6929 *
6930 * @param ctx Read / write interface definitions
6931 * @param val Change the values of start_config in reg MASTER_CONFIG
6932 * @retval Interface status (MANDATORY: return 0 -> no Error).
6933 *
6934 */
ism330dlc_sh_syncro_mode_set(const stmdev_ctx_t * ctx,ism330dlc_start_config_t val)6935 int32_t ism330dlc_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
6936 ism330dlc_start_config_t val)
6937 {
6938 ism330dlc_master_config_t master_config;
6939 int32_t ret;
6940 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6941 (uint8_t *)&master_config, 1);
6942
6943 if (ret == 0)
6944 {
6945 master_config.start_config = (uint8_t)val;
6946 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
6947 (uint8_t *)&master_config, 1);
6948 }
6949
6950 return ret;
6951 }
6952
6953 /**
6954 * @brief Sensor hub trigger signal selection.[get]
6955 *
6956 * @param ctx Read / write interface definitions
6957 * @param val Get the values of start_config in reg MASTER_CONFIG
6958 * @retval Interface status (MANDATORY: return 0 -> no Error).
6959 *
6960 */
ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t * ctx,ism330dlc_start_config_t * val)6961 int32_t ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
6962 ism330dlc_start_config_t *val)
6963 {
6964 ism330dlc_master_config_t master_config;
6965 int32_t ret;
6966 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
6967 (uint8_t *)&master_config, 1);
6968
6969 switch (master_config.start_config)
6970 {
6971 case ISM330DLC_XL_GY_DRDY:
6972 *val = ISM330DLC_XL_GY_DRDY;
6973 break;
6974
6975 case ISM330DLC_EXT_ON_INT2_PIN:
6976 *val = ISM330DLC_EXT_ON_INT2_PIN;
6977 break;
6978
6979 default:
6980 *val = ISM330DLC_XL_GY_DRDY;
6981 break;
6982 }
6983
6984 return ret;
6985 }
6986
6987 /**
6988 * @brief Manage the Master DRDY signal on INT1 pad.[set]
6989 *
6990 * @param ctx Read / write interface definitions
6991 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
6992 * @retval Interface status (MANDATORY: return 0 -> no Error).
6993 *
6994 */
ism330dlc_sh_drdy_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)6995 int32_t ism330dlc_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
6996 {
6997 ism330dlc_master_config_t master_config;
6998 int32_t ret;
6999 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
7000 (uint8_t *)&master_config, 1);
7001
7002 if (ret == 0)
7003 {
7004 master_config.drdy_on_int1 = val;
7005 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CONFIG,
7006 (uint8_t *)&master_config, 1);
7007 }
7008
7009 return ret;
7010 }
7011
7012 /**
7013 * @brief Manage the Master DRDY signal on INT1 pad.[get]
7014 *
7015 * @param ctx Read / write interface definitions
7016 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
7017 * @retval Interface status (MANDATORY: return 0 -> no Error).
7018 *
7019 */
ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)7020 int32_t ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
7021 {
7022 ism330dlc_master_config_t master_config;
7023 int32_t ret;
7024 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG,
7025 (uint8_t *)&master_config, 1);
7026 *val = master_config.drdy_on_int1;
7027
7028 return ret;
7029 }
7030
7031 /**
7032 * @brief Sensor hub output registers.[get]
7033 *
7034 * @param ctx Read / write interface definitions
7035 * @param val Structure of registers from SENSORHUB1_REG
7036 * @retval Interface status (MANDATORY: return 0 -> no Error).
7037 *
7038 */
ism330dlc_sh_read_data_raw_get(const stmdev_ctx_t * ctx,ism330dlc_emb_sh_read_t * val)7039 int32_t ism330dlc_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
7040 ism330dlc_emb_sh_read_t *val)
7041 {
7042 int32_t ret;
7043 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSORHUB1_REG,
7044 (uint8_t *) & (val->sh_byte_1), 12);
7045
7046 if (ret == 0)
7047 {
7048 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSORHUB13_REG,
7049 (uint8_t *) & (val->sh_byte_13), 6);
7050 }
7051
7052 return ret;
7053 }
7054
7055 /**
7056 * @brief Master command code used for stamping for sensor sync.[set]
7057 *
7058 * @param ctx Read / write interface definitions
7059 * @param val Change the values of master_cmd_code in
7060 * reg MASTER_CMD_CODE
7061 * @retval Interface status (MANDATORY: return 0 -> no Error).
7062 *
7063 */
ism330dlc_sh_cmd_sens_sync_set(const stmdev_ctx_t * ctx,uint8_t val)7064 int32_t ism330dlc_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val)
7065 {
7066 ism330dlc_master_cmd_code_t master_cmd_code;
7067 int32_t ret;
7068 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
7069 (uint8_t *)&master_cmd_code, 1);
7070
7071 if (ret == 0)
7072 {
7073 master_cmd_code.master_cmd_code = val;
7074 ret = ism330dlc_write_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
7075 (uint8_t *)&master_cmd_code, 1);
7076 }
7077
7078 return ret;
7079 }
7080
7081 /**
7082 * @brief Master command code used for stamping for sensor sync.[get]
7083 *
7084 * @param ctx Read / write interface definitions
7085 * @param val Change the values of master_cmd_code in
7086 * reg MASTER_CMD_CODE
7087 * @retval Interface status (MANDATORY: return 0 -> no Error).
7088 *
7089 */
ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t * ctx,uint8_t * val)7090 int32_t ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx,
7091 uint8_t *val)
7092 {
7093 ism330dlc_master_cmd_code_t master_cmd_code;
7094 int32_t ret;
7095 ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CMD_CODE,
7096 (uint8_t *)&master_cmd_code, 1);
7097 *val = master_cmd_code.master_cmd_code;
7098
7099 return ret;
7100 }
7101
7102 /**
7103 * @brief Error code used for sensor synchronization.[set]
7104 *
7105 * @param ctx Read / write interface definitions
7106 * @param val Change the values of error_code in
7107 * reg SENS_SYNC_SPI_ERROR_CODE.
7108 * @retval Interface status (MANDATORY: return 0 -> no Error).
7109 *
7110 */
ism330dlc_sh_spi_sync_error_set(const stmdev_ctx_t * ctx,uint8_t val)7111 int32_t ism330dlc_sh_spi_sync_error_set(const stmdev_ctx_t *ctx,
7112 uint8_t val)
7113 {
7114 ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7115 int32_t ret;
7116 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
7117 (uint8_t *)&sens_sync_spi_error_code, 1);
7118
7119 if (ret == 0)
7120 {
7121 sens_sync_spi_error_code.error_code = val;
7122 ret = ism330dlc_write_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
7123 (uint8_t *)&sens_sync_spi_error_code, 1);
7124 }
7125
7126 return ret;
7127 }
7128
7129 /**
7130 * @brief Error code used for sensor synchronization.[get]
7131 *
7132 * @param ctx Read / write interface definitions
7133 * @param val Change the values of error_code in
7134 * reg SENS_SYNC_SPI_ERROR_CODE.
7135 * @retval Interface status (MANDATORY: return 0 -> no Error).
7136 *
7137 */
ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t * ctx,uint8_t * val)7138 int32_t ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t *ctx,
7139 uint8_t *val)
7140 {
7141 ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7142 int32_t ret;
7143 ret = ism330dlc_read_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE,
7144 (uint8_t *)&sens_sync_spi_error_code, 1);
7145 *val = sens_sync_spi_error_code.error_code;
7146
7147 return ret;
7148 }
7149
7150 /**
7151 * @brief Number of external sensors to be read by the sensor hub.[set]
7152 *
7153 * @param ctx Read / write interface definitions
7154 * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG.
7155 * @retval Interface status (MANDATORY: return 0 -> no Error).
7156 *
7157 */
ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t * ctx,ism330dlc_aux_sens_on_t val)7158 int32_t ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx,
7159 ism330dlc_aux_sens_on_t val)
7160 {
7161 ism330dlc_slave0_config_t slave0_config;
7162 int32_t ret;
7163 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7164
7165 if (ret == 0)
7166 {
7167 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7168 (uint8_t *)&slave0_config, 1);
7169
7170 if (ret == 0)
7171 {
7172 slave0_config.aux_sens_on = (uint8_t) val;
7173 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7174 (uint8_t *)&slave0_config, 1);
7175
7176 if (ret == 0)
7177 {
7178 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7179 }
7180 }
7181 }
7182
7183 return ret;
7184 }
7185
7186 /**
7187 * @brief Number of external sensors to be read by the sensor hub.[get]
7188 *
7189 * @param ctx Read / write interface definitions
7190 * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG.
7191 * @retval Interface status (MANDATORY: return 0 -> no Error).
7192 *
7193 */
ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t * ctx,ism330dlc_aux_sens_on_t * val)7194 int32_t ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx,
7195 ism330dlc_aux_sens_on_t *val)
7196 {
7197 ism330dlc_slave0_config_t slave0_config;
7198 int32_t ret;
7199 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7200
7201 if (ret == 0)
7202 {
7203 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7204 (uint8_t *)&slave0_config, 1);
7205
7206 if (ret == 0)
7207 {
7208 switch (slave0_config.aux_sens_on)
7209 {
7210 case ISM330DLC_SLV_0:
7211 *val = ISM330DLC_SLV_0;
7212 break;
7213
7214 case ISM330DLC_SLV_0_1:
7215 *val = ISM330DLC_SLV_0_1;
7216 break;
7217
7218 case ISM330DLC_SLV_0_1_2:
7219 *val = ISM330DLC_SLV_0_1_2;
7220 break;
7221
7222 case ISM330DLC_SLV_0_1_2_3:
7223 *val = ISM330DLC_SLV_0_1_2_3;
7224 break;
7225
7226 default:
7227 *val = ISM330DLC_SLV_0;
7228 break;
7229 }
7230
7231 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7232 }
7233 }
7234
7235 return ret;
7236 }
7237
7238 /**
7239 * @brief Configure slave 0 for perform a write.[set]
7240 *
7241 * @param ctx Read / write interface definitions
7242 * @param val Structure that contain:
7243 * - uint8_t slv_add; 8 bit i2c device address
7244 * - uint8_t slv_subadd; 8 bit register device address
7245 * - uint8_t slv_data; 8 bit data to write
7246 * @retval Interface status (MANDATORY: return 0 -> no Error).
7247 *
7248 */
ism330dlc_sh_cfg_write(const stmdev_ctx_t * ctx,ism330dlc_sh_cfg_write_t * val)7249 int32_t ism330dlc_sh_cfg_write(const stmdev_ctx_t *ctx,
7250 ism330dlc_sh_cfg_write_t *val)
7251 {
7252 ism330dlc_slv0_add_t slv0_add;
7253 int32_t ret;
7254 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7255
7256 if (ret == 0)
7257 {
7258 slv0_add.slave0_add = val->slv0_add;
7259 slv0_add.rw_0 = 0;
7260 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_ADD,
7261 (uint8_t *)&slv0_add, 1);
7262
7263 if (ret == 0)
7264 {
7265 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_SUBADD,
7266 &(val->slv0_subadd), 1);
7267
7268 if (ret == 0)
7269 {
7270 ret = ism330dlc_write_reg(ctx, ISM330DLC_DATAWRITE_SRC_MODE_SUB_SLV0,
7271 &(val->slv0_data), 1);
7272
7273 if (ret == 0)
7274 {
7275 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7276 }
7277 }
7278 }
7279 }
7280
7281 return ret;
7282 }
7283
7284 /**
7285 * @brief Configure slave 0 for perform a read.[get]
7286 *
7287 * @param ctx Read / write interface definitions
7288 * @param val Structure that contain:
7289 * - uint8_t slv_add; 8 bit i2c device address
7290 * - uint8_t slv_subadd; 8 bit register device address
7291 * - uint8_t slv_len; num of bit to read
7292 * @retval Interface status (MANDATORY: return 0 -> no Error).
7293 *
7294 */
ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,ism330dlc_sh_cfg_read_t * val)7295 int32_t ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
7296 ism330dlc_sh_cfg_read_t *val)
7297 {
7298 ism330dlc_slave0_config_t slave0_config;
7299 ism330dlc_slv0_add_t slv0_add;
7300 int32_t ret;
7301 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7302
7303 if (ret == 0)
7304 {
7305 slv0_add.slave0_add = val->slv_add;
7306 slv0_add.rw_0 = 1;
7307 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_ADD,
7308 (uint8_t *)&slv0_add, 1);
7309
7310 if (ret == 0)
7311 {
7312 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV0_SUBADD,
7313 &(val->slv_subadd), 1);
7314
7315 if (ret == 0)
7316 {
7317 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7318 (uint8_t *)&slave0_config, 1);
7319 slave0_config.slave0_numop = val->slv_len;
7320
7321 if (ret == 0)
7322 {
7323 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7324 (uint8_t *)&slave0_config, 1);
7325
7326 if (ret == 0)
7327 {
7328 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7329 }
7330 }
7331 }
7332 }
7333 }
7334
7335 return ret;
7336 }
7337
7338 /**
7339 * @brief Configure slave 1 for perform a read.[get]
7340 *
7341 * @param ctx Read / write interface definitions
7342 * @param val Structure that contain:
7343 * - uint8_t slv_add; 8 bit i2c device address
7344 * - uint8_t slv_subadd; 8 bit register device address
7345 * - uint8_t slv_len; num of bit to read
7346 * @retval Interface status (MANDATORY: return 0 -> no Error).
7347 *
7348 */
ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,ism330dlc_sh_cfg_read_t * val)7349 int32_t ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
7350 ism330dlc_sh_cfg_read_t *val)
7351 {
7352 ism330dlc_slave1_config_t slave1_config;
7353 ism330dlc_slv1_add_t slv1_add;
7354 int32_t ret;
7355 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7356
7357 if (ret == 0)
7358 {
7359 slv1_add.slave1_add = val->slv_add;
7360 slv1_add.r_1 = 1;
7361 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV1_ADD,
7362 (uint8_t *)&slv1_add, 1);
7363
7364 if (ret == 0)
7365 {
7366 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV1_SUBADD,
7367 &(val->slv_subadd), 1);
7368
7369 if (ret == 0)
7370 {
7371 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7372 (uint8_t *)&slave1_config, 1);
7373 slave1_config.slave1_numop = val->slv_len;
7374
7375 if (ret == 0)
7376 {
7377 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7378 (uint8_t *)&slave1_config, 1);
7379
7380 if (ret == 0)
7381 {
7382 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7383 }
7384 }
7385 }
7386 }
7387 }
7388
7389 return ret;
7390 }
7391
7392 /**
7393 * @brief Configure slave 2 for perform a read.[get]
7394 *
7395 * @param ctx Read / write interface definitions
7396 * @param val Structure that contain:
7397 * - uint8_t slv_add; 8 bit i2c device address
7398 * - uint8_t slv_subadd; 8 bit register device address
7399 * - uint8_t slv_len; num of bit to read
7400 * @retval Interface status (MANDATORY: return 0 -> no Error).
7401 *
7402 */
ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,ism330dlc_sh_cfg_read_t * val)7403 int32_t ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
7404 ism330dlc_sh_cfg_read_t *val)
7405 {
7406 ism330dlc_slv2_add_t slv2_add;
7407 ism330dlc_slave2_config_t slave2_config;
7408 int32_t ret;
7409 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7410
7411 if (ret == 0)
7412 {
7413 slv2_add.slave2_add = val->slv_add;
7414 slv2_add.r_2 = 1;
7415 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV2_ADD,
7416 (uint8_t *)&slv2_add, 1);
7417
7418 if (ret == 0)
7419 {
7420 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV2_SUBADD,
7421 &(val->slv_subadd), 1);
7422
7423 if (ret == 0)
7424 {
7425 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
7426 (uint8_t *)&slave2_config, 1);
7427
7428 if (ret == 0)
7429 {
7430 slave2_config.slave2_numop = val->slv_len;
7431 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
7432 (uint8_t *)&slave2_config, 1);
7433
7434 if (ret == 0)
7435 {
7436 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7437 }
7438 }
7439 }
7440 }
7441 }
7442
7443 return ret;
7444 }
7445
7446 /**
7447 * @brief Configure slave 3 for perform a read.[get]
7448 *
7449 * @param ctx Read / write interface definitions
7450 * @param val Structure that contain:
7451 * - uint8_t slv_add; 8 bit i2c device address
7452 * - uint8_t slv_subadd; 8 bit register device address
7453 * - uint8_t slv_len; num of bit to read
7454 * @retval Interface status (MANDATORY: return 0 -> no Error).
7455 *
7456 */
ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,ism330dlc_sh_cfg_read_t * val)7457 int32_t ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
7458 ism330dlc_sh_cfg_read_t *val)
7459 {
7460 ism330dlc_slave3_config_t slave3_config;
7461 ism330dlc_slv3_add_t slv3_add;
7462 int32_t ret;
7463 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7464
7465 if (ret == 0)
7466 {
7467 slv3_add.slave3_add = val->slv_add;
7468 slv3_add.r_3 = 1;
7469 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV3_ADD,
7470 (uint8_t *)&slv3_add, 1);
7471
7472 if (ret == 0)
7473 {
7474 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLV3_SUBADD,
7475 (uint8_t *) & (val->slv_subadd), 1);
7476
7477 if (ret == 0)
7478 {
7479 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
7480 (uint8_t *)&slave3_config, 1);
7481
7482 if (ret == 0)
7483 {
7484 slave3_config.slave3_numop = val->slv_len;
7485 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
7486 (uint8_t *)&slave3_config, 1);
7487
7488 if (ret == 0)
7489 {
7490 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7491 }
7492 }
7493 }
7494 }
7495 }
7496
7497 return ret;
7498 }
7499
7500 /**
7501 * @brief Decimation of read operation on Slave 0 starting from the
7502 * sensor hub trigger.[set]
7503 *
7504 * @param ctx Read / write interface definitions
7505 * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG
7506 * @retval Interface status (MANDATORY: return 0 -> no Error).
7507 *
7508 */
ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t * ctx,ism330dlc_slave0_rate_t val)7509 int32_t ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t *ctx,
7510 ism330dlc_slave0_rate_t val)
7511 {
7512 ism330dlc_slave0_config_t slave0_config;
7513 int32_t ret;
7514 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7515
7516 if (ret == 0)
7517 {
7518 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7519 (uint8_t *)&slave0_config, 1);
7520
7521 if (ret == 0)
7522 {
7523 slave0_config.slave0_rate = (uint8_t) val;
7524 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7525 (uint8_t *)&slave0_config, 1);
7526
7527 if (ret == 0)
7528 {
7529 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7530 }
7531 }
7532 }
7533
7534 return ret;
7535 }
7536
7537 /**
7538 * @brief Decimation of read operation on Slave 0 starting from the
7539 * sensor hub trigger.[get]
7540 *
7541 * @param ctx Read / write interface definitions
7542 * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG
7543 * @retval Interface status (MANDATORY: return 0 -> no Error).
7544 *
7545 */
ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t * ctx,ism330dlc_slave0_rate_t * val)7546 int32_t ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t *ctx,
7547 ism330dlc_slave0_rate_t *val)
7548 {
7549 ism330dlc_slave0_config_t slave0_config;
7550 int32_t ret;
7551 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7552
7553 if (ret == 0)
7554 {
7555 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE0_CONFIG,
7556 (uint8_t *)&slave0_config, 1);
7557
7558 if (ret == 0)
7559 {
7560 switch (slave0_config.slave0_rate)
7561 {
7562 case ISM330DLC_SL0_NO_DEC:
7563 *val = ISM330DLC_SL0_NO_DEC;
7564 break;
7565
7566 case ISM330DLC_SL0_DEC_2:
7567 *val = ISM330DLC_SL0_DEC_2;
7568 break;
7569
7570 case ISM330DLC_SL0_DEC_4:
7571 *val = ISM330DLC_SL0_DEC_4;
7572 break;
7573
7574 case ISM330DLC_SL0_DEC_8:
7575 *val = ISM330DLC_SL0_DEC_8;
7576 break;
7577
7578 default:
7579 *val = ISM330DLC_SL0_NO_DEC;
7580 break;
7581 }
7582
7583 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7584 }
7585 }
7586
7587 return ret;
7588 }
7589
7590 /**
7591 * @brief Slave 0 write operation is performed only at the first sensor
7592 * hub cycle.
7593 * This is effective if the Aux_sens_on[1:0] field in
7594 * SLAVE0_CONFIG(04h) is set to a value other than 00.[set]
7595 *
7596 * @param ctx Read / write interface definitions
7597 * @param val Change the values of write_once in reg SLAVE1_CONFIG
7598 * @retval Interface status (MANDATORY: return 0 -> no Error).
7599 *
7600 */
ism330dlc_sh_write_mode_set(const stmdev_ctx_t * ctx,ism330dlc_write_once_t val)7601 int32_t ism330dlc_sh_write_mode_set(const stmdev_ctx_t *ctx,
7602 ism330dlc_write_once_t val)
7603 {
7604 ism330dlc_slave1_config_t slave1_config;
7605 int32_t ret;
7606 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7607
7608 if (ret == 0)
7609 {
7610 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7611 (uint8_t *)&slave1_config, 1);
7612 slave1_config.write_once = (uint8_t) val;
7613
7614 if (ret == 0)
7615 {
7616 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7617 (uint8_t *)&slave1_config, 1);
7618
7619 if (ret == 0)
7620 {
7621 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7622 }
7623 }
7624 }
7625
7626 return ret;
7627 }
7628
7629 /**
7630 * @brief Slave 0 write operation is performed only at the first sensor
7631 * hub cycle.
7632 * This is effective if the Aux_sens_on[1:0] field in
7633 * SLAVE0_CONFIG(04h) is set to a value other than 00.[get]
7634 *
7635 * @param ctx Read / write interface definitions
7636 * @param val Get the values of write_once in reg SLAVE1_CONFIG
7637 * @retval Interface status (MANDATORY: return 0 -> no Error).
7638 *
7639 */
ism330dlc_sh_write_mode_get(const stmdev_ctx_t * ctx,ism330dlc_write_once_t * val)7640 int32_t ism330dlc_sh_write_mode_get(const stmdev_ctx_t *ctx,
7641 ism330dlc_write_once_t *val)
7642 {
7643 ism330dlc_slave1_config_t slave1_config;
7644 int32_t ret;
7645 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7646
7647 if (ret == 0)
7648 {
7649 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7650 (uint8_t *)&slave1_config, 1);
7651
7652 if (ret == 0)
7653 {
7654 switch (slave1_config.write_once)
7655 {
7656 case ISM330DLC_EACH_SH_CYCLE:
7657 *val = ISM330DLC_EACH_SH_CYCLE;
7658 break;
7659
7660 case ISM330DLC_ONLY_FIRST_CYCLE:
7661 *val = ISM330DLC_ONLY_FIRST_CYCLE;
7662 break;
7663
7664 default:
7665 *val = ISM330DLC_EACH_SH_CYCLE;
7666 break;
7667 }
7668
7669 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7670 }
7671 }
7672
7673 return ret;
7674 }
7675
7676 /**
7677 * @brief Decimation of read operation on Slave 1 starting from the
7678 * sensor hub trigger.[set]
7679 *
7680 * @param ctx Read / write interface definitions
7681 * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG
7682 * @retval Interface status (MANDATORY: return 0 -> no Error).
7683 *
7684 */
ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t * ctx,ism330dlc_slave1_rate_t val)7685 int32_t ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t *ctx,
7686 ism330dlc_slave1_rate_t val)
7687 {
7688 ism330dlc_slave1_config_t slave1_config;
7689 int32_t ret;
7690 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7691
7692 if (ret == 0)
7693 {
7694 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7695 (uint8_t *)&slave1_config, 1);
7696
7697 if (ret == 0)
7698 {
7699 slave1_config.slave1_rate = (uint8_t) val;
7700 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7701 (uint8_t *)&slave1_config, 1);
7702
7703 if (ret == 0)
7704 {
7705 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7706 }
7707 }
7708 }
7709
7710 return ret;
7711 }
7712
7713 /**
7714 * @brief Decimation of read operation on Slave 1 starting from the
7715 * sensor hub trigger.[get]
7716 *
7717 * @param ctx Read / write interface definitions reg SLAVE1_CONFIG
7718 * @retval Interface status (MANDATORY: return 0 -> no Error).
7719 *
7720 */
ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t * ctx,ism330dlc_slave1_rate_t * val)7721 int32_t ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t *ctx,
7722 ism330dlc_slave1_rate_t *val)
7723 {
7724 ism330dlc_slave1_config_t slave1_config;
7725 int32_t ret;
7726 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7727
7728 if (ret == 0)
7729 {
7730 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE1_CONFIG,
7731 (uint8_t *)&slave1_config, 1);
7732
7733 if (ret == 0)
7734 {
7735 switch (slave1_config.slave1_rate)
7736 {
7737 case ISM330DLC_SL1_NO_DEC:
7738 *val = ISM330DLC_SL1_NO_DEC;
7739 break;
7740
7741 case ISM330DLC_SL1_DEC_2:
7742 *val = ISM330DLC_SL1_DEC_2;
7743 break;
7744
7745 case ISM330DLC_SL1_DEC_4:
7746 *val = ISM330DLC_SL1_DEC_4;
7747 break;
7748
7749 case ISM330DLC_SL1_DEC_8:
7750 *val = ISM330DLC_SL1_DEC_8;
7751 break;
7752
7753 default:
7754 *val = ISM330DLC_SL1_NO_DEC;
7755 break;
7756 }
7757
7758 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7759 }
7760 }
7761
7762 return ret;
7763 }
7764
7765 /**
7766 * @brief Decimation of read operation on Slave 2 starting from the
7767 * sensor hub trigger.[set]
7768 *
7769 * @param ctx Read / write interface definitions
7770 * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG
7771 * @retval Interface status (MANDATORY: return 0 -> no Error).
7772 *
7773 */
ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t * ctx,ism330dlc_slave2_rate_t val)7774 int32_t ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t *ctx,
7775 ism330dlc_slave2_rate_t val)
7776 {
7777 ism330dlc_slave2_config_t slave2_config;
7778 int32_t ret;
7779 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7780
7781 if (ret == 0)
7782 {
7783 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
7784 (uint8_t *)&slave2_config, 1);
7785
7786 if (ret == 0)
7787 {
7788 slave2_config.slave2_rate = (uint8_t) val;
7789 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
7790 (uint8_t *)&slave2_config, 1);
7791
7792 if (ret == 0)
7793 {
7794 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7795 }
7796 }
7797 }
7798
7799 return ret;
7800 }
7801
7802 /**
7803 * @brief Decimation of read operation on Slave 2 starting from the
7804 * sensor hub trigger.[get]
7805 *
7806 * @param ctx Read / write interface definitions
7807 * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG
7808 * @retval Interface status (MANDATORY: return 0 -> no Error).
7809 *
7810 */
ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t * ctx,ism330dlc_slave2_rate_t * val)7811 int32_t ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t *ctx,
7812 ism330dlc_slave2_rate_t *val)
7813 {
7814 ism330dlc_slave2_config_t slave2_config;
7815 int32_t ret;
7816 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7817
7818 if (ret == 0)
7819 {
7820 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE2_CONFIG,
7821 (uint8_t *)&slave2_config, 1);
7822
7823 if (ret == 0)
7824 {
7825 switch (slave2_config.slave2_rate)
7826 {
7827 case ISM330DLC_SL2_NO_DEC:
7828 *val = ISM330DLC_SL2_NO_DEC;
7829 break;
7830
7831 case ISM330DLC_SL2_DEC_2:
7832 *val = ISM330DLC_SL2_DEC_2;
7833 break;
7834
7835 case ISM330DLC_SL2_DEC_4:
7836 *val = ISM330DLC_SL2_DEC_4;
7837 break;
7838
7839 case ISM330DLC_SL2_DEC_8:
7840 *val = ISM330DLC_SL2_DEC_8;
7841 break;
7842
7843 default:
7844 *val = ISM330DLC_SL2_NO_DEC;
7845 break;
7846 }
7847
7848 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7849 }
7850 }
7851
7852 return ret;
7853 }
7854
7855 /**
7856 * @brief Decimation of read operation on Slave 3 starting from the
7857 * sensor hub trigger.[set]
7858 *
7859 * @param ctx Read / write interface definitions
7860 * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG
7861 * @retval Interface status (MANDATORY: return 0 -> no Error).
7862 *
7863 */
ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t * ctx,ism330dlc_slave3_rate_t val)7864 int32_t ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t *ctx,
7865 ism330dlc_slave3_rate_t val)
7866 {
7867 ism330dlc_slave3_config_t slave3_config;
7868 int32_t ret;
7869 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7870
7871 if (ret == 0)
7872 {
7873 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
7874 (uint8_t *)&slave3_config, 1);
7875 slave3_config.slave3_rate = (uint8_t)val;
7876
7877 if (ret == 0)
7878 {
7879 ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
7880 (uint8_t *)&slave3_config, 1);
7881
7882 if (ret == 0)
7883 {
7884 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7885 }
7886 }
7887 }
7888
7889 return ret;
7890 }
7891
7892 /**
7893 * @brief Decimation of read operation on Slave 3 starting from the
7894 * sensor hub trigger.[get]
7895 *
7896 * @param ctx Read / write interface definitions
7897 * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG.
7898 * @retval Interface status (MANDATORY: return 0 -> no Error).
7899 *
7900 */
ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t * ctx,ism330dlc_slave3_rate_t * val)7901 int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx,
7902 ism330dlc_slave3_rate_t *val)
7903 {
7904 ism330dlc_slave3_config_t slave3_config;
7905 int32_t ret;
7906 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_BANK_A);
7907
7908 if (ret == 0)
7909 {
7910 ret = ism330dlc_read_reg(ctx, ISM330DLC_SLAVE3_CONFIG,
7911 (uint8_t *)&slave3_config, 1);
7912
7913 if (ret == 0)
7914 {
7915 switch (slave3_config.slave3_rate)
7916 {
7917 case ISM330DLC_SL3_NO_DEC:
7918 *val = ISM330DLC_SL3_NO_DEC;
7919 break;
7920
7921 case ISM330DLC_SL3_DEC_2:
7922 *val = ISM330DLC_SL3_DEC_2;
7923 break;
7924
7925 case ISM330DLC_SL3_DEC_4:
7926 *val = ISM330DLC_SL3_DEC_4;
7927 break;
7928
7929 case ISM330DLC_SL3_DEC_8:
7930 *val = ISM330DLC_SL3_DEC_8;
7931 break;
7932
7933 default:
7934 *val = ISM330DLC_SL3_NO_DEC;
7935 break;
7936 }
7937
7938 ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK);
7939 }
7940 }
7941
7942 return ret;
7943 }
7944
7945 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7946
