1 /**
2 ******************************************************************************
3 * @file ism330bx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ISM330BX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ism330bx_reg.h"
21
22 /**
23 * @defgroup ISM330BX
24 * @brief This file provides a set of functions needed to drive the
25 * ism330bx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ism330bx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ism330bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
ism330bx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak ism330bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
ism330bx_from_sflp_to_mg(int16_t lsb)122 float_t ism330bx_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
ism330bx_from_fs2_to_mg(int16_t lsb)127 float_t ism330bx_from_fs2_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
ism330bx_from_fs4_to_mg(int16_t lsb)132 float_t ism330bx_from_fs4_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
ism330bx_from_fs8_to_mg(int16_t lsb)137 float_t ism330bx_from_fs8_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.244f;
140 }
141
ism330bx_from_fs16_to_mg(int16_t lsb)142 float_t ism330bx_from_fs16_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.488f;
145 }
146
ism330bx_from_fs125_to_mdps(int16_t lsb)147 float_t ism330bx_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
ism330bx_from_fs250_to_mdps(int16_t lsb)152 float_t ism330bx_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
ism330bx_from_fs500_to_mdps(int16_t lsb)157 float_t ism330bx_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
ism330bx_from_fs1000_to_mdps(int16_t lsb)162 float_t ism330bx_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
ism330bx_from_fs2000_to_mdps(int16_t lsb)167 float_t ism330bx_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
ism330bx_from_fs4000_to_mdps(int16_t lsb)172 float_t ism330bx_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
ism330bx_from_lsb_to_celsius(int16_t lsb)177 float_t ism330bx_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
ism330bx_from_lsb_to_nsec(uint32_t lsb)182 uint64_t ism330bx_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((uint64_t)lsb * 21750);
185 }
186
ism330bx_from_lsb_to_mv(int16_t lsb)187 float_t ism330bx_from_lsb_to_mv(int16_t lsb)
188 {
189 return ((float_t)lsb) / 78.0f;
190 }
191
192 /**
193 * @}
194 *
195 */
196
197 /**
198 * @defgroup Common
199 * @brief This section groups common useful functions.
200 *
201 */
202
203 /**
204 * @brief Reset of the device.[set]
205 *
206 * @param ctx read / write interface definitions
207 * @param val Reset of the device.
208 * @retval interface status (MANDATORY: return 0 -> no Error)
209 *
210 */
ism330bx_reset_set(const stmdev_ctx_t * ctx,ism330bx_reset_t val)211 int32_t ism330bx_reset_set(const stmdev_ctx_t *ctx, ism330bx_reset_t val)
212 {
213 ism330bx_func_cfg_access_t func_cfg_access;
214 ism330bx_ctrl3_t ctrl3;
215 int32_t ret;
216
217 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
218 if (ret == 0)
219 {
220 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
221 }
222
223 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
224 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
225 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
226
227 if (ret == 0)
228 {
229 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
230 }
231 if (ret == 0)
232 {
233 ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
234 }
235
236 return ret;
237 }
238
239 /**
240 * @brief Global reset of the device.[get]
241 *
242 * @param ctx read / write interface definitions
243 * @param val Global reset of the device.
244 * @retval interface status (MANDATORY: return 0 -> no Error)
245 *
246 */
ism330bx_reset_get(const stmdev_ctx_t * ctx,ism330bx_reset_t * val)247 int32_t ism330bx_reset_get(const stmdev_ctx_t *ctx, ism330bx_reset_t *val)
248 {
249 ism330bx_func_cfg_access_t func_cfg_access;
250 ism330bx_ctrl3_t ctrl3;
251 int32_t ret;
252
253 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
254 if (ret == 0)
255 {
256 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
257 }
258
259 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
260 {
261 case ISM330BX_READY:
262 *val = ISM330BX_READY;
263 break;
264
265 case ISM330BX_GLOBAL_RST:
266 *val = ISM330BX_GLOBAL_RST;
267 break;
268
269 case ISM330BX_RESTORE_CAL_PARAM:
270 *val = ISM330BX_RESTORE_CAL_PARAM;
271 break;
272
273 case ISM330BX_RESTORE_CTRL_REGS:
274 *val = ISM330BX_RESTORE_CTRL_REGS;
275 break;
276
277 default:
278 *val = ISM330BX_GLOBAL_RST;
279 break;
280 }
281 return ret;
282 }
283
284 /**
285 * @brief Change memory bank.[set]
286 *
287 * @param ctx read / write interface definitions
288 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
289 * @retval interface status (MANDATORY: return 0 -> no Error)
290 *
291 */
ism330bx_mem_bank_set(const stmdev_ctx_t * ctx,ism330bx_mem_bank_t val)292 int32_t ism330bx_mem_bank_set(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t val)
293 {
294 ism330bx_func_cfg_access_t func_cfg_access;
295 int32_t ret;
296
297 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
298 if (ret == 0)
299 {
300 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
301 ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
302 }
303
304 return ret;
305 }
306
307 /**
308 * @brief Change memory bank.[get]
309 *
310 * @param ctx read / write interface definitions
311 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
ism330bx_mem_bank_get(const stmdev_ctx_t * ctx,ism330bx_mem_bank_t * val)315 int32_t ism330bx_mem_bank_get(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t *val)
316 {
317 ism330bx_func_cfg_access_t func_cfg_access;
318 int32_t ret;
319
320 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
321
322 switch (func_cfg_access.emb_func_reg_access)
323 {
324 case ISM330BX_MAIN_MEM_BANK:
325 *val = ISM330BX_MAIN_MEM_BANK;
326 break;
327
328 case ISM330BX_EMBED_FUNC_MEM_BANK:
329 *val = ISM330BX_EMBED_FUNC_MEM_BANK;
330 break;
331
332 default:
333 *val = ISM330BX_MAIN_MEM_BANK;
334 break;
335 }
336 return ret;
337 }
338
339 /**
340 * @brief Device ID.[get]
341 *
342 * @param ctx read / write interface definitions
343 * @param val Device ID.
344 * @retval interface status (MANDATORY: return 0 -> no Error)
345 *
346 */
ism330bx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)347 int32_t ism330bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
348 {
349 ism330bx_who_am_i_t who_am_i;
350 int32_t ret;
351
352 ret = ism330bx_read_reg(ctx, ISM330BX_WHO_AM_I, (uint8_t *)&who_am_i, 1);
353 *val = who_am_i.id;
354
355 return ret;
356 }
357
358 /**
359 * @brief Accelerometer output data rate (ODR) selection.[set]
360 *
361 * @param ctx read / write interface definitions
362 * @param val ism330bx_xl_data_rate_t enum
363 * @retval interface status (MANDATORY: return 0 -> no Error)
364 *
365 */
ism330bx_xl_data_rate_set(const stmdev_ctx_t * ctx,ism330bx_xl_data_rate_t val)366 int32_t ism330bx_xl_data_rate_set(const stmdev_ctx_t *ctx,
367 ism330bx_xl_data_rate_t val)
368 {
369 ism330bx_ctrl1_t ctrl1;
370 int32_t ret;
371
372 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
373 if (ret == 0)
374 {
375 ctrl1.odr_xl = (uint8_t)val & 0xFU;
376 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
377 }
378
379 return ret;
380 }
381
382 /**
383 * @brief Accelerometer output data rate (ODR) selection.[get]
384 *
385 * @param ctx read / write interface definitions
386 * @param val ism330bx_xl_data_rate_t enum
387 * @retval interface status (MANDATORY: return 0 -> no Error)
388 *
389 */
ism330bx_xl_data_rate_get(const stmdev_ctx_t * ctx,ism330bx_xl_data_rate_t * val)390 int32_t ism330bx_xl_data_rate_get(const stmdev_ctx_t *ctx,
391 ism330bx_xl_data_rate_t *val)
392 {
393 ism330bx_ctrl1_t ctrl1;
394 int32_t ret;
395
396 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
397
398 switch (ctrl1.odr_xl)
399 {
400 case ISM330BX_XL_ODR_OFF:
401 *val = ISM330BX_XL_ODR_OFF;
402 break;
403
404 case ISM330BX_XL_ODR_AT_1Hz875:
405 *val = ISM330BX_XL_ODR_AT_1Hz875;
406 break;
407
408 case ISM330BX_XL_ODR_AT_7Hz5:
409 *val = ISM330BX_XL_ODR_AT_7Hz5;
410 break;
411
412 case ISM330BX_XL_ODR_AT_15Hz:
413 *val = ISM330BX_XL_ODR_AT_15Hz;
414 break;
415
416 case ISM330BX_XL_ODR_AT_30Hz:
417 *val = ISM330BX_XL_ODR_AT_30Hz;
418 break;
419
420 case ISM330BX_XL_ODR_AT_60Hz:
421 *val = ISM330BX_XL_ODR_AT_60Hz;
422 break;
423
424 case ISM330BX_XL_ODR_AT_120Hz:
425 *val = ISM330BX_XL_ODR_AT_120Hz;
426 break;
427
428 case ISM330BX_XL_ODR_AT_240Hz:
429 *val = ISM330BX_XL_ODR_AT_240Hz;
430 break;
431
432 case ISM330BX_XL_ODR_AT_480Hz:
433 *val = ISM330BX_XL_ODR_AT_480Hz;
434 break;
435
436 case ISM330BX_XL_ODR_AT_960Hz:
437 *val = ISM330BX_XL_ODR_AT_960Hz;
438 break;
439
440 case ISM330BX_XL_ODR_AT_1920Hz:
441 *val = ISM330BX_XL_ODR_AT_1920Hz;
442 break;
443
444 case ISM330BX_XL_ODR_AT_3840Hz:
445 *val = ISM330BX_XL_ODR_AT_3840Hz;
446 break;
447
448 default:
449 *val = ISM330BX_XL_ODR_OFF;
450 break;
451 }
452 return ret;
453 }
454
455 /**
456 * @brief Accelerometer operating mode selection.[set]
457 *
458 * @param ctx read / write interface definitions
459 * @param val ism330bx_xl_mode_t struct
460 * @retval interface status (MANDATORY: return 0 -> no Error)
461 *
462 */
ism330bx_xl_mode_set(const stmdev_ctx_t * ctx,ism330bx_xl_mode_t val)463 int32_t ism330bx_xl_mode_set(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t val)
464 {
465 ism330bx_ctrl1_t ctrl1;
466 int32_t ret;
467
468 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
469
470 if (ret == 0)
471 {
472 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
473 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
474 }
475
476 return ret;
477 }
478
479 /**
480 * @brief Accelerometer operating mode selection.[get]
481 *
482 * @param ctx read / write interface definitions
483 * @param val ism330bx_xl_mode_t struct
484 * @retval interface status (MANDATORY: return 0 -> no Error)
485 *
486 */
ism330bx_xl_mode_get(const stmdev_ctx_t * ctx,ism330bx_xl_mode_t * val)487 int32_t ism330bx_xl_mode_get(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t *val)
488 {
489 ism330bx_ctrl1_t ctrl1;
490 int32_t ret;
491
492 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1);
493
494 switch (ctrl1.op_mode_xl)
495 {
496 case ISM330BX_XL_HIGH_PERFORMANCE_MD:
497 *val = ISM330BX_XL_HIGH_PERFORMANCE_MD;
498 break;
499
500 case ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD:
501 *val = ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD;
502 break;
503
504 case ISM330BX_XL_LOW_POWER_2_AVG_MD:
505 *val = ISM330BX_XL_LOW_POWER_2_AVG_MD;
506 break;
507
508 case ISM330BX_XL_LOW_POWER_4_AVG_MD:
509 *val = ISM330BX_XL_LOW_POWER_4_AVG_MD;
510 break;
511
512 case ISM330BX_XL_LOW_POWER_8_AVG_MD:
513 *val = ISM330BX_XL_LOW_POWER_8_AVG_MD;
514 break;
515
516 default:
517 *val = ISM330BX_XL_HIGH_PERFORMANCE_MD;
518 break;
519 }
520 return ret;
521 }
522
523 /**
524 * @brief Gyroscope output data rate (ODR) selection.[set]
525 *
526 * @param ctx read / write interface definitions
527 * @param val ism330bx_gy_data_rate_t enum
528 * @retval interface status (MANDATORY: return 0 -> no Error)
529 *
530 */
ism330bx_gy_data_rate_set(const stmdev_ctx_t * ctx,ism330bx_gy_data_rate_t val)531 int32_t ism330bx_gy_data_rate_set(const stmdev_ctx_t *ctx,
532 ism330bx_gy_data_rate_t val)
533 {
534 ism330bx_ctrl2_t ctrl2;
535 int32_t ret;
536
537 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
538
539 if (ret == 0)
540 {
541 ctrl2.odr_g = (uint8_t)val & 0xFU;
542 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
543 }
544
545 return ret;
546 }
547
548 /**
549 * @brief Gyroscope output data rate (ODR) selection.[get]
550 *
551 * @param ctx read / write interface definitions
552 * @param val ism330bx_gy_data_rate_t enum
553 * @retval interface status (MANDATORY: return 0 -> no Error)
554 *
555 */
ism330bx_gy_data_rate_get(const stmdev_ctx_t * ctx,ism330bx_gy_data_rate_t * val)556 int32_t ism330bx_gy_data_rate_get(const stmdev_ctx_t *ctx,
557 ism330bx_gy_data_rate_t *val)
558 {
559 ism330bx_ctrl2_t ctrl2;
560 int32_t ret;
561
562 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
563
564 switch (ctrl2.odr_g)
565 {
566 case ISM330BX_GY_ODR_OFF:
567 *val = ISM330BX_GY_ODR_OFF;
568 break;
569
570 case ISM330BX_GY_ODR_AT_7Hz5:
571 *val = ISM330BX_GY_ODR_AT_7Hz5;
572 break;
573
574 case ISM330BX_GY_ODR_AT_15Hz:
575 *val = ISM330BX_GY_ODR_AT_15Hz;
576 break;
577
578 case ISM330BX_GY_ODR_AT_30Hz:
579 *val = ISM330BX_GY_ODR_AT_30Hz;
580 break;
581
582 case ISM330BX_GY_ODR_AT_60Hz:
583 *val = ISM330BX_GY_ODR_AT_60Hz;
584 break;
585
586 case ISM330BX_GY_ODR_AT_120Hz:
587 *val = ISM330BX_GY_ODR_AT_120Hz;
588 break;
589
590 case ISM330BX_GY_ODR_AT_240Hz:
591 *val = ISM330BX_GY_ODR_AT_240Hz;
592 break;
593
594 case ISM330BX_GY_ODR_AT_480Hz:
595 *val = ISM330BX_GY_ODR_AT_480Hz;
596 break;
597
598 case ISM330BX_GY_ODR_AT_960Hz:
599 *val = ISM330BX_GY_ODR_AT_960Hz;
600 break;
601
602 case ISM330BX_GY_ODR_AT_1920Hz:
603 *val = ISM330BX_GY_ODR_AT_1920Hz;
604 break;
605
606 case ISM330BX_GY_ODR_AT_3840Hz:
607 *val = ISM330BX_GY_ODR_AT_3840Hz;
608 break;
609
610 default:
611 *val = ISM330BX_GY_ODR_OFF;
612 break;
613 }
614 return ret;
615 }
616
617 /**
618 * @brief Gyroscope operating mode selection.[set]
619 *
620 * @param ctx read / write interface definitions
621 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
622 * @retval interface status (MANDATORY: return 0 -> no Error)
623 *
624 */
ism330bx_gy_mode_set(const stmdev_ctx_t * ctx,ism330bx_gy_mode_t val)625 int32_t ism330bx_gy_mode_set(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t val)
626 {
627 ism330bx_ctrl2_t ctrl2;
628 int32_t ret;
629
630 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
631 if (ret == 0)
632 {
633 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
634 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
635 }
636
637 return ret;
638 }
639
640 /**
641 * @brief Gyroscope operating mode selection.[get]
642 *
643 * @param ctx read / write interface definitions
644 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
645 * @retval interface status (MANDATORY: return 0 -> no Error)
646 *
647 */
ism330bx_gy_mode_get(const stmdev_ctx_t * ctx,ism330bx_gy_mode_t * val)648 int32_t ism330bx_gy_mode_get(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t *val)
649 {
650 ism330bx_ctrl2_t ctrl2;
651 int32_t ret;
652
653 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1);
654 switch (ctrl2.op_mode_g)
655 {
656 case ISM330BX_GY_HIGH_PERFORMANCE_MD:
657 *val = ISM330BX_GY_HIGH_PERFORMANCE_MD;
658 break;
659
660 case ISM330BX_GY_SLEEP_MD:
661 *val = ISM330BX_GY_SLEEP_MD;
662 break;
663
664 case ISM330BX_GY_LOW_POWER_MD:
665 *val = ISM330BX_GY_LOW_POWER_MD;
666 break;
667
668 default:
669 *val = ISM330BX_GY_HIGH_PERFORMANCE_MD;
670 break;
671 }
672 return ret;
673 }
674
675 /**
676 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
677 *
678 * @param ctx read / write interface definitions
679 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
680 * @retval interface status (MANDATORY: return 0 -> no Error)
681 *
682 */
ism330bx_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)683 int32_t ism330bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
684 {
685 ism330bx_ctrl3_t ctrl3;
686 int32_t ret;
687
688 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
689 if (ret == 0)
690 {
691 ctrl3.if_inc = val;
692 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
693 }
694
695 return ret;
696 }
697
698 /**
699 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
700 *
701 * @param ctx read / write interface definitions
702 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
703 * @retval interface status (MANDATORY: return 0 -> no Error)
704 *
705 */
ism330bx_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)706 int32_t ism330bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
707 {
708 ism330bx_ctrl3_t ctrl3;
709 int32_t ret;
710
711 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
712 *val = ctrl3.if_inc;
713
714
715 return ret;
716 }
717
718 /**
719 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
720 *
721 * @param ctx read / write interface definitions
722 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
723 * @retval interface status (MANDATORY: return 0 -> no Error)
724 *
725 */
ism330bx_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)726 int32_t ism330bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
727 {
728 ism330bx_ctrl3_t ctrl3;
729 int32_t ret;
730
731 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
732
733 if (ret == 0)
734 {
735 ctrl3.bdu = val;
736 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
737 }
738
739 return ret;
740 }
741
742 /**
743 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
744 *
745 * @param ctx read / write interface definitions
746 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
747 * @retval interface status (MANDATORY: return 0 -> no Error)
748 *
749 */
ism330bx_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)750 int32_t ism330bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
751 {
752 ism330bx_ctrl3_t ctrl3;
753 int32_t ret;
754
755 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1);
756 *val = ctrl3.bdu;
757
758 return ret;
759 }
760
761 /**
762 * @brief Enables pulsed data-ready mode (~75 us).[set]
763 *
764 * @param ctx read / write interface definitions
765 * @param val DRDY_LATCHED, DRDY_PULSED,
766 * @retval interface status (MANDATORY: return 0 -> no Error)
767 *
768 */
ism330bx_data_ready_mode_set(const stmdev_ctx_t * ctx,ism330bx_data_ready_mode_t val)769 int32_t ism330bx_data_ready_mode_set(const stmdev_ctx_t *ctx,
770 ism330bx_data_ready_mode_t val)
771 {
772 ism330bx_ctrl4_t ctrl4;
773 int32_t ret;
774
775 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
776
777 if (ret == 0)
778 {
779 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
780 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
781 }
782
783 return ret;
784 }
785
786 /**
787 * @brief Enables pulsed data-ready mode (~75 us).[get]
788 *
789 * @param ctx read / write interface definitions
790 * @param val DRDY_LATCHED, DRDY_PULSED,
791 * @retval interface status (MANDATORY: return 0 -> no Error)
792 *
793 */
ism330bx_data_ready_mode_get(const stmdev_ctx_t * ctx,ism330bx_data_ready_mode_t * val)794 int32_t ism330bx_data_ready_mode_get(const stmdev_ctx_t *ctx,
795 ism330bx_data_ready_mode_t *val)
796 {
797 ism330bx_ctrl4_t ctrl4;
798 int32_t ret;
799
800 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
801
802 switch (ctrl4.drdy_pulsed)
803 {
804 case ISM330BX_DRDY_LATCHED:
805 *val = ISM330BX_DRDY_LATCHED;
806 break;
807
808 case ISM330BX_DRDY_PULSED:
809 *val = ISM330BX_DRDY_PULSED;
810 break;
811
812 default:
813 *val = ISM330BX_DRDY_LATCHED;
814 break;
815 }
816 return ret;
817 }
818
819 /**
820 * @brief Gyroscope full-scale selection[set]
821 *
822 * @param ctx read / write interface definitions
823 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
824 * @retval interface status (MANDATORY: return 0 -> no Error)
825 *
826 */
ism330bx_gy_full_scale_set(const stmdev_ctx_t * ctx,ism330bx_gy_full_scale_t val)827 int32_t ism330bx_gy_full_scale_set(const stmdev_ctx_t *ctx,
828 ism330bx_gy_full_scale_t val)
829 {
830 ism330bx_ctrl6_t ctrl6;
831 int32_t ret;
832
833 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
834
835 if (ret == 0)
836 {
837 ctrl6.fs_g = (uint8_t)val & 0xFU;
838 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
839 }
840
841 return ret;
842 }
843
844 /**
845 * @brief Gyroscope full-scale selection[get]
846 *
847 * @param ctx read / write interface definitions
848 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
849 * @retval interface status (MANDATORY: return 0 -> no Error)
850 *
851 */
ism330bx_gy_full_scale_get(const stmdev_ctx_t * ctx,ism330bx_gy_full_scale_t * val)852 int32_t ism330bx_gy_full_scale_get(const stmdev_ctx_t *ctx,
853 ism330bx_gy_full_scale_t *val)
854 {
855 ism330bx_ctrl6_t ctrl6;
856 int32_t ret;
857
858 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
859
860 switch (ctrl6.fs_g)
861 {
862 case ISM330BX_125dps:
863 *val = ISM330BX_125dps;
864 break;
865
866 case ISM330BX_250dps:
867 *val = ISM330BX_250dps;
868 break;
869
870 case ISM330BX_500dps:
871 *val = ISM330BX_500dps;
872 break;
873
874 case ISM330BX_1000dps:
875 *val = ISM330BX_1000dps;
876 break;
877
878 case ISM330BX_2000dps:
879 *val = ISM330BX_2000dps;
880 break;
881
882 case ISM330BX_4000dps:
883 *val = ISM330BX_4000dps;
884 break;
885
886 default:
887 *val = ISM330BX_125dps;
888 break;
889 }
890 return ret;
891 }
892
893 /**
894 * @brief Accelerometer full-scale selection.[set]
895 *
896 * @param ctx read / write interface definitions
897 * @param val 2g, 4g, 8g, 16g,
898 * @retval interface status (MANDATORY: return 0 -> no Error)
899 *
900 */
ism330bx_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330bx_xl_full_scale_t val)901 int32_t ism330bx_xl_full_scale_set(const stmdev_ctx_t *ctx,
902 ism330bx_xl_full_scale_t val)
903 {
904 ism330bx_ctrl8_t ctrl8;
905 int32_t ret;
906
907 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
908
909 if (ret == 0)
910 {
911 ctrl8.fs_xl = (uint8_t)val & 0x3U;
912 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
913 }
914
915 return ret;
916 }
917
918 /**
919 * @brief Accelerometer full-scale selection.[get]
920 *
921 * @param ctx read / write interface definitions
922 * @param val 2g, 4g, 8g, 16g,
923 * @retval interface status (MANDATORY: return 0 -> no Error)
924 *
925 */
ism330bx_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330bx_xl_full_scale_t * val)926 int32_t ism330bx_xl_full_scale_get(const stmdev_ctx_t *ctx,
927 ism330bx_xl_full_scale_t *val)
928 {
929 ism330bx_ctrl8_t ctrl8;
930 int32_t ret;
931
932 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
933
934 switch (ctrl8.fs_xl)
935 {
936 case ISM330BX_2g:
937 *val = ISM330BX_2g;
938 break;
939
940 case ISM330BX_4g:
941 *val = ISM330BX_4g;
942 break;
943
944 case ISM330BX_8g:
945 *val = ISM330BX_8g;
946 break;
947
948 default:
949 *val = ISM330BX_2g;
950 break;
951 }
952 return ret;
953 }
954
955 /**
956 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
957 *
958 * @param ctx read / write interface definitions
959 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
960 * @retval interface status (MANDATORY: return 0 -> no Error)
961 *
962 */
ism330bx_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)963 int32_t ism330bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
964 {
965 ism330bx_ctrl8_t ctrl8;
966 int32_t ret;
967
968 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
969
970 if (ret == 0)
971 {
972 ctrl8.xl_dualc_en = val;
973 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
974 }
975
976 return ret;
977 }
978
979 /**
980 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
981 *
982 * @param ctx read / write interface definitions
983 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
984 * @retval interface status (MANDATORY: return 0 -> no Error)
985 *
986 */
ism330bx_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)987 int32_t ism330bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
988 {
989 ism330bx_ctrl8_t ctrl8;
990 int32_t ret;
991
992 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
993 *val = ctrl8.xl_dualc_en;
994
995 return ret;
996 }
997
998 /**
999 * @brief Accelerometer self-test selection.[set]
1000 *
1001 * @param ctx read / write interface definitions
1002 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1003 * @retval interface status (MANDATORY: return 0 -> no Error)
1004 *
1005 */
ism330bx_xl_self_test_set(const stmdev_ctx_t * ctx,ism330bx_xl_self_test_t val)1006 int32_t ism330bx_xl_self_test_set(const stmdev_ctx_t *ctx,
1007 ism330bx_xl_self_test_t val)
1008 {
1009 ism330bx_ctrl10_t ctrl10;
1010 int32_t ret;
1011
1012 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1013
1014 if (ret == 0)
1015 {
1016 ctrl10.st_xl = (uint8_t)val & 0x3U;
1017 ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2;
1018 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1019 }
1020
1021 return ret;
1022 }
1023
1024 /**
1025 * @brief Accelerometer self-test selection.[get]
1026 *
1027 * @param ctx read / write interface definitions
1028 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1029 * @retval interface status (MANDATORY: return 0 -> no Error)
1030 *
1031 */
ism330bx_xl_self_test_get(const stmdev_ctx_t * ctx,ism330bx_xl_self_test_t * val)1032 int32_t ism330bx_xl_self_test_get(const stmdev_ctx_t *ctx,
1033 ism330bx_xl_self_test_t *val)
1034 {
1035 ism330bx_ctrl10_t ctrl10;
1036 int32_t ret;
1037
1038 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1039
1040 //switch (ctrl10.xl_st_offset)
1041 switch (ctrl10.st_xl)
1042 {
1043 case ISM330BX_XL_ST_DISABLE:
1044 *val = ISM330BX_XL_ST_DISABLE;
1045 break;
1046
1047 case ISM330BX_XL_ST_POSITIVE:
1048 *val = ISM330BX_XL_ST_POSITIVE;
1049 break;
1050
1051 case ISM330BX_XL_ST_NEGATIVE:
1052 *val = ISM330BX_XL_ST_NEGATIVE;
1053 break;
1054
1055 default:
1056 *val = ISM330BX_XL_ST_DISABLE;
1057 break;
1058 }
1059 return ret;
1060 }
1061
1062 /**
1063 * @brief Gyroscope self-test selection.[set]
1064 *
1065 * @param ctx read / write interface definitions
1066 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1067 * @retval interface status (MANDATORY: return 0 -> no Error)
1068 *
1069 */
ism330bx_gy_self_test_set(const stmdev_ctx_t * ctx,ism330bx_gy_self_test_t val)1070 int32_t ism330bx_gy_self_test_set(const stmdev_ctx_t *ctx,
1071 ism330bx_gy_self_test_t val)
1072 {
1073 ism330bx_ctrl10_t ctrl10;
1074 int32_t ret;
1075
1076 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1077
1078 if (ret == 0)
1079 {
1080 ctrl10.st_g = (uint8_t)val & 0x3U;
1081 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1082 }
1083
1084 return ret;
1085 }
1086
1087 /**
1088 * @brief Gyroscope self-test selection.[get]
1089 *
1090 * @param ctx read / write interface definitions
1091 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1092 * @retval interface status (MANDATORY: return 0 -> no Error)
1093 *
1094 */
ism330bx_gy_self_test_get(const stmdev_ctx_t * ctx,ism330bx_gy_self_test_t * val)1095 int32_t ism330bx_gy_self_test_get(const stmdev_ctx_t *ctx,
1096 ism330bx_gy_self_test_t *val)
1097 {
1098 ism330bx_ctrl10_t ctrl10;
1099 int32_t ret;
1100
1101 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
1102
1103 switch (ctrl10.st_g)
1104 {
1105 case ISM330BX_GY_ST_DISABLE:
1106 *val = ISM330BX_GY_ST_DISABLE;
1107 break;
1108
1109 case ISM330BX_GY_ST_POSITIVE:
1110 *val = ISM330BX_GY_ST_POSITIVE;
1111 break;
1112
1113 case ISM330BX_GY_ST_NEGATIVE:
1114 *val = ISM330BX_GY_ST_NEGATIVE;
1115 break;
1116
1117 default:
1118 *val = ISM330BX_GY_ST_DISABLE;
1119 break;
1120 }
1121 return ret;
1122 }
1123
1124 /**
1125 * @brief Get the status of all the interrupt sources.[get]
1126 *
1127 * @param ctx read / write interface definitions
1128 * @param val Get the status of all the interrupt sources.
1129 * @retval interface status (MANDATORY: return 0 -> no Error)
1130 *
1131 */
ism330bx_all_sources_get(const stmdev_ctx_t * ctx,ism330bx_all_sources_t * val)1132 int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx,
1133 ism330bx_all_sources_t *val)
1134 {
1135 ism330bx_emb_func_status_mainpage_t emb_func_status_mainpage;
1136 ism330bx_emb_func_exec_status_t emb_func_exec_status;
1137 ism330bx_fsm_status_mainpage_t fsm_status_mainpage;
1138 ism330bx_mlc_status_mainpage_t mlc_status_mainpage;
1139 ism330bx_functions_enable_t functions_enable;
1140 ism330bx_emb_func_src_t emb_func_src;
1141 ism330bx_fifo_status2_t fifo_status2;
1142 ism330bx_all_int_src_t all_int_src;
1143 ism330bx_wake_up_src_t wake_up_src;
1144 ism330bx_status_reg_t status_reg;
1145 ism330bx_d6d_src_t d6d_src;
1146 ism330bx_tap_src_t tap_src;
1147 uint8_t buff[7];
1148 int32_t ret;
1149
1150 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1151 if (ret == 0)
1152 {
1153 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
1154 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1155 }
1156
1157 if (ret == 0)
1158 {
1159 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff, 4);
1160 }
1161 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
1162 bytecpy((uint8_t *)&all_int_src, &buff[2]);
1163 bytecpy((uint8_t *)&status_reg, &buff[3]);
1164
1165 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
1166 val->fifo_bdr = fifo_status2.counter_bdr_ia;
1167 val->fifo_full = fifo_status2.fifo_full_ia;
1168 val->fifo_th = fifo_status2.fifo_wtm_ia;
1169
1170 val->free_fall = all_int_src.ff_ia;
1171 val->wake_up = all_int_src.wu_ia;
1172 val->six_d = all_int_src.d6d_ia;
1173
1174 val->drdy_xl = status_reg.xlda;
1175 val->drdy_gy = status_reg.gda;
1176 val->drdy_temp = status_reg.tda;
1177 val->drdy_ah_qvar = status_reg.ah_qvarda;
1178 val->timestamp = status_reg.timestamp_endcount;
1179
1180 if (ret == 0)
1181 {
1182 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1183 }
1184 if (ret == 0)
1185 {
1186 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
1187 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1188 }
1189
1190 if (ret == 0)
1191 {
1192 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_SRC, (uint8_t *)&buff, 7);
1193 }
1194
1195 if (ret == 0)
1196 {
1197 bytecpy((uint8_t *)&wake_up_src, &buff[0]);
1198 bytecpy((uint8_t *)&tap_src, &buff[1]);
1199 bytecpy((uint8_t *)&d6d_src, &buff[2]);
1200 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]);
1201 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]);
1202 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]);
1203
1204 val->sleep_change = wake_up_src.sleep_change_ia;
1205 val->wake_up_x = wake_up_src.x_wu;
1206 val->wake_up_y = wake_up_src.y_wu;
1207 val->wake_up_z = wake_up_src.z_wu;
1208 val->sleep_state = wake_up_src.sleep_state;
1209
1210 val->tap_x = tap_src.x_tap;
1211 val->tap_y = tap_src.y_tap;
1212 val->tap_z = tap_src.z_tap;
1213 val->tap_sign = tap_src.tap_sign;
1214 val->double_tap = tap_src.double_tap;
1215 val->single_tap = tap_src.single_tap;
1216
1217 val->six_d_zl = d6d_src.zl;
1218 val->six_d_zh = d6d_src.zh;
1219 val->six_d_yl = d6d_src.yl;
1220 val->six_d_yh = d6d_src.yh;
1221 val->six_d_xl = d6d_src.xl;
1222 val->six_d_xh = d6d_src.xh;
1223
1224 val->step_detector = emb_func_status_mainpage.is_step_det;
1225 val->tilt = emb_func_status_mainpage.is_tilt;
1226 val->sig_mot = emb_func_status_mainpage.is_sigmot;
1227 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
1228
1229 val->fsm1 = fsm_status_mainpage.is_fsm1;
1230 val->fsm2 = fsm_status_mainpage.is_fsm2;
1231 val->fsm3 = fsm_status_mainpage.is_fsm3;
1232 val->fsm4 = fsm_status_mainpage.is_fsm4;
1233 val->fsm5 = fsm_status_mainpage.is_fsm5;
1234 val->fsm6 = fsm_status_mainpage.is_fsm6;
1235 val->fsm7 = fsm_status_mainpage.is_fsm7;
1236 val->fsm8 = fsm_status_mainpage.is_fsm8;
1237
1238 val->mlc1 = mlc_status_mainpage.is_mlc1;
1239 val->mlc2 = mlc_status_mainpage.is_mlc2;
1240 val->mlc3 = mlc_status_mainpage.is_mlc3;
1241 val->mlc4 = mlc_status_mainpage.is_mlc4;
1242 }
1243
1244
1245 if (ret == 0)
1246 {
1247 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
1248 }
1249 if (ret == 0)
1250 {
1251 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status,
1252 1);
1253 }
1254 if (ret == 0)
1255 {
1256 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
1257 }
1258
1259 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
1260
1261 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
1262 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
1263 val->step_count_inc = emb_func_src.stepcounter_bit_set;
1264 val->step_count_overflow = emb_func_src.step_overflow;
1265 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
1266
1267 val->step_detector = emb_func_src.step_detected;
1268
1269 return ret;
1270 }
1271
ism330bx_flag_data_ready_get(const stmdev_ctx_t * ctx,ism330bx_data_ready_t * val)1272 int32_t ism330bx_flag_data_ready_get(const stmdev_ctx_t *ctx,
1273 ism330bx_data_ready_t *val)
1274 {
1275 ism330bx_status_reg_t status;
1276 int32_t ret;
1277
1278 ret = ism330bx_read_reg(ctx, ISM330BX_STATUS_REG, (uint8_t *)&status, 1);
1279 val->drdy_xl = status.xlda;
1280 val->drdy_gy = status.gda;
1281 val->drdy_temp = status.tda;
1282 val->drdy_ah_qvar = status.ah_qvarda;
1283
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief Temperature data output register[get]
1289 *
1290 * @param ctx read / write interface definitions
1291 * @param val Temperature data output register
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
ism330bx_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1295 int32_t ism330bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1296 {
1297 uint8_t buff[2];
1298 int32_t ret;
1299
1300 ret = ism330bx_read_reg(ctx, ISM330BX_OUT_TEMP_L, &buff[0], 2);
1301 *val = (int16_t)buff[1];
1302 *val = (*val * 256) + (int16_t)buff[0];
1303
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Angular rate sensor.[get]
1309 *
1310 * @param ctx read / write interface definitions
1311 * @param val Angular rate sensor.
1312 * @retval interface status (MANDATORY: return 0 -> no Error)
1313 *
1314 */
ism330bx_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1315 int32_t ism330bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1316 {
1317 uint8_t buff[6];
1318 int32_t ret;
1319
1320 ret = ism330bx_read_reg(ctx, ISM330BX_OUTX_L_G, &buff[0], 6);
1321 val[0] = (int16_t)buff[1];
1322 val[0] = (val[0] * 256) + (int16_t)buff[0];
1323 val[1] = (int16_t)buff[3];
1324 val[1] = (val[1] * 256) + (int16_t)buff[2];
1325 val[2] = (int16_t)buff[5];
1326 val[2] = (val[2] * 256) + (int16_t)buff[4];
1327
1328 return ret;
1329 }
1330
1331 /**
1332 * @brief Linear acceleration sensor.[get]
1333 *
1334 * @param ctx read / write interface definitions
1335 * @param val Linear acceleration sensor.
1336 * @retval interface status (MANDATORY: return 0 -> no Error)
1337 *
1338 */
ism330bx_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1339 int32_t ism330bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1340 {
1341 uint8_t buff[6];
1342 int32_t ret;
1343
1344 ret = ism330bx_read_reg(ctx, ISM330BX_OUTZ_L_A, &buff[0], 6);
1345 val[2] = (int16_t)buff[1];
1346 val[2] = (val[2] * 256) + (int16_t)buff[0];
1347 val[1] = (int16_t)buff[3];
1348 val[1] = (val[1] * 256) + (int16_t)buff[2];
1349 val[0] = (int16_t)buff[5];
1350 val[0] = (val[0] * 256) + (int16_t)buff[4];
1351
1352 return ret;
1353 }
1354
1355 /**
1356 * @brief Linear acceleration sensor for Dual channel mode.[get]
1357 *
1358 * @param ctx read / write interface definitions
1359 * @param val Linear acceleration sensor or Dual channel mode.
1360 * @retval interface status (MANDATORY: return 0 -> no Error)
1361 *
1362 */
ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1363 int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1364 {
1365 uint8_t buff[6];
1366 int32_t ret;
1367
1368 ret = ism330bx_read_reg(ctx, ISM330BX_UI_OUTZ_L_A_DUALC, &buff[0], 6);
1369 val[2] = (int16_t)buff[1];
1370 val[2] = (val[2] * 256) + (int16_t)buff[0];
1371 val[1] = (int16_t)buff[3];
1372 val[1] = (val[1] * 256) + (int16_t)buff[2];
1373 val[0] = (int16_t)buff[5];
1374 val[0] = (val[0] * 256) + (int16_t)buff[4];
1375
1376 return ret;
1377 }
1378
1379 /**
1380 * @brief Qvar data output register.[get]
1381 *
1382 * @param ctx read / write interface definitions
1383 * @param val Qvar data output register.
1384 * @retval interface status (MANDATORY: return 0 -> no Error)
1385 *
1386 */
ism330bx_ah_qvar_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1387 int32_t ism330bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1388 {
1389 uint8_t buff[2];
1390 int32_t ret;
1391
1392 ret = ism330bx_read_reg(ctx, ISM330BX_AH_QVAR_OUT_L, &buff[0], 2);
1393 *val = (int16_t)buff[1];
1394 *val = (*val * 256) + (int16_t)buff[0];
1395
1396 return ret;
1397 }
1398
1399 /**
1400 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
1401 *
1402 * @param ctx read / write interface definitions
1403 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
1404 * @retval interface status (MANDATORY: return 0 -> no Error)
1405 *
1406 */
ism330bx_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)1407 int32_t ism330bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
1408 {
1409 ism330bx_internal_freq_t internal_freq;
1410 int32_t ret;
1411
1412 ret = ism330bx_read_reg(ctx, ISM330BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
1413 *val = (int8_t)internal_freq.freq_fine;
1414
1415 return ret;
1416 }
1417
1418 /**
1419 * @brief Enable accelerometer axis.[set]
1420 *
1421 * @param ctx read / write interface definitions
1422 * @param val Enable accelerometer axis.
1423 * @retval interface status (MANDATORY: return 0 -> no Error)
1424 *
1425 */
ism330bx_tdm_xl_axis_set(const stmdev_ctx_t * ctx,ism330bx_tdm_xl_axis_t val)1426 int32_t ism330bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t val)
1427 {
1428 ism330bx_tdm_cfg1_t tdm_cfg1;
1429 int32_t ret;
1430
1431 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1432 if (ret == 0)
1433 {
1434 tdm_cfg1.tdm_xl_z_en = val.z;
1435 tdm_cfg1.tdm_xl_y_en = val.y;
1436 tdm_cfg1.tdm_xl_x_en = val.x;
1437 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1438 }
1439
1440 return ret;
1441 }
1442
1443 /**
1444 * @brief Enable accelerometer axis.[get]
1445 *
1446 * @param ctx read / write interface definitions
1447 * @param val Enable accelerometer axis.
1448 * @retval interface status (MANDATORY: return 0 -> no Error)
1449 *
1450 */
ism330bx_tdm_xl_axis_get(const stmdev_ctx_t * ctx,ism330bx_tdm_xl_axis_t * val)1451 int32_t ism330bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t *val)
1452 {
1453 ism330bx_tdm_cfg1_t tdm_cfg1;
1454 int32_t ret;
1455
1456 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1457 val->x = tdm_cfg1.tdm_xl_x_en;
1458 val->y = tdm_cfg1.tdm_xl_y_en;
1459 val->z = tdm_cfg1.tdm_xl_z_en;
1460
1461 return ret;
1462 }
1463
1464 /**
1465 * @brief Write buffer in a page.[set]
1466 *
1467 * @param ctx read / write interface definitions
1468 * @param val Write buffer in a page.
1469 * @retval interface status (MANDATORY: return 0 -> no Error)
1470 *
1471 */
ism330bx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1472 int32_t ism330bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1473 uint8_t *buf, uint8_t len)
1474 {
1475 ism330bx_page_address_t page_address;
1476 ism330bx_page_sel_t page_sel;
1477 ism330bx_page_rw_t page_rw;
1478 uint8_t msb;
1479 uint8_t lsb;
1480 int32_t ret;
1481 uint8_t i ;
1482
1483 msb = ((uint8_t)(address >> 8) & 0x0FU);
1484 lsb = (uint8_t)address & 0xFFU;
1485
1486 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
1487
1488 /* set page write */
1489 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1490 page_rw.page_read = PROPERTY_DISABLE;
1491 page_rw.page_write = PROPERTY_ENABLE;
1492 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1493
1494 /* select page */
1495 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1496 page_sel.page_sel = msb;
1497 page_sel.not_used0 = 1; // Default value
1498 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1499 1);
1500
1501 /* set page addr */
1502 page_address.page_addr = lsb;
1503 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS,
1504 (uint8_t *)&page_address, 1);
1505
1506 for (i = 0; ((i < len) && (ret == 0)); i++)
1507 {
1508 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1);
1509 lsb++;
1510
1511 /* Check if page wrap */
1512 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1513 {
1514 msb++;
1515 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1516
1517 if (ret == 0)
1518 {
1519 page_sel.page_sel = msb;
1520 page_sel.not_used0 = 1; // Default value
1521 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1522 1);
1523 }
1524 }
1525 }
1526
1527 page_sel.page_sel = 0;
1528 page_sel.not_used0 = 1;// Default value
1529 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1530 1);
1531
1532 /* unset page write */
1533 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1534 page_rw.page_read = PROPERTY_DISABLE;
1535 page_rw.page_write = PROPERTY_DISABLE;
1536 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1537
1538 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief Read buffer in a page.[set]
1545 *
1546 * @param ctx read / write interface definitions
1547 * @param val Write buffer in a page.
1548 * @retval interface status (MANDATORY: return 0 -> no Error)
1549 *
1550 */
ism330bx_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1551 int32_t ism330bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address,
1552 uint8_t *buf, uint8_t len)
1553 {
1554 ism330bx_page_address_t page_address;
1555 ism330bx_page_sel_t page_sel;
1556 ism330bx_page_rw_t page_rw;
1557 uint8_t msb;
1558 uint8_t lsb;
1559 int32_t ret;
1560 uint8_t i ;
1561
1562 msb = ((uint8_t)(address >> 8) & 0x0FU);
1563 lsb = (uint8_t)address & 0xFFU;
1564
1565 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
1566
1567 /* set page write */
1568 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1569 page_rw.page_read = PROPERTY_ENABLE;
1570 page_rw.page_write = PROPERTY_DISABLE;
1571 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1572
1573 /* select page */
1574 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1575 page_sel.page_sel = msb;
1576 page_sel.not_used0 = 1; // Default value
1577 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1578 1);
1579
1580 /* set page addr */
1581 page_address.page_addr = lsb;
1582 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS,
1583 (uint8_t *)&page_address, 1);
1584
1585 for (i = 0; ((i < len) && (ret == 0)); i++)
1586 {
1587 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1);
1588 lsb++;
1589
1590 /* Check if page wrap */
1591 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1592 {
1593 msb++;
1594 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1595
1596 if (ret == 0)
1597 {
1598 page_sel.page_sel = msb;
1599 page_sel.not_used0 = 1; // Default value
1600 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1601 1);
1602 }
1603 }
1604 }
1605
1606 page_sel.page_sel = 0;
1607 page_sel.not_used0 = 1;// Default value
1608 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel,
1609 1);
1610
1611 /* unset page write */
1612 ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1613 page_rw.page_read = PROPERTY_DISABLE;
1614 page_rw.page_write = PROPERTY_DISABLE;
1615 ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1616
1617 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
1618
1619 return ret;
1620 }
1621
1622 /**
1623 * @}
1624 *
1625 */
1626
1627 /**
1628 * @defgroup Timestamp
1629 * @brief This section groups all the functions that manage the
1630 * timestamp generation.
1631 * @{
1632 *
1633 */
1634
1635 /**
1636 * @brief Enables timestamp counter.[set]
1637 *
1638 * @param ctx read / write interface definitions
1639 * @param val Enables timestamp counter.
1640 * @retval interface status (MANDATORY: return 0 -> no Error)
1641 *
1642 */
ism330bx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1643 int32_t ism330bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1644 {
1645 ism330bx_functions_enable_t functions_enable;
1646 int32_t ret;
1647
1648 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1649 if (ret == 0)
1650 {
1651 functions_enable.timestamp_en = val;
1652 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1653 }
1654
1655 return ret;
1656 }
1657
1658 /**
1659 * @brief Enables timestamp counter.[get]
1660 *
1661 * @param ctx read / write interface definitions
1662 * @param val Enables timestamp counter.
1663 * @retval interface status (MANDATORY: return 0 -> no Error)
1664 *
1665 */
ism330bx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1666 int32_t ism330bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1667 {
1668 ism330bx_functions_enable_t functions_enable;
1669 int32_t ret;
1670
1671 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1672 *val = functions_enable.timestamp_en;
1673
1674 return ret;
1675 }
1676
1677 /**
1678 * @brief Timestamp data output.[get]
1679 *
1680 * @param ctx read / write interface definitions
1681 * @param val Timestamp data output.
1682 * @retval interface status (MANDATORY: return 0 -> no Error)
1683 *
1684 */
ism330bx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1685 int32_t ism330bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1686 {
1687 uint8_t buff[4];
1688 int32_t ret;
1689
1690 ret = ism330bx_read_reg(ctx, ISM330BX_TIMESTAMP0, &buff[0], 4);
1691 *val = buff[3];
1692 *val = (*val * 256U) + buff[2];
1693 *val = (*val * 256U) + buff[1];
1694 *val = (*val * 256U) + buff[0];
1695
1696 return ret;
1697 }
1698
1699 /**
1700 * @}
1701 *
1702 */
1703
1704 /**
1705 * @defgroup Filters
1706 * @brief This section group all the functions concerning the
1707 * filters configuration
1708 * @{
1709 *
1710 */
1711
1712 /**
1713 * @brief Protocol anti-spike filters.[set]
1714 *
1715 * @param ctx read / write interface definitions
1716 * @param val AUTO, ALWAYS_ACTIVE,
1717 * @retval interface status (MANDATORY: return 0 -> no Error)
1718 *
1719 */
ism330bx_filt_anti_spike_set(const stmdev_ctx_t * ctx,ism330bx_filt_anti_spike_t val)1720 int32_t ism330bx_filt_anti_spike_set(const stmdev_ctx_t *ctx,
1721 ism330bx_filt_anti_spike_t val)
1722 {
1723 ism330bx_if_cfg_t if_cfg;
1724 int32_t ret;
1725
1726 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1727
1728 if (ret == 0)
1729 {
1730 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
1731 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1732 }
1733
1734 return ret;
1735 }
1736
1737 /**
1738 * @brief Protocol anti-spike filters.[get]
1739 *
1740 * @param ctx read / write interface definitions
1741 * @param val AUTO, ALWAYS_ACTIVE,
1742 * @retval interface status (MANDATORY: return 0 -> no Error)
1743 *
1744 */
ism330bx_filt_anti_spike_get(const stmdev_ctx_t * ctx,ism330bx_filt_anti_spike_t * val)1745 int32_t ism330bx_filt_anti_spike_get(const stmdev_ctx_t *ctx,
1746 ism330bx_filt_anti_spike_t *val)
1747 {
1748 ism330bx_if_cfg_t if_cfg;
1749 int32_t ret;
1750
1751 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1752 switch (if_cfg.asf_ctrl)
1753 {
1754 case ISM330BX_AUTO:
1755 *val = ISM330BX_AUTO;
1756 break;
1757
1758 case ISM330BX_ALWAYS_ACTIVE:
1759 *val = ISM330BX_ALWAYS_ACTIVE;
1760 break;
1761
1762 default:
1763 *val = ISM330BX_AUTO;
1764 break;
1765 }
1766 return ret;
1767 }
1768
1769 /**
1770 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
1771 *
1772 * @param ctx read / write interface definitions
1773 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1774 * @retval interface status (MANDATORY: return 0 -> no Error)
1775 *
1776 */
ism330bx_filt_settling_mask_set(const stmdev_ctx_t * ctx,ism330bx_filt_settling_mask_t val)1777 int32_t ism330bx_filt_settling_mask_set(const stmdev_ctx_t *ctx,
1778 ism330bx_filt_settling_mask_t val)
1779 {
1780 ism330bx_emb_func_cfg_t emb_func_cfg;
1781 ism330bx_tdm_cfg2_t tdm_cfg2;
1782 ism330bx_ctrl4_t ctrl4;
1783 int32_t ret;
1784
1785 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
1786
1787 if (ret == 0)
1788 {
1789 ctrl4.drdy_mask = val.drdy;
1790
1791 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
1792 }
1793
1794 if (ret == 0)
1795 {
1796 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1797 }
1798
1799 if (ret == 0)
1800 {
1801 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
1802 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
1803 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1804 }
1805
1806 if (ret == 0)
1807 {
1808 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1809 }
1810
1811 if (ret == 0)
1812 {
1813 tdm_cfg2.tdm_data_mask = val.tdm_excep_code;
1814 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1815 }
1816
1817 return ret;
1818 }
1819
1820 /**
1821 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
1822 *
1823 * @param ctx read / write interface definitions
1824 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1825 * @retval interface status (MANDATORY: return 0 -> no Error)
1826 *
1827 */
ism330bx_filt_settling_mask_get(const stmdev_ctx_t * ctx,ism330bx_filt_settling_mask_t * val)1828 int32_t ism330bx_filt_settling_mask_get(const stmdev_ctx_t *ctx,
1829 ism330bx_filt_settling_mask_t *val)
1830 {
1831 ism330bx_emb_func_cfg_t emb_func_cfg;
1832 ism330bx_tdm_cfg2_t tdm_cfg2;
1833 ism330bx_ctrl4_t ctrl4;
1834 int32_t ret;
1835
1836 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
1837 if (ret == 0)
1838 {
1839 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1840 }
1841 if (ret == 0)
1842 {
1843 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1844 }
1845
1846 val->drdy = ctrl4.drdy_mask;
1847 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
1848 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
1849 val->tdm_excep_code = tdm_cfg2.tdm_data_mask;
1850
1851 return ret;
1852 }
1853
1854 /**
1855 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
1856 *
1857 * @param ctx read / write interface definitions
1858 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1859 * @retval interface status (MANDATORY: return 0 -> no Error)
1860 *
1861 */
ism330bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,ism330bx_filt_gy_lp1_bandwidth_t val)1862 int32_t ism330bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
1863 ism330bx_filt_gy_lp1_bandwidth_t val)
1864 {
1865 ism330bx_ctrl6_t ctrl6;
1866 int32_t ret;
1867
1868 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
1869 if (ret == 0)
1870 {
1871 ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U;
1872 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
1873 }
1874
1875 return ret;
1876 }
1877
1878 /**
1879 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
1880 *
1881 * @param ctx read / write interface definitions
1882 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1883 * @retval interface status (MANDATORY: return 0 -> no Error)
1884 *
1885 */
ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,ism330bx_filt_gy_lp1_bandwidth_t * val)1886 int32_t ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
1887 ism330bx_filt_gy_lp1_bandwidth_t *val)
1888 {
1889 ism330bx_ctrl6_t ctrl6;
1890 int32_t ret;
1891
1892 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1);
1893
1894 switch (ctrl6.lpf1_g_bw)
1895 {
1896 case ISM330BX_GY_ULTRA_LIGHT:
1897 *val = ISM330BX_GY_ULTRA_LIGHT;
1898 break;
1899
1900 case ISM330BX_GY_VERY_LIGHT:
1901 *val = ISM330BX_GY_VERY_LIGHT;
1902 break;
1903
1904 case ISM330BX_GY_LIGHT:
1905 *val = ISM330BX_GY_LIGHT;
1906 break;
1907
1908 case ISM330BX_GY_MEDIUM:
1909 *val = ISM330BX_GY_MEDIUM;
1910 break;
1911
1912 case ISM330BX_GY_STRONG:
1913 *val = ISM330BX_GY_STRONG;
1914 break;
1915
1916 case ISM330BX_GY_VERY_STRONG:
1917 *val = ISM330BX_GY_VERY_STRONG;
1918 break;
1919
1920 case ISM330BX_GY_AGGRESSIVE:
1921 *val = ISM330BX_GY_AGGRESSIVE;
1922 break;
1923
1924 case ISM330BX_GY_XTREME:
1925 *val = ISM330BX_GY_XTREME;
1926 break;
1927
1928 default:
1929 *val = ISM330BX_GY_ULTRA_LIGHT;
1930 break;
1931 }
1932 return ret;
1933 }
1934
1935 /**
1936 * @brief It enables gyroscope digital LPF1 filter.[set]
1937 *
1938 * @param ctx read / write interface definitions
1939 * @param val It enables gyroscope digital LPF1 filter.
1940 * @retval interface status (MANDATORY: return 0 -> no Error)
1941 *
1942 */
ism330bx_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)1943 int32_t ism330bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
1944 {
1945 ism330bx_ctrl7_t ctrl7;
1946 int32_t ret;
1947
1948 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
1949
1950 if (ret == 0)
1951 {
1952 ctrl7.lpf1_g_en = val;
1953 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
1954 }
1955
1956 return ret;
1957 }
1958
1959 /**
1960 * @brief It enables gyroscope digital LPF1 filter.[get]
1961 *
1962 * @param ctx read / write interface definitions
1963 * @param val It enables gyroscope digital LPF1 filter.
1964 * @retval interface status (MANDATORY: return 0 -> no Error)
1965 *
1966 */
ism330bx_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)1967 int32_t ism330bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1968 {
1969 ism330bx_ctrl7_t ctrl7;
1970 int32_t ret;
1971
1972 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
1973 *val = ctrl7.lpf1_g_en;
1974
1975 return ret;
1976 }
1977
1978 /**
1979 * @brief Qvar filter configuration.[set]
1980 *
1981 * @param ctx read / write interface definitions
1982 * @param val Qvar filter configuration.
1983 * @retval interface status (MANDATORY: return 0 -> no Error)
1984 *
1985 */
ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t * ctx,ism330bx_filt_ah_qvar_conf_t val)1986 int32_t ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx,
1987 ism330bx_filt_ah_qvar_conf_t val)
1988 {
1989 ism330bx_ctrl9_t ctrl9;
1990 ism330bx_ctrl8_t ctrl8;
1991 int32_t ret;
1992
1993 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
1994 if (ret == 0)
1995 {
1996 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
1997 }
1998
1999 ctrl8.ah_qvar_hpf = val.hpf;
2000 ctrl9.ah_qvar_lpf = val.lpf;
2001
2002 if (ret == 0)
2003 {
2004 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
2005 }
2006 if (ret == 0)
2007 {
2008 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2009 }
2010
2011 return ret;
2012 }
2013
2014 /**
2015 * @brief Qvar filter configuration.[get]
2016 *
2017 * @param ctx read / write interface definitions
2018 * @param val Qvar filter configuration.
2019 * @retval interface status (MANDATORY: return 0 -> no Error)
2020 *
2021 */
ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t * ctx,ism330bx_filt_ah_qvar_conf_t * val)2022 int32_t ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx,
2023 ism330bx_filt_ah_qvar_conf_t *val)
2024 {
2025 ism330bx_ctrl8_t ctrl8;
2026 ism330bx_ctrl9_t ctrl9;
2027 int32_t ret;
2028
2029 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
2030 if (ret == 0)
2031 {
2032 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2033 }
2034
2035 val->lpf = ctrl9.ah_qvar_lpf;
2036 val->hpf = ctrl8.ah_qvar_hpf;
2037
2038 return ret;
2039 }
2040
2041 /**
2042 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
2043 *
2044 * @param ctx read / write interface definitions
2045 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2046 * @retval interface status (MANDATORY: return 0 -> no Error)
2047 *
2048 */
ism330bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,ism330bx_filt_xl_lp2_bandwidth_t val)2049 int32_t ism330bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
2050 ism330bx_filt_xl_lp2_bandwidth_t val)
2051 {
2052 ism330bx_ctrl8_t ctrl8;
2053 int32_t ret;
2054
2055 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
2056 if (ret == 0)
2057 {
2058 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U;
2059 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
2067 *
2068 * @param ctx read / write interface definitions
2069 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2070 * @retval interface status (MANDATORY: return 0 -> no Error)
2071 *
2072 */
ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,ism330bx_filt_xl_lp2_bandwidth_t * val)2073 int32_t ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
2074 ism330bx_filt_xl_lp2_bandwidth_t *val)
2075 {
2076 ism330bx_ctrl8_t ctrl8;
2077 int32_t ret;
2078
2079 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1);
2080 switch (ctrl8.hp_lpf2_xl_bw)
2081 {
2082 case ISM330BX_XL_ULTRA_LIGHT:
2083 *val = ISM330BX_XL_ULTRA_LIGHT;
2084 break;
2085
2086 case ISM330BX_XL_VERY_LIGHT:
2087 *val = ISM330BX_XL_VERY_LIGHT;
2088 break;
2089
2090 case ISM330BX_XL_LIGHT:
2091 *val = ISM330BX_XL_LIGHT;
2092 break;
2093
2094 case ISM330BX_XL_MEDIUM:
2095 *val = ISM330BX_XL_MEDIUM;
2096 break;
2097
2098 case ISM330BX_XL_STRONG:
2099 *val = ISM330BX_XL_STRONG;
2100 break;
2101
2102 case ISM330BX_XL_VERY_STRONG:
2103 *val = ISM330BX_XL_VERY_STRONG;
2104 break;
2105
2106 case ISM330BX_XL_AGGRESSIVE:
2107 *val = ISM330BX_XL_AGGRESSIVE;
2108 break;
2109
2110 case ISM330BX_XL_XTREME:
2111 *val = ISM330BX_XL_XTREME;
2112 break;
2113
2114 default:
2115 *val = ISM330BX_XL_ULTRA_LIGHT;
2116 break;
2117 }
2118 return ret;
2119 }
2120
2121 /**
2122 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
2123 *
2124 * @param ctx read / write interface definitions
2125 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2126 * @retval interface status (MANDATORY: return 0 -> no Error)
2127 *
2128 */
ism330bx_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2129 int32_t ism330bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2130 {
2131 ism330bx_ctrl9_t ctrl9;
2132 int32_t ret;
2133
2134 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2135 if (ret == 0)
2136 {
2137 ctrl9.lpf2_xl_en = val;
2138 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2139 }
2140
2141 return ret;
2142 }
2143
2144 /**
2145 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
2146 *
2147 * @param ctx read / write interface definitions
2148 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2149 * @retval interface status (MANDATORY: return 0 -> no Error)
2150 *
2151 */
ism330bx_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2152 int32_t ism330bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2153 {
2154 ism330bx_ctrl9_t ctrl9;
2155 int32_t ret;
2156
2157 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2158 *val = ctrl9.lpf2_xl_en;
2159
2160 return ret;
2161 }
2162
2163 /**
2164 * @brief Accelerometer slope filter / high-pass filter selection.[set]
2165 *
2166 * @param ctx read / write interface definitions
2167 * @param val Accelerometer slope filter / high-pass filter selection.
2168 * @retval interface status (MANDATORY: return 0 -> no Error)
2169 *
2170 */
ism330bx_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)2171 int32_t ism330bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
2172 {
2173 ism330bx_ctrl9_t ctrl9;
2174 int32_t ret;
2175
2176 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2177 if (ret == 0)
2178 {
2179 ctrl9.hp_slope_xl_en = val;
2180 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2181 }
2182
2183 return ret;
2184 }
2185
2186 /**
2187 * @brief Accelerometer slope filter / high-pass filter selection.[get]
2188 *
2189 * @param ctx read / write interface definitions
2190 * @param val Accelerometer slope filter / high-pass filter selection.
2191 * @retval interface status (MANDATORY: return 0 -> no Error)
2192 *
2193 */
ism330bx_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)2194 int32_t ism330bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
2195 {
2196 ism330bx_ctrl9_t ctrl9;
2197 int32_t ret;
2198
2199 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2200 *val = ctrl9.hp_slope_xl_en;
2201
2202 return ret;
2203 }
2204
2205 /**
2206 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
2207 *
2208 * @param ctx read / write interface definitions
2209 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2210 * @retval interface status (MANDATORY: return 0 -> no Error)
2211 *
2212 */
ism330bx_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2213 int32_t ism330bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2214 {
2215 ism330bx_ctrl9_t ctrl9;
2216 int32_t ret;
2217
2218 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2219 if (ret == 0)
2220 {
2221 ctrl9.xl_fastsettl_mode = val;
2222 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2223 }
2224
2225 return ret;
2226 }
2227
2228 /**
2229 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
2230 *
2231 * @param ctx read / write interface definitions
2232 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2233 * @retval interface status (MANDATORY: return 0 -> no Error)
2234 *
2235 */
ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2236 int32_t ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2237 {
2238 ism330bx_ctrl9_t ctrl9;
2239 int32_t ret;
2240
2241 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2242 *val = ctrl9.xl_fastsettl_mode;
2243
2244 return ret;
2245 }
2246
2247 /**
2248 * @brief Accelerometer high-pass filter mode.[set]
2249 *
2250 * @param ctx read / write interface definitions
2251 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2252 * @retval interface status (MANDATORY: return 0 -> no Error)
2253 *
2254 */
ism330bx_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,ism330bx_filt_xl_hp_mode_t val)2255 int32_t ism330bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
2256 ism330bx_filt_xl_hp_mode_t val)
2257 {
2258 ism330bx_ctrl9_t ctrl9;
2259 int32_t ret;
2260
2261 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2262 if (ret == 0)
2263 {
2264 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
2265 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2266 }
2267
2268 return ret;
2269 }
2270
2271 /**
2272 * @brief Accelerometer high-pass filter mode.[get]
2273 *
2274 * @param ctx read / write interface definitions
2275 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2276 * @retval interface status (MANDATORY: return 0 -> no Error)
2277 *
2278 */
ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,ism330bx_filt_xl_hp_mode_t * val)2279 int32_t ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
2280 ism330bx_filt_xl_hp_mode_t *val)
2281 {
2282 ism330bx_ctrl9_t ctrl9;
2283 int32_t ret;
2284
2285 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
2286 switch (ctrl9.hp_ref_mode_xl)
2287 {
2288 case ISM330BX_HP_MD_NORMAL:
2289 *val = ISM330BX_HP_MD_NORMAL;
2290 break;
2291
2292 case ISM330BX_HP_MD_REFERENCE:
2293 *val = ISM330BX_HP_MD_REFERENCE;
2294 break;
2295
2296 default:
2297 *val = ISM330BX_HP_MD_NORMAL;
2298 break;
2299 }
2300 return ret;
2301 }
2302
2303 /**
2304 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
2305 *
2306 * @param ctx read / write interface definitions
2307 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2308 * @retval interface status (MANDATORY: return 0 -> no Error)
2309 *
2310 */
ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,ism330bx_filt_wkup_act_feed_t val)2311 int32_t ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
2312 ism330bx_filt_wkup_act_feed_t val)
2313 {
2314 ism330bx_wake_up_ths_t wake_up_ths;
2315 ism330bx_tap_cfg0_t tap_cfg0;
2316 int32_t ret;
2317
2318 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2319 if (ret == 0)
2320 {
2321 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2322 }
2323
2324 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
2325 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
2326
2327 if (ret == 0)
2328 {
2329
2330 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2331 }
2332 if (ret == 0)
2333 {
2334
2335 ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2336 }
2337
2338 return ret;
2339 }
2340
2341 /**
2342 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
2343 *
2344 * @param ctx read / write interface definitions
2345 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2346 * @retval interface status (MANDATORY: return 0 -> no Error)
2347 *
2348 */
ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,ism330bx_filt_wkup_act_feed_t * val)2349 int32_t ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
2350 ism330bx_filt_wkup_act_feed_t *val)
2351 {
2352 ism330bx_wake_up_ths_t wake_up_ths;
2353 ism330bx_tap_cfg0_t tap_cfg0;
2354 int32_t ret;
2355
2356 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2357 if (ret == 0)
2358 {
2359 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2360 }
2361
2362 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
2363 {
2364 case ISM330BX_WK_FEED_SLOPE:
2365 *val = ISM330BX_WK_FEED_SLOPE;
2366 break;
2367
2368 case ISM330BX_WK_FEED_HIGH_PASS:
2369 *val = ISM330BX_WK_FEED_HIGH_PASS;
2370 break;
2371
2372 case ISM330BX_WK_FEED_LP_WITH_OFFSET:
2373 *val = ISM330BX_WK_FEED_LP_WITH_OFFSET;
2374 break;
2375
2376 default:
2377 *val = ISM330BX_WK_FEED_SLOPE;
2378 break;
2379 }
2380 return ret;
2381 }
2382
2383 /**
2384 * @brief Mask hw function triggers when xl is settling.[set]
2385 *
2386 * @param ctx read / write interface definitions
2387 * @param val 0 or 1,
2388 * @retval interface status (MANDATORY: return 0 -> no Error)
2389 *
2390 */
ism330bx_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)2391 int32_t ism330bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
2392 {
2393 ism330bx_tap_cfg0_t tap_cfg0;
2394 int32_t ret;
2395
2396 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2397
2398 if (ret == 0)
2399 {
2400 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
2401 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2402 }
2403
2404 return ret;
2405 }
2406
2407 /**
2408 * @brief Mask hw function triggers when xl is settling.[get]
2409 *
2410 * @param ctx read / write interface definitions
2411 * @param val 0 or 1,
2412 * @retval interface status (MANDATORY: return 0 -> no Error)
2413 *
2414 */
ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)2415 int32_t ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
2416 {
2417 ism330bx_tap_cfg0_t tap_cfg0;
2418 int32_t ret;
2419
2420 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2421 *val = tap_cfg0.hw_func_mask_xl_settl;
2422
2423 return ret;
2424 }
2425
2426
2427 /**
2428 * @brief LPF2 filter on 6D (sixd) function selection.[set]
2429 *
2430 * @param ctx read / write interface definitions
2431 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2432 * @retval interface status (MANDATORY: return 0 -> no Error)
2433 *
2434 */
ism330bx_filt_sixd_feed_set(const stmdev_ctx_t * ctx,ism330bx_filt_sixd_feed_t val)2435 int32_t ism330bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
2436 ism330bx_filt_sixd_feed_t val)
2437 {
2438 ism330bx_tap_cfg0_t tap_cfg0;
2439 int32_t ret;
2440
2441 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2442 if (ret == 0)
2443 {
2444 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
2445 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2446 }
2447
2448 return ret;
2449 }
2450
2451 /**
2452 * @brief LPF2 filter on 6D (sixd) function selection.[get]
2453 *
2454 * @param ctx read / write interface definitions
2455 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2456 * @retval interface status (MANDATORY: return 0 -> no Error)
2457 *
2458 */
ism330bx_filt_sixd_feed_get(const stmdev_ctx_t * ctx,ism330bx_filt_sixd_feed_t * val)2459 int32_t ism330bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
2460 ism330bx_filt_sixd_feed_t *val)
2461 {
2462 ism330bx_tap_cfg0_t tap_cfg0;
2463 int32_t ret;
2464
2465 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2466 switch (tap_cfg0.low_pass_on_6d)
2467 {
2468 case ISM330BX_SIXD_FEED_ODR_DIV_2:
2469 *val = ISM330BX_SIXD_FEED_ODR_DIV_2;
2470 break;
2471
2472 case ISM330BX_SIXD_FEED_LOW_PASS:
2473 *val = ISM330BX_SIXD_FEED_LOW_PASS;
2474 break;
2475
2476 default:
2477 *val = ISM330BX_SIXD_FEED_ODR_DIV_2;
2478 break;
2479 }
2480 return ret;
2481 }
2482
2483 /**
2484 * @}
2485 *
2486 */
2487
2488 /**
2489 * @defgroup Serial interfaces
2490 * @brief This section groups all the functions concerning
2491 * serial interfaces management (not auxiliary)
2492 * @{
2493 *
2494 */
2495
2496 /**
2497 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
2498 *
2499 * @param ctx read / write interface definitions
2500 * @param val Enables pull-up on SDO pin of UI (User Interface).
2501 * @retval interface status (MANDATORY: return 0 -> no Error)
2502 *
2503 */
ism330bx_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2504 int32_t ism330bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2505 {
2506 ism330bx_pin_ctrl_t pin_ctrl;
2507 int32_t ret;
2508
2509 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2510 if (ret == 0)
2511 {
2512 pin_ctrl.sdo_pu_en = val;
2513 ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2514 }
2515
2516 return ret;
2517 }
2518
2519 /**
2520 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
2521 *
2522 * @param ctx read / write interface definitions
2523 * @param val Enables pull-up on SDO pin of UI (User Interface).
2524 * @retval interface status (MANDATORY: return 0 -> no Error)
2525 *
2526 */
ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2527 int32_t ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2528 {
2529 ism330bx_pin_ctrl_t pin_ctrl;
2530 int32_t ret;
2531
2532 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2533 *val = pin_ctrl.sdo_pu_en;
2534
2535 return ret;
2536 }
2537
2538 /**
2539 * @brief Disables I2C and I3C on UI (User Interface).[set]
2540 *
2541 * @param ctx read / write interface definitions
2542 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2543 * @retval interface status (MANDATORY: return 0 -> no Error)
2544 *
2545 */
ism330bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,ism330bx_ui_i2c_i3c_mode_t val)2546 int32_t ism330bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
2547 ism330bx_ui_i2c_i3c_mode_t val)
2548 {
2549 ism330bx_if_cfg_t if_cfg;
2550 int32_t ret;
2551
2552 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2553 if (ret == 0)
2554 {
2555 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U;
2556 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2557 }
2558
2559 return ret;
2560 }
2561
2562 /**
2563 * @brief Disables I2C and I3C on UI (User Interface).[get]
2564 *
2565 * @param ctx read / write interface definitions
2566 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2567 * @retval interface status (MANDATORY: return 0 -> no Error)
2568 *
2569 */
ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,ism330bx_ui_i2c_i3c_mode_t * val)2570 int32_t ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
2571 ism330bx_ui_i2c_i3c_mode_t *val)
2572 {
2573 ism330bx_if_cfg_t if_cfg;
2574 int32_t ret;
2575
2576 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2577 switch (if_cfg.i2c_i3c_disable)
2578 {
2579 case ISM330BX_I2C_I3C_ENABLE:
2580 *val = ISM330BX_I2C_I3C_ENABLE;
2581 break;
2582
2583 case ISM330BX_I2C_I3C_DISABLE:
2584 *val = ISM330BX_I2C_I3C_DISABLE;
2585 break;
2586
2587 default:
2588 *val = ISM330BX_I2C_I3C_ENABLE;
2589 break;
2590 }
2591 return ret;
2592 }
2593
2594 /**
2595 * @brief SPI Serial Interface Mode selection.[set]
2596 *
2597 * @param ctx read / write interface definitions
2598 * @param val SPI_4_WIRE, SPI_3_WIRE,
2599 * @retval interface status (MANDATORY: return 0 -> no Error)
2600 *
2601 */
ism330bx_spi_mode_set(const stmdev_ctx_t * ctx,ism330bx_spi_mode_t val)2602 int32_t ism330bx_spi_mode_set(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t val)
2603 {
2604 ism330bx_if_cfg_t if_cfg;
2605 int32_t ret;
2606
2607 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2608 if (ret == 0)
2609 {
2610 if_cfg.sim = (uint8_t)val & 0x01U;
2611 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2612 }
2613
2614 return ret;
2615 }
2616
2617 /**
2618 * @brief SPI Serial Interface Mode selection.[get]
2619 *
2620 * @param ctx read / write interface definitions
2621 * @param val SPI_4_WIRE, SPI_3_WIRE,
2622 * @retval interface status (MANDATORY: return 0 -> no Error)
2623 *
2624 */
ism330bx_spi_mode_get(const stmdev_ctx_t * ctx,ism330bx_spi_mode_t * val)2625 int32_t ism330bx_spi_mode_get(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t *val)
2626 {
2627 ism330bx_if_cfg_t if_cfg;
2628 int32_t ret;
2629
2630 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2631 switch (if_cfg.sim)
2632 {
2633 case ISM330BX_SPI_4_WIRE:
2634 *val = ISM330BX_SPI_4_WIRE;
2635 break;
2636
2637 case ISM330BX_SPI_3_WIRE:
2638 *val = ISM330BX_SPI_3_WIRE;
2639 break;
2640
2641 default:
2642 *val = ISM330BX_SPI_4_WIRE;
2643 break;
2644 }
2645 return ret;
2646 }
2647
2648 /**
2649 * @brief Enables pull-up on SDA pin.[set]
2650 *
2651 * @param ctx read / write interface definitions
2652 * @param val Enables pull-up on SDA pin.
2653 * @retval interface status (MANDATORY: return 0 -> no Error)
2654 *
2655 */
ism330bx_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2656 int32_t ism330bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2657 {
2658 ism330bx_if_cfg_t if_cfg;
2659 int32_t ret;
2660
2661 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2662 if (ret == 0)
2663 {
2664 if_cfg.sda_pu_en = (uint8_t)val & 0x01U;
2665 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2666 }
2667
2668 return ret;
2669 }
2670
2671 /**
2672 * @brief Enables pull-up on SDA pin.[get]
2673 *
2674 * @param ctx read / write interface definitions
2675 * @param val Enables pull-up on SDA pin.
2676 * @retval interface status (MANDATORY: return 0 -> no Error)
2677 *
2678 */
ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2679 int32_t ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2680 {
2681 ism330bx_if_cfg_t if_cfg;
2682 int32_t ret;
2683
2684 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2685 *val = if_cfg.sda_pu_en;
2686
2687 return ret;
2688 }
2689
2690 /**
2691 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
2692 *
2693 * @param ctx read / write interface definitions
2694 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2695 * @retval interface status (MANDATORY: return 0 -> no Error)
2696 *
2697 */
ism330bx_i3c_ibi_time_set(const stmdev_ctx_t * ctx,ism330bx_i3c_ibi_time_t val)2698 int32_t ism330bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
2699 ism330bx_i3c_ibi_time_t val)
2700 {
2701 ism330bx_ctrl5_t ctrl5;
2702 int32_t ret;
2703
2704 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
2705 if (ret == 0)
2706 {
2707 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
2708 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
2709 }
2710
2711 return ret;
2712 }
2713
2714 /**
2715 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
2716 *
2717 * @param ctx read / write interface definitions
2718 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2719 * @retval interface status (MANDATORY: return 0 -> no Error)
2720 *
2721 */
ism330bx_i3c_ibi_time_get(const stmdev_ctx_t * ctx,ism330bx_i3c_ibi_time_t * val)2722 int32_t ism330bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
2723 ism330bx_i3c_ibi_time_t *val)
2724 {
2725 ism330bx_ctrl5_t ctrl5;
2726 int32_t ret;
2727
2728 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
2729 switch (ctrl5.bus_act_sel)
2730 {
2731 case ISM330BX_IBI_2us:
2732 *val = ISM330BX_IBI_2us;
2733 break;
2734
2735 case ISM330BX_IBI_50us:
2736 *val = ISM330BX_IBI_50us;
2737 break;
2738
2739 case ISM330BX_IBI_1ms:
2740 *val = ISM330BX_IBI_1ms;
2741 break;
2742
2743 case ISM330BX_IBI_25ms:
2744 *val = ISM330BX_IBI_25ms;
2745 break;
2746
2747 default:
2748 *val = ISM330BX_IBI_2us;
2749 break;
2750 }
2751 return ret;
2752 }
2753
2754 /**
2755 * @}
2756 *
2757 */
2758
2759 /**
2760 * @defgroup Interrupt pins
2761 * @brief This section groups all the functions that manage interrupt pins
2762 * @{
2763 *
2764 */
2765
2766 /**
2767 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
2768 *
2769 * @param ctx read / write interface definitions
2770 * @param val PUSH_PULL, OPEN_DRAIN,
2771 * @retval interface status (MANDATORY: return 0 -> no Error)
2772 *
2773 */
ism330bx_int_pin_mode_set(const stmdev_ctx_t * ctx,ism330bx_int_pin_mode_t val)2774 int32_t ism330bx_int_pin_mode_set(const stmdev_ctx_t *ctx,
2775 ism330bx_int_pin_mode_t val)
2776 {
2777 ism330bx_if_cfg_t if_cfg;
2778 int32_t ret;
2779
2780 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2781 if (ret == 0)
2782 {
2783 if_cfg.pp_od = (uint8_t)val & 0x01U;
2784 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2785 }
2786
2787 return ret;
2788 }
2789
2790 /**
2791 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
2792 *
2793 * @param ctx read / write interface definitions
2794 * @param val PUSH_PULL, OPEN_DRAIN,
2795 * @retval interface status (MANDATORY: return 0 -> no Error)
2796 *
2797 */
ism330bx_int_pin_mode_get(const stmdev_ctx_t * ctx,ism330bx_int_pin_mode_t * val)2798 int32_t ism330bx_int_pin_mode_get(const stmdev_ctx_t *ctx,
2799 ism330bx_int_pin_mode_t *val)
2800 {
2801 ism330bx_if_cfg_t if_cfg;
2802 int32_t ret;
2803
2804 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2805 switch (if_cfg.pp_od)
2806 {
2807 case ISM330BX_PUSH_PULL:
2808 *val = ISM330BX_PUSH_PULL;
2809 break;
2810
2811 case ISM330BX_OPEN_DRAIN:
2812 *val = ISM330BX_OPEN_DRAIN;
2813 break;
2814
2815 default:
2816 *val = ISM330BX_PUSH_PULL;
2817 break;
2818 }
2819 return ret;
2820 }
2821
2822 /**
2823 * @brief Interrupt activation level.[set]
2824 *
2825 * @param ctx read / write interface definitions
2826 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2827 * @retval interface status (MANDATORY: return 0 -> no Error)
2828 *
2829 */
ism330bx_pin_polarity_set(const stmdev_ctx_t * ctx,ism330bx_pin_polarity_t val)2830 int32_t ism330bx_pin_polarity_set(const stmdev_ctx_t *ctx,
2831 ism330bx_pin_polarity_t val)
2832 {
2833 ism330bx_if_cfg_t if_cfg;
2834 int32_t ret;
2835
2836 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2837 if (ret == 0)
2838 {
2839 if_cfg.h_lactive = (uint8_t)val & 0x01U;
2840 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2841 }
2842
2843 return ret;
2844 }
2845
2846 /**
2847 * @brief Interrupt activation level.[get]
2848 *
2849 * @param ctx read / write interface definitions
2850 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2851 * @retval interface status (MANDATORY: return 0 -> no Error)
2852 *
2853 */
ism330bx_pin_polarity_get(const stmdev_ctx_t * ctx,ism330bx_pin_polarity_t * val)2854 int32_t ism330bx_pin_polarity_get(const stmdev_ctx_t *ctx,
2855 ism330bx_pin_polarity_t *val)
2856 {
2857 ism330bx_if_cfg_t if_cfg;
2858 int32_t ret;
2859
2860 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2861 switch (if_cfg.h_lactive)
2862 {
2863 case ISM330BX_ACTIVE_HIGH:
2864 *val = ISM330BX_ACTIVE_HIGH;
2865 break;
2866
2867 case ISM330BX_ACTIVE_LOW:
2868 *val = ISM330BX_ACTIVE_LOW;
2869 break;
2870
2871 default:
2872 *val = ISM330BX_ACTIVE_HIGH;
2873 break;
2874 }
2875 return ret;
2876 }
2877
2878 /**
2879 * @brief It routes interrupt signals on INT 1 pin.[set]
2880 *
2881 * @param ctx read / write interface definitions
2882 * @param val It routes interrupt signals on INT 1 pin.
2883 * @retval interface status (MANDATORY: return 0 -> no Error)
2884 *
2885 */
ism330bx_pin_int1_route_set(const stmdev_ctx_t * ctx,ism330bx_pin_int_route_t val)2886 int32_t ism330bx_pin_int1_route_set(const stmdev_ctx_t *ctx,
2887 ism330bx_pin_int_route_t val)
2888 {
2889 ism330bx_functions_enable_t functions_enable;
2890 ism330bx_pin_int_route_t pin_int2_route;
2891 ism330bx_inactivity_dur_t inactivity_dur;
2892 ism330bx_emb_func_int1_t emb_func_int1;
2893 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
2894 ism330bx_int2_ctrl_t int2_ctrl;
2895 ism330bx_int1_ctrl_t int1_ctrl;
2896 ism330bx_fsm_int1_t fsm_int1;
2897 ism330bx_mlc_int1_t mlc_int1;
2898 ism330bx_md1_cfg_t md1_cfg;
2899 ism330bx_md2_cfg_t md2_cfg;
2900 ism330bx_ctrl4_t ctrl4;
2901 int32_t ret;
2902
2903 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
2904 if (ret == 0)
2905 {
2906 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2907 }
2908 if (ret == 0)
2909 {
2910 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2911 }
2912 if (ret == 0)
2913 {
2914 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2915 }
2916
2917 if (ret == 0)
2918 {
2919 emb_func_int1.int1_step_detector = val.step_detector;
2920 emb_func_int1.int1_tilt = val.tilt;
2921 emb_func_int1.int1_sig_mot = val.sig_mot;
2922 emb_func_int1.int1_fsm_lc = val.fsm_lc;
2923 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2924 }
2925 if (ret == 0)
2926 {
2927 fsm_int1.int1_fsm1 = val.fsm1;
2928 fsm_int1.int1_fsm2 = val.fsm2;
2929 fsm_int1.int1_fsm3 = val.fsm3;
2930 fsm_int1.int1_fsm4 = val.fsm4;
2931 fsm_int1.int1_fsm5 = val.fsm5;
2932 fsm_int1.int1_fsm6 = val.fsm6;
2933 fsm_int1.int1_fsm7 = val.fsm7;
2934 fsm_int1.int1_fsm8 = val.fsm8;
2935 ret = ism330bx_write_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2936 }
2937 if (ret == 0)
2938 {
2939 mlc_int1.int1_mlc1 = val.mlc1;
2940 mlc_int1.int1_mlc2 = val.mlc2;
2941 mlc_int1.int1_mlc3 = val.mlc3;
2942 mlc_int1.int1_mlc4 = val.mlc4;
2943 ret = ism330bx_write_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2944 }
2945
2946 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
2947
2948 if (ret == 0)
2949 {
2950 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
2951 }
2952 if (ret == 0)
2953 {
2954 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
2955 {
2956 ctrl4.int2_on_int1 = PROPERTY_ENABLE;
2957 }
2958 else
2959 {
2960 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
2961 }
2962 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
2963 }
2964
2965 if (ret == 0)
2966 {
2967 ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2968 }
2969
2970 if (ret == 0)
2971 {
2972 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
2973 ret = ism330bx_write_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2974 }
2975
2976
2977 if (ret == 0)
2978 {
2979 ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2980 }
2981
2982 if (ret == 0)
2983 {
2984 md2_cfg.int2_timestamp = val.timestamp;
2985 ret = ism330bx_write_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2986 }
2987
2988 if (ret == 0)
2989 {
2990 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
2991 }
2992
2993 if (ret == 0)
2994 {
2995 inactivity_dur.sleep_status_on_int = val.sleep_status;
2996 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
2997 }
2998
2999
3000 if (ret == 0)
3001 {
3002 ret = ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3003 }
3004
3005 if (ret == 0)
3006 {
3007 int1_ctrl.int1_drdy_xl = val.drdy_xl;
3008 int1_ctrl.int1_drdy_g = val.drdy_gy;
3009 int1_ctrl.int1_fifo_th = val.fifo_th;
3010 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
3011 int1_ctrl.int1_fifo_full = val.fifo_full;
3012 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
3013 ret = ism330bx_write_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3014 }
3015
3016 if (ret == 0)
3017 {
3018 ret = ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3019 }
3020
3021 if (ret == 0)
3022 {
3023 if ((emb_func_int1.int1_fsm_lc
3024 | emb_func_int1.int1_sig_mot
3025 | emb_func_int1.int1_step_detector
3026 | emb_func_int1.int1_tilt
3027 | fsm_int1.int1_fsm1
3028 | fsm_int1.int1_fsm2
3029 | fsm_int1.int1_fsm3
3030 | fsm_int1.int1_fsm4
3031 | fsm_int1.int1_fsm5
3032 | fsm_int1.int1_fsm6
3033 | fsm_int1.int1_fsm7
3034 | fsm_int1.int1_fsm8
3035 | mlc_int1.int1_mlc1
3036 | mlc_int1.int1_mlc2
3037 | mlc_int1.int1_mlc3
3038 | mlc_int1.int1_mlc4) != PROPERTY_DISABLE)
3039 {
3040 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3041 }
3042 else
3043 {
3044 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3045 }
3046 md1_cfg.int1_6d = val.six_d;
3047 md1_cfg.int1_double_tap = val.double_tap;
3048 md1_cfg.int1_ff = val.free_fall;
3049 md1_cfg.int1_wu = val.wake_up;
3050 md1_cfg.int1_single_tap = val.single_tap;
3051 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3052 {
3053 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
3054 }
3055 else
3056 {
3057 md1_cfg.int1_sleep_change = PROPERTY_DISABLE;
3058 }
3059 ret = ism330bx_write_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3060 }
3061
3062 if (ret == 0)
3063 {
3064 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3065 }
3066
3067 if (ret == 0)
3068 {
3069 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3070 ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3071 }
3072
3073
3074 if (ret == 0)
3075 {
3076 ret = ism330bx_pin_int2_route_get(ctx, &pin_int2_route);
3077 }
3078
3079 if (ret == 0)
3080 {
3081 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3082 }
3083 if (ret == 0)
3084 {
3085 if ((pin_int2_route.six_d
3086 | pin_int2_route.double_tap
3087 | pin_int2_route.free_fall
3088 | pin_int2_route.wake_up
3089 | pin_int2_route.single_tap
3090 | pin_int2_route.sleep_status
3091 | pin_int2_route.sleep_change
3092 | val.six_d
3093 | val.double_tap
3094 | val.free_fall
3095 | val.wake_up
3096 | val.single_tap
3097 | val.sleep_status
3098 | val.sleep_change) != PROPERTY_DISABLE)
3099 {
3100 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3101 }
3102
3103 else
3104 {
3105 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3106 }
3107
3108 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3109 }
3110
3111 return ret;
3112 }
3113
3114 /**
3115 * @brief It routes interrupt signals on INT 1 pin.[get]
3116 *
3117 * @param ctx read / write interface definitions
3118 * @param val It routes interrupt signals on INT 1 pin.
3119 * @retval interface status (MANDATORY: return 0 -> no Error)
3120 *
3121 */
ism330bx_pin_int1_route_get(const stmdev_ctx_t * ctx,ism330bx_pin_int_route_t * val)3122 int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx,
3123 ism330bx_pin_int_route_t *val)
3124 {
3125 ism330bx_inactivity_dur_t inactivity_dur;
3126 ism330bx_emb_func_int1_t emb_func_int1;
3127 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
3128 ism330bx_int1_ctrl_t int1_ctrl;
3129 ism330bx_int2_ctrl_t int2_ctrl;
3130 ism330bx_fsm_int1_t fsm_int1;
3131 ism330bx_mlc_int1_t mlc_int1;
3132 ism330bx_md1_cfg_t md1_cfg;
3133 ism330bx_md2_cfg_t md2_cfg;
3134 ism330bx_ctrl4_t ctrl4;
3135 int32_t ret;
3136
3137
3138 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
3139 if (ctrl4.int2_on_int1 == PROPERTY_ENABLE)
3140 {
3141 if (ret == 0)
3142 {
3143 ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3144 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3145 }
3146 if (ret == 0)
3147 {
3148 ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3149 val->timestamp = md2_cfg.int2_timestamp;
3150 }
3151 }
3152
3153 if (ret == 0)
3154 {
3155 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3156 val->sleep_status = inactivity_dur.sleep_status_on_int;
3157 }
3158
3159
3160 if (ret == 0)
3161 {
3162 ret = ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3163 val->drdy_xl = int1_ctrl.int1_drdy_xl;
3164 val->drdy_gy = int1_ctrl.int1_drdy_g;
3165 val->fifo_th = int1_ctrl.int1_fifo_th;
3166 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
3167 val->fifo_full = int1_ctrl.int1_fifo_full;
3168 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
3169 }
3170
3171
3172 if (ret == 0)
3173 {
3174 ret = ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3175 val->six_d = md1_cfg.int1_6d;
3176 val->double_tap = md1_cfg.int1_double_tap;
3177 val->free_fall = md1_cfg.int1_ff;
3178 val->wake_up = md1_cfg.int1_wu;
3179 val->single_tap = md1_cfg.int1_single_tap;
3180 val->sleep_change = md1_cfg.int1_sleep_change;
3181 }
3182
3183 if (ret == 0)
3184 {
3185 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
3186 }
3187 if (ret == 0)
3188 {
3189 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
3190 val->step_detector = emb_func_int1.int1_step_detector;
3191 val->tilt = emb_func_int1.int1_tilt;
3192 val->sig_mot = emb_func_int1.int1_sig_mot;
3193 val->fsm_lc = emb_func_int1.int1_fsm_lc;
3194 }
3195 if (ret == 0)
3196 {
3197 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
3198 val->fsm1 = fsm_int1.int1_fsm1;
3199 val->fsm2 = fsm_int1.int1_fsm2;
3200 val->fsm3 = fsm_int1.int1_fsm3;
3201 val->fsm4 = fsm_int1.int1_fsm4;
3202 val->fsm5 = fsm_int1.int1_fsm5;
3203 val->fsm6 = fsm_int1.int1_fsm6;
3204 val->fsm7 = fsm_int1.int1_fsm7;
3205 val->fsm8 = fsm_int1.int1_fsm8;
3206 }
3207 if (ret == 0)
3208 {
3209 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
3210 val->mlc1 = mlc_int1.int1_mlc1;
3211 val->mlc2 = mlc_int1.int1_mlc2;
3212 val->mlc3 = mlc_int1.int1_mlc3;
3213 val->mlc4 = mlc_int1.int1_mlc4;
3214 }
3215
3216 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
3217
3218 if (ret == 0)
3219 {
3220 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3221 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3222 }
3223
3224 return ret;
3225 }
3226
3227
3228 /**
3229 * @brief It routes interrupt signals on INT 2 pin.[set]
3230 *
3231 * @param ctx read / write interface definitions
3232 * @param val It routes interrupt signals on INT 2 pin.
3233 * @retval interface status (MANDATORY: return 0 -> no Error)
3234 *
3235 */
ism330bx_pin_int2_route_set(const stmdev_ctx_t * ctx,ism330bx_pin_int_route_t val)3236 int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx,
3237 ism330bx_pin_int_route_t val)
3238 {
3239 ism330bx_functions_enable_t functions_enable;
3240 ism330bx_pin_int_route_t pin_int1_route;
3241 ism330bx_inactivity_dur_t inactivity_dur;
3242 ism330bx_emb_func_int2_t emb_func_int2;
3243 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
3244 ism330bx_int2_ctrl_t int2_ctrl;
3245 ism330bx_fsm_int2_t fsm_int2;
3246 ism330bx_mlc_int2_t mlc_int2;
3247 ism330bx_ctrl7_t ctrl7;
3248 ism330bx_md2_cfg_t md2_cfg;
3249 ism330bx_ctrl4_t ctrl4;
3250 int32_t ret;
3251
3252
3253 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
3254 if (ret == 0)
3255 {
3256 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3257 }
3258 if (ret == 0)
3259 {
3260 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3261 }
3262 if (ret == 0)
3263 {
3264 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3265 }
3266
3267 if (ret == 0)
3268 {
3269 emb_func_int2.int2_step_detector = val.step_detector;
3270 emb_func_int2.int2_tilt = val.tilt;
3271 emb_func_int2.int2_sig_mot = val.sig_mot;
3272 emb_func_int2.int2_fsm_lc = val.fsm_lc;
3273 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3274 }
3275 if (ret == 0)
3276 {
3277 fsm_int2.int2_fsm1 = val.fsm1;
3278 fsm_int2.int2_fsm2 = val.fsm2;
3279 fsm_int2.int2_fsm3 = val.fsm3;
3280 fsm_int2.int2_fsm4 = val.fsm4;
3281 fsm_int2.int2_fsm5 = val.fsm5;
3282 fsm_int2.int2_fsm6 = val.fsm6;
3283 fsm_int2.int2_fsm7 = val.fsm7;
3284 fsm_int2.int2_fsm8 = val.fsm8;
3285 ret = ism330bx_write_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3286 }
3287 if (ret == 0)
3288 {
3289 mlc_int2.int2_mlc1 = val.mlc1;
3290 mlc_int2.int2_mlc2 = val.mlc2;
3291 mlc_int2.int2_mlc3 = val.mlc3;
3292 mlc_int2.int2_mlc4 = val.mlc4;
3293 ret = ism330bx_write_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3294 }
3295
3296 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
3297
3298 if (ret == 0)
3299 {
3300 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
3301 }
3302 if (ret == 0)
3303 {
3304 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
3305 {
3306 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
3307 }
3308 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
3309 }
3310
3311 if (ret == 0)
3312 {
3313 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3314 }
3315
3316 if (ret == 0)
3317 {
3318 inactivity_dur.sleep_status_on_int = val.sleep_status;
3319 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3320 }
3321
3322 if (ret == 0)
3323 {
3324 ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3325 }
3326
3327 if (ret == 0)
3328 {
3329 int2_ctrl.int2_drdy_xl = val.drdy_xl;
3330 int2_ctrl.int2_drdy_g = val.drdy_gy;
3331 int2_ctrl.int2_fifo_th = val.fifo_th;
3332 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
3333 int2_ctrl.int2_fifo_full = val.fifo_full;
3334 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
3335 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
3336 ret = ism330bx_write_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3337 }
3338
3339 if (ret == 0)
3340 {
3341 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
3342 ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar;
3343 ret += ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
3344 }
3345
3346 if (ret == 0)
3347 {
3348 ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3349 }
3350
3351 if (ret == 0)
3352 {
3353 if ((emb_func_int2.int2_fsm_lc
3354 | emb_func_int2.int2_sig_mot
3355 | emb_func_int2.int2_step_detector
3356 | emb_func_int2.int2_tilt
3357 | fsm_int2.int2_fsm1
3358 | fsm_int2.int2_fsm2
3359 | fsm_int2.int2_fsm3
3360 | fsm_int2.int2_fsm4
3361 | fsm_int2.int2_fsm5
3362 | fsm_int2.int2_fsm6
3363 | fsm_int2.int2_fsm7
3364 | fsm_int2.int2_fsm8
3365 | mlc_int2.int2_mlc1
3366 | mlc_int2.int2_mlc2
3367 | mlc_int2.int2_mlc3
3368 | mlc_int2.int2_mlc4) != PROPERTY_DISABLE)
3369 {
3370 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3371 }
3372 else
3373 {
3374 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3375 }
3376 md2_cfg.int2_6d = val.six_d;
3377 md2_cfg.int2_double_tap = val.double_tap;
3378 md2_cfg.int2_ff = val.free_fall;
3379 md2_cfg.int2_wu = val.wake_up;
3380 md2_cfg.int2_single_tap = val.single_tap;
3381 md2_cfg.int2_timestamp = val.timestamp;
3382 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3383 {
3384 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
3385 }
3386 else
3387 {
3388 md2_cfg.int2_sleep_change = PROPERTY_DISABLE;
3389 }
3390 ret = ism330bx_write_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3391 }
3392
3393 if (ret == 0)
3394 {
3395 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3396 }
3397
3398 if (ret == 0)
3399 {
3400 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3401 ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3402 }
3403
3404
3405 if (ret == 0)
3406 {
3407 ret = ism330bx_pin_int1_route_get(ctx, &pin_int1_route);
3408 }
3409
3410 if (ret == 0)
3411 {
3412 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3413 }
3414 if (ret == 0)
3415 {
3416 if ((pin_int1_route.six_d
3417 | pin_int1_route.double_tap
3418 | pin_int1_route.free_fall
3419 | pin_int1_route.wake_up
3420 | pin_int1_route.single_tap
3421 | pin_int1_route.sleep_status
3422 | pin_int1_route.sleep_change
3423 | val.six_d
3424 | val.double_tap
3425 | val.free_fall
3426 | val.wake_up
3427 | val.single_tap
3428 | val.sleep_status
3429 | val.sleep_change) != PROPERTY_DISABLE)
3430 {
3431 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3432 }
3433
3434 else
3435 {
3436 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3437 }
3438
3439 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3440 }
3441
3442 return ret;
3443 }
3444
3445 /**
3446 * @brief It routes interrupt signals on INT 2 pin.[get]
3447 *
3448 * @param ctx read / write interface definitions
3449 * @param val It routes interrupt signals on INT 2 pin.
3450 * @retval interface status (MANDATORY: return 0 -> no Error)
3451 *
3452 */
ism330bx_pin_int2_route_get(const stmdev_ctx_t * ctx,ism330bx_pin_int_route_t * val)3453 int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx,
3454 ism330bx_pin_int_route_t *val)
3455 {
3456 ism330bx_inactivity_dur_t inactivity_dur;
3457 ism330bx_emb_func_int2_t emb_func_int2;
3458 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
3459 ism330bx_int2_ctrl_t int2_ctrl;
3460 ism330bx_fsm_int2_t fsm_int2;
3461 ism330bx_mlc_int2_t mlc_int2;
3462 ism330bx_ctrl7_t ctrl7;
3463 ism330bx_md2_cfg_t md2_cfg;
3464 ism330bx_ctrl4_t ctrl4;
3465 int32_t ret;
3466
3467
3468 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1);
3469 if (ctrl4.int2_on_int1 == PROPERTY_DISABLE)
3470 {
3471 if (ret == 0)
3472 {
3473 ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3474 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3475 }
3476 if (ret == 0)
3477 {
3478 ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3479 val->timestamp = md2_cfg.int2_timestamp;
3480 }
3481 }
3482
3483 if (ret == 0)
3484 {
3485 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3486 val->sleep_status = inactivity_dur.sleep_status_on_int;
3487 }
3488
3489
3490 if (ret == 0)
3491 {
3492 ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3493 val->drdy_xl = int2_ctrl.int2_drdy_xl;
3494 val->drdy_gy = int2_ctrl.int2_drdy_g;
3495 val->fifo_th = int2_ctrl.int2_fifo_th;
3496 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
3497 val->fifo_full = int2_ctrl.int2_fifo_full;
3498 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
3499 }
3500
3501 if (ret == 0)
3502 {
3503 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
3504 val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar;
3505 }
3506
3507 if (ret == 0)
3508 {
3509 ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3510 val->six_d = md2_cfg.int2_6d;
3511 val->double_tap = md2_cfg.int2_double_tap;
3512 val->free_fall = md2_cfg.int2_ff;
3513 val->wake_up = md2_cfg.int2_wu;
3514 val->single_tap = md2_cfg.int2_single_tap;
3515 val->sleep_change = md2_cfg.int2_sleep_change;
3516 }
3517
3518 if (ret == 0)
3519 {
3520 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
3521 }
3522 if (ret == 0)
3523 {
3524 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3525 val->step_detector = emb_func_int2.int2_step_detector;
3526 val->tilt = emb_func_int2.int2_tilt;
3527 val->sig_mot = emb_func_int2.int2_sig_mot;
3528 val->fsm_lc = emb_func_int2.int2_fsm_lc;
3529 }
3530 if (ret == 0)
3531 {
3532 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3533 val->fsm1 = fsm_int2.int2_fsm1;
3534 val->fsm2 = fsm_int2.int2_fsm2;
3535 val->fsm3 = fsm_int2.int2_fsm3;
3536 val->fsm4 = fsm_int2.int2_fsm4;
3537 val->fsm5 = fsm_int2.int2_fsm5;
3538 val->fsm6 = fsm_int2.int2_fsm6;
3539 val->fsm7 = fsm_int2.int2_fsm7;
3540 val->fsm8 = fsm_int2.int2_fsm8;
3541 }
3542 if (ret == 0)
3543 {
3544 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3545 val->mlc1 = mlc_int2.int2_mlc1;
3546 val->mlc2 = mlc_int2.int2_mlc2;
3547 val->mlc3 = mlc_int2.int2_mlc3;
3548 val->mlc4 = mlc_int2.int2_mlc4;
3549 }
3550
3551 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
3552
3553 if (ret == 0)
3554 {
3555 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3556 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3557 }
3558
3559 return ret;
3560 }
3561
3562 /**
3563 * @brief Enables INT pin when I3C is enabled.[set]
3564 *
3565 * @param ctx read / write interface definitions
3566 * @param val Enables INT pin when I3C is enabled.
3567 * @retval interface status (MANDATORY: return 0 -> no Error)
3568 *
3569 */
ism330bx_pin_int_en_when_i2c_set(const stmdev_ctx_t * ctx,uint8_t val)3570 int32_t ism330bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val)
3571 {
3572 ism330bx_ctrl5_t ctrl5;
3573 int32_t ret;
3574
3575 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
3576 if (ret == 0)
3577 {
3578 ctrl5.int_en_i3c = val;
3579 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
3580 }
3581
3582 return ret;
3583 }
3584
3585 /**
3586 * @brief Enables INT pin when I3C is enabled.[get]
3587 *
3588 * @param ctx read / write interface definitions
3589 * @param val Enables INT pin when I3C is enabled.
3590 * @retval interface status (MANDATORY: return 0 -> no Error)
3591 *
3592 */
ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t * ctx,uint8_t * val)3593 int32_t ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val)
3594 {
3595 ism330bx_ctrl5_t ctrl5;
3596 int32_t ret;
3597
3598 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1);
3599 *val = ctrl5.int_en_i3c;
3600
3601 return ret;
3602 }
3603
3604 /**
3605 * @brief Interrupt notification mode.[set]
3606 *
3607 * @param ctx read / write interface definitions
3608 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3609 * @retval interface status (MANDATORY: return 0 -> no Error)
3610 *
3611 */
ism330bx_int_notification_set(const stmdev_ctx_t * ctx,ism330bx_int_notification_t val)3612 int32_t ism330bx_int_notification_set(const stmdev_ctx_t *ctx,
3613 ism330bx_int_notification_t val)
3614 {
3615 ism330bx_tap_cfg0_t tap_cfg0;
3616 ism330bx_page_rw_t page_rw;
3617 int32_t ret;
3618
3619 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3620 if (ret == 0)
3621 {
3622 tap_cfg0.lir = (uint8_t)val & 0x01U;
3623 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3624 }
3625
3626 if (ret == 0)
3627 {
3628 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
3629 }
3630 if (ret == 0)
3631 {
3632 ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3633 }
3634
3635 if (ret == 0)
3636 {
3637 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3638 ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3639 }
3640
3641 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
3642
3643 return ret;
3644 }
3645
3646 /**
3647 * @brief Interrupt notification mode.[get]
3648 *
3649 * @param ctx read / write interface definitions
3650 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3651 * @retval interface status (MANDATORY: return 0 -> no Error)
3652 *
3653 */
ism330bx_int_notification_get(const stmdev_ctx_t * ctx,ism330bx_int_notification_t * val)3654 int32_t ism330bx_int_notification_get(const stmdev_ctx_t *ctx,
3655 ism330bx_int_notification_t *val)
3656 {
3657 ism330bx_tap_cfg0_t tap_cfg0;
3658 ism330bx_page_rw_t page_rw;
3659 int32_t ret;
3660
3661 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3662 if (ret == 0)
3663 {
3664 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
3665 }
3666 if (ret == 0)
3667 {
3668 ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3669 }
3670
3671 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
3672
3673 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
3674 {
3675 case ISM330BX_ALL_INT_PULSED:
3676 *val = ISM330BX_ALL_INT_PULSED;
3677 break;
3678
3679 case ISM330BX_BASE_LATCHED_EMB_PULSED:
3680 *val = ISM330BX_BASE_LATCHED_EMB_PULSED;
3681 break;
3682
3683 case ISM330BX_BASE_PULSED_EMB_LATCHED:
3684 *val = ISM330BX_BASE_PULSED_EMB_LATCHED;
3685 break;
3686
3687 case ISM330BX_ALL_INT_LATCHED:
3688 *val = ISM330BX_ALL_INT_LATCHED;
3689 break;
3690
3691 default:
3692 *val = ISM330BX_ALL_INT_PULSED;
3693 break;
3694 }
3695 return ret;
3696 }
3697
3698 /**
3699 * @}
3700 *
3701 */
3702
3703 /**
3704 * @defgroup Wake Up event and Activity / Inactivity detection
3705 * @brief This section groups all the functions that manage the Wake Up
3706 * event generation.
3707 * @{
3708 *
3709 */
3710
3711 /**
3712 * @brief Enable activity/inactivity (sleep) function.[set]
3713 *
3714 * @param ctx read / write interface definitions
3715 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3716 * @retval interface status (MANDATORY: return 0 -> no Error)
3717 *
3718 */
ism330bx_act_mode_set(const stmdev_ctx_t * ctx,ism330bx_act_mode_t val)3719 int32_t ism330bx_act_mode_set(const stmdev_ctx_t *ctx, ism330bx_act_mode_t val)
3720 {
3721 ism330bx_functions_enable_t functions_enable;
3722 int32_t ret;
3723
3724 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3725 if (ret == 0)
3726 {
3727 functions_enable.inact_en = (uint8_t)val & 0x03U;
3728 ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3729 }
3730
3731 return ret;
3732 }
3733
3734 /**
3735 * @brief Enable activity/inactivity (sleep) function.[get]
3736 *
3737 * @param ctx read / write interface definitions
3738 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3739 * @retval interface status (MANDATORY: return 0 -> no Error)
3740 *
3741 */
ism330bx_act_mode_get(const stmdev_ctx_t * ctx,ism330bx_act_mode_t * val)3742 int32_t ism330bx_act_mode_get(const stmdev_ctx_t *ctx, ism330bx_act_mode_t *val)
3743 {
3744 ism330bx_functions_enable_t functions_enable;
3745 int32_t ret;
3746
3747 ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3748 switch (functions_enable.inact_en)
3749 {
3750 case ISM330BX_XL_AND_GY_NOT_AFFECTED:
3751 *val = ISM330BX_XL_AND_GY_NOT_AFFECTED;
3752 break;
3753
3754 case ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED:
3755 *val = ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED;
3756 break;
3757
3758 case ISM330BX_XL_LOW_POWER_GY_SLEEP:
3759 *val = ISM330BX_XL_LOW_POWER_GY_SLEEP;
3760 break;
3761
3762 case ISM330BX_XL_LOW_POWER_GY_POWER_DOWN:
3763 *val = ISM330BX_XL_LOW_POWER_GY_POWER_DOWN;
3764 break;
3765
3766 default:
3767 *val = ISM330BX_XL_AND_GY_NOT_AFFECTED;
3768 break;
3769 }
3770 return ret;
3771 }
3772
3773 /**
3774 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
3775 *
3776 * @param ctx read / write interface definitions
3777 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3778 * @retval interface status (MANDATORY: return 0 -> no Error)
3779 *
3780 */
ism330bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,ism330bx_act_from_sleep_to_act_dur_t val)3781 int32_t ism330bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
3782 ism330bx_act_from_sleep_to_act_dur_t val)
3783 {
3784 ism330bx_inactivity_dur_t inactivity_dur;
3785 int32_t ret;
3786
3787 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3788 if (ret == 0)
3789 {
3790 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
3791 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3792 }
3793
3794 return ret;
3795 }
3796
3797 /**
3798 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
3799 *
3800 * @param ctx read / write interface definitions
3801 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3802 * @retval interface status (MANDATORY: return 0 -> no Error)
3803 *
3804 */
ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,ism330bx_act_from_sleep_to_act_dur_t * val)3805 int32_t ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
3806 ism330bx_act_from_sleep_to_act_dur_t *val)
3807 {
3808 ism330bx_inactivity_dur_t inactivity_dur;
3809 int32_t ret;
3810
3811 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3812 switch (inactivity_dur.inact_dur)
3813 {
3814 case ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE:
3815 *val = ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3816 break;
3817
3818 case ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE:
3819 *val = ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE;
3820 break;
3821
3822 case ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE:
3823 *val = ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE;
3824 break;
3825
3826 case ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE:
3827 *val = ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE;
3828 break;
3829
3830 default:
3831 *val = ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3832 break;
3833 }
3834 return ret;
3835 }
3836
3837 /**
3838 * @brief Selects the accelerometer data rate during Inactivity.[set]
3839 *
3840 * @param ctx read / write interface definitions
3841 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3842 * @retval interface status (MANDATORY: return 0 -> no Error)
3843 *
3844 */
ism330bx_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,ism330bx_act_sleep_xl_odr_t val)3845 int32_t ism330bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
3846 ism330bx_act_sleep_xl_odr_t val)
3847 {
3848 ism330bx_inactivity_dur_t inactivity_dur;
3849 int32_t ret;
3850
3851 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3852 if (ret == 0)
3853 {
3854 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
3855 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3856 }
3857
3858 return ret;
3859 }
3860
3861 /**
3862 * @brief Selects the accelerometer data rate during Inactivity.[get]
3863 *
3864 * @param ctx read / write interface definitions
3865 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3866 * @retval interface status (MANDATORY: return 0 -> no Error)
3867 *
3868 */
ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,ism330bx_act_sleep_xl_odr_t * val)3869 int32_t ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
3870 ism330bx_act_sleep_xl_odr_t *val)
3871 {
3872 ism330bx_inactivity_dur_t inactivity_dur;
3873 int32_t ret;
3874
3875 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3876 switch (inactivity_dur.xl_inact_odr)
3877 {
3878 case ISM330BX_1Hz875:
3879 *val = ISM330BX_1Hz875;
3880 break;
3881
3882 case ISM330BX_15Hz:
3883 *val = ISM330BX_15Hz;
3884 break;
3885
3886 case ISM330BX_30Hz:
3887 *val = ISM330BX_30Hz;
3888 break;
3889
3890 case ISM330BX_60Hz:
3891 *val = ISM330BX_60Hz;
3892 break;
3893
3894 default:
3895 *val = ISM330BX_1Hz875;
3896 break;
3897 }
3898 return ret;
3899 }
3900
3901 /**
3902 * @brief Wakeup and activity/inactivity threshold.[set]
3903 *
3904 * @param ctx read / write interface definitions
3905 * @param val Wakeup and activity/inactivity threshold.
3906 * @retval interface status (MANDATORY: return 0 -> no Error)
3907 *
3908 */
ism330bx_act_thresholds_set(const stmdev_ctx_t * ctx,ism330bx_act_thresholds_t val)3909 int32_t ism330bx_act_thresholds_set(const stmdev_ctx_t *ctx,
3910 ism330bx_act_thresholds_t val)
3911 {
3912 ism330bx_inactivity_ths_t inactivity_ths;
3913 ism330bx_inactivity_dur_t inactivity_dur;
3914 ism330bx_wake_up_ths_t wake_up_ths;
3915 int32_t ret;
3916 float_t tmp;
3917
3918 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3919 if (ret == 0)
3920 {
3921 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3922 }
3923
3924 if (ret == 0)
3925 {
3926 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3927 }
3928
3929 if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f))
3930 && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f)))
3931 {
3932 inactivity_dur.wu_inact_ths_w = 0;
3933
3934 tmp = (float_t)val.inact_ths_mg / 7.8125f;
3935 inactivity_ths.inact_ths = (uint8_t)tmp;
3936
3937 tmp = (float_t)val.wk_ths_mg / 7.8125f;
3938 wake_up_ths.wk_ths = (uint8_t)tmp;
3939 }
3940 else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f))
3941 && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f)))
3942 {
3943 inactivity_dur.wu_inact_ths_w = 1;
3944
3945 tmp = (float_t)val.inact_ths_mg / 15.625f;
3946 inactivity_ths.inact_ths = (uint8_t)tmp;
3947
3948 tmp = (float_t)val.wk_ths_mg / 15.625f;
3949 wake_up_ths.wk_ths = (uint8_t)tmp;
3950 }
3951 else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f))
3952 && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f)))
3953 {
3954 inactivity_dur.wu_inact_ths_w = 2;
3955
3956 tmp = (float_t)val.inact_ths_mg / 31.25f;
3957 inactivity_ths.inact_ths = (uint8_t)tmp;
3958
3959 tmp = (float_t)val.wk_ths_mg / 31.25f;
3960 wake_up_ths.wk_ths = (uint8_t)tmp;
3961 }
3962 else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f))
3963 && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f)))
3964 {
3965 inactivity_dur.wu_inact_ths_w = 3;
3966
3967 tmp = (float_t)val.inact_ths_mg / 62.5f;
3968 inactivity_ths.inact_ths = (uint8_t)tmp;
3969
3970 tmp = (float_t)val.wk_ths_mg / 62.5f;
3971 wake_up_ths.wk_ths = (uint8_t)tmp;
3972 }
3973 else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f))
3974 && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f)))
3975 {
3976 inactivity_dur.wu_inact_ths_w = 4;
3977
3978 tmp = (float_t)val.inact_ths_mg / 125.0f;
3979 inactivity_ths.inact_ths = (uint8_t)tmp;
3980
3981 tmp = (float_t)val.wk_ths_mg / 125.0f;
3982 wake_up_ths.wk_ths = (uint8_t)tmp;
3983 }
3984 else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f))
3985 && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f)))
3986 {
3987 inactivity_dur.wu_inact_ths_w = 5;
3988
3989 tmp = (float_t)val.inact_ths_mg / 250.0f;
3990 inactivity_ths.inact_ths = (uint8_t)tmp;
3991
3992 tmp = (float_t)val.wk_ths_mg / 250.0f;
3993 wake_up_ths.wk_ths = (uint8_t)tmp;
3994 }
3995 else // out of limit
3996 {
3997 inactivity_dur.wu_inact_ths_w = 5;
3998 inactivity_ths.inact_ths = 0x3FU;
3999 wake_up_ths.wk_ths = 0x3FU;
4000 }
4001
4002 if (ret == 0)
4003 {
4004 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
4005 }
4006 if (ret == 0)
4007 {
4008
4009 ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
4010 }
4011 if (ret == 0)
4012 {
4013
4014 ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4015 }
4016
4017 return ret;
4018 }
4019
4020 /**
4021 * @brief Wakeup and activity/inactivity threshold.[get]
4022 *
4023 * @param ctx read / write interface definitions
4024 * @param val Wakeup and activity/inactivity threshold.
4025 * @retval interface status (MANDATORY: return 0 -> no Error)
4026 *
4027 */
ism330bx_act_thresholds_get(const stmdev_ctx_t * ctx,ism330bx_act_thresholds_t * val)4028 int32_t ism330bx_act_thresholds_get(const stmdev_ctx_t *ctx,
4029 ism330bx_act_thresholds_t *val)
4030 {
4031 ism330bx_inactivity_dur_t inactivity_dur;
4032 ism330bx_inactivity_ths_t inactivity_ths;
4033 ism330bx_wake_up_ths_t wake_up_ths;
4034 int32_t ret;
4035 float_t tmp;
4036
4037 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
4038 if (ret == 0)
4039 {
4040 ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
4041 }
4042 if (ret == 0)
4043 {
4044 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4045 }
4046
4047 switch (inactivity_dur.wu_inact_ths_w)
4048 {
4049 case 0:
4050 tmp = (float_t)wake_up_ths.wk_ths * 7.8125f;
4051 val->wk_ths_mg = (uint32_t)tmp;
4052
4053 tmp = (float_t)inactivity_ths.inact_ths * 7.8125f;
4054 val->inact_ths_mg = (uint32_t)tmp;
4055 break;
4056
4057 case 1:
4058 tmp = (float_t)wake_up_ths.wk_ths * 15.625f;
4059 val->wk_ths_mg = (uint32_t)tmp;
4060
4061 tmp = (float_t)inactivity_ths.inact_ths * 15.625f;
4062 val->inact_ths_mg = (uint32_t)tmp;
4063 break;
4064
4065 case 2:
4066 tmp = (float_t)wake_up_ths.wk_ths * 31.25f;
4067 val->wk_ths_mg = (uint32_t)tmp;
4068
4069 tmp = (float_t)inactivity_ths.inact_ths * 31.25f;
4070 val->inact_ths_mg = (uint32_t)tmp;
4071 break;
4072
4073 case 3:
4074 tmp = (float_t)wake_up_ths.wk_ths * 62.5f;
4075 val->wk_ths_mg = (uint32_t)tmp;
4076
4077 tmp = (float_t)inactivity_ths.inact_ths * 62.5f;
4078 val->inact_ths_mg = (uint32_t)tmp;
4079 break;
4080
4081 case 4:
4082 tmp = (float_t)wake_up_ths.wk_ths * 125.0f;
4083 val->wk_ths_mg = (uint32_t)tmp;
4084
4085 tmp = (float_t)inactivity_ths.inact_ths * 125.0f;
4086 val->inact_ths_mg = (uint32_t)tmp;
4087 break;
4088
4089 default:
4090 tmp = (float_t)wake_up_ths.wk_ths * 250.0f;
4091 val->wk_ths_mg = (uint32_t)tmp;
4092
4093 tmp = (float_t)inactivity_ths.inact_ths * 250.0f;
4094 val->inact_ths_mg = (uint32_t)tmp;
4095 break;
4096 }
4097
4098 return ret;
4099 }
4100
4101 /**
4102 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
4103 *
4104 * @param ctx read / write interface definitions
4105 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4106 * @retval interface status (MANDATORY: return 0 -> no Error)
4107 *
4108 */
ism330bx_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,ism330bx_act_wkup_time_windows_t val)4109 int32_t ism330bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
4110 ism330bx_act_wkup_time_windows_t val)
4111 {
4112 ism330bx_wake_up_dur_t wake_up_dur;
4113 int32_t ret;
4114
4115 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4116 if (ret == 0)
4117 {
4118 wake_up_dur.wake_dur = val.shock;
4119 wake_up_dur.sleep_dur = val.quiet;
4120 ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4121 }
4122
4123 return ret;
4124 }
4125
4126 /**
4127 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
4128 *
4129 * @param ctx read / write interface definitions
4130 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4131 * @retval interface status (MANDATORY: return 0 -> no Error)
4132 *
4133 */
ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,ism330bx_act_wkup_time_windows_t * val)4134 int32_t ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
4135 ism330bx_act_wkup_time_windows_t *val)
4136 {
4137 ism330bx_wake_up_dur_t wake_up_dur;
4138 int32_t ret;
4139
4140 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4141 val->shock = wake_up_dur.wake_dur;
4142 val->quiet = wake_up_dur.sleep_dur;
4143
4144 return ret;
4145 }
4146
4147 /**
4148 * @}
4149 *
4150 */
4151
4152 /**
4153 * @defgroup Tap Generator
4154 * @brief This section groups all the functions that manage the
4155 * tap and double tap event generation.
4156 * @{
4157 *
4158 */
4159
4160 /**
4161 * @brief Enable axis for Tap - Double Tap detection.[set]
4162 *
4163 * @param ctx read / write interface definitions
4164 * @param val Enable axis for Tap - Double Tap detection.
4165 * @retval interface status (MANDATORY: return 0 -> no Error)
4166 *
4167 */
ism330bx_tap_detection_set(const stmdev_ctx_t * ctx,ism330bx_tap_detection_t val)4168 int32_t ism330bx_tap_detection_set(const stmdev_ctx_t *ctx,
4169 ism330bx_tap_detection_t val)
4170 {
4171 ism330bx_tap_cfg0_t tap_cfg0;
4172 int32_t ret;
4173
4174 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4175 if (ret == 0)
4176 {
4177 tap_cfg0.tap_x_en = val.tap_x_en;
4178 tap_cfg0.tap_y_en = val.tap_y_en;
4179 tap_cfg0.tap_z_en = val.tap_z_en;
4180 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4181 }
4182
4183 return ret;
4184 }
4185
4186 /**
4187 * @brief Enable axis for Tap - Double Tap detection.[get]
4188 *
4189 * @param ctx read / write interface definitions
4190 * @param val Enable axis for Tap - Double Tap detection.
4191 * @retval interface status (MANDATORY: return 0 -> no Error)
4192 *
4193 */
ism330bx_tap_detection_get(const stmdev_ctx_t * ctx,ism330bx_tap_detection_t * val)4194 int32_t ism330bx_tap_detection_get(const stmdev_ctx_t *ctx,
4195 ism330bx_tap_detection_t *val)
4196 {
4197 ism330bx_tap_cfg0_t tap_cfg0;
4198 int32_t ret;
4199
4200 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4201 val->tap_x_en = tap_cfg0.tap_x_en;
4202 val->tap_y_en = tap_cfg0.tap_y_en;
4203 val->tap_z_en = tap_cfg0.tap_z_en;
4204
4205 return ret;
4206 }
4207
4208 /**
4209 * @brief axis Tap - Double Tap recognition thresholds.[set]
4210 *
4211 * @param ctx read / write interface definitions
4212 * @param val axis Tap - Double Tap recognition thresholds.
4213 * @retval interface status (MANDATORY: return 0 -> no Error)
4214 *
4215 */
ism330bx_tap_thresholds_set(const stmdev_ctx_t * ctx,ism330bx_tap_thresholds_t val)4216 int32_t ism330bx_tap_thresholds_set(const stmdev_ctx_t *ctx,
4217 ism330bx_tap_thresholds_t val)
4218 {
4219 ism330bx_tap_ths_6d_t tap_ths_6d;
4220 ism330bx_tap_cfg2_t tap_cfg2;
4221 ism330bx_tap_cfg1_t tap_cfg1;
4222 int32_t ret;
4223
4224 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4225 if (ret == 0)
4226 {
4227 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4228 }
4229 if (ret == 0)
4230 {
4231 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4232 }
4233
4234 tap_cfg1.tap_ths_z = val.z;
4235 tap_cfg2.tap_ths_y = val.y;
4236 tap_ths_6d.tap_ths_x = val.x;
4237
4238 if (ret == 0)
4239 {
4240 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4241 }
4242 if (ret == 0)
4243 {
4244 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4245 }
4246 if (ret == 0)
4247 {
4248 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4249 }
4250
4251 return ret;
4252 }
4253
4254 /**
4255 * @brief axis Tap - Double Tap recognition thresholds.[get]
4256 *
4257 * @param ctx read / write interface definitions
4258 * @param val axis Tap - Double Tap recognition thresholds.
4259 * @retval interface status (MANDATORY: return 0 -> no Error)
4260 *
4261 */
ism330bx_tap_thresholds_get(const stmdev_ctx_t * ctx,ism330bx_tap_thresholds_t * val)4262 int32_t ism330bx_tap_thresholds_get(const stmdev_ctx_t *ctx,
4263 ism330bx_tap_thresholds_t *val)
4264 {
4265 ism330bx_tap_ths_6d_t tap_ths_6d;
4266 ism330bx_tap_cfg2_t tap_cfg2;
4267 ism330bx_tap_cfg1_t tap_cfg1;
4268 int32_t ret;
4269
4270 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4271 if (ret == 0)
4272 {
4273 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4274 }
4275 if (ret == 0)
4276 {
4277 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4278 }
4279
4280 val->z = tap_cfg1.tap_ths_z;
4281 val->y = tap_cfg2.tap_ths_y;
4282 val->x = tap_ths_6d.tap_ths_x;
4283
4284 return ret;
4285 }
4286
4287 /**
4288 * @brief Selection of axis priority for TAP detection.[set]
4289 *
4290 * @param ctx read / write interface definitions
4291 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4292 * @retval interface status (MANDATORY: return 0 -> no Error)
4293 *
4294 */
ism330bx_tap_axis_priority_set(const stmdev_ctx_t * ctx,ism330bx_tap_axis_priority_t val)4295 int32_t ism330bx_tap_axis_priority_set(const stmdev_ctx_t *ctx,
4296 ism330bx_tap_axis_priority_t val)
4297 {
4298 ism330bx_tap_cfg1_t tap_cfg1;
4299 int32_t ret;
4300
4301 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4302 if (ret == 0)
4303 {
4304 tap_cfg1.tap_priority = (uint8_t)val & 0x07U;
4305 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4306 }
4307
4308 return ret;
4309 }
4310
4311 /**
4312 * @brief Selection of axis priority for TAP detection.[get]
4313 *
4314 * @param ctx read / write interface definitions
4315 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4316 * @retval interface status (MANDATORY: return 0 -> no Error)
4317 *
4318 */
ism330bx_tap_axis_priority_get(const stmdev_ctx_t * ctx,ism330bx_tap_axis_priority_t * val)4319 int32_t ism330bx_tap_axis_priority_get(const stmdev_ctx_t *ctx,
4320 ism330bx_tap_axis_priority_t *val)
4321 {
4322 ism330bx_tap_cfg1_t tap_cfg1;
4323 int32_t ret;
4324
4325 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4326 switch (tap_cfg1.tap_priority)
4327 {
4328 case ISM330BX_XYZ :
4329 *val = ISM330BX_XYZ ;
4330 break;
4331
4332 case ISM330BX_YXZ :
4333 *val = ISM330BX_YXZ ;
4334 break;
4335
4336 case ISM330BX_XZY:
4337 *val = ISM330BX_XZY;
4338 break;
4339
4340 case ISM330BX_ZYX :
4341 *val = ISM330BX_ZYX ;
4342 break;
4343
4344 case ISM330BX_YZX :
4345 *val = ISM330BX_YZX ;
4346 break;
4347
4348 case ISM330BX_ZXY :
4349 *val = ISM330BX_ZXY ;
4350 break;
4351
4352 default:
4353 *val = ISM330BX_XYZ ;
4354 break;
4355 }
4356 return ret;
4357 }
4358
4359
4360 /**
4361 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
4362 *
4363 * @param ctx read / write interface definitions
4364 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4365 * @retval interface status (MANDATORY: return 0 -> no Error)
4366 *
4367 */
ism330bx_tap_time_windows_set(const stmdev_ctx_t * ctx,ism330bx_tap_time_windows_t val)4368 int32_t ism330bx_tap_time_windows_set(const stmdev_ctx_t *ctx,
4369 ism330bx_tap_time_windows_t val)
4370 {
4371 ism330bx_tap_dur_t tap_dur;
4372 int32_t ret;
4373
4374 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4375 if (ret == 0)
4376 {
4377 tap_dur.shock = val.shock;
4378 tap_dur.quiet = val.quiet;
4379 tap_dur.dur = val.tap_gap;
4380 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4381 }
4382
4383 return ret;
4384 }
4385
4386 /**
4387 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
4388 *
4389 * @param ctx read / write interface definitions
4390 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4391 * @retval interface status (MANDATORY: return 0 -> no Error)
4392 *
4393 */
ism330bx_tap_time_windows_get(const stmdev_ctx_t * ctx,ism330bx_tap_time_windows_t * val)4394 int32_t ism330bx_tap_time_windows_get(const stmdev_ctx_t *ctx,
4395 ism330bx_tap_time_windows_t *val)
4396 {
4397 ism330bx_tap_dur_t tap_dur;
4398 int32_t ret;
4399
4400 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4401 val->shock = tap_dur.shock;
4402 val->quiet = tap_dur.quiet;
4403 val->tap_gap = tap_dur.dur;
4404
4405 return ret;
4406 }
4407
4408 /**
4409 * @brief Single/double-tap event enable.[set]
4410 *
4411 * @param ctx read / write interface definitions
4412 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4413 * @retval interface status (MANDATORY: return 0 -> no Error)
4414 *
4415 */
ism330bx_tap_mode_set(const stmdev_ctx_t * ctx,ism330bx_tap_mode_t val)4416 int32_t ism330bx_tap_mode_set(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t val)
4417 {
4418 ism330bx_wake_up_ths_t wake_up_ths;
4419 int32_t ret;
4420
4421 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4422 if (ret == 0)
4423 {
4424 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
4425 ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4426 }
4427
4428 return ret;
4429 }
4430
4431 /**
4432 * @brief Single/double-tap event enable.[get]
4433 *
4434 * @param ctx read / write interface definitions
4435 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4436 * @retval interface status (MANDATORY: return 0 -> no Error)
4437 *
4438 */
ism330bx_tap_mode_get(const stmdev_ctx_t * ctx,ism330bx_tap_mode_t * val)4439 int32_t ism330bx_tap_mode_get(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t *val)
4440 {
4441 ism330bx_wake_up_ths_t wake_up_ths;
4442 int32_t ret;
4443
4444 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4445 switch (wake_up_ths.single_double_tap)
4446 {
4447 case ISM330BX_ONLY_SINGLE:
4448 *val = ISM330BX_ONLY_SINGLE;
4449 break;
4450
4451 case ISM330BX_BOTH_SINGLE_DOUBLE:
4452 *val = ISM330BX_BOTH_SINGLE_DOUBLE;
4453 break;
4454
4455 default:
4456 *val = ISM330BX_ONLY_SINGLE;
4457 break;
4458 }
4459 return ret;
4460 }
4461
4462 /**
4463 * @}
4464 *
4465 */
4466
4467 /**
4468 * @defgroup Six position detection (6D)
4469 * @brief This section groups all the functions concerning six position
4470 * detection (6D).
4471 * @{
4472 *
4473 */
4474
4475 /**
4476 * @brief Threshold for 4D/6D function.[set]
4477 *
4478 * @param ctx read / write interface definitions
4479 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4480 * @retval interface status (MANDATORY: return 0 -> no Error)
4481 *
4482 */
ism330bx_6d_threshold_set(const stmdev_ctx_t * ctx,ism330bx_6d_threshold_t val)4483 int32_t ism330bx_6d_threshold_set(const stmdev_ctx_t *ctx,
4484 ism330bx_6d_threshold_t val)
4485 {
4486 ism330bx_tap_ths_6d_t tap_ths_6d;
4487 int32_t ret;
4488
4489 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4490 if (ret == 0)
4491 {
4492 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
4493 ret = ism330bx_write_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4494 }
4495
4496 return ret;
4497 }
4498
4499 /**
4500 * @brief Threshold for 4D/6D function.[get]
4501 *
4502 * @param ctx read / write interface definitions
4503 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4504 * @retval interface status (MANDATORY: return 0 -> no Error)
4505 *
4506 */
ism330bx_6d_threshold_get(const stmdev_ctx_t * ctx,ism330bx_6d_threshold_t * val)4507 int32_t ism330bx_6d_threshold_get(const stmdev_ctx_t *ctx,
4508 ism330bx_6d_threshold_t *val)
4509 {
4510 ism330bx_tap_ths_6d_t tap_ths_6d;
4511 int32_t ret;
4512
4513 ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4514 switch (tap_ths_6d.sixd_ths)
4515 {
4516 case ISM330BX_DEG_80:
4517 *val = ISM330BX_DEG_80;
4518 break;
4519
4520 case ISM330BX_DEG_70:
4521 *val = ISM330BX_DEG_70;
4522 break;
4523
4524 case ISM330BX_DEG_60:
4525 *val = ISM330BX_DEG_60;
4526 break;
4527
4528 case ISM330BX_DEG_50:
4529 *val = ISM330BX_DEG_50;
4530 break;
4531
4532 default:
4533 *val = ISM330BX_DEG_80;
4534 break;
4535 }
4536 return ret;
4537 }
4538
4539 /**
4540 * @}
4541 *
4542 */
4543
4544 /**
4545 * @defgroup Free fall
4546 * @brief This section group all the functions concerning the free
4547 * fall detection.
4548 * @{
4549 *
4550 */
4551
4552 /**
4553 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
4554 *
4555 * @param ctx read / write interface definitions
4556 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4557 * @retval interface status (MANDATORY: return 0 -> no Error)
4558 *
4559 */
ism330bx_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)4560 int32_t ism330bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
4561 {
4562 ism330bx_wake_up_dur_t wake_up_dur;
4563 ism330bx_free_fall_t free_fall;
4564 int32_t ret;
4565
4566 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4567 if (ret == 0)
4568 {
4569 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
4570 ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4571 }
4572 if (ret == 0)
4573 {
4574 ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4575 }
4576
4577 if (ret == 0)
4578 {
4579 free_fall.ff_dur = (uint8_t)val & 0x1FU;
4580 ret = ism330bx_write_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4581 }
4582
4583 return ret;
4584 }
4585
4586 /**
4587 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
4588 *
4589 * @param ctx read / write interface definitions
4590 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4591 * @retval interface status (MANDATORY: return 0 -> no Error)
4592 *
4593 */
ism330bx_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)4594 int32_t ism330bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
4595 {
4596 ism330bx_wake_up_dur_t wake_up_dur;
4597 ism330bx_free_fall_t free_fall;
4598 int32_t ret;
4599
4600 ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4601 if (ret == 0)
4602 {
4603 ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4604 }
4605
4606 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4607
4608 return ret;
4609 }
4610
4611 /**
4612 * @brief Free fall threshold setting.[set]
4613 *
4614 * @param ctx read / write interface definitions
4615 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4616 * @retval interface status (MANDATORY: return 0 -> no Error)
4617 *
4618 */
ism330bx_ff_thresholds_set(const stmdev_ctx_t * ctx,ism330bx_ff_thresholds_t val)4619 int32_t ism330bx_ff_thresholds_set(const stmdev_ctx_t *ctx,
4620 ism330bx_ff_thresholds_t val)
4621 {
4622 ism330bx_free_fall_t free_fall;
4623 int32_t ret;
4624
4625 ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4626 if (ret == 0)
4627 {
4628 free_fall.ff_ths = (uint8_t)val & 0x7U;
4629 ret = ism330bx_write_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4630 }
4631
4632 return ret;
4633 }
4634
4635 /**
4636 * @brief Free fall threshold setting.[get]
4637 *
4638 * @param ctx read / write interface definitions
4639 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4640 * @retval interface status (MANDATORY: return 0 -> no Error)
4641 *
4642 */
ism330bx_ff_thresholds_get(const stmdev_ctx_t * ctx,ism330bx_ff_thresholds_t * val)4643 int32_t ism330bx_ff_thresholds_get(const stmdev_ctx_t *ctx,
4644 ism330bx_ff_thresholds_t *val)
4645 {
4646 ism330bx_free_fall_t free_fall;
4647 int32_t ret;
4648
4649 ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4650
4651 switch (free_fall.ff_ths)
4652 {
4653 case ISM330BX_156_mg:
4654 *val = ISM330BX_156_mg;
4655 break;
4656
4657 case ISM330BX_219_mg:
4658 *val = ISM330BX_219_mg;
4659 break;
4660
4661 case ISM330BX_250_mg:
4662 *val = ISM330BX_250_mg;
4663 break;
4664
4665 case ISM330BX_312_mg:
4666 *val = ISM330BX_312_mg;
4667 break;
4668
4669 case ISM330BX_344_mg:
4670 *val = ISM330BX_344_mg;
4671 break;
4672
4673 case ISM330BX_406_mg:
4674 *val = ISM330BX_406_mg;
4675 break;
4676
4677 case ISM330BX_469_mg:
4678 *val = ISM330BX_469_mg;
4679 break;
4680
4681 case ISM330BX_500_mg:
4682 *val = ISM330BX_500_mg;
4683 break;
4684
4685 default:
4686 *val = ISM330BX_156_mg;
4687 break;
4688 }
4689 return ret;
4690 }
4691
4692 /**
4693 * @}
4694 *
4695 */
4696
4697 /**
4698 * @defgroup FIFO
4699 * @brief This section group all the functions concerning the fifo usage
4700 * @{
4701 *
4702 */
4703
4704 /**
4705 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
4706 *
4707 * @param ctx read / write interface definitions
4708 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4709 * @retval interface status (MANDATORY: return 0 -> no Error)
4710 *
4711 */
ism330bx_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)4712 int32_t ism330bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
4713 {
4714 ism330bx_fifo_ctrl1_t fifo_ctrl1;
4715 int32_t ret;
4716
4717 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4718
4719 if (ret == 0)
4720 {
4721 fifo_ctrl1.wtm = val;
4722 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4723 }
4724
4725 return ret;
4726 }
4727
4728 /**
4729 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
4730 *
4731 * @param ctx read / write interface definitions
4732 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4733 * @retval interface status (MANDATORY: return 0 -> no Error)
4734 *
4735 */
ism330bx_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)4736 int32_t ism330bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
4737 {
4738 ism330bx_fifo_ctrl1_t fifo_ctrl1;
4739 int32_t ret;
4740
4741 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4742 *val = fifo_ctrl1.wtm;
4743
4744 return ret;
4745 }
4746
4747 /**
4748 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
4749 *
4750 * @param ctx read / write interface definitions
4751 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4752 * @retval interface status (MANDATORY: return 0 -> no Error)
4753 *
4754 */
ism330bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4755 int32_t ism330bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4756 {
4757 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4758 int32_t ret;
4759
4760 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4761 if (ret == 0)
4762 {
4763 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
4764 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4765 }
4766
4767 return ret;
4768 }
4769
4770 /**
4771 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
4772 *
4773 * @param ctx read / write interface definitions
4774 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4775 * @retval interface status (MANDATORY: return 0 -> no Error)
4776 *
4777 */
ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4778 int32_t ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4779 {
4780 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4781 int32_t ret;
4782
4783 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4784 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
4785
4786 return ret;
4787 }
4788
4789 /**
4790 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
4791 *
4792 * @param ctx read / write interface definitions
4793 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4794 * @retval interface status (MANDATORY: return 0 -> no Error)
4795 *
4796 */
ism330bx_fifo_compress_algo_set(const stmdev_ctx_t * ctx,ism330bx_fifo_compress_algo_t val)4797 int32_t ism330bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
4798 ism330bx_fifo_compress_algo_t val)
4799 {
4800 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4801 int32_t ret;
4802
4803 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4804 if (ret == 0)
4805 {
4806 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
4807 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4808 }
4809
4810 return ret;
4811 }
4812
4813 /**
4814 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
4815 *
4816 * @param ctx read / write interface definitions
4817 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4818 * @retval interface status (MANDATORY: return 0 -> no Error)
4819 *
4820 */
ism330bx_fifo_compress_algo_get(const stmdev_ctx_t * ctx,ism330bx_fifo_compress_algo_t * val)4821 int32_t ism330bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
4822 ism330bx_fifo_compress_algo_t *val)
4823 {
4824 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4825 int32_t ret;
4826
4827 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4828
4829 switch (fifo_ctrl2.uncompr_rate)
4830 {
4831 case ISM330BX_CMP_DISABLE:
4832 *val = ISM330BX_CMP_DISABLE;
4833 break;
4834
4835 case ISM330BX_CMP_8_TO_1:
4836 *val = ISM330BX_CMP_8_TO_1;
4837 break;
4838
4839 case ISM330BX_CMP_16_TO_1:
4840 *val = ISM330BX_CMP_16_TO_1;
4841 break;
4842
4843 case ISM330BX_CMP_32_TO_1:
4844 *val = ISM330BX_CMP_32_TO_1;
4845 break;
4846
4847 default:
4848 *val = ISM330BX_CMP_DISABLE;
4849 break;
4850 }
4851 return ret;
4852 }
4853
4854 /**
4855 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4856 *
4857 * @param ctx read / write interface definitions
4858 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4859 * @retval interface status (MANDATORY: return 0 -> no Error)
4860 *
4861 */
ism330bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4862 int32_t ism330bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4863 uint8_t val)
4864 {
4865 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4866 int32_t ret;
4867
4868 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4869 if (ret == 0)
4870 {
4871 fifo_ctrl2.odr_chg_en = val;
4872 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4873 }
4874
4875 return ret;
4876 }
4877
4878 /**
4879 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4880 *
4881 * @param ctx read / write interface definitions
4882 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4883 * @retval interface status (MANDATORY: return 0 -> no Error)
4884 *
4885 */
ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4886 int32_t ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4887 uint8_t *val)
4888 {
4889 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4890 int32_t ret;
4891
4892 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4893 *val = fifo_ctrl2.odr_chg_en;
4894
4895 return ret;
4896 }
4897
4898 /**
4899 * @brief Enables/Disables compression algorithm runtime.[set]
4900 *
4901 * @param ctx read / write interface definitions
4902 * @param val Enables/Disables compression algorithm runtime.
4903 * @retval interface status (MANDATORY: return 0 -> no Error)
4904 *
4905 */
ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)4906 int32_t ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
4907 uint8_t val)
4908 {
4909 ism330bx_emb_func_en_b_t emb_func_en_b;
4910 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4911
4912 int32_t ret;
4913
4914 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4915 if (ret == 0)
4916 {
4917 fifo_ctrl2.fifo_compr_rt_en = val;
4918 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4919 }
4920
4921 if (ret == 0)
4922 {
4923 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
4924 }
4925 if (ret == 0)
4926 {
4927 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4928 }
4929 if (ret == 0)
4930 {
4931 emb_func_en_b.fifo_compr_en = val;
4932 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4933 }
4934
4935 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
4936
4937 return ret;
4938 }
4939
4940 /**
4941 * @brief Enables/Disables compression algorithm runtime.[get]
4942 *
4943 * @param ctx read / write interface definitions
4944 * @param val Enables/Disables compression algorithm runtime.
4945 * @retval interface status (MANDATORY: return 0 -> no Error)
4946 *
4947 */
ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)4948 int32_t ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
4949 uint8_t *val)
4950 {
4951 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4952 int32_t ret;
4953
4954 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4955
4956 *val = fifo_ctrl2.fifo_compr_rt_en;
4957
4958 return ret;
4959 }
4960
4961 /**
4962 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
4963 *
4964 * @param ctx read / write interface definitions
4965 * @param val Sensing chain FIFO stop values memorization at threshold level.
4966 * @retval interface status (MANDATORY: return 0 -> no Error)
4967 *
4968 */
ism330bx_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4969 int32_t ism330bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4970 {
4971 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4972 int32_t ret;
4973
4974 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4975 if (ret == 0)
4976 {
4977 fifo_ctrl2.stop_on_wtm = val;
4978 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4979 }
4980
4981 return ret;
4982 }
4983
4984 /**
4985 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
4986 *
4987 * @param ctx read / write interface definitions
4988 * @param val Sensing chain FIFO stop values memorization at threshold level.
4989 * @retval interface status (MANDATORY: return 0 -> no Error)
4990 *
4991 */
ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)4992 int32_t ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4993 {
4994 ism330bx_fifo_ctrl2_t fifo_ctrl2;
4995 int32_t ret;
4996
4997 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4998 *val = fifo_ctrl2.stop_on_wtm;
4999
5000 return ret;
5001 }
5002
5003 /**
5004 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
5005 *
5006 * @param ctx read / write interface definitions
5007 * @param val ism330bx_fifo_xl_batch_t enum
5008 * @retval interface status (MANDATORY: return 0 -> no Error)
5009 *
5010 */
ism330bx_fifo_xl_batch_set(const stmdev_ctx_t * ctx,ism330bx_fifo_xl_batch_t val)5011 int32_t ism330bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5012 ism330bx_fifo_xl_batch_t val)
5013 {
5014 ism330bx_fifo_ctrl3_t fifo_ctrl3;
5015 int32_t ret;
5016
5017 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5018 if (ret == 0)
5019 {
5020 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU;
5021 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5022 }
5023
5024 return ret;
5025 }
5026
5027 /**
5028 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
5029 *
5030 * @param ctx read / write interface definitions
5031 * @param val ism330bx_fifo_xl_batch_t enum
5032 * @retval interface status (MANDATORY: return 0 -> no Error)
5033 *
5034 */
ism330bx_fifo_xl_batch_get(const stmdev_ctx_t * ctx,ism330bx_fifo_xl_batch_t * val)5035 int32_t ism330bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5036 ism330bx_fifo_xl_batch_t *val)
5037 {
5038 ism330bx_fifo_ctrl3_t fifo_ctrl3;
5039 int32_t ret;
5040
5041 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5042 switch (fifo_ctrl3.bdr_xl)
5043 {
5044 case ISM330BX_XL_NOT_BATCHED:
5045 *val = ISM330BX_XL_NOT_BATCHED;
5046 break;
5047
5048 case ISM330BX_XL_BATCHED_AT_1Hz875:
5049 *val = ISM330BX_XL_BATCHED_AT_1Hz875;
5050 break;
5051
5052 case ISM330BX_XL_BATCHED_AT_7Hz5:
5053 *val = ISM330BX_XL_BATCHED_AT_7Hz5;
5054 break;
5055
5056 case ISM330BX_XL_BATCHED_AT_15Hz:
5057 *val = ISM330BX_XL_BATCHED_AT_15Hz;
5058 break;
5059
5060 case ISM330BX_XL_BATCHED_AT_30Hz:
5061 *val = ISM330BX_XL_BATCHED_AT_30Hz;
5062 break;
5063
5064 case ISM330BX_XL_BATCHED_AT_60Hz:
5065 *val = ISM330BX_XL_BATCHED_AT_60Hz;
5066 break;
5067
5068 case ISM330BX_XL_BATCHED_AT_120Hz:
5069 *val = ISM330BX_XL_BATCHED_AT_120Hz;
5070 break;
5071
5072 case ISM330BX_XL_BATCHED_AT_240Hz:
5073 *val = ISM330BX_XL_BATCHED_AT_240Hz;
5074 break;
5075
5076 case ISM330BX_XL_BATCHED_AT_480Hz:
5077 *val = ISM330BX_XL_BATCHED_AT_480Hz;
5078 break;
5079
5080 case ISM330BX_XL_BATCHED_AT_960Hz:
5081 *val = ISM330BX_XL_BATCHED_AT_960Hz;
5082 break;
5083
5084 case ISM330BX_XL_BATCHED_AT_1920Hz:
5085 *val = ISM330BX_XL_BATCHED_AT_1920Hz;
5086 break;
5087
5088 case ISM330BX_XL_BATCHED_AT_3840Hz:
5089 *val = ISM330BX_XL_BATCHED_AT_3840Hz;
5090 break;
5091
5092 default:
5093 *val = ISM330BX_XL_NOT_BATCHED;
5094 break;
5095 }
5096 return ret;
5097 }
5098
5099 /**
5100 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
5101 *
5102 * @param ctx read / write interface definitions
5103 * @param val ism330bx_fifo_gy_batch_t enum
5104 * @retval interface status (MANDATORY: return 0 -> no Error)
5105 *
5106 */
ism330bx_fifo_gy_batch_set(const stmdev_ctx_t * ctx,ism330bx_fifo_gy_batch_t val)5107 int32_t ism330bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5108 ism330bx_fifo_gy_batch_t val)
5109 {
5110 ism330bx_fifo_ctrl3_t fifo_ctrl3;
5111 int32_t ret;
5112
5113 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5114 if (ret == 0)
5115 {
5116 fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU;
5117 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5118 }
5119
5120 return ret;
5121 }
5122
5123 /**
5124 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
5125 *
5126 * @param ctx read / write interface definitions
5127 * @param val ism330bx_fifo_gy_batch_t enum
5128 * @retval interface status (MANDATORY: return 0 -> no Error)
5129 *
5130 */
ism330bx_fifo_gy_batch_get(const stmdev_ctx_t * ctx,ism330bx_fifo_gy_batch_t * val)5131 int32_t ism330bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5132 ism330bx_fifo_gy_batch_t *val)
5133 {
5134 ism330bx_fifo_ctrl3_t fifo_ctrl3;
5135 int32_t ret;
5136
5137 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5138 switch (fifo_ctrl3.bdr_gy)
5139 {
5140 case ISM330BX_GY_NOT_BATCHED:
5141 *val = ISM330BX_GY_NOT_BATCHED;
5142 break;
5143
5144 case ISM330BX_GY_BATCHED_AT_1Hz875:
5145 *val = ISM330BX_GY_BATCHED_AT_1Hz875;
5146 break;
5147
5148 case ISM330BX_GY_BATCHED_AT_7Hz5:
5149 *val = ISM330BX_GY_BATCHED_AT_7Hz5;
5150 break;
5151
5152 case ISM330BX_GY_BATCHED_AT_15Hz:
5153 *val = ISM330BX_GY_BATCHED_AT_15Hz;
5154 break;
5155
5156 case ISM330BX_GY_BATCHED_AT_30Hz:
5157 *val = ISM330BX_GY_BATCHED_AT_30Hz;
5158 break;
5159
5160 case ISM330BX_GY_BATCHED_AT_60Hz:
5161 *val = ISM330BX_GY_BATCHED_AT_60Hz;
5162 break;
5163
5164 case ISM330BX_GY_BATCHED_AT_120Hz:
5165 *val = ISM330BX_GY_BATCHED_AT_120Hz;
5166 break;
5167
5168 case ISM330BX_GY_BATCHED_AT_240Hz:
5169 *val = ISM330BX_GY_BATCHED_AT_240Hz;
5170 break;
5171
5172 case ISM330BX_GY_BATCHED_AT_480Hz:
5173 *val = ISM330BX_GY_BATCHED_AT_480Hz;
5174 break;
5175
5176 case ISM330BX_GY_BATCHED_AT_960Hz:
5177 *val = ISM330BX_GY_BATCHED_AT_960Hz;
5178 break;
5179
5180 case ISM330BX_GY_BATCHED_AT_1920Hz:
5181 *val = ISM330BX_GY_BATCHED_AT_1920Hz;
5182 break;
5183
5184 case ISM330BX_GY_BATCHED_AT_3840Hz:
5185 *val = ISM330BX_GY_BATCHED_AT_3840Hz;
5186 break;
5187
5188 default:
5189 *val = ISM330BX_GY_NOT_BATCHED;
5190 break;
5191 }
5192 return ret;
5193 }
5194
5195 /**
5196 * @brief FIFO mode selection.[set]
5197 *
5198 * @param ctx read / write interface definitions
5199 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5200 * @retval interface status (MANDATORY: return 0 -> no Error)
5201 *
5202 */
ism330bx_fifo_mode_set(const stmdev_ctx_t * ctx,ism330bx_fifo_mode_t val)5203 int32_t ism330bx_fifo_mode_set(const stmdev_ctx_t *ctx,
5204 ism330bx_fifo_mode_t val)
5205 {
5206 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5207 int32_t ret;
5208
5209 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5210 if (ret == 0)
5211 {
5212 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
5213 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5214 }
5215
5216 return ret;
5217 }
5218
5219 /**
5220 * @brief FIFO mode selection.[get]
5221 *
5222 * @param ctx read / write interface definitions
5223 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5224 * @retval interface status (MANDATORY: return 0 -> no Error)
5225 *
5226 */
ism330bx_fifo_mode_get(const stmdev_ctx_t * ctx,ism330bx_fifo_mode_t * val)5227 int32_t ism330bx_fifo_mode_get(const stmdev_ctx_t *ctx,
5228 ism330bx_fifo_mode_t *val)
5229 {
5230 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5231 int32_t ret;
5232
5233 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5234 switch (fifo_ctrl4.fifo_mode)
5235 {
5236 case ISM330BX_BYPASS_MODE:
5237 *val = ISM330BX_BYPASS_MODE;
5238 break;
5239
5240 case ISM330BX_FIFO_MODE:
5241 *val = ISM330BX_FIFO_MODE;
5242 break;
5243
5244 case ISM330BX_STREAM_WTM_TO_FULL_MODE:
5245 *val = ISM330BX_STREAM_WTM_TO_FULL_MODE;
5246 break;
5247
5248 case ISM330BX_STREAM_TO_FIFO_MODE:
5249 *val = ISM330BX_STREAM_TO_FIFO_MODE;
5250 break;
5251
5252 case ISM330BX_BYPASS_TO_STREAM_MODE:
5253 *val = ISM330BX_BYPASS_TO_STREAM_MODE;
5254 break;
5255
5256 case ISM330BX_STREAM_MODE:
5257 *val = ISM330BX_STREAM_MODE;
5258 break;
5259
5260 case ISM330BX_BYPASS_TO_FIFO_MODE:
5261 *val = ISM330BX_BYPASS_TO_FIFO_MODE;
5262 break;
5263
5264 default:
5265 *val = ISM330BX_BYPASS_MODE;
5266 break;
5267 }
5268 return ret;
5269 }
5270
5271 /**
5272 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
5273 *
5274 * @param ctx read / write interface definitions
5275 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5276 * @retval interface status (MANDATORY: return 0 -> no Error)
5277 *
5278 */
ism330bx_fifo_temp_batch_set(const stmdev_ctx_t * ctx,ism330bx_fifo_temp_batch_t val)5279 int32_t ism330bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
5280 ism330bx_fifo_temp_batch_t val)
5281 {
5282 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5283 int32_t ret;
5284
5285 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5286 if (ret == 0)
5287 {
5288 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
5289 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5290 }
5291
5292 return ret;
5293 }
5294
5295 /**
5296 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
5297 *
5298 * @param ctx read / write interface definitions
5299 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5300 * @retval interface status (MANDATORY: return 0 -> no Error)
5301 *
5302 */
ism330bx_fifo_temp_batch_get(const stmdev_ctx_t * ctx,ism330bx_fifo_temp_batch_t * val)5303 int32_t ism330bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
5304 ism330bx_fifo_temp_batch_t *val)
5305 {
5306 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5307 int32_t ret;
5308
5309 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5310 switch (fifo_ctrl4.odr_t_batch)
5311 {
5312 case ISM330BX_TEMP_NOT_BATCHED:
5313 *val = ISM330BX_TEMP_NOT_BATCHED;
5314 break;
5315
5316 case ISM330BX_TEMP_BATCHED_AT_1Hz875:
5317 *val = ISM330BX_TEMP_BATCHED_AT_1Hz875;
5318 break;
5319
5320 case ISM330BX_TEMP_BATCHED_AT_15Hz:
5321 *val = ISM330BX_TEMP_BATCHED_AT_15Hz;
5322 break;
5323
5324 case ISM330BX_TEMP_BATCHED_AT_60Hz:
5325 *val = ISM330BX_TEMP_BATCHED_AT_60Hz;
5326 break;
5327
5328 default:
5329 *val = ISM330BX_TEMP_NOT_BATCHED;
5330 break;
5331 }
5332 return ret;
5333 }
5334
5335 /**
5336 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
5337 *
5338 * @param ctx read / write interface definitions
5339 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5340 * @retval interface status (MANDATORY: return 0 -> no Error)
5341 *
5342 */
ism330bx_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,ism330bx_fifo_timestamp_batch_t val)5343 int32_t ism330bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
5344 ism330bx_fifo_timestamp_batch_t val)
5345 {
5346 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5347 int32_t ret;
5348
5349 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5350 if (ret == 0)
5351 {
5352 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U;
5353 ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5354 }
5355
5356 return ret;
5357 }
5358
5359 /**
5360 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
5361 *
5362 * @param ctx read / write interface definitions
5363 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5364 * @retval interface status (MANDATORY: return 0 -> no Error)
5365 *
5366 */
ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,ism330bx_fifo_timestamp_batch_t * val)5367 int32_t ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
5368 ism330bx_fifo_timestamp_batch_t *val)
5369 {
5370 ism330bx_fifo_ctrl4_t fifo_ctrl4;
5371 int32_t ret;
5372
5373 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5374 switch (fifo_ctrl4.dec_ts_batch)
5375 {
5376 case ISM330BX_TMSTMP_NOT_BATCHED:
5377 *val = ISM330BX_TMSTMP_NOT_BATCHED;
5378 break;
5379
5380 case ISM330BX_TMSTMP_DEC_1:
5381 *val = ISM330BX_TMSTMP_DEC_1;
5382 break;
5383
5384 case ISM330BX_TMSTMP_DEC_8:
5385 *val = ISM330BX_TMSTMP_DEC_8;
5386 break;
5387
5388 case ISM330BX_TMSTMP_DEC_32:
5389 *val = ISM330BX_TMSTMP_DEC_32;
5390 break;
5391
5392 default:
5393 *val = ISM330BX_TMSTMP_NOT_BATCHED;
5394 break;
5395 }
5396 return ret;
5397 }
5398
5399 /**
5400 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
5401 *
5402 * @param ctx read / write interface definitions
5403 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5404 * @retval interface status (MANDATORY: return 0 -> no Error)
5405 *
5406 */
ism330bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5407 int32_t ism330bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
5408 uint16_t val)
5409 {
5410 ism330bx_counter_bdr_reg1_t counter_bdr_reg1;
5411 ism330bx_counter_bdr_reg2_t counter_bdr_reg2;
5412 int32_t ret;
5413
5414 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5415
5416 if (ret == 0)
5417 {
5418 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
5419 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
5420 ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5421 ret += ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
5422 }
5423
5424 return ret;
5425 }
5426
5427 /**
5428 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
5429 *
5430 * @param ctx read / write interface definitions
5431 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5432 * @retval interface status (MANDATORY: return 0 -> no Error)
5433 *
5434 */
ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5435 int32_t ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5436 uint16_t *val)
5437 {
5438 uint8_t buff[2];
5439 int32_t ret;
5440
5441 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, &buff[0], 2);
5442 *val = (uint16_t)buff[0] & 0x3U;
5443 *val = (*val * 256U) + (uint16_t)buff[1];
5444
5445 return ret;
5446 }
5447
5448 /**
5449 * @brief Enables AH_QVAR batching in FIFO.[set]
5450 *
5451 * @param ctx read / write interface definitions
5452 * @param val Enables AH_QVAR batching in FIFO.
5453 * @retval interface status (MANDATORY: return 0 -> no Error)
5454 *
5455 */
ism330bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t * ctx,uint8_t val)5456 int32_t ism330bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val)
5457 {
5458 ism330bx_counter_bdr_reg1_t counter_bdr_reg1;
5459 int32_t ret;
5460
5461 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5462 if (ret == 0)
5463 {
5464 counter_bdr_reg1.ah_qvar_batch_en = val;
5465 ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5466 }
5467
5468 return ret;
5469 }
5470
5471 /**
5472 * @brief Enables AH_QVAR batching in FIFO.[get]
5473 *
5474 * @param ctx read / write interface definitions
5475 * @param val Enables AH_QVAR batching in FIFO.
5476 * @retval interface status (MANDATORY: return 0 -> no Error)
5477 *
5478 */
ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t * ctx,uint8_t * val)5479 int32_t ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val)
5480 {
5481 ism330bx_counter_bdr_reg1_t counter_bdr_reg1;
5482 int32_t ret;
5483
5484 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5485 *val = counter_bdr_reg1.ah_qvar_batch_en;
5486
5487 return ret;
5488 }
5489
5490 /**
5491 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set]
5492 *
5493 * @param ctx read / write interface definitions
5494 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5495 * @retval interface status (MANDATORY: return 0 -> no Error)
5496 *
5497 */
ism330bx_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,ism330bx_fifo_batch_cnt_event_t val)5498 int32_t ism330bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
5499 ism330bx_fifo_batch_cnt_event_t val)
5500 {
5501 ism330bx_counter_bdr_reg1_t counter_bdr_reg1;
5502 int32_t ret;
5503
5504 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5505
5506 if (ret == 0)
5507 {
5508 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
5509 ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5510 }
5511
5512 return ret;
5513 }
5514
5515 /**
5516 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get]
5517 *
5518 * @param ctx read / write interface definitions
5519 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5520 * @retval interface status (MANDATORY: return 0 -> no Error)
5521 *
5522 */
ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,ism330bx_fifo_batch_cnt_event_t * val)5523 int32_t ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
5524 ism330bx_fifo_batch_cnt_event_t *val)
5525 {
5526 ism330bx_counter_bdr_reg1_t counter_bdr_reg1;
5527 int32_t ret;
5528
5529 ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5530 switch (counter_bdr_reg1.trig_counter_bdr)
5531 {
5532 case ISM330BX_XL_BATCH_EVENT:
5533 *val = ISM330BX_XL_BATCH_EVENT;
5534 break;
5535
5536 case ISM330BX_GY_BATCH_EVENT:
5537 *val = ISM330BX_GY_BATCH_EVENT;
5538 break;
5539
5540 default:
5541 *val = ISM330BX_XL_BATCH_EVENT;
5542 break;
5543 }
5544 return ret;
5545 }
5546
5547 /**
5548 * @brief Batching in FIFO buffer of SFLP.[set]
5549 *
5550 * @param ctx read / write interface definitions
5551 * @param val Batching in FIFO buffer of SFLP values.
5552 * @retval interface status (MANDATORY: return 0 -> no Error)
5553 *
5554 */
ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,ism330bx_fifo_sflp_raw_t val)5555 int32_t ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
5556 ism330bx_fifo_sflp_raw_t val)
5557 {
5558 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5559 int32_t ret;
5560
5561 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5562 if (ret == 0)
5563 {
5564 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5565 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
5566 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
5567 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
5568 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A,
5569 (uint8_t *)&emb_func_fifo_en_a, 1);
5570 }
5571
5572 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5573
5574 return ret;
5575 }
5576
5577 /**
5578 * @brief Batching in FIFO buffer of SFLP.[get]
5579 *
5580 * @param ctx read / write interface definitions
5581 * @param val Batching in FIFO buffer of SFLP values.
5582 * @retval interface status (MANDATORY: return 0 -> no Error)
5583 *
5584 */
ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,ism330bx_fifo_sflp_raw_t * val)5585 int32_t ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
5586 ism330bx_fifo_sflp_raw_t *val)
5587 {
5588 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5589 int32_t ret;
5590
5591 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5592 if (ret == 0)
5593 {
5594 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5595
5596 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
5597 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
5598 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
5599 }
5600
5601 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5602
5603 return ret;
5604 }
5605
5606 /**
5607 * @brief Status of FIFO.[get]
5608 *
5609 * @param ctx read / write interface definitions
5610 * @param val Status of FIFO (level and flags).
5611 * @retval interface status (MANDATORY: return 0 -> no Error)
5612 *
5613 */
ism330bx_fifo_status_get(const stmdev_ctx_t * ctx,ism330bx_fifo_status_t * val)5614 int32_t ism330bx_fifo_status_get(const stmdev_ctx_t *ctx,
5615 ism330bx_fifo_status_t *val)
5616 {
5617 uint8_t buff[2];
5618 ism330bx_fifo_status2_t status;
5619 int32_t ret;
5620
5621 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
5622 bytecpy((uint8_t *)&status, &buff[1]);
5623
5624 val->fifo_bdr = status.counter_bdr_ia;
5625 val->fifo_ovr = status.fifo_ovr_ia;
5626 val->fifo_full = status.fifo_full_ia;
5627 val->fifo_th = status.fifo_wtm_ia;
5628
5629 val->fifo_level = (uint16_t)buff[1] & 0x01U;
5630 val->fifo_level = (val->fifo_level * 256U) + buff[0];
5631
5632 return ret;
5633 }
5634
5635 /**
5636 * @brief FIFO data output[get]
5637 *
5638 * @param ctx read / write interface definitions
5639 * @param val ism330bx_fifo_out_raw_t enum
5640 * @retval interface status (MANDATORY: return 0 -> no Error)
5641 *
5642 */
ism330bx_fifo_out_raw_get(const stmdev_ctx_t * ctx,ism330bx_fifo_out_raw_t * val)5643 int32_t ism330bx_fifo_out_raw_get(const stmdev_ctx_t *ctx,
5644 ism330bx_fifo_out_raw_t *val)
5645 {
5646 ism330bx_fifo_data_out_tag_t fifo_data_out_tag;
5647 uint8_t buff[7];
5648 int32_t ret;
5649
5650 ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_DATA_OUT_TAG, buff, 7);
5651 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
5652
5653 switch (fifo_data_out_tag.tag_sensor)
5654 {
5655 case ISM330BX_FIFO_EMPTY:
5656 val->tag = ISM330BX_FIFO_EMPTY;
5657 break;
5658
5659 case ISM330BX_GY_NC_TAG:
5660 val->tag = ISM330BX_GY_NC_TAG;
5661 break;
5662
5663 case ISM330BX_XL_NC_TAG:
5664 val->tag = ISM330BX_XL_NC_TAG;
5665 break;
5666
5667 case ISM330BX_TIMESTAMP_TAG:
5668 val->tag = ISM330BX_TIMESTAMP_TAG;
5669 break;
5670
5671 case ISM330BX_TEMPERATURE_TAG:
5672 val->tag = ISM330BX_TEMPERATURE_TAG;
5673 break;
5674
5675 case ISM330BX_CFG_CHANGE_TAG:
5676 val->tag = ISM330BX_CFG_CHANGE_TAG;
5677 break;
5678
5679 case ISM330BX_XL_NC_T_2_TAG:
5680 val->tag = ISM330BX_XL_NC_T_2_TAG;
5681 break;
5682
5683 case ISM330BX_XL_NC_T_1_TAG:
5684 val->tag = ISM330BX_XL_NC_T_1_TAG;
5685 break;
5686
5687 case ISM330BX_XL_2XC_TAG:
5688 val->tag = ISM330BX_XL_2XC_TAG;
5689 break;
5690
5691 case ISM330BX_XL_3XC_TAG:
5692 val->tag = ISM330BX_XL_3XC_TAG;
5693 break;
5694
5695 case ISM330BX_GY_NC_T_2_TAG:
5696 val->tag = ISM330BX_GY_NC_T_2_TAG;
5697 break;
5698
5699 case ISM330BX_GY_NC_T_1_TAG:
5700 val->tag = ISM330BX_GY_NC_T_1_TAG;
5701 break;
5702
5703 case ISM330BX_GY_2XC_TAG:
5704 val->tag = ISM330BX_GY_2XC_TAG;
5705 break;
5706
5707 case ISM330BX_GY_3XC_TAG:
5708 val->tag = ISM330BX_GY_3XC_TAG;
5709 break;
5710
5711 case ISM330BX_STEP_COUNTER_TAG:
5712 val->tag = ISM330BX_STEP_COUNTER_TAG;
5713 break;
5714
5715 case ISM330BX_MLC_RESULT_TAG:
5716 val->tag = ISM330BX_MLC_RESULT_TAG;
5717 break;
5718
5719 case ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG:
5720 val->tag = ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG;
5721 break;
5722
5723 case ISM330BX_SFLP_GYROSCOPE_BIAS_TAG:
5724 val->tag = ISM330BX_SFLP_GYROSCOPE_BIAS_TAG;
5725 break;
5726
5727 case ISM330BX_SFLP_GRAVITY_VECTOR_TAG:
5728 val->tag = ISM330BX_SFLP_GRAVITY_VECTOR_TAG;
5729 break;
5730
5731 case ISM330BX_MLC_FILTER:
5732 val->tag = ISM330BX_MLC_FILTER;
5733 break;
5734
5735 case ISM330BX_MLC_FEATURE:
5736 val->tag = ISM330BX_MLC_FEATURE;
5737 break;
5738
5739 case ISM330BX_XL_DUAL_CORE:
5740 val->tag = ISM330BX_XL_DUAL_CORE;
5741 break;
5742
5743 case ISM330BX_AH_QVAR:
5744 val->tag = ISM330BX_AH_QVAR;
5745 break;
5746
5747 default:
5748 val->tag = ISM330BX_FIFO_EMPTY;
5749 break;
5750 }
5751
5752 val->cnt = fifo_data_out_tag.tag_cnt;
5753
5754 val->data[0] = buff[1];
5755 val->data[1] = buff[2];
5756 val->data[2] = buff[3];
5757 val->data[3] = buff[4];
5758 val->data[4] = buff[5];
5759 val->data[5] = buff[6];
5760
5761 return ret;
5762 }
5763
5764 /**
5765 * @brief Batching in FIFO buffer of step counter value.[set]
5766 *
5767 * @param ctx read / write interface definitions
5768 * @param val Batching in FIFO buffer of step counter value.
5769 * @retval interface status (MANDATORY: return 0 -> no Error)
5770 *
5771 */
ism330bx_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5772 int32_t ism330bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5773 {
5774 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5775 int32_t ret;
5776
5777 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5778 if (ret == 0)
5779 {
5780 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5781 }
5782
5783 if (ret == 0)
5784 {
5785 emb_func_fifo_en_a.step_counter_fifo_en = val;
5786 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5787 }
5788
5789 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5790
5791 return ret;
5792 }
5793
5794 /**
5795 * @brief Batching in FIFO buffer of step counter value.[get]
5796 *
5797 * @param ctx read / write interface definitions
5798 * @param val Batching in FIFO buffer of step counter value.
5799 * @retval interface status (MANDATORY: return 0 -> no Error)
5800 *
5801 */
ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5802 int32_t ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5803 {
5804 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5805 int32_t ret;
5806
5807 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5808 if (ret == 0)
5809 {
5810 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5811 }
5812
5813 *val = emb_func_fifo_en_a.step_counter_fifo_en;
5814
5815 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5816
5817
5818 return ret;
5819 }
5820
5821 /**
5822 * @brief Batching in FIFO buffer of machine learning core results.[set]
5823 *
5824 * @param ctx read / write interface definitions
5825 * @param val Batching in FIFO buffer of machine learning core results.
5826 * @retval interface status (MANDATORY: return 0 -> no Error)
5827 *
5828 */
ism330bx_fifo_mlc_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5829 int32_t ism330bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5830 {
5831 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5832 int32_t ret;
5833
5834 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5835 if (ret == 0)
5836 {
5837 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5838 }
5839
5840 if (ret == 0)
5841 {
5842 emb_func_fifo_en_a.mlc_fifo_en = val;
5843 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5844 }
5845
5846 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5847
5848 return ret;
5849 }
5850
5851 /**
5852 * @brief Batching in FIFO buffer of machine learning core results.[get]
5853 *
5854 * @param ctx read / write interface definitions
5855 * @param val Batching in FIFO buffer of machine learning core results.
5856 * @retval interface status (MANDATORY: return 0 -> no Error)
5857 *
5858 */
ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5859 int32_t ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5860 {
5861 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5862 int32_t ret;
5863
5864 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5865 if (ret == 0)
5866 {
5867 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5868 }
5869
5870 *val = emb_func_fifo_en_a.mlc_fifo_en;
5871
5872 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5873
5874 return ret;
5875 }
5876
5877 /**
5878 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
5879 *
5880 * @param ctx read / write interface definitions
5881 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5882 * @retval interface status (MANDATORY: return 0 -> no Error)
5883 *
5884 */
ism330bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5885 int32_t ism330bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5886 {
5887 ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5888 int32_t ret;
5889
5890 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5891 if (ret == 0)
5892 {
5893 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5894 }
5895
5896 if (ret == 0)
5897 {
5898 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
5899 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5900 }
5901
5902 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5903
5904 return ret;
5905 }
5906
5907 /**
5908 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
5909 *
5910 * @param ctx read / write interface definitions
5911 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5912 * @retval interface status (MANDATORY: return 0 -> no Error)
5913 *
5914 */
ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5915 int32_t ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5916 {
5917 ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5918 int32_t ret;
5919
5920 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5921 if (ret == 0)
5922 {
5923 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5924 }
5925
5926 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
5927
5928 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5929
5930 return ret;
5931 }
5932
5933 /**
5934 * @}
5935 *
5936 */
5937
5938 /**
5939 * @defgroup Step Counter
5940 * @brief This section groups all the functions that manage pedometer.
5941 * @{
5942 *
5943 */
5944
5945 /**
5946 * @brief Step counter mode[set]
5947 *
5948 * @param ctx read / write interface definitions
5949 * @param val false_step_rej, step_counter, step_detector,
5950 * @retval interface status (MANDATORY: return 0 -> no Error)
5951 *
5952 */
ism330bx_stpcnt_mode_set(const stmdev_ctx_t * ctx,ism330bx_stpcnt_mode_t val)5953 int32_t ism330bx_stpcnt_mode_set(const stmdev_ctx_t *ctx,
5954 ism330bx_stpcnt_mode_t val)
5955 {
5956 ism330bx_emb_func_en_a_t emb_func_en_a;
5957 ism330bx_emb_func_en_b_t emb_func_en_b;
5958 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
5959 int32_t ret;
5960
5961 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
5962 if (ret == 0)
5963 {
5964 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5965 }
5966 if (ret == 0)
5967 {
5968 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5969 }
5970 if ((val.false_step_rej == PROPERTY_ENABLE)
5971 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
5972 PROPERTY_DISABLE))
5973 {
5974 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
5975 }
5976 if (ret == 0)
5977 {
5978 emb_func_en_a.pedo_en = val.step_counter_enable;
5979 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5980 }
5981
5982 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
5983
5984 if (ret == 0)
5985 {
5986 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5987 }
5988 if (ret == 0)
5989 {
5990 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
5991 ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5992 }
5993
5994 return ret;
5995 }
5996
5997 /**
5998 * @brief Step counter mode[get]
5999 *
6000 * @param ctx read / write interface definitions
6001 * @param val false_step_rej, step_counter, step_detector,
6002 * @retval interface status (MANDATORY: return 0 -> no Error)
6003 *
6004 */
ism330bx_stpcnt_mode_get(const stmdev_ctx_t * ctx,ism330bx_stpcnt_mode_t * val)6005 int32_t ism330bx_stpcnt_mode_get(const stmdev_ctx_t *ctx,
6006 ism330bx_stpcnt_mode_t *val)
6007 {
6008 ism330bx_emb_func_en_a_t emb_func_en_a;
6009 ism330bx_pedo_cmd_reg_t pedo_cmd_reg;
6010 int32_t ret;
6011
6012 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6013 if (ret == 0)
6014 {
6015 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6016 }
6017
6018 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6019
6020 if (ret == 0)
6021 {
6022 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
6023 }
6024 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
6025 val->step_counter_enable = emb_func_en_a.pedo_en;
6026
6027 return ret;
6028 }
6029
6030 /**
6031 * @brief Step counter output, number of detected steps.[get]
6032 *
6033 * @param ctx read / write interface definitions
6034 * @param val Step counter output, number of detected steps.
6035 * @retval interface status (MANDATORY: return 0 -> no Error)
6036 *
6037 */
ism330bx_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)6038 int32_t ism330bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
6039 {
6040 uint8_t buff[2];
6041 int32_t ret;
6042
6043 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6044 if (ret == 0)
6045 {
6046 ret = ism330bx_read_reg(ctx, ISM330BX_STEP_COUNTER_L, &buff[0], 2);
6047 }
6048
6049 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6050
6051 *val = buff[1];
6052 *val = (*val * 256U) + buff[0];
6053
6054 return ret;
6055 }
6056
6057 /**
6058 * @brief Reset step counter.[set]
6059 *
6060 * @param ctx read / write interface definitions
6061 * @param val Reset step counter.
6062 * @retval interface status (MANDATORY: return 0 -> no Error)
6063 *
6064 */
ism330bx_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)6065 int32_t ism330bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
6066 {
6067 ism330bx_emb_func_src_t emb_func_src;
6068 int32_t ret;
6069
6070 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6071 if (ret == 0)
6072 {
6073 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6074 }
6075
6076 if (ret == 0)
6077 {
6078 emb_func_src.pedo_rst_step = val;
6079 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6080 }
6081
6082 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6083
6084 return ret;
6085 }
6086
6087 /**
6088 * @brief Reset step counter.[get]
6089 *
6090 * @param ctx read / write interface definitions
6091 * @param val Reset step counter.
6092 * @retval interface status (MANDATORY: return 0 -> no Error)
6093 *
6094 */
ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)6095 int32_t ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
6096 {
6097 ism330bx_emb_func_src_t emb_func_src;
6098 int32_t ret;
6099
6100 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6101 if (ret == 0)
6102 {
6103 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6104 }
6105
6106 *val = emb_func_src.pedo_rst_step;
6107
6108 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6109
6110 return ret;
6111 }
6112
6113 /**
6114 * @brief Pedometer debounce configuration.[set]
6115 *
6116 * @param ctx read / write interface definitions
6117 * @param val Pedometer debounce configuration.
6118 * @retval interface status (MANDATORY: return 0 -> no Error)
6119 *
6120 */
ism330bx_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)6121 int32_t ism330bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
6122 {
6123 ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6124 int32_t ret;
6125
6126 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6127 1);
6128 if (ret == 0)
6129 {
6130 pedo_deb_steps_conf.deb_step = val;
6131 ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6132 1);
6133 }
6134
6135 return ret;
6136 }
6137
6138 /**
6139 * @brief Pedometer debounce configuration.[get]
6140 *
6141 * @param ctx read / write interface definitions
6142 * @param val Pedometer debounce configuration.
6143 * @retval interface status (MANDATORY: return 0 -> no Error)
6144 *
6145 */
ism330bx_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)6146 int32_t ism330bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
6147 {
6148 ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6149 int32_t ret;
6150
6151 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6152 1);
6153 *val = pedo_deb_steps_conf.deb_step;
6154
6155 return ret;
6156 }
6157
6158 /**
6159 * @brief Time period register for step detection on delta time.[set]
6160 *
6161 * @param ctx read / write interface definitions
6162 * @param val Time period register for step detection on delta time.
6163 * @retval interface status (MANDATORY: return 0 -> no Error)
6164 *
6165 */
ism330bx_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)6166 int32_t ism330bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
6167 {
6168 uint8_t buff[2];
6169 int32_t ret;
6170
6171 buff[1] = (uint8_t)(val / 256U);
6172 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6173
6174 ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2);
6175
6176 return ret;
6177 }
6178
6179 /**
6180 * @brief Time period register for step detection on delta time.[get]
6181 *
6182 * @param ctx read / write interface definitions
6183 * @param val Time period register for step detection on delta time.
6184 * @retval interface status (MANDATORY: return 0 -> no Error)
6185 *
6186 */
ism330bx_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)6187 int32_t ism330bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
6188 {
6189 uint8_t buff[2];
6190 int32_t ret;
6191
6192 ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_SC_DELTAT_L, &buff[0], 2);
6193 *val = buff[1];
6194 *val = (*val * 256U) + buff[0];
6195
6196 return ret;
6197 }
6198
6199 /**
6200 * @}
6201 *
6202 */
6203
6204 /**
6205 * @defgroup Significant motion
6206 * @brief This section groups all the functions that manage the
6207 * significant motion detection.
6208 * @{
6209 *
6210 */
6211
6212 /**
6213 * @brief Enables significant motion detection function.[set]
6214 *
6215 * @param ctx read / write interface definitions
6216 * @param val Enables significant motion detection function.
6217 * @retval interface status (MANDATORY: return 0 -> no Error)
6218 *
6219 */
ism330bx_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6220 int32_t ism330bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6221 {
6222 ism330bx_emb_func_en_a_t emb_func_en_a;
6223 int32_t ret;
6224
6225 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6226 if (ret == 0)
6227 {
6228 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6229 }
6230 if (ret == 0)
6231 {
6232 emb_func_en_a.sign_motion_en = val;
6233 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6234 }
6235
6236 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6237
6238
6239 return ret;
6240 }
6241
6242 /**
6243 * @brief Enables significant motion detection function.[get]
6244 *
6245 * @param ctx read / write interface definitions
6246 * @param val Enables significant motion detection function.
6247 * @retval interface status (MANDATORY: return 0 -> no Error)
6248 *
6249 */
ism330bx_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6250 int32_t ism330bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6251 {
6252 ism330bx_emb_func_en_a_t emb_func_en_a;
6253 int32_t ret;
6254
6255 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6256 if (ret == 0)
6257 {
6258 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6259 }
6260 *val = emb_func_en_a.sign_motion_en;
6261
6262 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6263
6264
6265 return ret;
6266 }
6267
6268 /**
6269 * @}
6270 *
6271 */
6272
6273 /**
6274 * @defgroup Tilt detection
6275 * @brief This section groups all the functions that manage the tilt
6276 * event detection.
6277 * @{
6278 *
6279 */
6280
6281 /**
6282 * @brief Tilt calculation.[set]
6283 *
6284 * @param ctx read / write interface definitions
6285 * @param val Tilt calculation.
6286 * @retval interface status (MANDATORY: return 0 -> no Error)
6287 *
6288 */
ism330bx_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6289 int32_t ism330bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6290 {
6291 ism330bx_emb_func_en_a_t emb_func_en_a;
6292 int32_t ret;
6293
6294 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6295 if (ret == 0)
6296 {
6297 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6298 }
6299 if (ret == 0)
6300 {
6301 emb_func_en_a.tilt_en = val;
6302 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6303 }
6304
6305 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6306
6307 return ret;
6308 }
6309
6310 /**
6311 * @brief Tilt calculation.[get]
6312 *
6313 * @param ctx read / write interface definitions
6314 * @param val Tilt calculation.
6315 * @retval interface status (MANDATORY: return 0 -> no Error)
6316 *
6317 */
ism330bx_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6318 int32_t ism330bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6319 {
6320 ism330bx_emb_func_en_a_t emb_func_en_a;
6321 int32_t ret;
6322
6323 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6324 if (ret == 0)
6325 {
6326 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6327 }
6328 *val = emb_func_en_a.tilt_en;
6329
6330 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6331
6332 return ret;
6333 }
6334
6335 /**
6336 * @}
6337 *
6338 */
6339
6340 /**
6341 * @defgroup Sensor Fusion Low Power (SFLP)
6342 * @brief This section groups all the functions that manage pedometer.
6343 * @{
6344 *
6345 */
6346
6347 /**
6348 * @brief Enable SFLP Game Rotation Vector (6x).[set]
6349 *
6350 * @param ctx read / write interface definitions
6351 * @param val Enable/Disable game rotation value (0/1).
6352 * @retval interface status (MANDATORY: return 0 -> no Error)
6353 *
6354 */
ism330bx_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint16_t val)6355 int32_t ism330bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val)
6356 {
6357 ism330bx_emb_func_en_a_t emb_func_en_a;
6358 int32_t ret;
6359
6360 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6361 if (ret == 0)
6362 {
6363 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6364 emb_func_en_a.sflp_game_en = val;
6365 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A,
6366 (uint8_t *)&emb_func_en_a, 1);
6367 }
6368
6369 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6370
6371 return ret;
6372 }
6373
6374 /**
6375 * @brief Enable SFLP Game Rotation Vector (6x).[get]
6376 *
6377 * @param ctx read / write interface definitions
6378 * @param val Enable/Disable game rotation value (0/1).
6379 * @retval interface status (MANDATORY: return 0 -> no Error)
6380 *
6381 */
ism330bx_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint16_t * val)6382 int32_t ism330bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val)
6383 {
6384 ism330bx_emb_func_en_a_t emb_func_en_a;
6385 int32_t ret;
6386
6387 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6388 if (ret == 0)
6389 {
6390 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6391 *val = emb_func_en_a.sflp_game_en;
6392 }
6393
6394 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6395
6396 return ret;
6397 }
6398
6399 /**
6400 * @brief SFLP Data Rate (ODR) configuration.[set]
6401 *
6402 * @param ctx read / write interface definitions
6403 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6404 * @retval interface status (MANDATORY: return 0 -> no Error)
6405 *
6406 */
ism330bx_sflp_data_rate_set(const stmdev_ctx_t * ctx,ism330bx_sflp_data_rate_t val)6407 int32_t ism330bx_sflp_data_rate_set(const stmdev_ctx_t *ctx,
6408 ism330bx_sflp_data_rate_t val)
6409 {
6410 ism330bx_sflp_odr_t sflp_odr;
6411 int32_t ret;
6412
6413 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6414 if (ret == 0)
6415 {
6416 ret = ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6417 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
6418 ret += ism330bx_write_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr,
6419 1);
6420 }
6421
6422 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6423
6424 return ret;
6425 }
6426
6427 /**
6428 * @brief SFLP Data Rate (ODR) configuration.[get]
6429 *
6430 * @param ctx read / write interface definitions
6431 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6432 * @retval interface status (MANDATORY: return 0 -> no Error)
6433 *
6434 */
ism330bx_sflp_data_rate_get(const stmdev_ctx_t * ctx,ism330bx_sflp_data_rate_t * val)6435 int32_t ism330bx_sflp_data_rate_get(const stmdev_ctx_t *ctx,
6436 ism330bx_sflp_data_rate_t *val)
6437 {
6438 ism330bx_sflp_odr_t sflp_odr;
6439 int32_t ret;
6440
6441 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6442 ret += ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6443 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6444
6445 switch (sflp_odr.sflp_game_odr)
6446 {
6447 case ISM330BX_SFLP_15Hz:
6448 *val = ISM330BX_SFLP_15Hz;
6449 break;
6450
6451 case ISM330BX_SFLP_30Hz:
6452 *val = ISM330BX_SFLP_30Hz;
6453 break;
6454
6455 case ISM330BX_SFLP_60Hz:
6456 *val = ISM330BX_SFLP_60Hz;
6457 break;
6458
6459 case ISM330BX_SFLP_120Hz:
6460 *val = ISM330BX_SFLP_120Hz;
6461 break;
6462
6463 case ISM330BX_SFLP_240Hz:
6464 *val = ISM330BX_SFLP_240Hz;
6465 break;
6466
6467 case ISM330BX_SFLP_480Hz:
6468 *val = ISM330BX_SFLP_480Hz;
6469 break;
6470
6471 default:
6472 *val = ISM330BX_SFLP_15Hz;
6473 break;
6474 }
6475 return ret;
6476 }
6477
6478 /*
6479 * Original conversion routines taken from: https://github.com/numpy/numpy
6480 *
6481 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6482 * uint16_t npy_float_to_half(float_t f);
6483 *
6484 * Released under BSD-3-Clause License
6485 */
6486
6487 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6488 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6489 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6490 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6491 #endif
6492
npy_floatbits_to_halfbits(uint32_t f)6493 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6494 {
6495 uint32_t f_exp, f_sig;
6496 uint16_t h_sgn, h_exp, h_sig;
6497
6498 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6499 f_exp = (f & 0x7f800000u);
6500
6501 /* Exponent overflow/NaN converts to signed inf/NaN */
6502 if (f_exp >= 0x47800000u)
6503 {
6504 if (f_exp == 0x7f800000u)
6505 {
6506 /* Inf or NaN */
6507 f_sig = (f & 0x007fffffu);
6508 if (f_sig != 0)
6509 {
6510 /* NaN - propagate the flag in the significand... */
6511 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6512 /* ...but make sure it stays a NaN */
6513 if (ret == 0x7c00u)
6514 {
6515 ret++;
6516 }
6517 return h_sgn + ret;
6518 }
6519 else
6520 {
6521 /* signed inf */
6522 return (uint16_t)(h_sgn + 0x7c00u);
6523 }
6524 }
6525 else
6526 {
6527 /* overflow to signed inf */
6528 #if NPY_HALF_GENERATE_OVERFLOW
6529 npy_set_floatstatus_overflow();
6530 #endif
6531 return (uint16_t)(h_sgn + 0x7c00u);
6532 }
6533 }
6534
6535 /* Exponent underflow converts to a subnormal half or signed zero */
6536 if (f_exp <= 0x38000000u)
6537 {
6538 /*
6539 * Signed zeros, subnormal floats, and floats with small
6540 * exponents all convert to signed zero half-floats.
6541 */
6542 if (f_exp < 0x33000000u)
6543 {
6544 #if NPY_HALF_GENERATE_UNDERFLOW
6545 /* If f != 0, it underflowed to 0 */
6546 if ((f & 0x7fffffff) != 0)
6547 {
6548 npy_set_floatstatus_underflow();
6549 }
6550 #endif
6551 return h_sgn;
6552 }
6553 /* Make the subnormal significand */
6554 f_exp >>= 23;
6555 f_sig = (0x00800000u + (f & 0x007fffffu));
6556 #if NPY_HALF_GENERATE_UNDERFLOW
6557 /* If it's not exactly represented, it underflowed */
6558 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6559 {
6560 npy_set_floatstatus_underflow();
6561 }
6562 #endif
6563 /*
6564 * Usually the significand is shifted by 13. For subnormals an
6565 * additional shift needs to occur. This shift is one for the largest
6566 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6567 * offsets the new first bit. At most the shift can be 1+10 bits.
6568 */
6569 f_sig >>= (113 - f_exp);
6570 /* Handle rounding by adding 1 to the bit beyond half precision */
6571 #if NPY_HALF_ROUND_TIES_TO_EVEN
6572 /*
6573 * If the last bit in the half significand is 0 (already even), and
6574 * the remaining bit pattern is 1000...0, then we do not add one
6575 * to the bit after the half significand. However, the (113 - f_exp)
6576 * shift can lose up to 11 bits, so the || checks them in the original.
6577 * In all other cases, we can just add one.
6578 */
6579 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6580 {
6581 f_sig += 0x00001000u;
6582 }
6583 #else
6584 f_sig += 0x00001000u;
6585 #endif
6586 h_sig = (uint16_t)(f_sig >> 13);
6587 /*
6588 * If the rounding causes a bit to spill into h_exp, it will
6589 * increment h_exp from zero to one and h_sig will be zero.
6590 * This is the correct result.
6591 */
6592 return (uint16_t)(h_sgn + h_sig);
6593 }
6594
6595 /* Regular case with no overflow or underflow */
6596 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6597 /* Handle rounding by adding 1 to the bit beyond half precision */
6598 f_sig = (f & 0x007fffffu);
6599 #if NPY_HALF_ROUND_TIES_TO_EVEN
6600 /*
6601 * If the last bit in the half significand is 0 (already even), and
6602 * the remaining bit pattern is 1000...0, then we do not add one
6603 * to the bit after the half significand. In all other cases, we do.
6604 */
6605 if ((f_sig & 0x00003fffu) != 0x00001000u)
6606 {
6607 f_sig += 0x00001000u;
6608 }
6609 #else
6610 f_sig += 0x00001000u;
6611 #endif
6612 h_sig = (uint16_t)(f_sig >> 13);
6613 /*
6614 * If the rounding causes a bit to spill into h_exp, it will
6615 * increment h_exp by one and h_sig will be zero. This is the
6616 * correct result. h_exp may increment to 15, at greatest, in
6617 * which case the result overflows to a signed inf.
6618 */
6619 #if NPY_HALF_GENERATE_OVERFLOW
6620 h_sig += h_exp;
6621 if (h_sig == 0x7c00u)
6622 {
6623 npy_set_floatstatus_overflow();
6624 }
6625 return h_sgn + h_sig;
6626 #else
6627 return h_sgn + h_exp + h_sig;
6628 #endif
6629 }
6630
npy_float_to_half(float_t f)6631 static uint16_t npy_float_to_half(float_t f)
6632 {
6633 union
6634 {
6635 float_t f;
6636 uint32_t fbits;
6637 } conv;
6638 conv.f = f;
6639 return npy_floatbits_to_halfbits(conv.fbits);
6640 }
6641
6642 /**
6643 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6644 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6645 * bits; F: 10 fraction bits).[set]
6646 *
6647 * @param ctx read / write interface definitions
6648 * @param val GBIAS x/y/z val.
6649 * @retval interface status (MANDATORY: return 0 -> no Error)
6650 *
6651 */
ism330bx_sflp_game_gbias_set(const stmdev_ctx_t * ctx,ism330bx_sflp_gbias_t * val)6652 int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6653 ism330bx_sflp_gbias_t *val)
6654 {
6655 ism330bx_sflp_data_rate_t sflp_odr;
6656 ism330bx_emb_func_exec_status_t emb_func_sts;
6657 ism330bx_data_ready_t drdy;
6658 ism330bx_xl_full_scale_t xl_fs;
6659 ism330bx_ctrl10_t ctrl10;
6660 uint8_t master_config;
6661 uint8_t emb_func_en_saved[2];
6662 uint8_t conf_saved[2];
6663 uint8_t reg_zero[2] = {0x0, 0x0};
6664 uint16_t gbias_hf[3];
6665 float_t k = 0.005f;
6666 int16_t xl_data[3];
6667 int32_t data_tmp;
6668 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6669 uint8_t i, j;
6670 int32_t ret;
6671
6672 ret = ism330bx_sflp_data_rate_get(ctx, &sflp_odr);
6673 if (ret != 0)
6674 {
6675 return ret;
6676 }
6677
6678 /* Calculate k factor */
6679 switch (sflp_odr)
6680 {
6681 case ISM330BX_SFLP_15Hz:
6682 k = 0.04f;
6683 break;
6684 case ISM330BX_SFLP_30Hz:
6685 k = 0.02f;
6686 break;
6687 case ISM330BX_SFLP_60Hz:
6688 k = 0.01f;
6689 break;
6690 case ISM330BX_SFLP_120Hz:
6691 k = 0.005f;
6692 break;
6693 case ISM330BX_SFLP_240Hz:
6694 k = 0.0025f;
6695 break;
6696 case ISM330BX_SFLP_480Hz:
6697 k = 0.00125f;
6698 break;
6699 }
6700
6701 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6702 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6703 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6704 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6705
6706 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6707 ret += ism330bx_read_reg(ctx, ISM330BX_CTRL1, conf_saved, 2);
6708 ret += ism330bx_xl_mode_set(ctx, ISM330BX_XL_HIGH_PERFORMANCE_MD);
6709 ret += ism330bx_gy_mode_set(ctx, ISM330BX_GY_HIGH_PERFORMANCE_MD);
6710 if ((conf_saved[0] & 0x0FU) == ISM330BX_XL_ODR_OFF)
6711 {
6712 ret += ism330bx_xl_data_rate_set(ctx, ISM330BX_XL_ODR_AT_120Hz);
6713 }
6714
6715 /* disable algos */
6716 ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6717 ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved,
6718 2);
6719 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, reg_zero, 2);
6720 do
6721 {
6722 ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS,
6723 (uint8_t *)&emb_func_sts, 1);
6724 } while (emb_func_sts.emb_func_endop != 1);
6725 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6726
6727 // enable gbias setting
6728 ret += ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
6729 ctrl10.emb_func_debug = 1;
6730 ret += ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
6731
6732 /* enable algos */
6733 ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6734 emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */
6735 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved,
6736 2);
6737 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6738
6739 ret += ism330bx_xl_full_scale_get(ctx, &xl_fs);
6740
6741 /* Read XL data */
6742 do
6743 {
6744 ret += ism330bx_flag_data_ready_get(ctx, &drdy);
6745 } while (drdy.drdy_xl != 1);
6746 ret += ism330bx_acceleration_raw_get(ctx, xl_data);
6747
6748 /* force sflp initialization */
6749 master_config = 0x40;
6750 ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config,
6751 1);
6752 for (i = 0; i < 3; i++)
6753 {
6754 j = 0;
6755 data_tmp = (int32_t)xl_data[i];
6756 data_tmp <<= xl_fs; // shift based on current fs
6757 ret += ism330bx_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1);
6758 ret += ism330bx_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1);
6759 ret += ism330bx_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1);
6760 }
6761 for (i = 0; i < 3; i++)
6762 {
6763 j = 0;
6764 data_tmp = 0;
6765 ret += ism330bx_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1);
6766 ret += ism330bx_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1);
6767 ret += ism330bx_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1);
6768 }
6769 master_config = 0x00;
6770 ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config,
6771 1);
6772
6773 // wait end_op (and at least 30 us)
6774 ctx->mdelay(1);
6775 ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6776 do
6777 {
6778 ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS,
6779 (uint8_t *)&emb_func_sts, 1);
6780 } while (emb_func_sts.emb_func_endop != 1);
6781 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6782
6783 /* write gbias in embedded advanced features registers */
6784 ret += ism330bx_ln_pg_write(ctx, ISM330BX_SFLP_GAME_GBIASX_L,
6785 (uint8_t *)gbias_hf, 6);
6786
6787 /* reload previous sensor configuration */
6788 ret += ism330bx_write_reg(ctx, ISM330BX_CTRL1, conf_saved, 2);
6789
6790 // disable gbias setting
6791 ctrl10.emb_func_debug = 0;
6792 ret += ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
6793
6794 return ret;
6795 }
6796
6797 /**
6798 * @brief SFLP initial configuration [set]
6799 *
6800 * @param ctx read / write interface definitions
6801 * @retval interface status (MANDATORY: return 0 -> no Error)
6802 *
6803 */
ism330bx_sflp_configure(const stmdev_ctx_t * ctx)6804 int32_t ism330bx_sflp_configure(const stmdev_ctx_t *ctx)
6805 {
6806 uint8_t val = 0x50;
6807 int32_t ret;
6808
6809 ret = ism330bx_ln_pg_write(ctx, 0xD2, &val, 1);
6810
6811 return ret;
6812 }
6813
6814 /**
6815 * @}
6816 *
6817 */
6818
6819 /**
6820 * @defgroup Finite State Machine (FSM)
6821 * @brief This section groups all the functions that manage the
6822 * state_machine.
6823 * @{
6824 *
6825 */
6826
6827 /**
6828 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
6829 *
6830 * @param ctx read / write interface definitions
6831 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6832 * @retval interface status (MANDATORY: return 0 -> no Error)
6833 *
6834 */
ism330bx_fsm_permission_set(const stmdev_ctx_t * ctx,ism330bx_fsm_permission_t val)6835 int32_t ism330bx_fsm_permission_set(const stmdev_ctx_t *ctx,
6836 ism330bx_fsm_permission_t val)
6837 {
6838 ism330bx_func_cfg_access_t func_cfg_access;
6839 int32_t ret;
6840
6841 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6842 if (ret == 0)
6843 {
6844 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
6845 ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6846 }
6847
6848 return ret;
6849 }
6850
6851 /**
6852 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
6853 *
6854 * @param ctx read / write interface definitions
6855 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6856 * @retval interface status (MANDATORY: return 0 -> no Error)
6857 *
6858 */
ism330bx_fsm_permission_get(const stmdev_ctx_t * ctx,ism330bx_fsm_permission_t * val)6859 int32_t ism330bx_fsm_permission_get(const stmdev_ctx_t *ctx,
6860 ism330bx_fsm_permission_t *val)
6861 {
6862 ism330bx_func_cfg_access_t func_cfg_access;
6863 int32_t ret;
6864
6865 ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6866 switch (func_cfg_access.fsm_wr_ctrl_en)
6867 {
6868 case ISM330BX_PROTECT_CTRL_REGS:
6869 *val = ISM330BX_PROTECT_CTRL_REGS;
6870 break;
6871
6872 case ISM330BX_WRITE_CTRL_REG:
6873 *val = ISM330BX_WRITE_CTRL_REG;
6874 break;
6875
6876 default:
6877 *val = ISM330BX_PROTECT_CTRL_REGS;
6878 break;
6879 }
6880 return ret;
6881 }
6882
6883 /**
6884 * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get]
6885 *
6886 * @param ctx read / write interface definitions
6887 * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control.
6888 * @retval interface status (MANDATORY: return 0 -> no Error)
6889 *
6890 */
ism330bx_fsm_permission_status(const stmdev_ctx_t * ctx,ism330bx_fsm_permission_status_t * val)6891 int32_t ism330bx_fsm_permission_status(const stmdev_ctx_t *ctx,
6892 ism330bx_fsm_permission_status_t *val)
6893 {
6894 ism330bx_ctrl_status_t status;
6895 int32_t ret;
6896
6897 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL_STATUS, (uint8_t *)&status, 1);
6898 *val = (status.fsm_wr_ctrl_status == 0) ? ISM330BX_STD_IF_CONTROL : ISM330BX_FSM_CONTROL;
6899
6900 return ret;
6901 }
6902
6903 /**
6904 * @brief Enable Finite State Machine (FSM) feature.[set]
6905 *
6906 * @param ctx read / write interface definitions
6907 * @param val Enable Finite State Machine (FSM) feature.
6908 * @retval interface status (MANDATORY: return 0 -> no Error)
6909 *
6910 */
ism330bx_fsm_mode_set(const stmdev_ctx_t * ctx,ism330bx_fsm_mode_t val)6911 int32_t ism330bx_fsm_mode_set(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t val)
6912 {
6913 ism330bx_emb_func_en_b_t emb_func_en_b;
6914 ism330bx_fsm_enable_t fsm_enable;
6915 int32_t ret;
6916
6917 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6918 if (ret == 0)
6919 {
6920 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6921 }
6922 if (ret == 0)
6923 {
6924 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6925 }
6926 if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en
6927 | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE)
6928 {
6929 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6930 }
6931 else
6932 {
6933 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6934 }
6935 if (ret == 0)
6936 {
6937 fsm_enable.fsm1_en = val.fsm1_en;
6938 fsm_enable.fsm2_en = val.fsm2_en;
6939 fsm_enable.fsm3_en = val.fsm3_en;
6940 fsm_enable.fsm4_en = val.fsm4_en;
6941 fsm_enable.fsm5_en = val.fsm5_en;
6942 fsm_enable.fsm6_en = val.fsm6_en;
6943 fsm_enable.fsm7_en = val.fsm7_en;
6944 fsm_enable.fsm8_en = val.fsm8_en;
6945 ret = ism330bx_write_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6946 }
6947 if (ret == 0)
6948 {
6949 ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6950 }
6951
6952 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6953
6954 return ret;
6955 }
6956
6957 /**
6958 * @brief Enable Finite State Machine (FSM) feature.[get]
6959 *
6960 * @param ctx read / write interface definitions
6961 * @param val Enable Finite State Machine (FSM) feature.
6962 * @retval interface status (MANDATORY: return 0 -> no Error)
6963 *
6964 */
ism330bx_fsm_mode_get(const stmdev_ctx_t * ctx,ism330bx_fsm_mode_t * val)6965 int32_t ism330bx_fsm_mode_get(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t *val)
6966 {
6967 ism330bx_fsm_enable_t fsm_enable;
6968 int32_t ret;
6969
6970 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
6971 if (ret == 0)
6972 {
6973 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6974 }
6975
6976 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
6977
6978 val->fsm1_en = fsm_enable.fsm1_en;
6979 val->fsm2_en = fsm_enable.fsm2_en;
6980 val->fsm3_en = fsm_enable.fsm3_en;
6981 val->fsm4_en = fsm_enable.fsm4_en;
6982 val->fsm5_en = fsm_enable.fsm5_en;
6983 val->fsm6_en = fsm_enable.fsm6_en;
6984 val->fsm7_en = fsm_enable.fsm7_en;
6985 val->fsm8_en = fsm_enable.fsm8_en;
6986
6987 return ret;
6988 }
6989
6990 /**
6991 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
6992 *
6993 * @param ctx read / write interface definitions
6994 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6995 * @retval interface status (MANDATORY: return 0 -> no Error)
6996 *
6997 */
ism330bx_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6998 int32_t ism330bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6999 {
7000 uint8_t buff[2];
7001 int32_t ret;
7002
7003 buff[1] = (uint8_t)(val / 256U);
7004 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7005
7006 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7007 if (ret == 0)
7008 {
7009 ret = ism330bx_write_reg(ctx, ISM330BX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
7010 }
7011
7012 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7013
7014 return ret;
7015 }
7016
7017 /**
7018 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
7019 *
7020 * @param ctx read / write interface definitions
7021 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
7022 * @retval interface status (MANDATORY: return 0 -> no Error)
7023 *
7024 */
ism330bx_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)7025 int32_t ism330bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
7026 {
7027 uint8_t buff[2];
7028 int32_t ret;
7029
7030 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7031 if (ret == 0)
7032 {
7033 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_LONG_COUNTER_L, &buff[0], 2);
7034 }
7035
7036 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7037
7038 *val = buff[1];
7039 *val = (*val * 256U) + buff[0];
7040
7041 return ret;
7042 }
7043
7044 /**
7045 * @brief FSM output registers[get]
7046 *
7047 * @param ctx read / write interface definitions
7048 * @param val FSM output registers
7049 * @retval interface status (MANDATORY: return 0 -> no Error)
7050 *
7051 */
ism330bx_fsm_out_get(const stmdev_ctx_t * ctx,ism330bx_fsm_out_t * val)7052 int32_t ism330bx_fsm_out_get(const stmdev_ctx_t *ctx, ism330bx_fsm_out_t *val)
7053 {
7054 int32_t ret;
7055
7056 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7057 if (ret == 0)
7058 {
7059 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_OUTS1, (uint8_t *)val, 8);
7060 }
7061
7062 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7063
7064 return ret;
7065 }
7066
7067 /**
7068 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
7069 *
7070 * @param ctx read / write interface definitions
7071 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7072 * @retval interface status (MANDATORY: return 0 -> no Error)
7073 *
7074 */
ism330bx_fsm_data_rate_set(const stmdev_ctx_t * ctx,ism330bx_fsm_data_rate_t val)7075 int32_t ism330bx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
7076 ism330bx_fsm_data_rate_t val)
7077 {
7078 ism330bx_fsm_odr_t fsm_odr;
7079 int32_t ret;
7080
7081 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7082 if (ret == 0)
7083 {
7084 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7085 }
7086
7087 if (ret == 0)
7088 {
7089 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
7090 ret = ism330bx_write_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7091 }
7092
7093 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7094
7095 return ret;
7096 }
7097
7098 /**
7099 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
7100 *
7101 * @param ctx read / write interface definitions
7102 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7103 * @retval interface status (MANDATORY: return 0 -> no Error)
7104 *
7105 */
ism330bx_fsm_data_rate_get(const stmdev_ctx_t * ctx,ism330bx_fsm_data_rate_t * val)7106 int32_t ism330bx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
7107 ism330bx_fsm_data_rate_t *val)
7108 {
7109 ism330bx_fsm_odr_t fsm_odr;
7110 int32_t ret;
7111
7112 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7113 if (ret == 0)
7114 {
7115 ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7116 }
7117
7118 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7119
7120 switch (fsm_odr.fsm_odr)
7121 {
7122 case ISM330BX_FSM_15Hz:
7123 *val = ISM330BX_FSM_15Hz;
7124 break;
7125
7126 case ISM330BX_FSM_30Hz:
7127 *val = ISM330BX_FSM_30Hz;
7128 break;
7129
7130 case ISM330BX_FSM_60Hz:
7131 *val = ISM330BX_FSM_60Hz;
7132 break;
7133
7134 case ISM330BX_FSM_120Hz:
7135 *val = ISM330BX_FSM_120Hz;
7136 break;
7137
7138 case ISM330BX_FSM_240Hz:
7139 *val = ISM330BX_FSM_240Hz;
7140 break;
7141
7142 case ISM330BX_FSM_480Hz:
7143 *val = ISM330BX_FSM_480Hz;
7144 break;
7145
7146 case ISM330BX_FSM_960Hz:
7147 *val = ISM330BX_FSM_960Hz;
7148 break;
7149
7150 default:
7151 *val = ISM330BX_FSM_15Hz;
7152 break;
7153 }
7154 return ret;
7155 }
7156
7157 /**
7158 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
7159 *
7160 * @param ctx read / write interface definitions
7161 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7162 * @retval interface status (MANDATORY: return 0 -> no Error)
7163 *
7164 */
ism330bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)7165 int32_t ism330bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
7166 {
7167 uint8_t buff[2];
7168 int32_t ret;
7169
7170 buff[1] = (uint8_t)(val / 256U);
7171 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7172 ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2);
7173
7174 return ret;
7175 }
7176
7177 /**
7178 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
7179 *
7180 * @param ctx read / write interface definitions
7181 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7182 * @retval interface status (MANDATORY: return 0 -> no Error)
7183 *
7184 */
ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)7185 int32_t ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
7186 {
7187 uint8_t buff[2];
7188 int32_t ret;
7189
7190 ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_LC_TIMEOUT_L, &buff[0], 2);
7191 *val = buff[1];
7192 *val = (*val * 256U) + buff[0];
7193
7194 return ret;
7195 }
7196
7197 /**
7198 * @brief FSM number of programs.[set]
7199 *
7200 * @param ctx read / write interface definitions
7201 * @param val FSM number of programs.
7202 * @retval interface status (MANDATORY: return 0 -> no Error)
7203 *
7204 */
ism330bx_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)7205 int32_t ism330bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
7206 {
7207 ism330bx_fsm_programs_t fsm_programs;
7208 int32_t ret;
7209
7210 ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7211 if (ret == 0)
7212 {
7213 fsm_programs.fsm_n_prog = val;
7214 ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7215 }
7216
7217 return ret;
7218 }
7219
7220 /**
7221 * @brief FSM number of programs.[get]
7222 *
7223 * @param ctx read / write interface definitions
7224 * @param val FSM number of programs.
7225 * @retval interface status (MANDATORY: return 0 -> no Error)
7226 *
7227 */
ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)7228 int32_t ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
7229 {
7230 ism330bx_fsm_programs_t fsm_programs;
7231 int32_t ret;
7232
7233 ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7234 *val = fsm_programs.fsm_n_prog;
7235
7236
7237 return ret;
7238 }
7239
7240 /**
7241 * @brief FSM start address. First available address is 0x35C.[set]
7242 *
7243 * @param ctx read / write interface definitions
7244 * @param val FSM start address. First available address is 0x35C.
7245 * @retval interface status (MANDATORY: return 0 -> no Error)
7246 *
7247 */
ism330bx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7248 int32_t ism330bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7249 {
7250 uint8_t buff[2];
7251 int32_t ret;
7252
7253 buff[1] = (uint8_t)(val / 256U);
7254 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7255 ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2);
7256
7257 return ret;
7258 }
7259
7260 /**
7261 * @brief FSM start address. First available address is 0x35C.[get]
7262 *
7263 * @param ctx read / write interface definitions
7264 * @param val FSM start address. First available address is 0x35C.
7265 * @retval interface status (MANDATORY: return 0 -> no Error)
7266 *
7267 */
ism330bx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7268 int32_t ism330bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7269 {
7270 uint8_t buff[2];
7271 int32_t ret;
7272
7273 ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_START_ADD_L, &buff[0], 2);
7274 *val = buff[1];
7275 *val = (*val * 256U) + buff[0];
7276
7277 return ret;
7278 }
7279
7280 /**
7281 * @}
7282 *
7283 */
7284
7285 /**
7286 * @addtogroup Machine Learning Core
7287 * @brief This section group all the functions concerning the
7288 * usage of Machine Learning Core
7289 * @{
7290 *
7291 */
7292
7293 /**
7294 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set]
7295 *
7296 * @param ctx read / write interface definitions
7297 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7298 * @retval interface status (MANDATORY: return 0 -> no Error)
7299 *
7300 */
ism330bx_mlc_set(const stmdev_ctx_t * ctx,ism330bx_mlc_mode_t val)7301 int32_t ism330bx_mlc_set(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t val)
7302 {
7303 ism330bx_emb_func_en_b_t emb_en_b;
7304 ism330bx_emb_func_en_a_t emb_en_a;
7305 int32_t ret;
7306
7307 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7308
7309 if (ret == 0)
7310 {
7311 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7312 ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7313
7314 switch (val)
7315 {
7316 case ISM330BX_MLC_OFF:
7317 emb_en_a.mlc_before_fsm_en = 0;
7318 emb_en_b.mlc_en = 0;
7319 break;
7320 case ISM330BX_MLC_ON:
7321 emb_en_a.mlc_before_fsm_en = 0;
7322 emb_en_b.mlc_en = 1;
7323 break;
7324 case ISM330BX_MLC_ON_BEFORE_FSM:
7325 emb_en_a.mlc_before_fsm_en = 1;
7326 emb_en_b.mlc_en = 0;
7327 break;
7328 default:
7329 break;
7330 }
7331
7332 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7333 ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7334 }
7335
7336 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7337
7338 return ret;
7339 }
7340
7341 /**
7342 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get]
7343 *
7344 * @param ctx read / write interface definitions
7345 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7346 * @retval interface status (MANDATORY: return 0 -> no Error)
7347 *
7348 */
ism330bx_mlc_get(const stmdev_ctx_t * ctx,ism330bx_mlc_mode_t * val)7349 int32_t ism330bx_mlc_get(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t *val)
7350 {
7351 ism330bx_emb_func_en_b_t emb_en_b;
7352 ism330bx_emb_func_en_a_t emb_en_a;
7353 int32_t ret;
7354
7355 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7356
7357 if (ret == 0)
7358 {
7359 ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7360 ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7361
7362 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
7363 {
7364 *val = ISM330BX_MLC_OFF;
7365 }
7366 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
7367 {
7368 *val = ISM330BX_MLC_ON;
7369 }
7370 else if (emb_en_a.mlc_before_fsm_en == 1U)
7371 {
7372 *val = ISM330BX_MLC_ON_BEFORE_FSM;
7373 }
7374 else
7375 {
7376 /* Do nothing */
7377 }
7378 }
7379
7380 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7381
7382 return ret;
7383 }
7384
7385 /**
7386 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
7387 *
7388 * @param ctx read / write interface definitions
7389 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7390 * @retval interface status (MANDATORY: return 0 -> no Error)
7391 *
7392 */
ism330bx_mlc_data_rate_set(const stmdev_ctx_t * ctx,ism330bx_mlc_data_rate_t val)7393 int32_t ism330bx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7394 ism330bx_mlc_data_rate_t val)
7395 {
7396 ism330bx_mlc_odr_t mlc_odr;
7397 int32_t ret;
7398
7399 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7400 if (ret == 0)
7401 {
7402 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7403 }
7404
7405 if (ret == 0)
7406 {
7407 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
7408 ret = ism330bx_write_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7409 }
7410
7411 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7412
7413 return ret;
7414 }
7415
7416 /**
7417 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
7418 *
7419 * @param ctx read / write interface definitions
7420 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7421 * @retval interface status (MANDATORY: return 0 -> no Error)
7422 *
7423 */
ism330bx_mlc_data_rate_get(const stmdev_ctx_t * ctx,ism330bx_mlc_data_rate_t * val)7424 int32_t ism330bx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7425 ism330bx_mlc_data_rate_t *val)
7426 {
7427 ism330bx_mlc_odr_t mlc_odr;
7428 int32_t ret;
7429
7430 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7431 if (ret == 0)
7432 {
7433 ret = ism330bx_read_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7434 }
7435
7436 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7437
7438 switch (mlc_odr.mlc_odr)
7439 {
7440 case ISM330BX_MLC_15Hz:
7441 *val = ISM330BX_MLC_15Hz;
7442 break;
7443
7444 case ISM330BX_MLC_30Hz:
7445 *val = ISM330BX_MLC_30Hz;
7446 break;
7447
7448 case ISM330BX_MLC_60Hz:
7449 *val = ISM330BX_MLC_60Hz;
7450 break;
7451
7452 case ISM330BX_MLC_120Hz:
7453 *val = ISM330BX_MLC_120Hz;
7454 break;
7455
7456 case ISM330BX_MLC_240Hz:
7457 *val = ISM330BX_MLC_240Hz;
7458 break;
7459
7460 case ISM330BX_MLC_480Hz:
7461 *val = ISM330BX_MLC_480Hz;
7462 break;
7463
7464 case ISM330BX_MLC_960Hz:
7465 *val = ISM330BX_MLC_960Hz;
7466 break;
7467
7468 default:
7469 *val = ISM330BX_MLC_15Hz;
7470 break;
7471 }
7472 return ret;
7473 }
7474
7475 /**
7476 * @brief Output value of all MLC decision trees.[get]
7477 *
7478 * @param ctx read / write interface definitions
7479 * @param val Output value of all MLC decision trees.
7480 * @retval interface status (MANDATORY: return 0 -> no Error)
7481 *
7482 */
ism330bx_mlc_out_get(const stmdev_ctx_t * ctx,ism330bx_mlc_out_t * val)7483 int32_t ism330bx_mlc_out_get(const stmdev_ctx_t *ctx, ism330bx_mlc_out_t *val)
7484 {
7485 int32_t ret;
7486
7487 ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK);
7488 if (ret == 0)
7489 {
7490 ret = ism330bx_read_reg(ctx, ISM330BX_MLC1_SRC, (uint8_t *)val, 4);
7491 }
7492
7493 ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK);
7494 return ret;
7495 }
7496
7497 /**
7498 * @brief Qvar sensor sensitivity value register for the Machine Learning Core.
7499 * This register corresponds to the conversion value of the Qvar sensor.
7500 * The register value is expressed as half-precision floating-point format:
7501 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7502 *
7503 * @param ctx read / write interface definitions
7504 * @param val Qvar sensor sensitivity value register for the Machine Learning Core.
7505 * @retval interface status (MANDATORY: return 0 -> no Error)
7506 *
7507 */
ism330bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7508 int32_t ism330bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7509 {
7510 uint8_t buff[2];
7511 int32_t ret;
7512
7513 buff[1] = (uint8_t)(val / 256U);
7514 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7515 ret = ism330bx_ln_pg_write(ctx, ISM330BX_MLC_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7516
7517 return ret;
7518 }
7519
7520 /**
7521 * @brief Qvar sensor sensitivity value register for the Machine Learning Core.
7522 * This register corresponds to the conversion value of the Qvar sensor.
7523 * The register value is expressed as half-precision floating-point format:
7524 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7525 *
7526 * @param ctx read / write interface definitions
7527 * @param val Qvar sensor sensitivity value register for the Machine Learning Core.
7528 * @retval interface status (MANDATORY: return 0 -> no Error)
7529 *
7530 */
ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7531 int32_t ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7532 {
7533 uint8_t buff[2];
7534 int32_t ret;
7535
7536 ret = ism330bx_ln_pg_read(ctx, ISM330BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2);
7537 *val = buff[1];
7538 *val = (*val * 256U) + buff[0];
7539
7540 return ret;
7541 }
7542
7543 /**
7544 * @}
7545 *
7546 */
7547
7548 /**
7549 * @addtogroup Accelerometer user offset correction
7550 * @brief This section group all the functions concerning the
7551 * usage of Accelerometer user offset correction
7552 * @{
7553 *
7554 */
7555
7556 /**
7557 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
7558 *
7559 * @param ctx read / write interface definitions
7560 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7561 * @retval interface status (MANDATORY: return 0 -> no Error)
7562 *
7563 */
ism330bx_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)7564 int32_t ism330bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
7565 {
7566 ism330bx_ctrl9_t ctrl9;
7567 int32_t ret;
7568
7569 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7570 if (ret == 0)
7571 {
7572 ctrl9.usr_off_on_out = val;
7573 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7574 }
7575
7576 return ret;
7577 }
7578
7579 /**
7580 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
7581 *
7582 * @param ctx read / write interface definitions
7583 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7584 * @retval interface status (MANDATORY: return 0 -> no Error)
7585 *
7586 */
ism330bx_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)7587 int32_t ism330bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
7588 {
7589 ism330bx_ctrl9_t ctrl9;
7590 int32_t ret;
7591
7592 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7593 *val = ctrl9.usr_off_on_out;
7594
7595 return ret;
7596 }
7597
7598 /**
7599 * @brief Accelerometer user offset correction values in mg.[set]
7600 *
7601 * @param ctx read / write interface definitions
7602 * @param val Accelerometer user offset correction values in mg.
7603 * @retval interface status (MANDATORY: return 0 -> no Error)
7604 *
7605 */
ism330bx_xl_offset_mg_set(const stmdev_ctx_t * ctx,ism330bx_xl_offset_mg_t val)7606 int32_t ism330bx_xl_offset_mg_set(const stmdev_ctx_t *ctx,
7607 ism330bx_xl_offset_mg_t val)
7608 {
7609 ism330bx_z_ofs_usr_t z_ofs_usr;
7610 ism330bx_y_ofs_usr_t y_ofs_usr;
7611 ism330bx_x_ofs_usr_t x_ofs_usr;
7612 ism330bx_ctrl9_t ctrl9;
7613 int32_t ret;
7614 float_t tmp;
7615
7616 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7617 if (ret == 0)
7618 {
7619 ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7620 }
7621 if (ret == 0)
7622 {
7623 ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7624 }
7625 if (ret == 0)
7626 {
7627 ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7628 }
7629
7630
7631 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
7632 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
7633 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
7634 {
7635 ctrl9.usr_off_w = 0;
7636
7637 tmp = val.z_mg / 0.0078125f;
7638 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7639
7640 tmp = val.y_mg / 0.0078125f;
7641 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7642
7643 tmp = val.x_mg / 0.0078125f;
7644 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7645 }
7646 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
7647 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
7648 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
7649 {
7650 ctrl9.usr_off_w = 1;
7651
7652 tmp = val.z_mg / 0.125f;
7653 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7654
7655 tmp = val.y_mg / 0.125f;
7656 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7657
7658 tmp = val.x_mg / 0.125f;
7659 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7660 }
7661 else // out of limit
7662 {
7663 ctrl9.usr_off_w = 1;
7664 z_ofs_usr.z_ofs_usr = 0xFFU;
7665 y_ofs_usr.y_ofs_usr = 0xFFU;
7666 x_ofs_usr.x_ofs_usr = 0xFFU;
7667 }
7668
7669 if (ret == 0)
7670 {
7671 ret = ism330bx_write_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7672 }
7673 if (ret == 0)
7674 {
7675 ret = ism330bx_write_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7676 }
7677 if (ret == 0)
7678 {
7679 ret = ism330bx_write_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7680 }
7681 if (ret == 0)
7682 {
7683 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7684 }
7685 return ret;
7686 }
7687
7688 /**
7689 * @brief Accelerometer user offset correction values in mg.[get]
7690 *
7691 * @param ctx read / write interface definitions
7692 * @param val Accelerometer user offset correction values in mg.
7693 * @retval interface status (MANDATORY: return 0 -> no Error)
7694 *
7695 */
ism330bx_xl_offset_mg_get(const stmdev_ctx_t * ctx,ism330bx_xl_offset_mg_t * val)7696 int32_t ism330bx_xl_offset_mg_get(const stmdev_ctx_t *ctx,
7697 ism330bx_xl_offset_mg_t *val)
7698 {
7699 ism330bx_z_ofs_usr_t z_ofs_usr;
7700 ism330bx_y_ofs_usr_t y_ofs_usr;
7701 ism330bx_x_ofs_usr_t x_ofs_usr;
7702 ism330bx_ctrl9_t ctrl9;
7703 int32_t ret;
7704
7705 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1);
7706 if (ret == 0)
7707 {
7708 ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7709 }
7710 if (ret == 0)
7711 {
7712 ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7713 }
7714 if (ret == 0)
7715 {
7716 ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7717 }
7718
7719 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
7720 {
7721 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
7722 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
7723 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
7724 }
7725 else
7726 {
7727 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
7728 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
7729 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
7730 }
7731
7732 return ret;
7733 }
7734
7735 /**
7736 * @}
7737 *
7738 */
7739
7740 /**
7741 * @addtogroup AH_QVAR
7742 * @brief This section group all the functions concerning the
7743 * usage of AH_QVAR
7744 * @{
7745 *
7746 */
7747
7748 /**
7749 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are
7750 * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1,
7751 * the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
7752 *
7753 * @param ctx read / write interface definitions
7754 * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain
7755 * @retval interface status (MANDATORY: return 0 -> no Error)
7756 *
7757 */
ism330bx_ah_qvar_mode_set(const stmdev_ctx_t * ctx,ism330bx_ah_qvar_mode_t val)7758 int32_t ism330bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx,
7759 ism330bx_ah_qvar_mode_t val)
7760 {
7761 ism330bx_ctrl10_t ctrl10;
7762 ism330bx_ctrl7_t ctrl7;
7763 int32_t ret;
7764
7765 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7766 if (ret == 0)
7767 {
7768 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
7769 }
7770
7771 if (ret == 0)
7772 {
7773 if ((val.ah_qvar1_en | val.ah_qvar2_en) == PROPERTY_ENABLE)
7774 {
7775 ctrl7.ah_qvar_en = PROPERTY_ENABLE;
7776 }
7777 else
7778 {
7779 ctrl7.ah_qvar_en = PROPERTY_DISABLE;
7780 }
7781 ctrl7.ah_qvar1_en = val.ah_qvar1_en;
7782 ctrl7.ah_qvar2_en = val.ah_qvar2_en;
7783 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7784 }
7785 if (ret == 0)
7786 {
7787 ctrl10.ah_qvar_sw = val.swaps;
7788 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
7789 }
7790 return ret;
7791 }
7792
7793 /**
7794 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are
7795 * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1,
7796 * the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
7797 *
7798 * @param ctx read / write interface definitions
7799 * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain
7800 * @retval interface status (MANDATORY: return 0 -> no Error)
7801 *
7802 */
ism330bx_ah_qvar_mode_get(const stmdev_ctx_t * ctx,ism330bx_ah_qvar_mode_t * val)7803 int32_t ism330bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx,
7804 ism330bx_ah_qvar_mode_t *val)
7805 {
7806 ism330bx_ctrl10_t ctrl10;
7807 ism330bx_ctrl7_t ctrl7;
7808 int32_t ret;
7809
7810 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7811 if (ret == 0)
7812 {
7813 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1);
7814 }
7815
7816 val->ah_qvar1_en = ctrl7.ah_qvar1_en;
7817 val->ah_qvar2_en = ctrl7.ah_qvar2_en;
7818 val->swaps = ctrl10.ah_qvar_sw;
7819
7820 return ret;
7821 }
7822
7823 /**
7824 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
7825 *
7826 * @param ctx read / write interface definitions
7827 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7828 * @retval interface status (MANDATORY: return 0 -> no Error)
7829 *
7830 */
ism330bx_ah_qvar_zin_set(const stmdev_ctx_t * ctx,ism330bx_ah_qvar_zin_t val)7831 int32_t ism330bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx,
7832 ism330bx_ah_qvar_zin_t val)
7833 {
7834 ism330bx_ctrl7_t ctrl7;
7835 int32_t ret;
7836
7837 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7838 if (ret == 0)
7839 {
7840 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
7841 ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7842 }
7843
7844 return ret;
7845 }
7846
7847 /**
7848 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
7849 *
7850 * @param ctx read / write interface definitions
7851 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7852 * @retval interface status (MANDATORY: return 0 -> no Error)
7853 *
7854 */
ism330bx_ah_qvar_zin_get(const stmdev_ctx_t * ctx,ism330bx_ah_qvar_zin_t * val)7855 int32_t ism330bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx,
7856 ism330bx_ah_qvar_zin_t *val)
7857 {
7858 ism330bx_ctrl7_t ctrl7;
7859 int32_t ret;
7860
7861 ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1);
7862 switch (ctrl7.ah_qvar_c_zin)
7863 {
7864 case ISM330BX_2400MOhm:
7865 *val = ISM330BX_2400MOhm;
7866 break;
7867
7868 case ISM330BX_730MOhm:
7869 *val = ISM330BX_730MOhm;
7870 break;
7871
7872 case ISM330BX_300MOhm:
7873 *val = ISM330BX_300MOhm;
7874 break;
7875
7876 case ISM330BX_255MOhm:
7877 *val = ISM330BX_255MOhm;
7878 break;
7879
7880 default:
7881 *val = ISM330BX_2400MOhm;
7882 break;
7883 }
7884 return ret;
7885 }
7886
7887 /**
7888 * @brief Qvar sensor sensitivity value register for the Finite State Machine.
7889 * This register corresponds to the conversion value of the Qvar sensor.
7890 * The register value is expressed as half-precision floating-point format:
7891 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7892 *
7893 * @param ctx read / write interface definitions
7894 * @param val Qvar sensor sensitivity value register for the Finite State Machine.
7895 * @retval interface status (MANDATORY: return 0 -> no Error)
7896 *
7897 */
ism330bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7898 int32_t ism330bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7899 {
7900 uint8_t buff[2];
7901 int32_t ret;
7902
7903 buff[1] = (uint8_t)(val / 256U);
7904 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7905 ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7906
7907 return ret;
7908 }
7909
7910 /**
7911 * @brief Qvar sensor sensitivity value register for the Finite State Machine.
7912 * This register corresponds to the conversion value of the Qvar sensor.
7913 * The register value is expressed as half-precision floating-point format:
7914 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7915 *
7916 * @param ctx read / write interface definitions
7917 * @param val Qvar sensor sensitivity value register for the Finite State Machine.
7918 * @retval interface status (MANDATORY: return 0 -> no Error)
7919 *
7920 */
ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7921 int32_t ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7922 {
7923 uint8_t buff[2];
7924 int32_t ret;
7925
7926 ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2);
7927 *val = buff[1];
7928 *val = (*val * 256U) + buff[0];
7929
7930 return ret;
7931 }
7932
7933 /**
7934 * @}
7935 *
7936 */
7937
7938 /**
7939 * @addtogroup SenseWire (I3C)
7940 * @brief This section group all the functions concerning the
7941 * usage of SenseWire (I3C)
7942 * @{
7943 *
7944 */
7945
7946 /**
7947 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7948 *
7949 * @param ctx read / write interface definitions
7950 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7951 * @retval interface status (MANDATORY: return 0 -> no Error)
7952 *
7953 */
ism330bx_i3c_reset_mode_set(const stmdev_ctx_t * ctx,ism330bx_i3c_reset_mode_t val)7954 int32_t ism330bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
7955 ism330bx_i3c_reset_mode_t val)
7956 {
7957 ism330bx_pin_ctrl_t pin_ctrl;
7958 int32_t ret;
7959
7960 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7961 if (ret == 0)
7962 {
7963 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7964 ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7965 }
7966
7967 return ret;
7968 }
7969
7970 /**
7971 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7972 *
7973 * @param ctx read / write interface definitions
7974 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7975 * @retval interface status (MANDATORY: return 0 -> no Error)
7976 *
7977 */
ism330bx_i3c_reset_mode_get(const stmdev_ctx_t * ctx,ism330bx_i3c_reset_mode_t * val)7978 int32_t ism330bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
7979 ism330bx_i3c_reset_mode_t *val)
7980 {
7981 ism330bx_pin_ctrl_t pin_ctrl;
7982 int32_t ret;
7983
7984 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7985 switch (pin_ctrl.ibhr_por_en)
7986 {
7987 case ISM330BX_SW_RST_DYN_ADDRESS_RST:
7988 *val = ISM330BX_SW_RST_DYN_ADDRESS_RST;
7989 break;
7990
7991 case ISM330BX_I3C_GLOBAL_RST:
7992 *val = ISM330BX_I3C_GLOBAL_RST;
7993 break;
7994
7995 default:
7996 *val = ISM330BX_SW_RST_DYN_ADDRESS_RST;
7997 break;
7998 }
7999 return ret;
8000 }
8001
8002 /**
8003 * @}
8004 *
8005 */
8006
8007 /**
8008 * @addtogroup Time-Division Multiplexing (TDM)
8009 * @brief This section group all the functions concerning the
8010 * usage of Time-Division Multiplexing (TDM)
8011 * @{
8012 *
8013 */
8014
8015 /**
8016 * @brief Disables pull-up on WCLK pin.[set]
8017 *
8018 * @param ctx read / write interface definitions
8019 * @param val Disables pull-up on WCLK pin.
8020 * @retval interface status (MANDATORY: return 0 -> no Error)
8021 *
8022 */
ism330bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8023 int32_t ism330bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8024 {
8025 ism330bx_pin_ctrl_t pin_ctrl;
8026 int32_t ret;
8027
8028 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8029 if (ret == 0)
8030 {
8031 pin_ctrl.tdm_wclk_pu_dis = val;
8032 ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8033 }
8034
8035 return ret;
8036 }
8037
8038 /**
8039 * @brief Disables pull-up on WCLK pin.[get]
8040 *
8041 * @param ctx read / write interface definitions
8042 * @param val Disables pull-up on WCLK pin.
8043 * @retval interface status (MANDATORY: return 0 -> no Error)
8044 *
8045 */
ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8046 int32_t ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8047 {
8048 ism330bx_pin_ctrl_t pin_ctrl;
8049 int32_t ret;
8050
8051 ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8052 *val = pin_ctrl.tdm_wclk_pu_dis;
8053
8054 return ret;
8055 }
8056
8057 /**
8058 * @brief Enables pull-up on TDMout pin.[set]
8059 *
8060 * @param ctx read / write interface definitions
8061 * @param val Enables pull-up on TDMout pin.
8062 * @retval interface status (MANDATORY: return 0 -> no Error)
8063 *
8064 */
ism330bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8065 int32_t ism330bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8066 {
8067 ism330bx_if_cfg_t if_cfg;
8068 int32_t ret;
8069
8070 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8071 if (ret == 0)
8072 {
8073 if_cfg.tdm_out_pu_en = val;
8074 ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8075 }
8076
8077 return ret;
8078 }
8079
8080 /**
8081 * @brief Enables pull-up on TDMout pin.[get]
8082 *
8083 * @param ctx read / write interface definitions
8084 * @param val Enables pull-up on TDMout pin.
8085 * @retval interface status (MANDATORY: return 0 -> no Error)
8086 *
8087 */
ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8088 int32_t ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8089 {
8090 ism330bx_if_cfg_t if_cfg;
8091 int32_t ret;
8092
8093 ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8094 *val = if_cfg.tdm_out_pu_en;
8095
8096 return ret;
8097 }
8098
8099 /**
8100 * @brief WCLK and BCLK frequencies.[set]
8101 *
8102 * @param ctx read / write interface definitions
8103 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8104 * @retval interface status (MANDATORY: return 0 -> no Error)
8105 *
8106 */
ism330bx_tdm_wclk_bclk_set(const stmdev_ctx_t * ctx,ism330bx_tdm_wclk_bclk_t val)8107 int32_t ism330bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx,
8108 ism330bx_tdm_wclk_bclk_t val)
8109 {
8110 ism330bx_tdm_cfg0_t tdm_cfg0;
8111 int32_t ret;
8112
8113 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8114 if (ret == 0)
8115 {
8116 tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2;
8117 tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U;
8118 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8119 }
8120
8121 return ret;
8122 }
8123
8124 /**
8125 * @brief WCLK and BCLK frequencies.[get]
8126 *
8127 * @param ctx read / write interface definitions
8128 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8129 * @retval interface status (MANDATORY: return 0 -> no Error)
8130 *
8131 */
ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t * ctx,ism330bx_tdm_wclk_bclk_t * val)8132 int32_t ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx,
8133 ism330bx_tdm_wclk_bclk_t *val)
8134 {
8135 ism330bx_tdm_cfg0_t tdm_cfg0;
8136 int32_t ret;
8137
8138 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8139 switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk)
8140 {
8141 case ISM330BX_WCLK_16kHZ_BCLK_2048kHz:
8142 *val = ISM330BX_WCLK_16kHZ_BCLK_2048kHz;
8143 break;
8144
8145 case ISM330BX_WCLK_8kHZ_BCLK_2048kHz:
8146 *val = ISM330BX_WCLK_8kHZ_BCLK_2048kHz;
8147 break;
8148
8149 default:
8150 *val = ISM330BX_WCLK_8kHZ_BCLK_2048kHz;
8151 break;
8152 }
8153 return ret;
8154 }
8155
8156 /**
8157 * @brief Selection of TDM slot for transmission.[set]
8158 *
8159 * @param ctx read / write interface definitions
8160 * @param val SLOT_012, SLOT_456,
8161 * @retval interface status (MANDATORY: return 0 -> no Error)
8162 *
8163 */
ism330bx_tdm_slot_set(const stmdev_ctx_t * ctx,ism330bx_tdm_slot_t val)8164 int32_t ism330bx_tdm_slot_set(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t val)
8165 {
8166 ism330bx_tdm_cfg0_t tdm_cfg0;
8167 int32_t ret;
8168
8169 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8170 if (ret == 0)
8171 {
8172 tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U;
8173 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8174 }
8175
8176 return ret;
8177 }
8178
8179 /**
8180 * @brief Selection of TDM slot for transmission.[get]
8181 *
8182 * @param ctx read / write interface definitions
8183 * @param val SLOT_012, SLOT_456,
8184 * @retval interface status (MANDATORY: return 0 -> no Error)
8185 *
8186 */
ism330bx_tdm_slot_get(const stmdev_ctx_t * ctx,ism330bx_tdm_slot_t * val)8187 int32_t ism330bx_tdm_slot_get(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t *val)
8188 {
8189 ism330bx_tdm_cfg0_t tdm_cfg0;
8190 int32_t ret;
8191
8192 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8193 switch (tdm_cfg0.tdm_slot_sel)
8194 {
8195 case ISM330BX_SLOT_012:
8196 *val = ISM330BX_SLOT_012;
8197 break;
8198
8199 case ISM330BX_SLOT_456:
8200 *val = ISM330BX_SLOT_456;
8201 break;
8202
8203 default:
8204 *val = ISM330BX_SLOT_012;
8205 break;
8206 }
8207 return ret;
8208 }
8209
8210 /**
8211 * @brief BCLK edge selection for TDM interface.[set]
8212 *
8213 * @param ctx read / write interface definitions
8214 * @param val BCLK_RISING, BCLK_FALLING,
8215 * @retval interface status (MANDATORY: return 0 -> no Error)
8216 *
8217 */
ism330bx_tdm_bclk_edge_set(const stmdev_ctx_t * ctx,ism330bx_tdm_bclk_edge_t val)8218 int32_t ism330bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx,
8219 ism330bx_tdm_bclk_edge_t val)
8220 {
8221 ism330bx_tdm_cfg0_t tdm_cfg0;
8222 int32_t ret;
8223
8224 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8225 if (ret == 0)
8226 {
8227 tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U;
8228 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8229 }
8230
8231 return ret;
8232 }
8233
8234 /**
8235 * @brief BCLK edge selection for TDM interface.[get]
8236 *
8237 * @param ctx read / write interface definitions
8238 * @param val BCLK_RISING, BCLK_FALLING,
8239 * @retval interface status (MANDATORY: return 0 -> no Error)
8240 *
8241 */
ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t * ctx,ism330bx_tdm_bclk_edge_t * val)8242 int32_t ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx,
8243 ism330bx_tdm_bclk_edge_t *val)
8244 {
8245 ism330bx_tdm_cfg0_t tdm_cfg0;
8246 int32_t ret;
8247
8248 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8249 switch (tdm_cfg0.tdm_bclk_edge_sel)
8250 {
8251 case ISM330BX_BCLK_RISING:
8252 *val = ISM330BX_BCLK_RISING;
8253 break;
8254
8255 case ISM330BX_BCLK_FALLING:
8256 *val = ISM330BX_BCLK_FALLING;
8257 break;
8258
8259 default:
8260 *val = ISM330BX_BCLK_RISING;
8261 break;
8262 }
8263 return ret;
8264 }
8265
8266 /**
8267 * @brief Enables TDM delayed configuration.[set]
8268 *
8269 * @param ctx read / write interface definitions
8270 * @param val Enables TDM delayed configuration.
8271 * @retval interface status (MANDATORY: return 0 -> no Error)
8272 *
8273 */
ism330bx_tdm_delayed_conf_set(const stmdev_ctx_t * ctx,uint8_t val)8274 int32_t ism330bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val)
8275 {
8276 ism330bx_tdm_cfg0_t tdm_cfg0;
8277 int32_t ret;
8278
8279 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8280 if (ret == 0)
8281 {
8282 tdm_cfg0.tdm_delayed_cfg = val;
8283 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8284 }
8285
8286 return ret;
8287 }
8288
8289 /**
8290 * @brief Enables TDM delayed configuration.[get]
8291 *
8292 * @param ctx read / write interface definitions
8293 * @param val Enables TDM delayed configuration.
8294 * @retval interface status (MANDATORY: return 0 -> no Error)
8295 *
8296 */
ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t * ctx,uint8_t * val)8297 int32_t ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val)
8298 {
8299 ism330bx_tdm_cfg0_t tdm_cfg0;
8300 int32_t ret;
8301
8302 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8303 *val = tdm_cfg0.tdm_delayed_cfg;
8304
8305 return ret;
8306 }
8307
8308
8309 /**
8310 * @brief Selects order of transmission of TDM axes.[set]
8311 *
8312 * @param ctx read / write interface definitions
8313 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8314 * @retval interface status (MANDATORY: return 0 -> no Error)
8315 *
8316 */
ism330bx_tdm_axis_order_set(const stmdev_ctx_t * ctx,ism330bx_tdm_axis_order_t val)8317 int32_t ism330bx_tdm_axis_order_set(const stmdev_ctx_t *ctx,
8318 ism330bx_tdm_axis_order_t val)
8319 {
8320 ism330bx_tdm_cfg1_t tdm_cfg1;
8321 int32_t ret;
8322
8323 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8324 if (ret == 0)
8325 {
8326 tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U;
8327 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8328 }
8329
8330 return ret;
8331 }
8332
8333 /**
8334 * @brief Selects order of transmission of TDM axes.[get]
8335 *
8336 * @param ctx read / write interface definitions
8337 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8338 * @retval interface status (MANDATORY: return 0 -> no Error)
8339 *
8340 */
ism330bx_tdm_axis_order_get(const stmdev_ctx_t * ctx,ism330bx_tdm_axis_order_t * val)8341 int32_t ism330bx_tdm_axis_order_get(const stmdev_ctx_t *ctx,
8342 ism330bx_tdm_axis_order_t *val)
8343 {
8344 ism330bx_tdm_cfg1_t tdm_cfg1;
8345 int32_t ret;
8346
8347 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8348 switch (tdm_cfg1.tdm_axes_ord_sel)
8349 {
8350 case ISM330BX_TDM_ORDER_ZYX:
8351 *val = ISM330BX_TDM_ORDER_ZYX;
8352 break;
8353
8354 case ISM330BX_TDM_ORDER_XZY:
8355 *val = ISM330BX_TDM_ORDER_XZY;
8356 break;
8357
8358 case ISM330BX_TDM_ORDER_XYZ:
8359 *val = ISM330BX_TDM_ORDER_XYZ;
8360 break;
8361
8362 default:
8363 *val = ISM330BX_TDM_ORDER_ZYX;
8364 break;
8365 }
8366 return ret;
8367 }
8368
8369 /**
8370 * @brief TDM channel accelerometer full-scale selection.[set]
8371 *
8372 * @param ctx read / write interface definitions
8373 * @param val TDM_2g, TDM_4g, TDM_8g,
8374 * @retval interface status (MANDATORY: return 0 -> no Error)
8375 *
8376 */
ism330bx_tdm_xl_full_scale_set(const stmdev_ctx_t * ctx,ism330bx_tdm_xl_full_scale_t val)8377 int32_t ism330bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx,
8378 ism330bx_tdm_xl_full_scale_t val)
8379 {
8380 ism330bx_tdm_cfg2_t tdm_cfg2;
8381 int32_t ret;
8382
8383 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8384 if (ret == 0)
8385 {
8386 tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U;
8387 ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8388 }
8389
8390 return ret;
8391 }
8392
8393 /**
8394 * @brief TDM channel accelerometer full-scale selection.[get]
8395 *
8396 * @param ctx read / write interface definitions
8397 * @param val TDM_2g, TDM_4g, TDM_8g,
8398 * @retval interface status (MANDATORY: return 0 -> no Error)
8399 *
8400 */
ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t * ctx,ism330bx_tdm_xl_full_scale_t * val)8401 int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx,
8402 ism330bx_tdm_xl_full_scale_t *val)
8403 {
8404 ism330bx_tdm_cfg2_t tdm_cfg2;
8405 int32_t ret;
8406
8407 ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8408 switch (tdm_cfg2.tdm_fs_xl)
8409 {
8410 case ISM330BX_TDM_2g:
8411 *val = ISM330BX_TDM_2g;
8412 break;
8413
8414 case ISM330BX_TDM_4g:
8415 *val = ISM330BX_TDM_4g;
8416 break;
8417
8418 case ISM330BX_TDM_8g:
8419 *val = ISM330BX_TDM_8g;
8420 break;
8421
8422 default:
8423 *val = ISM330BX_TDM_2g;
8424 break;
8425 }
8426 return ret;
8427 }
8428
8429 /**
8430 * @}
8431 *
8432 */
8433
8434 /**
8435 * @}
8436 *
8437 */
8438
8439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8440
