1 /**
2 ******************************************************************************
3 * @file ism303dac_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ISM303DAC driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ism303dac_reg.h"
21
22 /**
23 * @defgroup ISM303DAC
24 * @brief This file provides a set of functions needed to drive the
25 * ism303dac enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ISM303DAC_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ism303dac_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ism303dac_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
ism303dac_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak ism303dac_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup ISM303DAC_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
ism303dac_from_fs2g_to_mg(int16_t lsb)103 float_t ism303dac_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
ism303dac_from_fs4g_to_mg(int16_t lsb)108 float_t ism303dac_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
ism303dac_from_fs8g_to_mg(int16_t lsb)113 float_t ism303dac_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
ism303dac_from_fs16g_to_mg(int16_t lsb)118 float_t ism303dac_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
ism303dac_from_lsb_to_mG(int16_t lsb)123 float_t ism303dac_from_lsb_to_mG(int16_t lsb)
124 {
125 return ((float_t)lsb * 1.5f);
126 }
127
ism303dac_from_lsb_to_celsius(int16_t lsb)128 float_t ism303dac_from_lsb_to_celsius(int16_t lsb)
129 {
130 return (((float_t)lsb / 256.0f) + 25.0f);
131 }
132
133 /**
134 * @}
135 *
136 */
137
138 /**
139 * @defgroup ISM303DAC_data_generation_c
140 * @brief This section groups all the functions concerning data generation
141 * @{
142 *
143 */
144
145 /**
146 * @brief Read all the interrupt/status flag of the device.[get]
147 *
148 * @param ctx read / write interface definitions.(ptr)
149 * @param val Get FIFO_SRC, STATUS_DUP, WAKE_UP_SRC, TAP_SRC, 6D_SRC,
150 * FUNC_CK_GATE, FUNC_SRC.(ptr)
151 * @retval Interface status (MANDATORY: return 0 -> no Error).
152 *
153 */
ism303dac_xl_all_sources_get(const stmdev_ctx_t * ctx,ism303dac_xl_all_sources_t * val)154 int32_t ism303dac_xl_all_sources_get(const stmdev_ctx_t *ctx,
155 ism303dac_xl_all_sources_t *val)
156 {
157 int32_t ret;
158
159 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
160 (uint8_t *) & (val->fifo_src_a), 1);
161
162 if (ret == 0)
163 {
164 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_DUP_A,
165 (uint8_t *) & (val->status_dup_a), 1);
166 }
167
168 if (ret == 0)
169 {
170 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_SRC_A,
171 (uint8_t *) & (val->wake_up_src_a), 1);
172 }
173
174 if (ret == 0)
175 {
176 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_SRC_A,
177 (uint8_t *) & (val->tap_src_a), 1);
178 }
179
180 if (ret == 0)
181 {
182 ret = ism303dac_read_reg(ctx, ISM303DAC_6D_SRC_A,
183 (uint8_t *) & (val->_6d_src_a), 1);
184 }
185
186 if (ret == 0)
187 {
188 ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_SRC_A,
189 (uint8_t *) & (val->func_src_a), 1);
190 }
191
192 return ret;
193 }
194
195 /**
196 * @brief Block data update.[set]
197 *
198 * @param ctx read / write interface definitions.(ptr)
199 * @param val Change the values of bdu in reg CTRL1
200 * @retval Interface status (MANDATORY: return 0 -> no Error).
201 *
202 */
ism303dac_xl_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)203 int32_t ism303dac_xl_block_data_update_set(const stmdev_ctx_t *ctx,
204 uint8_t val)
205 {
206 ism303dac_ctrl1_a_t ctrl1_a;
207 int32_t ret;
208
209 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
210
211 if (ret == 0)
212 {
213 ctrl1_a.bdu = val;
214 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
215 }
216
217 return ret;
218 }
219
220 /**
221 * @brief Block data update.[get]
222 *
223 * @param ctx read / write interface definitions.(ptr)
224 * @param val Get the values of bdu in reg CTRL1.(ptr)
225 * @retval Interface status (MANDATORY: return 0 -> no Error).
226 *
227 */
ism303dac_xl_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)228 int32_t ism303dac_xl_block_data_update_get(const stmdev_ctx_t *ctx,
229 uint8_t *val)
230 {
231 ism303dac_ctrl1_a_t ctrl1_a;
232 int32_t ret;
233
234 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
235 *val = ctrl1_a.bdu;
236
237 return ret;
238 }
239
240 /**
241 * @brief Block data update.[set]
242 *
243 * @param ctx read / write interface definitions.(ptr)
244 * @param val Change the values of bdu in reg CFG_REG_C
245 * @retval Interface status (MANDATORY: return 0 -> no Error).
246 *
247 */
ism303dac_mg_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)248 int32_t ism303dac_mg_block_data_update_set(const stmdev_ctx_t *ctx,
249 uint8_t val)
250 {
251 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
252 int32_t ret;
253
254 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
255 (uint8_t *)&cfg_reg_c_m, 1);
256
257 if (ret == 0)
258 {
259 cfg_reg_c_m.bdu = val;
260 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
261 (uint8_t *)&cfg_reg_c_m, 1);
262 }
263
264 return ret;
265 }
266
267 /**
268 * @brief Block data update.[get]
269 *
270 * @param ctx read / write interface definitions.(ptr)
271 * @param val Get the values of bdu in reg CFG_REG_C.(ptr)
272 * @retval Interface status (MANDATORY: return 0 -> no Error).
273 *
274 */
ism303dac_mg_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)275 int32_t ism303dac_mg_block_data_update_get(const stmdev_ctx_t *ctx,
276 uint8_t *val)
277 {
278 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
279 int32_t ret;
280
281 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
282 (uint8_t *)&cfg_reg_c_m, 1);
283 *val = cfg_reg_c_m.bdu;
284
285 return ret;
286 }
287
288 /**
289 * @brief Big/Little Endian data selection.[set]
290 *
291 * @param ctx read / write interface definitions.(ptr)
292 * @param val Change the values of ble in reg CFG_REG_C
293 * @retval Interface status (MANDATORY: return 0 -> no Error).
294 *
295 */
ism303dac_mg_data_format_set(const stmdev_ctx_t * ctx,ism303dac_mg_ble_t val)296 int32_t ism303dac_mg_data_format_set(const stmdev_ctx_t *ctx,
297 ism303dac_mg_ble_t val)
298 {
299 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
300 int32_t ret;
301
302 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
303 (uint8_t *)&cfg_reg_c_m, 1);
304
305 if (ret == 0)
306 {
307 cfg_reg_c_m.ble = (uint8_t)val;
308 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
309 (uint8_t *)&cfg_reg_c_m, 1);
310 }
311
312 return ret;
313 }
314
315 /**
316 * @brief Big/Little Endian data selection.[get]
317 *
318 * @param ctx read / write interface definitions.(ptr)
319 * @param val Get the values of ble in reg CFG_REG_C.(ptr)
320 * @retval Interface status (MANDATORY: return 0 -> no Error).
321 *
322 */
ism303dac_mg_data_format_get(const stmdev_ctx_t * ctx,ism303dac_mg_ble_t * val)323 int32_t ism303dac_mg_data_format_get(const stmdev_ctx_t *ctx,
324 ism303dac_mg_ble_t *val)
325 {
326 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
327 int32_t ret;
328
329 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
330 (uint8_t *)&cfg_reg_c_m, 1);
331
332 switch (cfg_reg_c_m.ble)
333 {
334 case ISM303DAC_MG_LSB_AT_LOW_ADD:
335 *val = ISM303DAC_MG_LSB_AT_LOW_ADD;
336 break;
337
338 case ISM303DAC_MG_MSB_AT_LOW_ADD:
339 *val = ISM303DAC_MG_MSB_AT_LOW_ADD;
340 break;
341
342 default:
343 *val = ISM303DAC_MG_LSB_AT_LOW_ADD;
344 break;
345 }
346
347 return ret;
348 }
349
350 /**
351 * @brief Accelerometer full-scale selection.[set]
352 *
353 * @param ctx read / write interface definitions.(ptr)
354 * @param val Change the values of fs in reg CTRL1
355 * @retval Interface status (MANDATORY: return 0 -> no Error).
356 *
357 */
ism303dac_xl_full_scale_set(const stmdev_ctx_t * ctx,ism303dac_xl_fs_t val)358 int32_t ism303dac_xl_full_scale_set(const stmdev_ctx_t *ctx,
359 ism303dac_xl_fs_t val)
360 {
361 ism303dac_ctrl1_a_t ctrl1_a;
362 int32_t ret;
363
364 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
365
366 if (ret == 0)
367 {
368 ctrl1_a.fs = (uint8_t)val;
369 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
370 }
371
372 return ret;
373 }
374
375 /**
376 * @brief Accelerometer full-scale selection.[get]
377 *
378 * @param ctx read / write interface definitions.(ptr)
379 * @param val Get the values of fs in reg CTRL1.(ptr)
380 * @retval Interface status (MANDATORY: return 0 -> no Error).
381 *
382 */
ism303dac_xl_full_scale_get(const stmdev_ctx_t * ctx,ism303dac_xl_fs_t * val)383 int32_t ism303dac_xl_full_scale_get(const stmdev_ctx_t *ctx,
384 ism303dac_xl_fs_t *val)
385 {
386 ism303dac_ctrl1_a_t ctrl1_a;
387 int32_t ret;
388
389 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
390
391 switch (ctrl1_a.fs)
392 {
393 case ISM303DAC_XL_2g:
394 *val = ISM303DAC_XL_2g;
395 break;
396
397 case ISM303DAC_XL_16g:
398 *val = ISM303DAC_XL_16g;
399 break;
400
401 case ISM303DAC_XL_4g:
402 *val = ISM303DAC_XL_4g;
403 break;
404
405 case ISM303DAC_XL_8g:
406 *val = ISM303DAC_XL_8g;
407 break;
408
409 default:
410 *val = ISM303DAC_XL_2g;
411 break;
412 }
413
414 return ret;
415 }
416
417 /**
418 * @brief Accelerometer data rate selection.[set]
419 *
420 * @param ctx read / write interface definitions.(ptr)
421 * @param val Change the values of odr in reg CTRL1
422 * @retval Interface status (MANDATORY: return 0 -> no Error).
423 *
424 */
ism303dac_xl_data_rate_set(const stmdev_ctx_t * ctx,ism303dac_xl_odr_t val)425 int32_t ism303dac_xl_data_rate_set(const stmdev_ctx_t *ctx,
426 ism303dac_xl_odr_t val)
427 {
428 ism303dac_ctrl1_a_t ctrl1_a;
429 int32_t ret;
430
431 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
432
433 if (ret == 0)
434 {
435 ctrl1_a.odr = (uint8_t)val & 0x0FU;
436 ctrl1_a.hf_odr = ((uint8_t)val & 0x10U) >> 4;
437 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
438 }
439
440 return ret;
441 }
442
443 /**
444 * @brief Accelerometer data rate selection.[get]
445 *
446 * @param ctx read / write interface definitions.(ptr)
447 * @param val Get the values of odr in reg CTRL1.(ptr)
448 * @retval Interface status (MANDATORY: return 0 -> no Error).
449 *
450 */
ism303dac_xl_data_rate_get(const stmdev_ctx_t * ctx,ism303dac_xl_odr_t * val)451 int32_t ism303dac_xl_data_rate_get(const stmdev_ctx_t *ctx,
452 ism303dac_xl_odr_t *val)
453 {
454 ism303dac_ctrl1_a_t ctrl1_a;
455 int32_t ret;
456
457 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1);
458
459 switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr)
460 {
461 case ISM303DAC_XL_ODR_OFF:
462 *val = ISM303DAC_XL_ODR_OFF;
463 break;
464
465 case ISM303DAC_XL_ODR_1Hz_LP:
466 *val = ISM303DAC_XL_ODR_1Hz_LP;
467 break;
468
469 case ISM303DAC_XL_ODR_12Hz5_LP:
470 *val = ISM303DAC_XL_ODR_12Hz5_LP;
471 break;
472
473 case ISM303DAC_XL_ODR_25Hz_LP:
474 *val = ISM303DAC_XL_ODR_25Hz_LP;
475 break;
476
477 case ISM303DAC_XL_ODR_50Hz_LP:
478 *val = ISM303DAC_XL_ODR_50Hz_LP;
479 break;
480
481 case ISM303DAC_XL_ODR_100Hz_LP:
482 *val = ISM303DAC_XL_ODR_100Hz_LP;
483 break;
484
485 case ISM303DAC_XL_ODR_200Hz_LP:
486 *val = ISM303DAC_XL_ODR_200Hz_LP;
487 break;
488
489 case ISM303DAC_XL_ODR_400Hz_LP:
490 *val = ISM303DAC_XL_ODR_400Hz_LP;
491 break;
492
493 case ISM303DAC_XL_ODR_800Hz_LP:
494 *val = ISM303DAC_XL_ODR_800Hz_LP;
495 break;
496
497 case ISM303DAC_XL_ODR_12Hz5_HR:
498 *val = ISM303DAC_XL_ODR_12Hz5_HR;
499 break;
500
501 case ISM303DAC_XL_ODR_25Hz_HR:
502 *val = ISM303DAC_XL_ODR_25Hz_HR;
503 break;
504
505 case ISM303DAC_XL_ODR_50Hz_HR:
506 *val = ISM303DAC_XL_ODR_50Hz_HR;
507 break;
508
509 case ISM303DAC_XL_ODR_100Hz_HR:
510 *val = ISM303DAC_XL_ODR_100Hz_HR;
511 break;
512
513 case ISM303DAC_XL_ODR_200Hz_HR:
514 *val = ISM303DAC_XL_ODR_200Hz_HR;
515 break;
516
517 case ISM303DAC_XL_ODR_400Hz_HR:
518 *val = ISM303DAC_XL_ODR_400Hz_HR;
519 break;
520
521 case ISM303DAC_XL_ODR_800Hz_HR:
522 *val = ISM303DAC_XL_ODR_800Hz_HR;
523 break;
524
525 case ISM303DAC_XL_ODR_1k6Hz_HF:
526 *val = ISM303DAC_XL_ODR_1k6Hz_HF;
527 break;
528
529 case ISM303DAC_XL_ODR_3k2Hz_HF:
530 *val = ISM303DAC_XL_ODR_3k2Hz_HF;
531 break;
532
533 case ISM303DAC_XL_ODR_6k4Hz_HF:
534 *val = ISM303DAC_XL_ODR_6k4Hz_HF;
535 break;
536
537 default:
538 *val = ISM303DAC_XL_ODR_OFF;
539 break;
540 }
541
542 return ret;
543 }
544
545 /**
546 * @brief The STATUS_REG register.[get]
547 *
548 * @param ctx read / write interface definitions.(ptr)
549 * @param val Get registers STATUS.(ptr)
550 * @retval Interface status (MANDATORY: return 0 -> no Error).
551 *
552 */
ism303dac_xl_status_reg_get(const stmdev_ctx_t * ctx,ism303dac_status_a_t * val)553 int32_t ism303dac_xl_status_reg_get(const stmdev_ctx_t *ctx,
554 ism303dac_status_a_t *val)
555 {
556 int32_t ret;
557
558 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A, (uint8_t *) val, 1);
559
560 return ret;
561 }
562
563 /**
564 * @brief Info about device status.[get]
565 *
566 * @param ctx read / write interface definitions.(ptr)
567 * @param val Get registers STATUS_REG.(ptr)
568 * @retval Interface status (MANDATORY: return 0 -> no Error).
569 *
570 */
ism303dac_mg_status_get(const stmdev_ctx_t * ctx,ism303dac_status_reg_m_t * val)571 int32_t ism303dac_mg_status_get(const stmdev_ctx_t *ctx,
572 ism303dac_status_reg_m_t *val)
573 {
574 int32_t ret;
575
576 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M, (uint8_t *) val, 1);
577
578 return ret;
579 }
580
581 /**
582 * @brief Accelerometer new data available.[get]
583 *
584 * @param ctx read / write interface definitions.(ptr)
585 * @param val Get the values of drdy in reg STATUS.(ptr)
586 * @retval Interface status (MANDATORY: return 0 -> no Error).
587 *
588 */
ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)589 int32_t ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
590 uint8_t *val)
591 {
592 ism303dac_status_a_t status_a;
593 int32_t ret;
594
595 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A,
596 (uint8_t *)&status_a, 1);
597 *val = status_a.drdy;
598
599 return ret;
600 }
601
602 /**
603 * @brief Magnetic set of data available.[get]
604 *
605 * @param ctx read / write interface definitions.(ptr)
606 * @param val Get the values of zyxda in reg STATUS_REG.(ptr)
607 * @retval Interface status (MANDATORY: return 0 -> no Error).
608 *
609 */
ism303dac_mg_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)610 int32_t ism303dac_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
611 {
612 ism303dac_status_reg_m_t status_reg_m;
613 int32_t ret;
614
615 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M,
616 (uint8_t *)&status_reg_m, 1);
617 *val = status_reg_m.zyxda;
618
619 return ret;
620 }
621
622 /**
623 * @brief Magnetic set of data overrun.[get]
624 *
625 * @param ctx read / write interface definitions.(ptr)
626 * @param val Get the values of zyxor in reg STATUS_REG.(ptr)
627 * @retval Interface status (MANDATORY: return 0 -> no Error).
628 *
629 */
ism303dac_mg_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)630 int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
631 {
632 ism303dac_status_reg_m_t status_reg_m;
633 int32_t ret;
634
635 ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M,
636 (uint8_t *)&status_reg_m, 1);
637 *val = status_reg_m.zyxor;
638
639 return ret;
640 }
641
642 /**
643 * @brief These registers comprise a 3 group of 16-bit number and represent
644 * hard-iron offset in order to compensate environmental effects.
645 * Data format is the same of output data raw: two’s complement with
646 * 1LSb = 1.5mG. These values act on the magnetic output data value
647 * in order to delete the environmental offset.[set]
648 *
649 * @param ctx read / write interface definitions.(ptr)
650 * @param buff buffer that contains data to write.(ptr)
651 * @retval Interface status (MANDATORY: return 0 -> no Error).
652 *
653 */
ism303dac_mg_user_offset_set(const stmdev_ctx_t * ctx,uint16_t * val)654 int32_t ism303dac_mg_user_offset_set(const stmdev_ctx_t *ctx, uint16_t *val)
655 {
656 uint8_t buff[6];
657 int32_t ret;
658
659 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
660 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
661 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
662 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
663 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
664 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
665 ret = ism303dac_write_reg(ctx, ISM303DAC_OFFSET_X_REG_L_M, buff, 6);
666
667 return ret;
668 }
669
670 /**
671 * @brief These registers comprise a 3 group of 16-bit number and represent
672 * hard-iron offset in order to compensate environmental effects.
673 * Data format is the same of output data raw: two’s complement with
674 * 1LSb = 1.5mG. These values act on the magnetic output data value
675 * in order to delete the environmental offset.[get]
676 *
677 * @param ctx read / write interface definitions.(ptr)
678 * @param buff buffer that stores data read.(ptr)
679 * @retval Interface status (MANDATORY: return 0 -> no Error).
680 *
681 */
ism303dac_mg_user_offset_get(const stmdev_ctx_t * ctx,uint16_t * val)682 int32_t ism303dac_mg_user_offset_get(const stmdev_ctx_t *ctx, uint16_t *val)
683 {
684 uint8_t buff[6];
685 int32_t ret;
686
687 ret = ism303dac_read_reg(ctx, ISM303DAC_OFFSET_X_REG_L_M, buff, 6);
688 val[0] = (int16_t)buff[1];
689 val[0] = (val[0] * 256) + (int16_t)buff[0];
690 val[1] = (int16_t)buff[3];
691 val[1] = (val[1] * 256) + (int16_t)buff[2];
692 val[2] = (int16_t)buff[5];
693 val[2] = (val[2] * 256) + (int16_t)buff[4];
694
695 return ret;
696 }
697
698 /**
699 * @brief Operating mode selection.[set]
700 *
701 * @param ctx read / write interface definitions.(ptr)
702 * @param val Change the values of md in reg CFG_REG_A
703 * @retval Interface status (MANDATORY: return 0 -> no Error).
704 *
705 */
ism303dac_mg_operating_mode_set(const stmdev_ctx_t * ctx,ism303dac_mg_md_t val)706 int32_t ism303dac_mg_operating_mode_set(const stmdev_ctx_t *ctx,
707 ism303dac_mg_md_t val)
708 {
709 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
710 int32_t ret;
711
712 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
713 (uint8_t *)&cfg_reg_a_m, 1);
714
715 if (ret == 0)
716 {
717 cfg_reg_a_m.md = (uint8_t)val;
718 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
719 (uint8_t *)&cfg_reg_a_m, 1);
720 }
721
722 return ret;
723 }
724
725 /**
726 * @brief Operating mode selection.[get]
727 *
728 * @param ctx read / write interface definitions.(ptr)
729 * @param val Get the values of md in reg CFG_REG_A.(ptr)
730 * @retval Interface status (MANDATORY: return 0 -> no Error).
731 *
732 */
ism303dac_mg_operating_mode_get(const stmdev_ctx_t * ctx,ism303dac_mg_md_t * val)733 int32_t ism303dac_mg_operating_mode_get(const stmdev_ctx_t *ctx,
734 ism303dac_mg_md_t *val)
735 {
736 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
737 int32_t ret;
738
739 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
740 (uint8_t *)&cfg_reg_a_m, 1);
741
742 switch (cfg_reg_a_m.md)
743 {
744 case ISM303DAC_MG_CONTINUOUS_MODE:
745 *val = ISM303DAC_MG_CONTINUOUS_MODE;
746 break;
747
748 case ISM303DAC_MG_SINGLE_TRIGGER:
749 *val = ISM303DAC_MG_SINGLE_TRIGGER;
750 break;
751
752 case ISM303DAC_MG_POWER_DOWN:
753 *val = ISM303DAC_MG_POWER_DOWN;
754 break;
755
756 default:
757 *val = ISM303DAC_MG_CONTINUOUS_MODE;
758 break;
759 }
760
761 return ret;
762 }
763
764 /**
765 * @brief Output data rate selection.[set]
766 *
767 * @param ctx read / write interface definitions.(ptr)
768 * @param val Change the values of odr in reg CFG_REG_A
769 * @retval Interface status (MANDATORY: return 0 -> no Error).
770 *
771 */
ism303dac_mg_data_rate_set(const stmdev_ctx_t * ctx,ism303dac_mg_odr_t val)772 int32_t ism303dac_mg_data_rate_set(const stmdev_ctx_t *ctx,
773 ism303dac_mg_odr_t val)
774 {
775 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
776 int32_t ret;
777
778 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
779 (uint8_t *)&cfg_reg_a_m, 1);
780
781 if (ret == 0)
782 {
783 cfg_reg_a_m.odr = (uint8_t)val;
784 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
785 (uint8_t *)&cfg_reg_a_m, 1);
786 }
787
788 return ret;
789 }
790
791 /**
792 * @brief Output data rate selection.[get]
793 *
794 * @param ctx read / write interface definitions.(ptr)
795 * @param val Get the values of odr in reg CFG_REG_A.(ptr)
796 * @retval Interface status (MANDATORY: return 0 -> no Error).
797 *
798 */
ism303dac_mg_data_rate_get(const stmdev_ctx_t * ctx,ism303dac_mg_odr_t * val)799 int32_t ism303dac_mg_data_rate_get(const stmdev_ctx_t *ctx,
800 ism303dac_mg_odr_t *val)
801 {
802 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
803 int32_t ret;
804
805 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
806 (uint8_t *)&cfg_reg_a_m, 1);
807
808 switch (cfg_reg_a_m.odr)
809 {
810 case ISM303DAC_MG_ODR_10Hz:
811 *val = ISM303DAC_MG_ODR_10Hz;
812 break;
813
814 case ISM303DAC_MG_ODR_20Hz:
815 *val = ISM303DAC_MG_ODR_20Hz;
816 break;
817
818 case ISM303DAC_MG_ODR_50Hz:
819 *val = ISM303DAC_MG_ODR_50Hz;
820 break;
821
822 case ISM303DAC_MG_ODR_100Hz:
823 *val = ISM303DAC_MG_ODR_100Hz;
824 break;
825
826 default:
827 *val = ISM303DAC_MG_ODR_10Hz;
828 break;
829 }
830
831 return ret;
832 }
833
834 /**
835 * @brief Enables high-resolution/low-power mode.[set]
836 *
837 * @param ctx read / write interface definitions.(ptr)
838 * @param val Change the values of lp in reg CFG_REG_A
839 * @retval Interface status (MANDATORY: return 0 -> no Error).
840 *
841 */
ism303dac_mg_power_mode_set(const stmdev_ctx_t * ctx,ism303dac_mg_lp_t val)842 int32_t ism303dac_mg_power_mode_set(const stmdev_ctx_t *ctx,
843 ism303dac_mg_lp_t val)
844 {
845 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
846 int32_t ret;
847
848 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
849 (uint8_t *)&cfg_reg_a_m, 1);
850
851 if (ret == 0)
852 {
853 cfg_reg_a_m.lp = (uint8_t)val;
854 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
855 (uint8_t *)&cfg_reg_a_m, 1);
856 }
857
858 return ret;
859 }
860
861 /**
862 * @brief Enables high-resolution/low-power mode.[get]
863 *
864 * @param ctx read / write interface definitions.(ptr)
865 * @param val Get the values of lp in reg CFG_REG_A.(ptr)
866 * @retval Interface status (MANDATORY: return 0 -> no Error).
867 *
868 */
ism303dac_mg_power_mode_get(const stmdev_ctx_t * ctx,ism303dac_mg_lp_t * val)869 int32_t ism303dac_mg_power_mode_get(const stmdev_ctx_t *ctx,
870 ism303dac_mg_lp_t *val)
871 {
872 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
873 int32_t ret;
874
875 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
876 (uint8_t *)&cfg_reg_a_m, 1);
877
878 switch (cfg_reg_a_m.lp)
879 {
880 case ISM303DAC_MG_HIGH_RESOLUTION:
881 *val = ISM303DAC_MG_HIGH_RESOLUTION;
882 break;
883
884 case ISM303DAC_MG_LOW_POWER:
885 *val = ISM303DAC_MG_LOW_POWER;
886 break;
887
888 default:
889 *val = ISM303DAC_MG_HIGH_RESOLUTION;
890 break;
891 }
892
893 return ret;
894 }
895
896 /**
897 * @brief Enables the magnetometer temperature compensation.[set]
898 *
899 * @param ctx read / write interface definitions.(ptr)
900 * @param val Change the values of comp_temp_en in reg CFG_REG_A
901 * @retval Interface status (MANDATORY: return 0 -> no Error).
902 *
903 */
ism303dac_mg_offset_temp_comp_set(const stmdev_ctx_t * ctx,uint8_t val)904 int32_t ism303dac_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx,
905 uint8_t val)
906 {
907 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
908 int32_t ret;
909
910 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
911 (uint8_t *)&cfg_reg_a_m, 1);
912
913 if (ret == 0)
914 {
915 cfg_reg_a_m.comp_temp_en = val;
916 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
917 (uint8_t *)&cfg_reg_a_m, 1);
918 }
919
920 return ret;
921 }
922
923 /**
924 * @brief Enables the magnetometer temperature compensation.[get]
925 *
926 * @param ctx read / write interface definitions.(ptr)
927 * @param val Change the values of comp_temp_en in reg CFG_REG_A.(ptr)
928 * @retval Interface status (MANDATORY: return 0 -> no Error).
929 *
930 */
ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t * ctx,uint8_t * val)931 int32_t ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx,
932 uint8_t *val)
933 {
934 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
935 int32_t ret;
936
937 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
938 (uint8_t *)&cfg_reg_a_m, 1);
939 *val = cfg_reg_a_m.comp_temp_en;
940
941 return ret;
942 }
943
944 /**
945 * @brief set_rst_mode: [set]
946 *
947 * @param ctx read / write interface definitions.(ptr)
948 * @param val Change the values of set_rst in reg CFG_REG_B
949 * @retval Interface status (MANDATORY: return 0 -> no Error).
950 *
951 */
ism303dac_mg_set_rst_mode_set(const stmdev_ctx_t * ctx,ism303dac_mg_set_rst_t val)952 int32_t ism303dac_mg_set_rst_mode_set(const stmdev_ctx_t *ctx,
953 ism303dac_mg_set_rst_t val)
954 {
955 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
956 int32_t ret;
957
958 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
959 (uint8_t *)&cfg_reg_b_m, 1);
960
961 if (ret == 0)
962 {
963 cfg_reg_b_m.set_rst = (uint8_t)val;
964 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
965 (uint8_t *)&cfg_reg_b_m, 1);
966 }
967
968 return ret;
969 }
970
971 /**
972 * @brief set_rst_mode: [get]
973 *
974 * @param ctx read / write interface definitions.(ptr)
975 * @param val Get the values of set_rst in reg CFG_REG_B.(ptr)
976 * @retval Interface status (MANDATORY: return 0 -> no Error).
977 *
978 */
ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t * ctx,ism303dac_mg_set_rst_t * val)979 int32_t ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t *ctx,
980 ism303dac_mg_set_rst_t *val)
981 {
982 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
983 int32_t ret;
984
985 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
986 (uint8_t *)&cfg_reg_b_m, 1);
987
988 switch (cfg_reg_b_m.set_rst)
989 {
990 case ISM303DAC_MG_SET_SENS_ODR_DIV_63:
991 *val = ISM303DAC_MG_SET_SENS_ODR_DIV_63;
992 break;
993
994 case ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR:
995 *val = ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR;
996 break;
997
998 case ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON:
999 *val = ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON;
1000 break;
1001
1002 default:
1003 *val = ISM303DAC_MG_SET_SENS_ODR_DIV_63;
1004 break;
1005 }
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Enables offset cancellation in single measurement mode.
1012 * The OFF_CANC bit must be set to 1 when enabling offset cancellation
1013 * in single measurement mode this means a call function: set_rst_mode
1014 * (SENS_OFF_CANC_EVERY_ODR) is need.[set]
1015 *
1016 * @param ctx read / write interface definitions.(ptr)
1017 * @param val Change the values of off_canc_one_shot in reg CFG_REG_B
1018 * @retval Interface status (MANDATORY: return 0 -> no Error).
1019 *
1020 */
ism303dac_mg_set_rst_sensor_single_set(const stmdev_ctx_t * ctx,uint8_t val)1021 int32_t ism303dac_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx,
1022 uint8_t val)
1023 {
1024 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
1025 int32_t ret;
1026
1027 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
1028 (uint8_t *)&cfg_reg_b_m, 1);
1029
1030 if (ret == 0)
1031 {
1032 cfg_reg_b_m.off_canc_one_shot = val;
1033 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
1034 (uint8_t *)&cfg_reg_b_m, 1);
1035 }
1036
1037 return ret;
1038 }
1039
1040 /**
1041 * @brief Enables offset cancellation in single measurement mode.
1042 * The OFF_CANC bit must be set to 1 when enabling offset cancellation
1043 * in single measurement mode this means a call function: set_rst_mode
1044 * (SENS_OFF_CANC_EVERY_ODR) is need.[get]
1045 *
1046 * @param ctx read / write interface definitions.(ptr)
1047 * @param val Get the values of off_canc_one_shot in reg CFG_REG_B.(ptr)
1048 * @retval Interface status (MANDATORY: return 0 -> no Error).
1049 *
1050 */
ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t * ctx,uint8_t * val)1051 int32_t ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx,
1052 uint8_t *val)
1053 {
1054 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
1055 int32_t ret;
1056
1057 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
1058 (uint8_t *)&cfg_reg_b_m, 1);
1059 *val = cfg_reg_b_m.off_canc_one_shot;
1060
1061 return ret;
1062 }
1063
1064 /**
1065 * @}
1066 *
1067 */
1068
1069 /**
1070 * @defgroup ISM303DAC_Dataoutput
1071 * @brief This section groups all the data output functions.
1072 * @{
1073 *
1074 */
1075
1076 /**
1077 * @brief Module output value (8-bit).[get]
1078 *
1079 * @param ctx read / write interface definitions.(ptr)
1080 * @param buff buffer that stores data read
1081 * @retval Interface status (MANDATORY: return 0 -> no Error).
1082 *
1083 */
ism303dac_acceleration_module_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1084 int32_t ism303dac_acceleration_module_raw_get(const stmdev_ctx_t *ctx,
1085 uint8_t *buff)
1086 {
1087 int32_t ret;
1088
1089 ret = ism303dac_read_reg(ctx, ISM303DAC_MODULE_8BIT_A, buff, 1);
1090
1091 return ret;
1092 }
1093
1094 /**
1095 * @brief Temperature data output register (r). L and H registers together
1096 * express a 16-bit word in two’s complement.[get]
1097 *
1098 * @param ctx read / write interface definitions.(ptr)
1099 * @param buff buffer that stores data read
1100 * @retval Interface status (MANDATORY: return 0 -> no Error).
1101 *
1102 */
ism303dac_xl_temperature_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1103 int32_t ism303dac_xl_temperature_raw_get(const stmdev_ctx_t *ctx,
1104 uint8_t *buff)
1105 {
1106 int32_t ret;
1107
1108 ret = ism303dac_read_reg(ctx, ISM303DAC_OUT_T_A, buff, 1);
1109
1110 return ret;
1111 }
1112
1113 /**
1114 * @brief Linear acceleration output register. The value is expressed as a
1115 * 16-bit word in two’s complement.[get]
1116 *
1117 * @param ctx read / write interface definitions.(ptr)
1118 * @param buff buffer that stores data read
1119 * @retval Interface status (MANDATORY: return 0 -> no Error).
1120 *
1121 */
ism303dac_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1122 int32_t ism303dac_acceleration_raw_get(const stmdev_ctx_t *ctx,
1123 int16_t *val)
1124 {
1125 uint8_t buff[6];
1126 int32_t ret;
1127
1128 ret = ism303dac_read_reg(ctx, ISM303DAC_OUT_X_L_A, buff, 6);
1129 val[0] = (int16_t)buff[1];
1130 val[0] = (val[0] * 256) + (int16_t)buff[0];
1131 val[1] = (int16_t)buff[3];
1132 val[1] = (val[1] * 256) + (int16_t)buff[2];
1133 val[2] = (int16_t)buff[5];
1134 val[2] = (val[2] * 256) + (int16_t)buff[4];
1135
1136 return ret;
1137 }
1138
1139 /**
1140 * @brief Magnetic output value.[get]
1141 *
1142 * @param ctx read / write interface definitions.(ptr)
1143 * @param buff buffer that stores data read
1144 * @retval Interface status (MANDATORY: return 0 -> no Error).
1145 *
1146 */
ism303dac_magnetic_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1147 int32_t ism303dac_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1148 {
1149 uint8_t buff[6];
1150 int32_t ret;
1151
1152 ret = ism303dac_read_reg(ctx, ISM303DAC_OUTX_L_REG_M, buff, 6);
1153 val[0] = (int16_t)buff[1];
1154 val[0] = (val[0] * 256) + (int16_t)buff[0];
1155 val[1] = (int16_t)buff[3];
1156 val[1] = (val[1] * 256) + (int16_t)buff[2];
1157 val[2] = (int16_t)buff[5];
1158 val[2] = (val[2] * 256) + (int16_t)buff[4];
1159
1160 return ret;
1161 }
1162
1163 /**
1164 * @}
1165 *
1166 */
1167
1168 /**
1169 * @defgroup ISM303DAC_common
1170 * @brief This section groups common useful functions.
1171 * @{
1172 *
1173 */
1174
1175 /**
1176 * @brief DeviceWhoamI.[get]
1177 *
1178 * @param ctx read / write interface definitions.(ptr)
1179 * @param buff buffer that stores data read
1180 * @retval Interface status (MANDATORY: return 0 -> no Error).
1181 *
1182 */
ism303dac_xl_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1183 int32_t ism303dac_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1184 {
1185 int32_t ret;
1186
1187 ret = ism303dac_read_reg(ctx, ISM303DAC_WHO_AM_I_A, buff, 1);
1188
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief DeviceWhoamI.[get]
1194 *
1195 * @param ctx read / write interface definitions.(ptr)
1196 * @param buff buffer that stores data read
1197 * @retval Interface status (MANDATORY: return 0 -> no Error).
1198 *
1199 */
ism303dac_mg_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1200 int32_t ism303dac_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1201 {
1202 int32_t ret;
1203
1204 ret = ism303dac_read_reg(ctx, ISM303DAC_WHO_AM_I_M, buff, 1);
1205
1206 return ret;
1207 }
1208
1209 /**
1210 * @brief Register address automatically incremented during a multiple byte
1211 * access with a serial interface.[set]
1212 *
1213 * @param ctx read / write interface definitions.(ptr)
1214 * @param val Change the values of if_add_inc in reg CTRL2
1215 * @retval Interface status (MANDATORY: return 0 -> no Error).
1216 *
1217 */
ism303dac_xl_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1218 int32_t ism303dac_xl_auto_increment_set(const stmdev_ctx_t *ctx,
1219 uint8_t val)
1220 {
1221 ism303dac_ctrl2_a_t ctrl2_a;
1222 int32_t ret;
1223
1224 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1225
1226 if (ret == 0)
1227 {
1228 ctrl2_a.if_add_inc = val;
1229 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1230 }
1231
1232 return ret;
1233 }
1234
1235 /**
1236 * @brief Register address automatically incremented during a multiple byte
1237 * access with a serial interface.[get]
1238 *
1239 * @param ctx read / write interface definitions.(ptr)
1240 * @param val Get the values of if_add_inc in reg CTRL2.(ptr)
1241 * @retval Interface status (MANDATORY: return 0 -> no Error).
1242 *
1243 */
ism303dac_xl_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1244 int32_t ism303dac_xl_auto_increment_get(const stmdev_ctx_t *ctx,
1245 uint8_t *val)
1246 {
1247 ism303dac_ctrl2_a_t ctrl2_a;
1248 int32_t ret;
1249
1250 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1251 *val = ctrl2_a.if_add_inc;
1252
1253 return ret;
1254 }
1255
1256
1257 /**
1258 * @brief Software reset. Restore the default values in user registers.[set]
1259 *
1260 * @param ctx read / write interface definitions.(ptr)
1261 * @param val Change the values of soft_reset in reg CTRL2
1262 * @retval Interface status (MANDATORY: return 0 -> no Error).
1263 *
1264 */
ism303dac_xl_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1265 int32_t ism303dac_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1266 {
1267 ism303dac_ctrl2_a_t ctrl2_a;
1268 int32_t ret;
1269
1270 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1271
1272 if (ret == 0)
1273 {
1274 ctrl2_a.soft_reset = val;
1275 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1276 }
1277
1278 return ret;
1279 }
1280
1281 /**
1282 * @brief Software reset. Restore the default values in user registers.[get]
1283 *
1284 * @param ctx read / write interface definitions.(ptr)
1285 * @param val Get the values of soft_reset in reg CTRL2.(ptr)
1286 * @retval Interface status (MANDATORY: return 0 -> no Error).
1287 *
1288 */
ism303dac_xl_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1289 int32_t ism303dac_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1290 {
1291 ism303dac_ctrl2_a_t ctrl2_a;
1292 int32_t ret;
1293
1294 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1295 *val = ctrl2_a.soft_reset;
1296
1297 return ret;
1298 }
1299
1300 /**
1301 * @brief Software reset. Restore the default values in user registers.[set]
1302 *
1303 * @param ctx read / write interface definitions.(ptr)
1304 * @param val Change the values of soft_rst in reg CFG_REG_A
1305 * @retval Interface status (MANDATORY: return 0 -> no Error).
1306 *
1307 */
ism303dac_mg_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1308 int32_t ism303dac_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1309 {
1310 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
1311 int32_t ret;
1312
1313 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
1314 (uint8_t *)&cfg_reg_a_m, 1);
1315
1316 if (ret == 0)
1317 {
1318 cfg_reg_a_m.soft_rst = val;
1319 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
1320 (uint8_t *)&cfg_reg_a_m, 1);
1321 }
1322
1323 return ret;
1324 }
1325
1326 /**
1327 * @brief Software reset. Restore the default values in user registers.[get]
1328 *
1329 * @param ctx read / write interface definitions.(ptr)
1330 * @param val Get the values of soft_rst in reg CFG_REG_A.(ptr)
1331 * @retval Interface status (MANDATORY: return 0 -> no Error).
1332 *
1333 */
ism303dac_mg_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1334 int32_t ism303dac_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1335 {
1336 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
1337 int32_t ret;
1338
1339 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
1340 (uint8_t *)&cfg_reg_a_m, 1);
1341 *val = cfg_reg_a_m.soft_rst;
1342
1343 return ret;
1344 }
1345
1346 /**
1347 * @brief Reboot memory content. Reload the calibration parameters.[set]
1348 *
1349 * @param ctx read / write interface definitions.(ptr)
1350 * @param val Change the values of boot in reg CTRL2
1351 * @retval Interface status (MANDATORY: return 0 -> no Error).
1352 *
1353 */
ism303dac_xl_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1354 int32_t ism303dac_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1355 {
1356 ism303dac_ctrl2_a_t ctrl2_a;
1357 int32_t ret;
1358
1359 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1360
1361 if (ret == 0)
1362 {
1363 ctrl2_a.boot = val;
1364 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1365 }
1366
1367 return ret;
1368 }
1369
1370 /**
1371 * @brief Reboot memory content. Reload the calibration parameters.[get]
1372 *
1373 * @param ctx read / write interface definitions.(ptr)
1374 * @param val Get the values of boot in reg CTRL2.(ptr)
1375 * @retval Interface status (MANDATORY: return 0 -> no Error).
1376 *
1377 */
ism303dac_xl_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1378 int32_t ism303dac_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1379 {
1380 ism303dac_ctrl2_a_t ctrl2_a;
1381 int32_t ret;
1382
1383 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1384 *val = ctrl2_a.boot;
1385
1386 return ret;
1387 }
1388
1389 /**
1390 * @brief Reboot memory content. Reload the calibration parameters.[set]
1391 *
1392 * @param ctx read / write interface definitions.(ptr)
1393 * @param val Change the values of reboot in reg CFG_REG_A
1394 * @retval Interface status (MANDATORY: return 0 -> no Error).
1395 *
1396 */
ism303dac_mg_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1397 int32_t ism303dac_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1398 {
1399 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
1400 int32_t ret;
1401
1402 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
1403 (uint8_t *)&cfg_reg_a_m, 1);
1404
1405 if (ret == 0)
1406 {
1407 cfg_reg_a_m.reboot = val;
1408 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_A_M,
1409 (uint8_t *)&cfg_reg_a_m, 1);
1410 }
1411
1412 return ret;
1413 }
1414
1415 /**
1416 * @brief Reboot memory content. Reload the calibration parameters.[get]
1417 *
1418 * @param ctx read / write interface definitions.(ptr)
1419 * @param val Get the values of reboot in reg CFG_REG_A.(ptr)
1420 * @retval Interface status (MANDATORY: return 0 -> no Error).
1421 *
1422 */
ism303dac_mg_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1423 int32_t ism303dac_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1424 {
1425 ism303dac_cfg_reg_a_m_t cfg_reg_a_m;
1426 int32_t ret;
1427
1428 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M,
1429 (uint8_t *)&cfg_reg_a_m, 1);
1430 *val = cfg_reg_a_m.reboot;
1431
1432 return ret;
1433 }
1434
1435 /**
1436 * @brief xl_self_test: [set]
1437 *
1438 * @param ctx read / write interface definitions.(ptr)
1439 * @param val Change the values of st in reg CTRL3
1440 * @retval Interface status (MANDATORY: return 0 -> no Error).
1441 *
1442 */
ism303dac_xl_self_test_set(const stmdev_ctx_t * ctx,ism303dac_xl_st_t val)1443 int32_t ism303dac_xl_self_test_set(const stmdev_ctx_t *ctx,
1444 ism303dac_xl_st_t val)
1445 {
1446 ism303dac_ctrl3_a_t ctrl3_a;
1447 int32_t ret;
1448
1449 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
1450
1451 if (ret == 0)
1452 {
1453 ctrl3_a.st = (uint8_t)val;
1454 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
1455 }
1456
1457 return ret;
1458 }
1459
1460 /**
1461 * @brief xl_self_test: [get]
1462 *
1463 * @param ctx read / write interface definitions.(ptr)
1464 * @param val Get the values of st in reg CTRL3.(ptr)
1465 * @retval Interface status (MANDATORY: return 0 -> no Error).
1466 *
1467 */
ism303dac_xl_self_test_get(const stmdev_ctx_t * ctx,ism303dac_xl_st_t * val)1468 int32_t ism303dac_xl_self_test_get(const stmdev_ctx_t *ctx,
1469 ism303dac_xl_st_t *val)
1470 {
1471 ism303dac_ctrl3_a_t ctrl3_a;
1472 int32_t ret;
1473
1474 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
1475
1476 switch (ctrl3_a.st)
1477 {
1478 case ISM303DAC_XL_ST_DISABLE:
1479 *val = ISM303DAC_XL_ST_DISABLE;
1480 break;
1481
1482 case ISM303DAC_XL_ST_POSITIVE:
1483 *val = ISM303DAC_XL_ST_POSITIVE;
1484 break;
1485
1486 case ISM303DAC_XL_ST_NEGATIVE:
1487 *val = ISM303DAC_XL_ST_NEGATIVE;
1488 break;
1489
1490 default:
1491 *val = ISM303DAC_XL_ST_DISABLE;
1492 break;
1493 }
1494
1495 return ret;
1496 }
1497
1498 /**
1499 * @brief Selftest.[set]
1500 *
1501 * @param ctx read / write interface definitions.(ptr)
1502 * @param val Change the values of self_test in reg CFG_REG_C
1503 * @retval Interface status (MANDATORY: return 0 -> no Error).
1504 *
1505 */
ism303dac_mg_self_test_set(const stmdev_ctx_t * ctx,uint8_t val)1506 int32_t ism303dac_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
1507 {
1508 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
1509 int32_t ret;
1510
1511 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
1512 (uint8_t *)&cfg_reg_c_m, 1);
1513
1514 if (ret == 0)
1515 {
1516 cfg_reg_c_m.self_test = val;
1517 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
1518 (uint8_t *)&cfg_reg_c_m, 1);
1519 }
1520
1521 return ret;
1522 }
1523
1524 /**
1525 * @brief Selftest.[get]
1526 *
1527 * @param ctx read / write interface definitions.(ptr)
1528 * @param val Get the values of self_test in reg CFG_REG_C.(ptr)
1529 * @retval Interface status (MANDATORY: return 0 -> no Error).
1530 *
1531 */
ism303dac_mg_self_test_get(const stmdev_ctx_t * ctx,uint8_t * val)1532 int32_t ism303dac_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
1533 {
1534 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
1535 int32_t ret;
1536
1537 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
1538 (uint8_t *)&cfg_reg_c_m, 1);
1539 *val = cfg_reg_c_m.self_test;
1540
1541 return ret;
1542 }
1543
1544 /**
1545 * @brief data_ready_mode: [set]
1546 *
1547 * @param ctx read / write interface definitions.(ptr)
1548 * @param val Change the values of drdy_pulsed in reg CTRL5
1549 * @retval Interface status (MANDATORY: return 0 -> no Error).
1550 *
1551 */
ism303dac_xl_data_ready_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_drdy_pulsed_t val)1552 int32_t ism303dac_xl_data_ready_mode_set(const stmdev_ctx_t *ctx,
1553 ism303dac_xl_drdy_pulsed_t val)
1554 {
1555 ism303dac_ctrl5_a_t ctrl5_a;
1556 int32_t ret;
1557
1558 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
1559
1560 if (ret == 0)
1561 {
1562 ctrl5_a.drdy_pulsed = (uint8_t)val;
1563 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
1564 }
1565
1566 return ret;
1567 }
1568
1569 /**
1570 * @brief data_ready_mode: [get]
1571 *
1572 * @param ctx read / write interface definitions.(ptr)
1573 * @param val Get the values of drdy_pulsed in reg CTRL5.(ptr)
1574 * @retval Interface status (MANDATORY: return 0 -> no Error).
1575 *
1576 */
ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_drdy_pulsed_t * val)1577 int32_t ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t *ctx,
1578 ism303dac_xl_drdy_pulsed_t *val)
1579 {
1580 ism303dac_ctrl5_a_t ctrl5_a;
1581 int32_t ret;
1582
1583 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
1584
1585 switch (ctrl5_a.drdy_pulsed)
1586 {
1587 case ISM303DAC_XL_DRDY_LATCHED:
1588 *val = ISM303DAC_XL_DRDY_LATCHED;
1589 break;
1590
1591 case ISM303DAC_XL_DRDY_PULSED:
1592 *val = ISM303DAC_XL_DRDY_PULSED;
1593 break;
1594
1595 default:
1596 *val = ISM303DAC_XL_DRDY_LATCHED;
1597 break;
1598 }
1599
1600 return ret;
1601 }
1602
1603 /**
1604 * @}
1605 *
1606 */
1607
1608 /**
1609 * @defgroup ISM303DAC_Filters
1610 * @brief This section group all the functions concerning the filters
1611 * configuration.
1612 * @{
1613 *
1614 */
1615
1616 /**
1617 * @brief High-pass filter data selection on output register and FIFO.[set]
1618 *
1619 * @param ctx read / write interface definitions.(ptr)
1620 * @param val Change the values of fds_slope in reg CTRL2
1621 * @retval Interface status (MANDATORY: return 0 -> no Error).
1622 *
1623 */
ism303dac_xl_hp_path_set(const stmdev_ctx_t * ctx,ism303dac_xl_fds_slope_t val)1624 int32_t ism303dac_xl_hp_path_set(const stmdev_ctx_t *ctx,
1625 ism303dac_xl_fds_slope_t val)
1626 {
1627 ism303dac_ctrl2_a_t ctrl2_a;
1628 int32_t ret;
1629
1630 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1631
1632 if (ret == 0)
1633 {
1634 ctrl2_a.fds_slope = (uint8_t)val;
1635 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1636 }
1637
1638 return ret;
1639 }
1640
1641 /**
1642 * @brief High-pass filter data selection on output register and FIFO.[get]
1643 *
1644 * @param ctx read / write interface definitions.(ptr)
1645 * @param val Get the values of fds_slope in reg CTRL2.(ptr)
1646 * @retval Interface status (MANDATORY: return 0 -> no Error).
1647 *
1648 */
ism303dac_xl_hp_path_get(const stmdev_ctx_t * ctx,ism303dac_xl_fds_slope_t * val)1649 int32_t ism303dac_xl_hp_path_get(const stmdev_ctx_t *ctx,
1650 ism303dac_xl_fds_slope_t *val)
1651 {
1652 ism303dac_ctrl2_a_t ctrl2_a;
1653 int32_t ret;
1654
1655 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1656
1657 switch (ctrl2_a.fds_slope)
1658 {
1659 case ISM303DAC_XL_HP_INTERNAL_ONLY:
1660 *val = ISM303DAC_XL_HP_INTERNAL_ONLY;
1661 break;
1662
1663 case ISM303DAC_XL_HP_ON_OUTPUTS:
1664 *val = ISM303DAC_XL_HP_ON_OUTPUTS;
1665 break;
1666
1667 default:
1668 *val = ISM303DAC_XL_HP_INTERNAL_ONLY;
1669 break;
1670 }
1671
1672 return ret;
1673 }
1674
1675 /**
1676 * @brief Low-pass bandwidth selection.[set]
1677 *
1678 * @param ctx read / write interface definitions.(ptr)
1679 * @param val Change the values of lpf in reg CFG_REG_B
1680 * @retval Interface status (MANDATORY: return 0 -> no Error).
1681 *
1682 */
ism303dac_mg_low_pass_bandwidth_set(const stmdev_ctx_t * ctx,ism303dac_mg_lpf_t val)1683 int32_t ism303dac_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx,
1684 ism303dac_mg_lpf_t val)
1685 {
1686 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
1687 int32_t ret;
1688
1689 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
1690 (uint8_t *)&cfg_reg_b_m, 1);
1691
1692 if (ret == 0)
1693 {
1694 cfg_reg_b_m.lpf = (uint8_t)val;
1695 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
1696 (uint8_t *)&cfg_reg_b_m, 1);
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief Low-pass bandwidth selection.[get]
1704 *
1705 * @param ctx read / write interface definitions.(ptr)
1706 * @param val Get the values of lpf in reg CFG_REG_B.(ptr)
1707 * @retval Interface status (MANDATORY: return 0 -> no Error).
1708 *
1709 */
ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t * ctx,ism303dac_mg_lpf_t * val)1710 int32_t ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx,
1711 ism303dac_mg_lpf_t *val)
1712 {
1713 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
1714 int32_t ret;
1715
1716 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
1717 (uint8_t *)&cfg_reg_b_m, 1);
1718
1719 switch (cfg_reg_b_m.lpf)
1720 {
1721 case ISM303DAC_MG_ODR_DIV_2:
1722 *val = ISM303DAC_MG_ODR_DIV_2;
1723 break;
1724
1725 case ISM303DAC_MG_ODR_DIV_4:
1726 *val = ISM303DAC_MG_ODR_DIV_4;
1727 break;
1728
1729 default:
1730 *val = ISM303DAC_MG_ODR_DIV_2;
1731 break;
1732 }
1733
1734 return ret;
1735 }
1736
1737 /**
1738 * @}
1739 *
1740 */
1741
1742 /**
1743 * @defgroup ISM303DAC_ Auxiliary_interface
1744 * @brief This section groups all the functions concerning auxiliary
1745 * interface.
1746 * @{
1747 *
1748 */
1749
1750 /**
1751 * @brief SPI Serial Interface Mode selection.[set]
1752 *
1753 * @param ctx read / write interface definitions.(ptr)
1754 * @param val Change the values of sim in reg CTRL2
1755 * @retval Interface status (MANDATORY: return 0 -> no Error).
1756 *
1757 */
ism303dac_xl_spi_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_sim_t val)1758 int32_t ism303dac_xl_spi_mode_set(const stmdev_ctx_t *ctx,
1759 ism303dac_xl_sim_t val)
1760 {
1761 ism303dac_ctrl2_a_t ctrl2_a;
1762 int32_t ret;
1763
1764 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1765
1766 if (ret == 0)
1767 {
1768 ctrl2_a.sim = (uint8_t)val;
1769 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1770 }
1771
1772 return ret;
1773 }
1774
1775 /**
1776 * @brief SPI Serial Interface Mode selection.[get]
1777 *
1778 * @param ctx read / write interface definitions.(ptr)
1779 * @param val Get the values of sim in reg CTRL2.(ptr)
1780 * @retval Interface status (MANDATORY: return 0 -> no Error).
1781 *
1782 */
ism303dac_xl_spi_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_sim_t * val)1783 int32_t ism303dac_xl_spi_mode_get(const stmdev_ctx_t *ctx,
1784 ism303dac_xl_sim_t *val)
1785 {
1786 ism303dac_ctrl2_a_t ctrl2_a;
1787 int32_t ret;
1788
1789 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1790
1791 switch (ctrl2_a.sim)
1792 {
1793 case ISM303DAC_XL_SPI_4_WIRE:
1794 *val = ISM303DAC_XL_SPI_4_WIRE;
1795 break;
1796
1797 case ISM303DAC_XL_SPI_3_WIRE:
1798 *val = ISM303DAC_XL_SPI_3_WIRE;
1799 break;
1800
1801 default:
1802 *val = ISM303DAC_XL_SPI_4_WIRE;
1803 break;
1804 }
1805
1806 return ret;
1807 }
1808
1809 /**
1810 * @brief Disable / Enable I2C interface.[set]
1811 *
1812 * @param ctx read / write interface definitions.(ptr)
1813 * @param val Change the values of i2c_disable in reg CTRL2
1814 * @retval Interface status (MANDATORY: return 0 -> no Error).
1815 *
1816 */
ism303dac_xl_i2c_interface_set(const stmdev_ctx_t * ctx,ism303dac_xl_i2c_disable_t val)1817 int32_t ism303dac_xl_i2c_interface_set(const stmdev_ctx_t *ctx,
1818 ism303dac_xl_i2c_disable_t val)
1819 {
1820 ism303dac_ctrl2_a_t ctrl2_a;
1821 int32_t ret;
1822
1823 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1824
1825 if (ret == 0)
1826 {
1827 ctrl2_a.i2c_disable = (uint8_t)val;
1828 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1829 }
1830
1831 return ret;
1832 }
1833
1834 /**
1835 * @brief Disable / Enable I2C interface.[get]
1836 *
1837 * @param ctx read / write interface definitions.(ptr)
1838 * @param val Get the values of i2c_disable in reg CTRL2.(ptr)
1839 * @retval Interface status (MANDATORY: return 0 -> no Error).
1840 *
1841 */
ism303dac_xl_i2c_interface_get(const stmdev_ctx_t * ctx,ism303dac_xl_i2c_disable_t * val)1842 int32_t ism303dac_xl_i2c_interface_get(const stmdev_ctx_t *ctx,
1843 ism303dac_xl_i2c_disable_t *val)
1844 {
1845 ism303dac_ctrl2_a_t ctrl2_a;
1846 int32_t ret;
1847
1848 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1);
1849
1850 switch (ctrl2_a.i2c_disable)
1851 {
1852 case ISM303DAC_XL_I2C_ENABLE:
1853 *val = ISM303DAC_XL_I2C_ENABLE;
1854 break;
1855
1856 case ISM303DAC_XL_I2C_DISABLE:
1857 *val = ISM303DAC_XL_I2C_DISABLE;
1858 break;
1859
1860 default:
1861 *val = ISM303DAC_XL_I2C_ENABLE;
1862 break;
1863 }
1864
1865 return ret;
1866 }
1867
1868 /**
1869 * @brief Enable/Disable I2C interface.[set]
1870 *
1871 * @param ctx read / write interface definitions.(ptr)
1872 * @param val Change the values of i2c_dis in reg CFG_REG_C
1873 * @retval Interface status (MANDATORY: return 0 -> no Error).
1874 *
1875 */
ism303dac_mg_i2c_interface_set(const stmdev_ctx_t * ctx,ism303dac_mg_i2c_dis_t val)1876 int32_t ism303dac_mg_i2c_interface_set(const stmdev_ctx_t *ctx,
1877 ism303dac_mg_i2c_dis_t val)
1878 {
1879 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
1880 int32_t ret;
1881
1882 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
1883 (uint8_t *)&cfg_reg_c_m, 1);
1884
1885 if (ret == 0)
1886 {
1887 cfg_reg_c_m.i2c_dis = (uint8_t)val;
1888 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
1889 (uint8_t *)&cfg_reg_c_m, 1);
1890 }
1891
1892 return ret;
1893 }
1894
1895 /**
1896 * @brief Enable/Disable I2C interface.[get]
1897 *
1898 * @param ctx read / write interface definitions.(ptr)
1899 * @param val Get the values of i2c_dis in reg CFG_REG_C.(ptr)
1900 * @retval Interface status (MANDATORY: return 0 -> no Error).
1901 *
1902 */
ism303dac_mg_i2c_interface_get(const stmdev_ctx_t * ctx,ism303dac_mg_i2c_dis_t * val)1903 int32_t ism303dac_mg_i2c_interface_get(const stmdev_ctx_t *ctx,
1904 ism303dac_mg_i2c_dis_t *val)
1905 {
1906 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
1907 int32_t ret;
1908
1909 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
1910 (uint8_t *)&cfg_reg_c_m, 1);
1911
1912 switch (cfg_reg_c_m.i2c_dis)
1913 {
1914 case ISM303DAC_MG_I2C_ENABLE:
1915 *val = ISM303DAC_MG_I2C_ENABLE;
1916 break;
1917
1918 case ISM303DAC_MG_I2C_DISABLE:
1919 *val = ISM303DAC_MG_I2C_DISABLE;
1920 break;
1921
1922 default:
1923 *val = ISM303DAC_MG_I2C_ENABLE;
1924 break;
1925 }
1926
1927 return ret;
1928 }
1929
1930 /**
1931 * @brief Connect/Disconnects pull-up in if_cs pad.[set]
1932 *
1933 * @param ctx read / write interface definitions.(ptr)
1934 * @param ism303dac_xl_if_cs_pu_dis_t: change the values of if_cs_pu_dis
1935 * in reg FIFO_CTRL
1936 * @retval Interface status (MANDATORY: return 0 -> no Error).
1937 *
1938 */
ism303dac_xl_cs_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_if_cs_pu_dis_t val)1939 int32_t ism303dac_xl_cs_mode_set(const stmdev_ctx_t *ctx,
1940 ism303dac_xl_if_cs_pu_dis_t val)
1941 {
1942 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
1943 int32_t ret;
1944
1945 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
1946 (uint8_t *)&fifo_ctrl_a, 1);
1947
1948 if (ret == 0)
1949 {
1950 fifo_ctrl_a.if_cs_pu_dis = (uint8_t)val;
1951 ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
1952 (uint8_t *)&fifo_ctrl_a, 1);
1953 }
1954
1955 return ret;
1956 }
1957
1958 /**
1959 * @brief Connect/Disconnects pull-up in if_cs pad.[get]
1960 *
1961 * @param ctx read / write interface definitions.(ptr)
1962 * @param val Get the values of if_cs_pu_dis in reg FIFO_CTRL.(ptr)
1963 * @retval Interface status (MANDATORY: return 0 -> no Error).
1964 *
1965 */
ism303dac_xl_cs_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_if_cs_pu_dis_t * val)1966 int32_t ism303dac_xl_cs_mode_get(const stmdev_ctx_t *ctx,
1967 ism303dac_xl_if_cs_pu_dis_t *val)
1968 {
1969 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
1970 int32_t ret;
1971
1972 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
1973 (uint8_t *)&fifo_ctrl_a, 1);
1974
1975 switch (fifo_ctrl_a.if_cs_pu_dis)
1976 {
1977 case ISM303DAC_XL_PULL_UP_CONNECTED:
1978 *val = ISM303DAC_XL_PULL_UP_CONNECTED;
1979 break;
1980
1981 case ISM303DAC_XL_PULL_UP_DISCONNECTED:
1982 *val = ISM303DAC_XL_PULL_UP_DISCONNECTED;
1983 break;
1984
1985 default:
1986 *val = ISM303DAC_XL_PULL_UP_CONNECTED;
1987 break;
1988 }
1989
1990 return ret;
1991 }
1992
1993 /**
1994 * @}
1995 *
1996 */
1997
1998 /**
1999 * @defgroup ISM303DAC_ main_serial_interface
2000 * @brief This section groups all the functions concerning main serial
2001 * interface management (not auxiliary)
2002 * @{
2003 *
2004 */
2005
2006 /**
2007 * @brief Push-pull/open-drain selection on interrupt pad.[set]
2008 *
2009 * @param ctx read / write interface definitions.(ptr)
2010 * @param val Change the values of pp_od in reg CTRL3
2011 * @retval Interface status (MANDATORY: return 0 -> no Error).
2012 *
2013 */
ism303dac_xl_pin_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_pp_od_t val)2014 int32_t ism303dac_xl_pin_mode_set(const stmdev_ctx_t *ctx,
2015 ism303dac_xl_pp_od_t val)
2016 {
2017 ism303dac_ctrl3_a_t ctrl3_a;
2018 int32_t ret;
2019
2020 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2021
2022 if (ret == 0)
2023 {
2024 ctrl3_a.pp_od = (uint8_t)val;
2025 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2026 }
2027
2028 return ret;
2029 }
2030
2031 /**
2032 * @brief Push-pull/open-drain selection on interrupt pad.[get]
2033 *
2034 * @param ctx read / write interface definitions.(ptr)
2035 * @param val Get the values of pp_od in reg CTRL3.(ptr)
2036 * @retval Interface status (MANDATORY: return 0 -> no Error).
2037 *
2038 */
ism303dac_xl_pin_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_pp_od_t * val)2039 int32_t ism303dac_xl_pin_mode_get(const stmdev_ctx_t *ctx,
2040 ism303dac_xl_pp_od_t *val)
2041 {
2042 ism303dac_ctrl3_a_t ctrl3_a;
2043 int32_t ret;
2044
2045 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2046
2047 switch (ctrl3_a.pp_od)
2048 {
2049 case ISM303DAC_XL_PUSH_PULL:
2050 *val = ISM303DAC_XL_PUSH_PULL;
2051 break;
2052
2053 case ISM303DAC_XL_OPEN_DRAIN:
2054 *val = ISM303DAC_XL_OPEN_DRAIN;
2055 break;
2056
2057 default:
2058 *val = ISM303DAC_XL_PUSH_PULL;
2059 break;
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Interrupt active-high/low.[set]
2067 *
2068 * @param ctx read / write interface definitions.(ptr)
2069 * @param val Change the values of h_lactive in reg CTRL3
2070 * @retval Interface status (MANDATORY: return 0 -> no Error).
2071 *
2072 */
ism303dac_xl_pin_polarity_set(const stmdev_ctx_t * ctx,ism303dac_xl_h_lactive_t val)2073 int32_t ism303dac_xl_pin_polarity_set(const stmdev_ctx_t *ctx,
2074 ism303dac_xl_h_lactive_t val)
2075 {
2076 ism303dac_ctrl3_a_t ctrl3_a;
2077 int32_t ret;
2078
2079 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2080
2081 if (ret == 0)
2082 {
2083 ctrl3_a.h_lactive = (uint8_t)val;
2084 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2085 }
2086
2087 return ret;
2088 }
2089
2090 /**
2091 * @brief Interrupt active-high/low.[get]
2092 *
2093 * @param ctx read / write interface definitions.(ptr)
2094 * @param val Get the values of h_lactive in reg CTRL3.(ptr)
2095 * @retval Interface status (MANDATORY: return 0 -> no Error).
2096 *
2097 */
ism303dac_xl_pin_polarity_get(const stmdev_ctx_t * ctx,ism303dac_xl_h_lactive_t * val)2098 int32_t ism303dac_xl_pin_polarity_get(const stmdev_ctx_t *ctx,
2099 ism303dac_xl_h_lactive_t *val)
2100 {
2101 ism303dac_ctrl3_a_t ctrl3_a;
2102 int32_t ret;
2103
2104 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2105
2106 switch (ctrl3_a.h_lactive)
2107 {
2108 case ISM303DAC_XL_ACTIVE_HIGH:
2109 *val = ISM303DAC_XL_ACTIVE_HIGH;
2110 break;
2111
2112 case ISM303DAC_XL_ACTIVE_LOW:
2113 *val = ISM303DAC_XL_ACTIVE_LOW;
2114 break;
2115
2116 default:
2117 *val = ISM303DAC_XL_ACTIVE_HIGH;
2118 break;
2119 }
2120
2121 return ret;
2122 }
2123
2124 /**
2125 * @brief Latched/pulsed interrupt.[set]
2126 *
2127 * @param ctx read / write interface definitions.(ptr)
2128 * @param val Change the values of lir in reg CTRL3
2129 * @retval Interface status (MANDATORY: return 0 -> no Error).
2130 *
2131 */
ism303dac_xl_int_notification_set(const stmdev_ctx_t * ctx,ism303dac_xl_lir_t val)2132 int32_t ism303dac_xl_int_notification_set(const stmdev_ctx_t *ctx,
2133 ism303dac_xl_lir_t val)
2134 {
2135 ism303dac_ctrl3_a_t ctrl3_a;
2136 int32_t ret;
2137
2138 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2139
2140 if (ret == 0)
2141 {
2142 ctrl3_a.lir = (uint8_t)val;
2143 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2144 }
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Latched/pulsed interrupt.[get]
2151 *
2152 * @param ctx read / write interface definitions.(ptr)
2153 * @param val Get the values of lir in reg CTRL3.(ptr)
2154 * @retval Interface status (MANDATORY: return 0 -> no Error).
2155 *
2156 */
ism303dac_xl_int_notification_get(const stmdev_ctx_t * ctx,ism303dac_xl_lir_t * val)2157 int32_t ism303dac_xl_int_notification_get(const stmdev_ctx_t *ctx,
2158 ism303dac_xl_lir_t *val)
2159 {
2160 ism303dac_ctrl3_a_t ctrl3_a;
2161 int32_t ret;
2162
2163 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2164
2165 switch (ctrl3_a.lir)
2166 {
2167 case ISM303DAC_XL_INT_PULSED:
2168 *val = ISM303DAC_XL_INT_PULSED;
2169 break;
2170
2171 case ISM303DAC_XL_INT_LATCHED:
2172 *val = ISM303DAC_XL_INT_LATCHED;
2173 break;
2174
2175 default:
2176 *val = ISM303DAC_XL_INT_PULSED;
2177 break;
2178 }
2179
2180 return ret;
2181 }
2182
2183 /**
2184 * @brief Select the signal that need to route on int1 pad.[set]
2185 *
2186 * @param ctx read / write interface definitions.(ptr)
2187 * @param val Change union of registers from CTRL4 to
2188 * @retval Interface status (MANDATORY: return 0 -> no Error).
2189 *
2190 */
ism303dac_xl_pin_int1_route_set(const stmdev_ctx_t * ctx,ism303dac_xl_pin_int1_route_t val)2191 int32_t ism303dac_xl_pin_int1_route_set(const stmdev_ctx_t *ctx,
2192 ism303dac_xl_pin_int1_route_t val)
2193 {
2194 ism303dac_ctrl4_a_t ctrl4_a;
2195 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2196 int32_t ret;
2197
2198 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
2199
2200 if (ret == 0)
2201 {
2202 ctrl4_a.int1_drdy = val.int1_drdy;
2203 ctrl4_a.int1_fth = val.int1_fth;
2204 ctrl4_a.int1_6d = val.int1_6d;
2205 ctrl4_a.int1_tap = val.int1_tap;
2206 ctrl4_a.int1_ff = val.int1_ff;
2207 ctrl4_a.int1_wu = val.int1_wu;
2208 ctrl4_a.int1_s_tap = val.int1_s_tap;
2209 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
2210 }
2211
2212 if (ret == 0)
2213 {
2214 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2215 (uint8_t *)&wake_up_dur_a, 1);
2216 }
2217
2218 if (ret == 0)
2219 {
2220 wake_up_dur_a.int1_fss7 = val.int1_fss7;
2221 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2222 (uint8_t *)&wake_up_dur_a, 1);
2223 }
2224
2225 return ret;
2226 }
2227
2228 /**
2229 * @brief Select the signal that need to route on int1 pad.[get]
2230 *
2231 * @param ctx read / write interface definitions.(ptr)
2232 * @param val Get union of registers from CTRL4 to.(ptr)
2233 * @retval Interface status (MANDATORY: return 0 -> no Error).
2234 *
2235 */
ism303dac_xl_pin_int1_route_get(const stmdev_ctx_t * ctx,ism303dac_xl_pin_int1_route_t * val)2236 int32_t ism303dac_xl_pin_int1_route_get(const stmdev_ctx_t *ctx,
2237 ism303dac_xl_pin_int1_route_t *val)
2238 {
2239 ism303dac_ctrl4_a_t ctrl4_a;
2240 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2241 int32_t ret;
2242
2243 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL4_A, (uint8_t *)&ctrl4_a, 1);
2244
2245 if (ret == 0)
2246 {
2247 val->int1_drdy = ctrl4_a.int1_drdy;
2248 val->int1_fth = ctrl4_a.int1_fth;
2249 val->int1_6d = ctrl4_a.int1_6d;
2250 val->int1_tap = ctrl4_a.int1_tap;
2251 val->int1_ff = ctrl4_a.int1_ff;
2252 val->int1_wu = ctrl4_a.int1_wu;
2253 val->int1_s_tap = ctrl4_a.int1_s_tap;
2254 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2255 (uint8_t *)&wake_up_dur_a, 1);
2256 }
2257
2258 if (ret == 0)
2259 {
2260 val->int1_fss7 = wake_up_dur_a.int1_fss7;
2261 }
2262
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief Select the signal that need to route on int2 pad.[set]
2268 *
2269 * @param ctx read / write interface definitions.(ptr)
2270 * @param val Change union of registers from CTRL5 to
2271 * @retval Interface status (MANDATORY: return 0 -> no Error).
2272 *
2273 */
ism303dac_xl_pin_int2_route_set(const stmdev_ctx_t * ctx,ism303dac_xl_pin_int2_route_t val)2274 int32_t ism303dac_xl_pin_int2_route_set(const stmdev_ctx_t *ctx,
2275 ism303dac_xl_pin_int2_route_t val)
2276 {
2277 ism303dac_ctrl5_a_t ctrl5_a;
2278 int32_t ret;
2279
2280 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2281
2282 if (ret == 0)
2283 {
2284 ctrl5_a.int2_boot = val.int2_boot;
2285 ctrl5_a.int2_fth = val.int2_fth;
2286 ctrl5_a.int2_drdy = val.int2_drdy;
2287 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2288 }
2289
2290 return ret;
2291 }
2292
2293 /**
2294 * @brief Select the signal that need to route on int2 pad.[get]
2295 *
2296 * @param ctx read / write interface definitions.(ptr)
2297 * @param val Get union of registers from CTRL5 to.(ptr)
2298 * @retval Interface status (MANDATORY: return 0 -> no Error).
2299 *
2300 */
ism303dac_xl_pin_int2_route_get(const stmdev_ctx_t * ctx,ism303dac_xl_pin_int2_route_t * val)2301 int32_t ism303dac_xl_pin_int2_route_get(const stmdev_ctx_t *ctx,
2302 ism303dac_xl_pin_int2_route_t *val)
2303 {
2304 ism303dac_ctrl5_a_t ctrl5_a;
2305 int32_t ret;
2306
2307 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2308
2309 if (ret == 0)
2310 {
2311 val->int2_boot = ctrl5_a.int2_boot;
2312 val->int2_fth = ctrl5_a.int2_fth;
2313 val->int2_drdy = ctrl5_a.int2_drdy;
2314 }
2315
2316 return ret;
2317 }
2318
2319 /**
2320 * @brief All interrupt signals become available on INT1 pin.[set]
2321 *
2322 * @param ctx read / write interface definitions.(ptr)
2323 * @param val Change the values of int2_on_int1 in reg CTRL5
2324 * @retval Interface status (MANDATORY: return 0 -> no Error).
2325 *
2326 */
ism303dac_xl_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)2327 int32_t ism303dac_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
2328 {
2329 ism303dac_ctrl5_a_t ctrl5_a;
2330 int32_t ret;
2331
2332 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2333
2334 if (ret == 0)
2335 {
2336 ctrl5_a.int2_on_int1 = val;
2337 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2338 }
2339
2340 return ret;
2341 }
2342
2343 /**
2344 * @brief All interrupt signals become available on INT1 pin.[get]
2345 *
2346 * @param ctx read / write interface definitions.(ptr)
2347 * @param val Get the values of int2_on_int1 in reg CTRL5.(ptr)
2348 * @retval Interface status (MANDATORY: return 0 -> no Error).
2349 *
2350 */
ism303dac_xl_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)2351 int32_t ism303dac_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2352 {
2353 ism303dac_ctrl5_a_t ctrl5_a;
2354 int32_t ret;
2355
2356 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1);
2357 *val = ctrl5_a.int2_on_int1;
2358
2359 return ret;
2360 }
2361
2362 /**
2363 * @brief Data-ready signal on INT_DRDY pin.[set]
2364 *
2365 * @param ctx read / write interface definitions.(ptr)
2366 * @param val Change the values of drdy_on_pin in reg CFG_REG_C
2367 * @retval Interface status (MANDATORY: return 0 -> no Error).
2368 *
2369 */
ism303dac_mg_drdy_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)2370 int32_t ism303dac_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
2371 {
2372 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
2373 int32_t ret;
2374
2375 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
2376 (uint8_t *)&cfg_reg_c_m, 1);
2377
2378 if (ret == 0)
2379 {
2380 cfg_reg_c_m.int_mag = val;
2381 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
2382 (uint8_t *)&cfg_reg_c_m, 1);
2383 }
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * @brief Data-ready signal on INT_DRDY pin.[get]
2390 *
2391 * @param ctx read / write interface definitions.(ptr)
2392 * @param val Get the values of drdy_on_pin in reg CFG_REG_C_M.(ptr)
2393 * @retval Interface status (MANDATORY: return 0 -> no Error).
2394 *
2395 */
ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)2396 int32_t ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
2397 {
2398 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
2399 int32_t ret;
2400
2401 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
2402 (uint8_t *)&cfg_reg_c_m, 1);
2403 *val = cfg_reg_c_m.int_mag;
2404
2405 return ret;
2406 }
2407
2408 /**
2409 * @brief Interrupt signal on INT_DRDY pin.[set]
2410 *
2411 * @param ctx read / write interface definitions.(ptr)
2412 * @param val Change the values of int_on_pin in reg CFG_REG_C_M
2413 * @retval Interface status (MANDATORY: return 0 -> no Error).
2414 *
2415 */
ism303dac_mg_int_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)2416 int32_t ism303dac_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
2417 {
2418 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
2419 int32_t ret;
2420
2421 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
2422 (uint8_t *)&cfg_reg_c_m, 1);
2423
2424 if (ret == 0)
2425 {
2426 cfg_reg_c_m.int_mag_pin = val;
2427 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_C_M,
2428 (uint8_t *)&cfg_reg_c_m, 1);
2429 }
2430
2431 return ret;
2432 }
2433
2434 /**
2435 * @brief Interrupt signal on INT_DRDY pin.[get]
2436 *
2437 * @param ctx read / write interface definitions.(ptr)
2438 * @param val Get the values of int_on_pin in reg CFG_REG_C_M.(ptr)
2439 * @retval Interface status (MANDATORY: return 0 -> no Error).
2440 *
2441 */
ism303dac_mg_int_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)2442 int32_t ism303dac_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
2443 {
2444 ism303dac_cfg_reg_c_m_t cfg_reg_c_m;
2445 int32_t ret;
2446
2447 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M,
2448 (uint8_t *)&cfg_reg_c_m, 1);
2449 *val = cfg_reg_c_m.int_mag_pin;
2450
2451 return ret;
2452 }
2453
2454 /**
2455 * @brief Interrupt generator configuration register.[set]
2456 *
2457 * @param ctx read / write interface definitions.(ptr)
2458 * @param val Change registers INT_CRTL_REG.(ptr)
2459 * @retval Interface status (MANDATORY: return 0 -> no Error).
2460 *
2461 */
ism303dac_mg_int_gen_conf_set(const stmdev_ctx_t * ctx,ism303dac_int_crtl_reg_m_t * val)2462 int32_t ism303dac_mg_int_gen_conf_set(const stmdev_ctx_t *ctx,
2463 ism303dac_int_crtl_reg_m_t *val)
2464 {
2465 int32_t ret;
2466
2467 ret = ism303dac_write_reg(ctx, ISM303DAC_INT_CRTL_REG_M,
2468 (uint8_t *) val, 1);
2469
2470 return ret;
2471 }
2472
2473 /**
2474 * @brief Interrupt generator configuration register.[get]
2475 *
2476 * @param ctx read / write interface definitions.(ptr)
2477 * @param val Get registers INT_CRTL_REG.(ptr)
2478 * @retval Interface status (MANDATORY: return 0 -> no Error).
2479 *
2480 */
ism303dac_mg_int_gen_conf_get(const stmdev_ctx_t * ctx,ism303dac_int_crtl_reg_m_t * val)2481 int32_t ism303dac_mg_int_gen_conf_get(const stmdev_ctx_t *ctx,
2482 ism303dac_int_crtl_reg_m_t *val)
2483 {
2484 int32_t ret;
2485
2486 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_CRTL_REG_M,
2487 (uint8_t *) val, 1);
2488
2489 return ret;
2490 }
2491
2492 /**
2493 * @brief Interrupt generator source register.[get]
2494 *
2495 * @param ctx read / write interface definitions.(ptr)
2496 * @param val Get registers INT_SOURCE_REG.(ptr)
2497 * @retval Interface status (MANDATORY: return 0 -> no Error).
2498 *
2499 */
ism303dac_mg_int_gen_source_get(const stmdev_ctx_t * ctx,ism303dac_int_source_reg_m_t * val)2500 int32_t ism303dac_mg_int_gen_source_get(const stmdev_ctx_t *ctx,
2501 ism303dac_int_source_reg_m_t *val)
2502 {
2503 int32_t ret;
2504
2505 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_SOURCE_REG_M,
2506 (uint8_t *) val, 1);
2507
2508 return ret;
2509 }
2510
2511 /**
2512 * @brief User-defined threshold value for xl interrupt event on generator.
2513 * Data format is the same of output data raw: two’s complement with
2514 * 1LSb = 1.5mG.[set]
2515 *
2516 * @param ctx read / write interface definitions.(ptr)
2517 * @param buff buffer that contains data to write
2518 * @retval Interface status (MANDATORY: return 0 -> no Error).
2519 *
2520 */
ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)2521 int32_t ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx,
2522 uint16_t val)
2523 {
2524 uint8_t buff[2];
2525 int32_t ret;
2526
2527 buff[1] = (uint8_t)(val / 256U);
2528 buff[0] = (uint8_t)(val - (buff[1] * 256U));
2529 ret = ism303dac_write_reg(ctx, ISM303DAC_INT_THS_L_REG_M, buff, 2);
2530
2531 return ret;
2532 }
2533
2534 /**
2535 * @brief User-defined threshold value for xl interrupt event on generator.
2536 * Data format is the same of output data raw: two’s complement with
2537 * 1LSb = 1.5mG.[get]
2538 *
2539 * @param ctx read / write interface definitions.(ptr)
2540 * @param buff buffer that stores data read
2541 * @retval Interface status (MANDATORY: return 0 -> no Error).
2542 *
2543 */
ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)2544 int32_t ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx,
2545 uint16_t *val)
2546 {
2547 uint8_t buff[2];
2548 int32_t ret;
2549
2550 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_THS_L_REG_M, buff, 2);
2551 *val = buff[1];
2552 *val = (*val * 256U) + buff[0];
2553
2554 return ret;
2555 }
2556
2557 /**
2558 * @}
2559 *
2560 */
2561
2562 /**
2563 * @defgroup ISM303DAC_interrupt_pins
2564 * @brief This section groups all the functions that manage interrupt pins
2565 * @{
2566 *
2567 */
2568
2569 /**
2570 * @}
2571 *
2572 */
2573
2574 /**
2575 * @defgroup ISM303DAC_Wake_Up_event
2576 * @brief This section groups all the functions that manage the Wake Up
2577 * event generation.
2578 * @{
2579 *
2580 */
2581
2582 /**
2583 * @brief The interrupt block recognition checks data after/before the
2584 * hard-iron correction to discover the interrupt.[set]
2585 *
2586 * @param ctx read / write interface definitions.(ptr)
2587 * @param val Change the values of int_on_dataoff in reg CFG_REG_B
2588 * @retval Interface status (MANDATORY: return 0 -> no Error).
2589 *
2590 */
ism303dac_mg_offset_int_conf_set(const stmdev_ctx_t * ctx,ism303dac_mg_int_on_dataoff_t val)2591 int32_t ism303dac_mg_offset_int_conf_set(const stmdev_ctx_t *ctx,
2592 ism303dac_mg_int_on_dataoff_t val)
2593 {
2594 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
2595 int32_t ret;
2596
2597 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
2598 (uint8_t *)&cfg_reg_b_m, 1);
2599
2600 if (ret == 0)
2601 {
2602 cfg_reg_b_m.int_on_dataoff = (uint8_t)val;
2603 ret = ism303dac_write_reg(ctx, ISM303DAC_CFG_REG_B_M,
2604 (uint8_t *)&cfg_reg_b_m, 1);
2605 }
2606
2607 return ret;
2608 }
2609
2610 /**
2611 * @brief The interrupt block recognition checks data after/before the
2612 * hard-iron correction to discover the interrupt.[get]
2613 *
2614 * @param ctx read / write interface definitions.(ptr)
2615 * @param val Get the values of int_on_dataoff in reg CFG_REG_B.(ptr)
2616 * @retval Interface status (MANDATORY: return 0 -> no Error).
2617 *
2618 */
ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t * ctx,ism303dac_mg_int_on_dataoff_t * val)2619 int32_t ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t *ctx,
2620 ism303dac_mg_int_on_dataoff_t *val)
2621 {
2622 ism303dac_cfg_reg_b_m_t cfg_reg_b_m;
2623 int32_t ret;
2624
2625 ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M,
2626 (uint8_t *)&cfg_reg_b_m, 1);
2627
2628 switch (cfg_reg_b_m.int_on_dataoff)
2629 {
2630 case ISM303DAC_MG_CHECK_BEFORE:
2631 *val = ISM303DAC_MG_CHECK_BEFORE;
2632 break;
2633
2634 case ISM303DAC_MG_CHECK_AFTER:
2635 *val = ISM303DAC_MG_CHECK_AFTER;
2636 break;
2637
2638 default:
2639 *val = ISM303DAC_MG_CHECK_BEFORE;
2640 break;
2641 }
2642
2643 return ret;
2644 }
2645
2646 /**
2647 * @brief Threshold for wakeup [1 LSb = FS_XL / 64].[set]
2648 *
2649 * @param ctx read / write interface definitions.(ptr)
2650 * @param val Change the values of wu_ths in reg WAKE_UP_THS
2651 * @retval Interface status (MANDATORY: return 0 -> no Error).
2652 *
2653 */
ism303dac_xl_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2654 int32_t ism303dac_xl_wkup_threshold_set(const stmdev_ctx_t *ctx,
2655 uint8_t val)
2656 {
2657 ism303dac_wake_up_ths_a_t wake_up_ths_a;
2658 int32_t ret;
2659
2660 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2661 (uint8_t *)&wake_up_ths_a, 1);
2662
2663 if (ret == 0)
2664 {
2665 wake_up_ths_a.wu_ths = val;
2666 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2667 (uint8_t *)&wake_up_ths_a, 1);
2668 }
2669
2670 return ret;
2671 }
2672
2673 /**
2674 * @brief Threshold for wakeup [1 LSb = FS_XL / 64].[get]
2675 *
2676 * @param ctx read / write interface definitions.(ptr)
2677 * @param val Get the values of wu_ths in reg WAKE_UP_THS.(ptr)
2678 * @retval Interface status (MANDATORY: return 0 -> no Error).
2679 *
2680 */
ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2681 int32_t ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t *ctx,
2682 uint8_t *val)
2683 {
2684 ism303dac_wake_up_ths_a_t wake_up_ths_a;
2685 int32_t ret;
2686
2687 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2688 (uint8_t *)&wake_up_ths_a, 1);
2689 *val = wake_up_ths_a.wu_ths;
2690
2691 return ret;
2692 }
2693
2694 /**
2695 * @brief Wakeup duration [1 LSb = 1 / ODR].[set]
2696 *
2697 * @param ctx read / write interface definitions.(ptr)
2698 * @param val Change the values of wu_dur in reg WAKE_UP_DUR
2699 * @retval Interface status (MANDATORY: return 0 -> no Error).
2700 *
2701 */
ism303dac_xl_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2702 int32_t ism303dac_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2703 {
2704 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2705 int32_t ret;
2706
2707 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2708 (uint8_t *)&wake_up_dur_a, 1);
2709
2710 if (ret == 0)
2711 {
2712 wake_up_dur_a.wu_dur = val;
2713 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2714 (uint8_t *)&wake_up_dur_a, 1);
2715 }
2716
2717 return ret;
2718 }
2719
2720 /**
2721 * @brief Wakeup duration [1 LSb = 1 / ODR].[get]
2722 *
2723 * @param ctx read / write interface definitions.(ptr)
2724 * @param val Get the values of wu_dur in reg WAKE_UP_DUR.(ptr)
2725 * @retval Interface status (MANDATORY: return 0 -> no Error).
2726 *
2727 */
ism303dac_xl_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2728 int32_t ism303dac_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2729 {
2730 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2731 int32_t ret;
2732
2733 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2734 (uint8_t *)&wake_up_dur_a, 1);
2735 *val = wake_up_dur_a.wu_dur;
2736
2737 return ret;
2738 }
2739
2740 /**
2741 * @}
2742 *
2743 */
2744
2745 /**
2746 * @defgroup ISM303DAC_ Activity/Inactivity_detection
2747 * @brief This section groups all the functions concerning
2748 * activity/inactivity detection.
2749 * @{
2750 *
2751 */
2752
2753 /**
2754 * @brief Enables gyroscope Sleep mode.[set]
2755 *
2756 * @param ctx read / write interface definitions.(ptr)
2757 * @param val Change the values of sleep_on in reg WAKE_UP_THS
2758 * @retval Interface status (MANDATORY: return 0 -> no Error).
2759 *
2760 */
ism303dac_xl_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2761 int32_t ism303dac_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2762 {
2763 ism303dac_wake_up_ths_a_t wake_up_ths_a;
2764 int32_t ret;
2765
2766 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2767 (uint8_t *)&wake_up_ths_a, 1);
2768
2769 if (ret == 0)
2770 {
2771 wake_up_ths_a.sleep_on = val;
2772 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2773 (uint8_t *)&wake_up_ths_a, 1);
2774 }
2775
2776 return ret;
2777 }
2778
2779 /**
2780 * @brief Enables gyroscope Sleep mode.[get]
2781 *
2782 * @param ctx read / write interface definitions.(ptr)
2783 * @param val Get the values of sleep_on in reg WAKE_UP_THS.(ptr)
2784 * @retval Interface status (MANDATORY: return 0 -> no Error).
2785 *
2786 */
ism303dac_xl_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2787 int32_t ism303dac_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2788 {
2789 ism303dac_wake_up_ths_a_t wake_up_ths_a;
2790 int32_t ret;
2791
2792 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
2793 (uint8_t *)&wake_up_ths_a, 1);
2794 *val = wake_up_ths_a.sleep_on;
2795
2796 return ret;
2797 }
2798
2799 /**
2800 * @brief Duration to go in sleep mode [1 LSb = 512 / ODR].[set]
2801 *
2802 * @param ctx read / write interface definitions.(ptr)
2803 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
2804 * @retval Interface status (MANDATORY: return 0 -> no Error).
2805 *
2806 */
ism303dac_xl_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2807 int32_t ism303dac_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2808 {
2809 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2810 int32_t ret;
2811
2812 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2813 (uint8_t *)&wake_up_dur_a, 1);
2814
2815 if (ret == 0)
2816 {
2817 wake_up_dur_a.sleep_dur = val;
2818 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2819 (uint8_t *)&wake_up_dur_a, 1);
2820 }
2821
2822 return ret;
2823 }
2824
2825 /**
2826 * @brief Duration to go in sleep mode [1 LSb = 512 / ODR].[get]
2827 *
2828 * @param ctx read / write interface definitions.(ptr)
2829 * @param val Get the values of sleep_dur in reg WAKE_UP_DUR.(ptr)
2830 * @retval Interface status (MANDATORY: return 0 -> no Error).
2831 *
2832 */
ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2833 int32_t ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx,
2834 uint8_t *val)
2835 {
2836 ism303dac_wake_up_dur_a_t wake_up_dur_a;
2837 int32_t ret;
2838
2839 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
2840 (uint8_t *)&wake_up_dur_a, 1);
2841 *val = wake_up_dur_a.sleep_dur;
2842
2843 return ret;
2844 }
2845
2846 /**
2847 * @}
2848 *
2849 */
2850
2851 /**
2852 * @defgroup ISM303DAC_tap_generator
2853 * @brief This section groups all the functions that manage the tap and
2854 * double tap event generation.
2855 * @{
2856 *
2857 */
2858
2859 /**
2860 * @brief Enable Z direction in tap recognition.[set]
2861 *
2862 * @param ctx read / write interface definitions.(ptr)
2863 * @param val Change the values of tap_z_en in reg CTRL3
2864 * @retval Interface status (MANDATORY: return 0 -> no Error).
2865 *
2866 */
ism303dac_xl_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)2867 int32_t ism303dac_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
2868 uint8_t val)
2869 {
2870 ism303dac_ctrl3_a_t ctrl3_a;
2871 int32_t ret;
2872
2873 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2874
2875 if (ret == 0)
2876 {
2877 ctrl3_a.tap_z_en = val;
2878 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2879 }
2880
2881 return ret;
2882 }
2883
2884 /**
2885 * @brief Enable Z direction in tap recognition.[get]
2886 *
2887 * @param ctx read / write interface definitions.(ptr)
2888 * @param val Get the values of tap_z_en in reg CTRL3.(ptr)
2889 * @retval Interface status (MANDATORY: return 0 -> no Error).
2890 *
2891 */
ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2892 int32_t ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
2893 uint8_t *val)
2894 {
2895 ism303dac_ctrl3_a_t ctrl3_a;
2896 int32_t ret;
2897
2898 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2899 *val = ctrl3_a.tap_z_en;
2900
2901 return ret;
2902 }
2903
2904 /**
2905 * @brief Enable Y direction in tap recognition.[set]
2906 *
2907 * @param ctx read / write interface definitions.(ptr)
2908 * @param val Change the values of tap_y_en in reg CTRL3
2909 * @retval Interface status (MANDATORY: return 0 -> no Error).
2910 *
2911 */
ism303dac_xl_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)2912 int32_t ism303dac_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
2913 uint8_t val)
2914 {
2915 ism303dac_ctrl3_a_t ctrl3_a;
2916 int32_t ret;
2917
2918 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2919
2920 if (ret == 0)
2921 {
2922 ctrl3_a.tap_y_en = val;
2923 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2924 }
2925
2926 return ret;
2927 }
2928
2929 /**
2930 * @brief Enable Y direction in tap recognition.[get]
2931 *
2932 * @param ctx read / write interface definitions.(ptr)
2933 * @param val Get the values of tap_y_en in reg CTRL3.(ptr)
2934 * @retval Interface status (MANDATORY: return 0 -> no Error).
2935 *
2936 */
ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2937 int32_t ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
2938 uint8_t *val)
2939 {
2940 ism303dac_ctrl3_a_t ctrl3_a;
2941 int32_t ret;
2942
2943 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2944 *val = ctrl3_a.tap_y_en;
2945
2946 return ret;
2947 }
2948
2949 /**
2950 * @brief Enable X direction in tap recognition.[set]
2951 *
2952 * @param ctx read / write interface definitions.(ptr)
2953 * @param val Change the values of tap_x_en in reg CTRL3
2954 * @retval Interface status (MANDATORY: return 0 -> no Error).
2955 *
2956 */
ism303dac_xl_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)2957 int32_t ism303dac_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
2958 uint8_t val)
2959 {
2960 ism303dac_ctrl3_a_t ctrl3_a;
2961 int32_t ret;
2962
2963 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2964
2965 if (ret == 0)
2966 {
2967 ctrl3_a.tap_x_en = val;
2968 ret = ism303dac_write_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2969 }
2970
2971 return ret;
2972 }
2973
2974 /**
2975 * @brief Enable X direction in tap recognition.[get]
2976 *
2977 * @param ctx read / write interface definitions.(ptr)
2978 * @param val Get the values of tap_x_en in reg CTRL3.(ptr)
2979 * @retval Interface status (MANDATORY: return 0 -> no Error).
2980 *
2981 */
ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2982 int32_t ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
2983 uint8_t *val)
2984 {
2985 ism303dac_ctrl3_a_t ctrl3_a;
2986 int32_t ret;
2987
2988 ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1);
2989 *val = ctrl3_a.tap_x_en;
2990
2991 return ret;
2992 }
2993
2994 /**
2995 * @brief Threshold for tap recognition [1 LSb = FS/32].[set]
2996 *
2997 * @param ctx read / write interface definitions.(ptr)
2998 * @param val Change the values of tap_ths in reg TAP_6D_THS
2999 * @retval Interface status (MANDATORY: return 0 -> no Error).
3000 *
3001 */
ism303dac_xl_tap_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3002 int32_t ism303dac_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3003 {
3004 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3005 int32_t ret;
3006
3007 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3008 (uint8_t *)&tap_6d_ths_a, 1);
3009
3010 if (ret == 0)
3011 {
3012 tap_6d_ths_a.tap_ths = val;
3013 ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3014 (uint8_t *)&tap_6d_ths_a, 1);
3015 }
3016
3017 return ret;
3018 }
3019
3020 /**
3021 * @brief Threshold for tap recognition [1 LSb = FS/32].[get]
3022 *
3023 * @param ctx read / write interface definitions.(ptr)
3024 * @param val Get the values of tap_ths in reg TAP_6D_THS.(ptr)
3025 * @retval Interface status (MANDATORY: return 0 -> no Error).
3026 *
3027 */
ism303dac_xl_tap_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3028 int32_t ism303dac_xl_tap_threshold_get(const stmdev_ctx_t *ctx,
3029 uint8_t *val)
3030 {
3031 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3032 int32_t ret;
3033
3034 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3035 (uint8_t *)&tap_6d_ths_a, 1);
3036 *val = tap_6d_ths_a.tap_ths;
3037
3038 return ret;
3039 }
3040
3041 /**
3042 * @brief Maximum duration is the maximum time of an overthreshold
3043 * signal detection to be recognized as a tap event. The default
3044 * value of these bits is 00b which corresponds to 4*ODR_XL time.
3045 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3046 * corresponds to 8*ODR_XL time.[set]
3047 *
3048 * @param ctx read / write interface definitions.(ptr)
3049 * @param val Change the values of shock in reg INT_DUR
3050 * @retval Interface status (MANDATORY: return 0 -> no Error).
3051 *
3052 */
ism303dac_xl_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)3053 int32_t ism303dac_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
3054 {
3055 ism303dac_int_dur_a_t int_dur_a;
3056 int32_t ret;
3057
3058 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3059 (uint8_t *)&int_dur_a, 1);
3060
3061 if (ret == 0)
3062 {
3063 int_dur_a.shock = val;
3064 ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
3065 (uint8_t *)&int_dur_a, 1);
3066 }
3067
3068 return ret;
3069 }
3070
3071 /**
3072 * @brief Maximum duration is the maximum time of an overthreshold
3073 * signal detection to be recognized as a tap event. The default
3074 * value of these bits is 00b which corresponds to 4*ODR_XL time.
3075 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3076 * corresponds to 8*ODR_XL time.[get]
3077 *
3078 * @param ctx read / write interface definitions.(ptr)
3079 * @param val Get the values of shock in reg INT_DUR.(ptr)
3080 * @retval Interface status (MANDATORY: return 0 -> no Error).
3081 *
3082 */
ism303dac_xl_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)3083 int32_t ism303dac_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
3084 {
3085 ism303dac_int_dur_a_t int_dur_a;
3086 int32_t ret;
3087
3088 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3089 (uint8_t *)&int_dur_a, 1);
3090 *val = int_dur_a.shock;
3091
3092 return ret;
3093 }
3094
3095 /**
3096 * @brief Quiet time is the time after the first detected tap in which there
3097 * must not be any overthreshold event. The default value of these
3098 * bits is 00b which corresponds to 2*ODR_XL time.
3099 * If the QUIET[1:0] bits are set to a different value,
3100 * 1LSB corresponds to 4*ODR_XL time.[set]
3101 *
3102 * @param ctx read / write interface definitions.(ptr)
3103 * @param val Change the values of quiet in reg INT_DUR
3104 * @retval Interface status (MANDATORY: return 0 -> no Error).
3105 *
3106 */
ism303dac_xl_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)3107 int32_t ism303dac_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
3108 {
3109 ism303dac_int_dur_a_t int_dur_a;
3110 int32_t ret;
3111
3112 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3113 (uint8_t *)&int_dur_a, 1);
3114
3115 if (ret == 0)
3116 {
3117 int_dur_a.quiet = val;
3118 ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
3119 (uint8_t *)&int_dur_a, 1);
3120 }
3121
3122 return ret;
3123 }
3124
3125 /**
3126 * @brief Quiet time is the time after the first detected tap in which there
3127 * must not be any overthreshold event. The default value of these
3128 * bits is 00b which corresponds to 2*ODR_XL time.
3129 * If the QUIET[1:0] bits are set to a different value,
3130 * 1LSB corresponds to 4*ODR_XL time.[get]
3131 *
3132 * @param ctx read / write interface definitions.(ptr)
3133 * @param val Get the values of quiet in reg INT_DUR.(ptr)
3134 * @retval Interface status (MANDATORY: return 0 -> no Error).
3135 *
3136 */
ism303dac_xl_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)3137 int32_t ism303dac_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
3138 {
3139 ism303dac_int_dur_a_t int_dur_a;
3140 int32_t ret;
3141
3142 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3143 (uint8_t *)&int_dur_a, 1);
3144 *val = int_dur_a.quiet;
3145
3146 return ret;
3147 }
3148
3149 /**
3150 * @brief When double tap recognition is enabled, this register expresses the
3151 * maximum time between two consecutive detected taps to determine a
3152 * double tap event. The default value of these bits is 0000b which
3153 * corresponds to 16*ODR_XL time.
3154 * If the DUR[3:0] bits are set to a different value,
3155 * 1LSB corresponds to 32*ODR_XL time.[set]
3156 *
3157 * @param ctx read / write interface definitions.(ptr)
3158 * @param val Change the values of lat in reg INT_DUR
3159 * @retval Interface status (MANDATORY: return 0 -> no Error).
3160 *
3161 */
ism303dac_xl_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3162 int32_t ism303dac_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3163 {
3164 ism303dac_int_dur_a_t int_dur_a;
3165 int32_t ret;
3166
3167 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3168 (uint8_t *)&int_dur_a, 1);
3169
3170 if (ret == 0)
3171 {
3172 int_dur_a.lat = val;
3173 ret = ism303dac_write_reg(ctx, ISM303DAC_INT_DUR_A,
3174 (uint8_t *)&int_dur_a, 1);
3175 }
3176
3177 return ret;
3178 }
3179
3180 /**
3181 * @brief When double tap recognition is enabled, this register expresses the
3182 * maximum time between two consecutive detected taps to determine a
3183 * double tap event. The default value of these bits is 0000b which
3184 * corresponds to 16*ODR_XL time.
3185 * If the DUR[3:0] bits are set to a different value,
3186 * 1LSB corresponds to 32*ODR_XL time.[get]
3187 *
3188 * @param ctx read / write interface definitions.(ptr)
3189 * @param val Get the values of lat in reg INT_DUR.(ptr)
3190 * @retval Interface status (MANDATORY: return 0 -> no Error).
3191 *
3192 */
ism303dac_xl_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3193 int32_t ism303dac_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3194 {
3195 ism303dac_int_dur_a_t int_dur_a;
3196 int32_t ret;
3197
3198 ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A,
3199 (uint8_t *)&int_dur_a, 1);
3200 *val = int_dur_a.lat;
3201
3202 return ret;
3203 }
3204
3205 /**
3206 * @brief Single/double-tap event enable/disable.[set]
3207 *
3208 * @param ctx read / write interface definitions.(ptr)
3209 * @param val Change the values of single_double_tap in regWAKE_UP_THS
3210 * @retval Interface status (MANDATORY: return 0 -> no Error).
3211 *
3212 */
ism303dac_xl_tap_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_single_double_tap_t val)3213 int32_t ism303dac_xl_tap_mode_set(const stmdev_ctx_t *ctx,
3214 ism303dac_xl_single_double_tap_t val)
3215 {
3216 ism303dac_wake_up_ths_a_t wake_up_ths_a;
3217 int32_t ret;
3218
3219 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
3220 (uint8_t *)&wake_up_ths_a, 1);
3221
3222 if (ret == 0)
3223 {
3224 wake_up_ths_a.single_double_tap = (uint8_t)val;
3225 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
3226 (uint8_t *)&wake_up_ths_a, 1);
3227 }
3228
3229 return ret;
3230 }
3231
3232 /**
3233 * @brief Single/double-tap event enable/disable.[get]
3234 *
3235 * @param ctx read / write interface definitions.(ptr)
3236 * @param val Get the values of single_double_tap in reg WAKE_UP_THS.(ptr)
3237 * @retval Interface status (MANDATORY: return 0 -> no Error).
3238 *
3239 */
ism303dac_xl_tap_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_single_double_tap_t * val)3240 int32_t ism303dac_xl_tap_mode_get(const stmdev_ctx_t *ctx,
3241 ism303dac_xl_single_double_tap_t *val)
3242 {
3243 ism303dac_wake_up_ths_a_t wake_up_ths_a;
3244 int32_t ret;
3245
3246 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A,
3247 (uint8_t *)&wake_up_ths_a, 1);
3248
3249 switch (wake_up_ths_a.single_double_tap)
3250 {
3251 case ISM303DAC_XL_ONLY_SINGLE:
3252 *val = ISM303DAC_XL_ONLY_SINGLE;
3253 break;
3254
3255 case ISM303DAC_XL_ONLY_DOUBLE:
3256 *val = ISM303DAC_XL_ONLY_DOUBLE;
3257 break;
3258
3259 default:
3260 *val = ISM303DAC_XL_ONLY_SINGLE;
3261 break;
3262 }
3263
3264 return ret;
3265 }
3266
3267 /**
3268 * @brief TAP source register[get]
3269 *
3270 * @param ctx read / write interface definitions.(ptr)
3271 * @param val Get registers TAP_SRC.(ptr)
3272 * @retval Interface status (MANDATORY: return 0 -> no Error).
3273 *
3274 */
ism303dac_xl_tap_src_get(const stmdev_ctx_t * ctx,ism303dac_tap_src_a_t * val)3275 int32_t ism303dac_xl_tap_src_get(const stmdev_ctx_t *ctx,
3276 ism303dac_tap_src_a_t *val)
3277 {
3278 int32_t ret;
3279
3280 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_SRC_A, (uint8_t *) val, 1);
3281
3282 return ret;
3283 }
3284
3285 /**
3286 * @}
3287 *
3288 */
3289
3290 /**
3291 * @defgroup ISM303DAC_ Six_position_detection(6D/4D)
3292 * @brief This section groups all the functions concerning six
3293 * position detection (6D).
3294 * @{
3295 *
3296 */
3297
3298 /**
3299 * @brief Threshold for 4D/6D function.[set]
3300 *
3301 * @param ctx read / write interface definitions.(ptr)
3302 * @param val Change the values of 6d_ths in reg TAP_6D_THS
3303 * @retval Interface status (MANDATORY: return 0 -> no Error).
3304 *
3305 */
ism303dac_xl_6d_threshold_set(const stmdev_ctx_t * ctx,ism303dac_xl_6d_ths_t val)3306 int32_t ism303dac_xl_6d_threshold_set(const stmdev_ctx_t *ctx,
3307 ism303dac_xl_6d_ths_t val)
3308 {
3309 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3310 int32_t ret;
3311
3312 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3313 (uint8_t *)&tap_6d_ths_a, 1);
3314
3315 if (ret == 0)
3316 {
3317 tap_6d_ths_a._6d_ths = (uint8_t)val;
3318 ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3319 (uint8_t *)&tap_6d_ths_a, 1);
3320 }
3321
3322 return ret;
3323 }
3324
3325 /**
3326 * @brief Threshold for 4D/6D function.[get]
3327 *
3328 * @param ctx read / write interface definitions.(ptr)
3329 * @param val Get the values of 6d_ths in reg TAP_6D_THS.(ptr)
3330 * @retval Interface status (MANDATORY: return 0 -> no Error).
3331 *
3332 */
ism303dac_xl_6d_threshold_get(const stmdev_ctx_t * ctx,ism303dac_xl_6d_ths_t * val)3333 int32_t ism303dac_xl_6d_threshold_get(const stmdev_ctx_t *ctx,
3334 ism303dac_xl_6d_ths_t *val)
3335 {
3336 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3337 int32_t ret;
3338
3339 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3340 (uint8_t *)&tap_6d_ths_a, 1);
3341
3342 switch (tap_6d_ths_a._6d_ths)
3343 {
3344 case ISM303DAC_XL_DEG_80:
3345 *val = ISM303DAC_XL_DEG_80;
3346 break;
3347
3348 case ISM303DAC_XL_DEG_70:
3349 *val = ISM303DAC_XL_DEG_70;
3350 break;
3351
3352 case ISM303DAC_XL_DEG_60:
3353 *val = ISM303DAC_XL_DEG_60;
3354 break;
3355
3356 case ISM303DAC_XL_DEG_50:
3357 *val = ISM303DAC_XL_DEG_50;
3358 break;
3359
3360 default:
3361 *val = ISM303DAC_XL_DEG_80;
3362 break;
3363 }
3364
3365 return ret;
3366 }
3367
3368 /**
3369 * @brief 4D orientation detection enable.[set]
3370 *
3371 * @param ctx read / write interface definitions.(ptr)
3372 * @param val Change the values of 4d_en in reg TAP_6D_THS
3373 * @retval Interface status (MANDATORY: return 0 -> no Error).
3374 *
3375 */
ism303dac_xl_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)3376 int32_t ism303dac_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
3377 {
3378 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3379 int32_t ret;
3380
3381 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3382 (uint8_t *)&tap_6d_ths_a, 1);
3383
3384 if (ret == 0)
3385 {
3386 tap_6d_ths_a._4d_en = val;
3387 ret = ism303dac_write_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3388 (uint8_t *)&tap_6d_ths_a, 1);
3389 }
3390
3391 return ret;
3392 }
3393
3394 /**
3395 * @brief 4D orientation detection enable.[get]
3396 *
3397 * @param ctx read / write interface definitions.(ptr)
3398 * @param val Get the values of 4d_en in reg TAP_6D_THS.(ptr)
3399 * @retval Interface status (MANDATORY: return 0 -> no Error).
3400 *
3401 */
ism303dac_xl_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)3402 int32_t ism303dac_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
3403 {
3404 ism303dac_tap_6d_ths_a_t tap_6d_ths_a;
3405 int32_t ret;
3406
3407 ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A,
3408 (uint8_t *)&tap_6d_ths_a, 1);
3409 *val = tap_6d_ths_a._4d_en;
3410
3411 return ret;
3412 }
3413
3414 /**
3415 * @brief 6D source register.[get]
3416 *
3417 * @param ctx read / write interface definitions.(ptr)
3418 * @param val Get union of registers from 6D_SRC to.(ptr)
3419 * @retval Interface status (MANDATORY: return 0 -> no Error).
3420 *
3421 */
ism303dac_xl_6d_src_get(const stmdev_ctx_t * ctx,ism303dac_6d_src_a_t * val)3422 int32_t ism303dac_xl_6d_src_get(const stmdev_ctx_t *ctx,
3423 ism303dac_6d_src_a_t *val)
3424 {
3425 int32_t ret;
3426
3427 ret = ism303dac_read_reg(ctx, ISM303DAC_6D_SRC_A, (uint8_t *) val, 1);
3428
3429 return ret;
3430 }
3431
3432 /**
3433 * @}
3434 *
3435 */
3436
3437 /**
3438 * @defgroup ISM303DAC_free_fall
3439 * @brief This section group all the functions concerning the
3440 * free fall detection.
3441 * @{
3442 *
3443 */
3444
3445 /**
3446 * @brief Free-fall duration [1 LSb = 1 / ODR].[set]
3447 *
3448 * @param ctx read / write interface definitions.(ptr)
3449 * @param val Change the values of ff_dur in reg WAKE_UP_DUR/FREE_FALL
3450 * @retval Interface status (MANDATORY: return 0 -> no Error).
3451 *
3452 */
ism303dac_xl_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3453 int32_t ism303dac_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3454 {
3455 ism303dac_wake_up_dur_a_t wake_up_dur_a;
3456 ism303dac_free_fall_a_t free_fall_a;
3457 int32_t ret;
3458
3459 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
3460 (uint8_t *)&wake_up_dur_a, 1);
3461
3462 if (ret == 0)
3463 {
3464 wake_up_dur_a.ff_dur = (val & 0x20U) >> 5;
3465 ret = ism303dac_write_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
3466 (uint8_t *)&wake_up_dur_a, 1);
3467 }
3468
3469 if (ret == 0)
3470 {
3471 ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
3472 (uint8_t *)&free_fall_a, 1);
3473 }
3474
3475 if (ret == 0)
3476 {
3477 free_fall_a.ff_dur = val & 0x1FU;
3478 ret = ism303dac_write_reg(ctx, ISM303DAC_FREE_FALL_A,
3479 (uint8_t *)&free_fall_a, 1);
3480 }
3481
3482 return ret;
3483 }
3484
3485 /**
3486 * @brief Free-fall duration [1 LSb = 1 / ODR].[get]
3487 *
3488 * @param ctx read / write interface definitions.(ptr)
3489 * @param val Get the values of ff_dur in reg WAKE_UP_DUR/FREE_FALL.(ptr)
3490 * @retval Interface status (MANDATORY: return 0 -> no Error).
3491 *
3492 */
ism303dac_xl_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3493 int32_t ism303dac_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3494 {
3495 ism303dac_wake_up_dur_a_t wake_up_dur_a;
3496 ism303dac_free_fall_a_t free_fall_a;
3497 int32_t ret;
3498
3499 ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A,
3500 (uint8_t *)&wake_up_dur_a, 1);
3501
3502 if (ret == 0)
3503 {
3504 ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
3505 (uint8_t *)&free_fall_a, 1);
3506 }
3507
3508 *val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur;
3509
3510 return ret;
3511 }
3512
3513 /**
3514 * @brief Free-fall threshold [1 LSB = 31.25 mg].[set]
3515 *
3516 * @param ctx read / write interface definitions.(ptr)
3517 * @param val Change the values of ff_ths in reg FREE_FALL
3518 * @retval Interface status (MANDATORY: return 0 -> no Error).
3519 *
3520 */
ism303dac_xl_ff_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3521 int32_t ism303dac_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3522 {
3523 ism303dac_free_fall_a_t free_fall_a;
3524 int32_t ret;
3525
3526 ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
3527 (uint8_t *)&free_fall_a, 1);
3528
3529 if (ret == 0)
3530 {
3531 free_fall_a.ff_ths = val;
3532 ret = ism303dac_write_reg(ctx, ISM303DAC_FREE_FALL_A,
3533 (uint8_t *)&free_fall_a, 1);
3534 }
3535
3536 return ret;
3537 }
3538
3539 /**
3540 * @brief Free-fall threshold [1 LSB = 31.25 mg].[get]
3541 *
3542 * @param ctx read / write interface definitions.(ptr)
3543 * @param val Get the values of ff_ths in reg FREE_FALL.(ptr)
3544 * @retval Interface status (MANDATORY: return 0 -> no Error).
3545 *
3546 */
ism303dac_xl_ff_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3547 int32_t ism303dac_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3548 {
3549 ism303dac_free_fall_a_t free_fall_a;
3550 int32_t ret;
3551
3552 ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A,
3553 (uint8_t *)&free_fall_a, 1);
3554 *val = free_fall_a.ff_ths;
3555
3556 return ret;
3557 }
3558
3559 /**
3560 * @}
3561 *
3562 */
3563
3564 /**
3565 * @defgroup ISM303DAC_Fifo
3566 * @brief This section group all the functions concerning the fifo usage
3567 * @{
3568 *
3569 */
3570
3571 /**
3572 * @brief Module routine result is send to
3573 * FIFO instead of X,Y,Z acceleration data.[set]
3574 *
3575 * @param ctx read / write interface definitions.(ptr)
3576 * @param val Change the values of module_to_fifo in reg FIFO_CTRL
3577 * @retval Interface status (MANDATORY: return 0 -> no Error).
3578 *
3579 */
ism303dac_xl_fifo_xl_module_batch_set(const stmdev_ctx_t * ctx,uint8_t val)3580 int32_t ism303dac_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx,
3581 uint8_t val)
3582 {
3583 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
3584 int32_t ret;
3585
3586 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3587 (uint8_t *)&fifo_ctrl_a, 1);
3588
3589 if (ret == 0)
3590 {
3591 fifo_ctrl_a.module_to_fifo = val;
3592 ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3593 (uint8_t *)&fifo_ctrl_a, 1);
3594 }
3595
3596 return ret;
3597 }
3598
3599 /**
3600 * @brief Module routine result is send to FIFO instead of X,Y,Z
3601 * acceleration data[get]
3602 *
3603 * @param ctx read / write interface definitions.(ptr)
3604 * @param val Get the values of module_to_fifo in reg FIFO_CTRL.(ptr)
3605 * @retval Interface status (MANDATORY: return 0 -> no Error).
3606 *
3607 */
ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)3608 int32_t ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx,
3609 uint8_t *val)
3610 {
3611 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
3612 int32_t ret;
3613
3614 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3615 (uint8_t *)&fifo_ctrl_a, 1);
3616 *val = fifo_ctrl_a.module_to_fifo;
3617
3618 return ret;
3619 }
3620
3621 /**
3622 * @brief FIFO mode selection.[set]
3623 *
3624 * @param ctx read / write interface definitions.(ptr)
3625 * @param val Change the values of fmode in reg FIFO_CTRL
3626 * @retval Interface status (MANDATORY: return 0 -> no Error).
3627 *
3628 */
ism303dac_xl_fifo_mode_set(const stmdev_ctx_t * ctx,ism303dac_xl_fmode_t val)3629 int32_t ism303dac_xl_fifo_mode_set(const stmdev_ctx_t *ctx,
3630 ism303dac_xl_fmode_t val)
3631 {
3632 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
3633 int32_t ret;
3634
3635 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3636 (uint8_t *)&fifo_ctrl_a, 1);
3637
3638 if (ret == 0)
3639 {
3640 fifo_ctrl_a.fmode = (uint8_t)val;
3641 ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3642 (uint8_t *)&fifo_ctrl_a, 1);
3643 }
3644
3645 return ret;
3646 }
3647
3648 /**
3649 * @brief FIFO mode selection.[get]
3650 *
3651 * @param ctx read / write interface definitions.(ptr)
3652 * @param val Get the values of fmode in reg FIFO_CTRL.(ptr)
3653 * @retval Interface status (MANDATORY: return 0 -> no Error).
3654 *
3655 */
ism303dac_xl_fifo_mode_get(const stmdev_ctx_t * ctx,ism303dac_xl_fmode_t * val)3656 int32_t ism303dac_xl_fifo_mode_get(const stmdev_ctx_t *ctx,
3657 ism303dac_xl_fmode_t *val)
3658 {
3659 ism303dac_fifo_ctrl_a_t fifo_ctrl_a;
3660 int32_t ret;
3661
3662 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A,
3663 (uint8_t *)&fifo_ctrl_a, 1);
3664
3665 switch (fifo_ctrl_a.fmode)
3666 {
3667 case ISM303DAC_XL_BYPASS_MODE:
3668 *val = ISM303DAC_XL_BYPASS_MODE;
3669 break;
3670
3671 case ISM303DAC_XL_FIFO_MODE:
3672 *val = ISM303DAC_XL_FIFO_MODE;
3673 break;
3674
3675 case ISM303DAC_XL_STREAM_TO_FIFO_MODE:
3676 *val = ISM303DAC_XL_STREAM_TO_FIFO_MODE;
3677 break;
3678
3679 case ISM303DAC_XL_BYPASS_TO_STREAM_MODE:
3680 *val = ISM303DAC_XL_BYPASS_TO_STREAM_MODE;
3681 break;
3682
3683 case ISM303DAC_XL_STREAM_MODE:
3684 *val = ISM303DAC_XL_STREAM_MODE;
3685 break;
3686
3687 default:
3688 *val = ISM303DAC_XL_BYPASS_MODE;
3689 break;
3690 }
3691
3692 return ret;
3693 }
3694
3695 /**
3696 * @brief FIFO watermark level selection.[set]
3697 *
3698 * @param ctx read / write interface definitions.(ptr)
3699 * @param val Change the values of fifo_watermark in reg FIFO_THS
3700 * @retval Interface status (MANDATORY: return 0 -> no Error).
3701 *
3702 */
ism303dac_xl_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3703 int32_t ism303dac_xl_fifo_watermark_set(const stmdev_ctx_t *ctx,
3704 uint8_t val)
3705 {
3706 int32_t ret;
3707
3708 ret = ism303dac_write_reg(ctx, ISM303DAC_FIFO_THS_A, &val, 1);
3709
3710 return ret;
3711 }
3712
3713 /**
3714 * @brief FIFO watermark level selection.[get]
3715 *
3716 * @param ctx read / write interface definitions.(ptr)
3717 * @param val Get the values of fifo_watermark in reg FIFO_THS.(ptr)
3718 * @retval Interface status (MANDATORY: return 0 -> no Error).
3719 *
3720 */
ism303dac_xl_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3721 int32_t ism303dac_xl_fifo_watermark_get(const stmdev_ctx_t *ctx,
3722 uint8_t *val)
3723 {
3724 int32_t ret;
3725
3726 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_THS_A, val, 1);
3727
3728 return ret;
3729 }
3730
3731 /**
3732 * @brief FIFO full, 256 unread samples.[get]
3733 *
3734 * @param ctx read / write interface definitions.(ptr)
3735 * @param val Get the values of diff in reg FIFO_SRC.(ptr)
3736 * @retval Interface status (MANDATORY: return 0 -> no Error).
3737 *
3738 */
ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3739 int32_t ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx,
3740 uint8_t *val)
3741 {
3742 ism303dac_fifo_src_a_t fifo_src_a;
3743 int32_t ret;
3744
3745 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
3746 (uint8_t *)&fifo_src_a, 1);
3747 *val = fifo_src_a.diff;
3748
3749 return ret;
3750 }
3751
3752 /**
3753 * @brief FIFO overrun status.[get]
3754 *
3755 * @param ctx read / write interface definitions.(ptr)
3756 * @param val Get the values of fifo_ovr in reg FIFO_SRC.(ptr)
3757 * @retval Interface status (MANDATORY: return 0 -> no Error).
3758 *
3759 */
ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3760 int32_t ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx,
3761 uint8_t *val)
3762 {
3763 ism303dac_fifo_src_a_t fifo_src_a;
3764 int32_t ret;
3765
3766 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
3767 (uint8_t *)&fifo_src_a, 1);
3768 *val = fifo_src_a.fifo_ovr;
3769
3770 return ret;
3771 }
3772
3773 /**
3774 * @brief FIFO threshold status.[get]
3775 *
3776 * @param ctx read / write interface definitions.(ptr)
3777 * @param val Get the values of fth in reg FIFO_SRC.(ptr)
3778 * @retval Interface status (MANDATORY: return 0 -> no Error).
3779 *
3780 */
ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3781 int32_t ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx,
3782 uint8_t *val)
3783 {
3784 ism303dac_fifo_src_a_t fifo_src_a;
3785 int32_t ret;
3786
3787 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
3788 (uint8_t *)&fifo_src_a, 1);
3789 *val = fifo_src_a.fth;
3790
3791 return ret;
3792 }
3793
3794 /**
3795 * @brief The number of unread samples stored in FIFO.[get]
3796 *
3797 * @param ctx read / write interface definitions.(ptr)
3798 * @param val Get the values of diff in reg FIFO_SAMPLES.(ptr)
3799 * @retval Interface status (MANDATORY: return 0 -> no Error).
3800 *
3801 */
ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)3802 int32_t ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t *ctx,
3803 uint16_t *val)
3804 {
3805 ism303dac_fifo_src_a_t fifo_src_a;
3806 ism303dac_fifo_samples_a_t fifo_samples_a;
3807 int32_t ret;
3808
3809 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A,
3810 (uint8_t *)&fifo_src_a, 1);
3811
3812 if (ret == 0)
3813 {
3814 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SAMPLES_A,
3815 (uint8_t *)&fifo_samples_a, 1);
3816 *val = fifo_src_a.diff;
3817 *val = *val << 7;
3818 *val += fifo_samples_a.diff;
3819 }
3820
3821 return ret;
3822 }
3823
3824 /**
3825 * @brief FIFO_SRCregister.[get]
3826 *
3827 * @param ctx read / write interface definitions.(ptr)
3828 * @param val Get registers FIFO_SRC.(ptr)
3829 * @retval Interface status (MANDATORY: return 0 -> no Error).
3830 *
3831 */
ism303dac_xl_fifo_src_get(const stmdev_ctx_t * ctx,ism303dac_fifo_src_a_t * val)3832 int32_t ism303dac_xl_fifo_src_get(const stmdev_ctx_t *ctx,
3833 ism303dac_fifo_src_a_t *val)
3834 {
3835 int32_t ret;
3836
3837 ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t *) val, 1);
3838
3839 return ret;
3840 }
3841
3842 /**
3843 * @}
3844 *
3845 */
3846
3847 /**
3848 * @defgroup ISM303DAC_module
3849 * @brief This section groups all the functions that manage
3850 * module calculation
3851 * @{
3852 *
3853 */
3854
3855 /**
3856 * @brief Module processing enable.[set]
3857 *
3858 * @param ctx read / write interface definitions.(ptr)
3859 * @param val Change the values of module_on in reg FUNC_CTRL
3860 * @retval Interface status (MANDATORY: return 0 -> no Error).
3861 *
3862 */
ism303dac_xl_module_sens_set(const stmdev_ctx_t * ctx,uint8_t val)3863 int32_t ism303dac_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
3864 {
3865 ism303dac_func_ctrl_a_t func_ctrl_a;
3866 int32_t ret;
3867
3868 ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_CTRL_A,
3869 (uint8_t *)&func_ctrl_a, 1);
3870
3871 if (ret == 0)
3872 {
3873 func_ctrl_a.module_on = val;
3874 ret = ism303dac_write_reg(ctx, ISM303DAC_FUNC_CTRL_A,
3875 (uint8_t *)&func_ctrl_a, 1);
3876 }
3877
3878 return ret;
3879 }
3880
3881 /**
3882 * @brief Module processing enable.[get]
3883 *
3884 * @param ctx read / write interface definitions.(ptr)
3885 * @param val Get the values of module_on in reg FUNC_CTRL.(ptr)
3886 * @retval Interface status (MANDATORY: return 0 -> no Error).
3887 *
3888 */
ism303dac_xl_module_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)3889 int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
3890 {
3891 ism303dac_func_ctrl_a_t func_ctrl_a;
3892 int32_t ret;
3893
3894 ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_CTRL_A,
3895 (uint8_t *)&func_ctrl_a, 1);
3896 *val = func_ctrl_a.module_on;
3897
3898 return ret;
3899 }
3900
3901 /**
3902 * @}
3903 *
3904 */
3905
3906 /**
3907 * @}
3908 *
3909 */
3910
3911 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3912
