1 /** 2 ****************************************************************************** 3 * @file ism303dac_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ism303dac_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ISM303DAC_REGS_H 23 #define ISM303DAC_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ISM303DAC 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ism303dac_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define ISM303DAC_I2C_ADD_XL 0x3BU 173 #define ISM303DAC_I2C_ADD_MG 0x3DU 174 175 /** Device Identification (Who am I) **/ 176 #define ISM303DAC_ID_XL 0x43U 177 #define ISM303DAC_ID_MG 0x40U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define ISM303DAC_MODULE_8BIT_A 0x0CU 185 #define ISM303DAC_WHO_AM_I_A 0x0FU 186 #define ISM303DAC_CTRL1_A 0x20U 187 typedef struct 188 { 189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 190 uint8_t bdu : 1; 191 uint8_t hf_odr : 1; 192 uint8_t fs : 2; 193 uint8_t odr : 4; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t odr : 4; 196 uint8_t fs : 2; 197 uint8_t hf_odr : 1; 198 uint8_t bdu : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } ism303dac_ctrl1_a_t; 201 202 #define ISM303DAC_CTRL2_A 0x21U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t sim : 1; 207 uint8_t i2c_disable : 1; 208 uint8_t if_add_inc : 1; 209 uint8_t fds_slope : 1; 210 uint8_t not_used_01 : 2; 211 uint8_t soft_reset : 1; 212 uint8_t boot : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t boot : 1; 215 uint8_t soft_reset : 1; 216 uint8_t not_used_01 : 2; 217 uint8_t fds_slope : 1; 218 uint8_t if_add_inc : 1; 219 uint8_t i2c_disable : 1; 220 uint8_t sim : 1; 221 #endif /* DRV_BYTE_ORDER */ 222 } ism303dac_ctrl2_a_t; 223 224 #define ISM303DAC_CTRL3_A 0x22U 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t pp_od : 1; 229 uint8_t h_lactive : 1; 230 uint8_t lir : 1; 231 uint8_t tap_z_en : 1; 232 uint8_t tap_y_en : 1; 233 uint8_t tap_x_en : 1; 234 uint8_t st : 2; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t st : 2; 237 uint8_t tap_x_en : 1; 238 uint8_t tap_y_en : 1; 239 uint8_t tap_z_en : 1; 240 uint8_t lir : 1; 241 uint8_t h_lactive : 1; 242 uint8_t pp_od : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } ism303dac_ctrl3_a_t; 245 246 #define ISM303DAC_CTRL4_A 0x23U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t int1_drdy : 1; 251 uint8_t int1_fth : 1; 252 uint8_t int1_6d : 1; 253 uint8_t int1_tap : 1; 254 uint8_t int1_ff : 1; 255 uint8_t int1_wu : 1; 256 uint8_t int1_s_tap : 1; 257 uint8_t not_used_01 : 1; 258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 259 uint8_t not_used_01 : 1; 260 uint8_t int1_s_tap : 1; 261 uint8_t int1_wu : 1; 262 uint8_t int1_ff : 1; 263 uint8_t int1_tap : 1; 264 uint8_t int1_6d : 1; 265 uint8_t int1_fth : 1; 266 uint8_t int1_drdy : 1; 267 #endif /* DRV_BYTE_ORDER */ 268 } ism303dac_ctrl4_a_t; 269 270 #define ISM303DAC_CTRL5_A 0x24U 271 typedef struct 272 { 273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 274 uint8_t int2_drdy : 1; 275 uint8_t int2_fth : 1; 276 uint8_t not_used_01 : 3; 277 uint8_t int2_on_int1 : 1; 278 uint8_t int2_boot : 1; 279 uint8_t drdy_pulsed : 1; 280 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 281 uint8_t drdy_pulsed : 1; 282 uint8_t int2_boot : 1; 283 uint8_t int2_on_int1 : 1; 284 uint8_t not_used_01 : 3; 285 uint8_t int2_fth : 1; 286 uint8_t int2_drdy : 1; 287 #endif /* DRV_BYTE_ORDER */ 288 } ism303dac_ctrl5_a_t; 289 290 #define ISM303DAC_FIFO_CTRL_A 0x25U 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t if_cs_pu_dis : 1; 295 uint8_t not_used_01 : 2; 296 uint8_t module_to_fifo : 1; 297 uint8_t not_used_02 : 1; 298 uint8_t fmode : 3; 299 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 300 uint8_t fmode : 3; 301 uint8_t not_used_02 : 1; 302 uint8_t module_to_fifo : 1; 303 uint8_t not_used_01 : 2; 304 uint8_t if_cs_pu_dis : 1; 305 #endif /* DRV_BYTE_ORDER */ 306 } ism303dac_fifo_ctrl_a_t; 307 308 #define ISM303DAC_OUT_T_A 0x26U 309 #define ISM303DAC_STATUS_A 0x27U 310 typedef struct 311 { 312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 313 uint8_t drdy : 1; 314 uint8_t ff_ia : 1; 315 uint8_t _6d_ia : 1; 316 uint8_t single_tap : 1; 317 uint8_t double_tap : 1; 318 uint8_t sleep_state : 1; 319 uint8_t wu_ia : 1; 320 uint8_t fifo_ths : 1; 321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 322 uint8_t fifo_ths : 1; 323 uint8_t wu_ia : 1; 324 uint8_t sleep_state : 1; 325 uint8_t double_tap : 1; 326 uint8_t single_tap : 1; 327 uint8_t _6d_ia : 1; 328 uint8_t ff_ia : 1; 329 uint8_t drdy : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } ism303dac_status_a_t; 332 333 #define ISM303DAC_OUT_X_L_A 0x28U 334 #define ISM303DAC_OUT_X_H_A 0x29U 335 #define ISM303DAC_OUT_Y_L_A 0x2AU 336 #define ISM303DAC_OUT_Y_H_A 0x2BU 337 #define ISM303DAC_OUT_Z_L_A 0x2CU 338 #define ISM303DAC_OUT_Z_H_A 0x2DU 339 #define ISM303DAC_FIFO_THS_A 0x2EU 340 #define ISM303DAC_FIFO_SRC_A 0x2FU 341 typedef struct 342 { 343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 344 uint8_t not_used_01 : 5; 345 uint8_t diff : 1; 346 uint8_t fifo_ovr : 1; 347 uint8_t fth : 1; 348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 349 uint8_t fth : 1; 350 uint8_t fifo_ovr : 1; 351 uint8_t diff : 1; 352 uint8_t not_used_01 : 5; 353 #endif /* DRV_BYTE_ORDER */ 354 } ism303dac_fifo_src_a_t; 355 356 #define ISM303DAC_FIFO_SAMPLES_A 0x30U 357 typedef struct 358 { 359 uint8_t diff : 8; 360 } ism303dac_fifo_samples_a_t; 361 362 #define ISM303DAC_TAP_6D_THS_A 0x31U 363 typedef struct 364 { 365 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 366 uint8_t tap_ths : 5; 367 uint8_t _6d_ths : 2; 368 uint8_t _4d_en : 1; 369 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 370 uint8_t _4d_en : 1; 371 uint8_t _6d_ths : 2; 372 uint8_t tap_ths : 5; 373 #endif /* DRV_BYTE_ORDER */ 374 } ism303dac_tap_6d_ths_a_t; 375 376 #define ISM303DAC_INT_DUR_A 0x32U 377 typedef struct 378 { 379 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 380 uint8_t shock : 2; 381 uint8_t quiet : 2; 382 uint8_t lat : 4; 383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 384 uint8_t lat : 4; 385 uint8_t quiet : 2; 386 uint8_t shock : 2; 387 #endif /* DRV_BYTE_ORDER */ 388 389 } ism303dac_int_dur_a_t; 390 391 #define ISM303DAC_WAKE_UP_THS_A 0x33U 392 typedef struct 393 { 394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 395 uint8_t wu_ths : 6; 396 uint8_t sleep_on : 1; 397 uint8_t single_double_tap : 1; 398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 399 uint8_t single_double_tap : 1; 400 uint8_t sleep_on : 1; 401 uint8_t wu_ths : 6; 402 #endif /* DRV_BYTE_ORDER */ 403 404 } ism303dac_wake_up_ths_a_t; 405 406 #define ISM303DAC_WAKE_UP_DUR_A 0x34U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t sleep_dur : 4; 411 uint8_t int1_fss7 : 1; 412 uint8_t wu_dur : 2; 413 uint8_t ff_dur : 1; 414 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 415 uint8_t ff_dur : 1; 416 uint8_t wu_dur : 2; 417 uint8_t int1_fss7 : 1; 418 uint8_t sleep_dur : 4; 419 #endif /* DRV_BYTE_ORDER */ 420 421 } ism303dac_wake_up_dur_a_t; 422 423 #define ISM303DAC_FREE_FALL_A 0x35U 424 typedef struct 425 { 426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 427 uint8_t ff_ths : 3; 428 uint8_t ff_dur : 5; 429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 430 uint8_t ff_dur : 5; 431 uint8_t ff_ths : 3; 432 #endif /* DRV_BYTE_ORDER */ 433 } ism303dac_free_fall_a_t; 434 435 #define ISM303DAC_STATUS_DUP_A 0x36U 436 typedef struct 437 { 438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 439 uint8_t drdy : 1; 440 uint8_t ff_ia : 1; 441 uint8_t _6d_ia : 1; 442 uint8_t single_tap : 1; 443 uint8_t double_tap : 1; 444 uint8_t sleep_state : 1; 445 uint8_t wu_ia : 1; 446 uint8_t ovr : 1; 447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 448 uint8_t ovr : 1; 449 uint8_t wu_ia : 1; 450 uint8_t sleep_state : 1; 451 uint8_t double_tap : 1; 452 uint8_t single_tap : 1; 453 uint8_t _6d_ia : 1; 454 uint8_t ff_ia : 1; 455 uint8_t drdy : 1; 456 #endif /* DRV_BYTE_ORDER */ 457 } ism303dac_status_dup_a_t; 458 459 #define ISM303DAC_WAKE_UP_SRC_A 0x37U 460 typedef struct 461 { 462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 463 uint8_t z_wu : 1; 464 uint8_t y_wu : 1; 465 uint8_t x_wu : 1; 466 uint8_t wu_ia : 1; 467 uint8_t sleep_state_ia : 1; 468 uint8_t ff_ia : 1; 469 uint8_t not_used_01 : 2; 470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 471 uint8_t not_used_01 : 2; 472 uint8_t ff_ia : 1; 473 uint8_t sleep_state_ia : 1; 474 uint8_t wu_ia : 1; 475 uint8_t x_wu : 1; 476 uint8_t y_wu : 1; 477 uint8_t z_wu : 1; 478 #endif /* DRV_BYTE_ORDER */ 479 } ism303dac_wake_up_src_a_t; 480 481 #define ISM303DAC_TAP_SRC_A 0x38U 482 typedef struct 483 { 484 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 485 uint8_t z_tap : 1; 486 uint8_t y_tap : 1; 487 uint8_t x_tap : 1; 488 uint8_t tap_sign : 1; 489 uint8_t double_tap : 1; 490 uint8_t single_tap : 1; 491 uint8_t tap_ia : 1; 492 uint8_t not_used_01 : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t not_used_01 : 1; 495 uint8_t tap_ia : 1; 496 uint8_t single_tap : 1; 497 uint8_t double_tap : 1; 498 uint8_t tap_sign : 1; 499 uint8_t x_tap : 1; 500 uint8_t y_tap : 1; 501 uint8_t z_tap : 1; 502 #endif /* DRV_BYTE_ORDER */ 503 } ism303dac_tap_src_a_t; 504 505 #define ISM303DAC_6D_SRC_A 0x39U 506 typedef struct 507 { 508 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 509 uint8_t xl : 1; 510 uint8_t xh : 1; 511 uint8_t yl : 1; 512 uint8_t yh : 1; 513 uint8_t zl : 1; 514 uint8_t zh : 1; 515 uint8_t _6d_ia : 1; 516 uint8_t not_used_01 : 1; 517 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 518 uint8_t not_used_01 : 1; 519 uint8_t _6d_ia : 1; 520 uint8_t zh : 1; 521 uint8_t zl : 1; 522 uint8_t yh : 1; 523 uint8_t yl : 1; 524 uint8_t xh : 1; 525 uint8_t xl : 1; 526 #endif /* DRV_BYTE_ORDER */ 527 } ism303dac_6d_src_a_t; 528 529 #define ISM303DAC_FUNC_SRC_A 0x3EU 530 typedef struct 531 { 532 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 533 uint8_t not_used_01 : 1; 534 uint8_t module_ready : 1; 535 uint8_t not_used_02 : 6; 536 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 537 uint8_t not_used_02 : 6; 538 uint8_t module_ready : 1; 539 uint8_t not_used_01 : 1; 540 #endif /* DRV_BYTE_ORDER */ 541 } ism303dac_func_src_a_t; 542 543 #define ISM303DAC_FUNC_CTRL_A 0x3FU 544 typedef struct 545 { 546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 547 uint8_t not_used_01 : 5; 548 uint8_t module_on : 1; 549 uint8_t not_used_02 : 2; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used_02 : 2; 552 uint8_t module_on : 1; 553 uint8_t not_used_01 : 5; 554 #endif /* DRV_BYTE_ORDER */ 555 556 } ism303dac_func_ctrl_a_t; 557 558 #define ISM303DAC_OFFSET_X_REG_L_M 0x45U 559 #define ISM303DAC_OFFSET_X_REG_H_M 0x46U 560 #define ISM303DAC_OFFSET_Y_REG_L_M 0x47U 561 #define ISM303DAC_OFFSET_Y_REG_H_M 0x48U 562 #define ISM303DAC_OFFSET_Z_REG_L_M 0x49U 563 #define ISM303DAC_OFFSET_Z_REG_H_M 0x4AU 564 #define ISM303DAC_WHO_AM_I_M 0x4FU 565 #define ISM303DAC_CFG_REG_A_M 0x60U 566 typedef struct 567 { 568 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 569 uint8_t md : 2; 570 uint8_t odr : 2; 571 uint8_t lp : 1; 572 uint8_t soft_rst : 1; 573 uint8_t reboot : 1; 574 uint8_t comp_temp_en : 1; 575 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 576 uint8_t comp_temp_en : 1; 577 uint8_t reboot : 1; 578 uint8_t soft_rst : 1; 579 uint8_t lp : 1; 580 uint8_t odr : 2; 581 uint8_t md : 2; 582 #endif /* DRV_BYTE_ORDER */ 583 584 } ism303dac_cfg_reg_a_m_t; 585 586 #define ISM303DAC_CFG_REG_B_M 0x61U 587 typedef struct 588 { 589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 590 uint8_t lpf : 1; 591 uint8_t set_rst : 2; /* off_canc + set_freq */ 592 uint8_t int_on_dataoff : 1; 593 uint8_t off_canc_one_shot : 1; 594 uint8_t not_used_01 : 3; 595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 596 uint8_t not_used_01 : 3; 597 uint8_t off_canc_one_shot : 1; 598 uint8_t int_on_dataoff : 1; 599 uint8_t set_rst : 2; /* off_canc + set_freq */ 600 uint8_t lpf : 1; 601 #endif /* DRV_BYTE_ORDER */ 602 603 } ism303dac_cfg_reg_b_m_t; 604 605 #define ISM303DAC_CFG_REG_C_M 0x62U 606 typedef struct 607 { 608 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 609 uint8_t int_mag : 1; 610 uint8_t self_test : 1; 611 uint8_t not_used_01 : 1; 612 uint8_t ble : 1; 613 uint8_t bdu : 1; 614 uint8_t i2c_dis : 1; 615 uint8_t int_mag_pin : 1; 616 uint8_t not_used_02 : 1; 617 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 618 uint8_t not_used_02 : 1; 619 uint8_t int_mag_pin : 1; 620 uint8_t i2c_dis : 1; 621 uint8_t bdu : 1; 622 uint8_t ble : 1; 623 uint8_t not_used_01 : 1; 624 uint8_t self_test : 1; 625 uint8_t int_mag : 1; 626 #endif /* DRV_BYTE_ORDER */ 627 } ism303dac_cfg_reg_c_m_t; 628 629 #define ISM303DAC_INT_CRTL_REG_M 0x63U 630 typedef struct 631 { 632 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 633 uint8_t ien : 1; 634 uint8_t iel : 1; 635 uint8_t iea : 1; 636 uint8_t not_used_01 : 2; 637 uint8_t zien : 1; 638 uint8_t yien : 1; 639 uint8_t xien : 1; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t xien : 1; 642 uint8_t yien : 1; 643 uint8_t zien : 1; 644 uint8_t not_used_01 : 2; 645 uint8_t iea : 1; 646 uint8_t iel : 1; 647 uint8_t ien : 1; 648 #endif /* DRV_BYTE_ORDER */ 649 } ism303dac_int_crtl_reg_m_t; 650 651 #define ISM303DAC_INT_SOURCE_REG_M 0x64U 652 typedef struct 653 { 654 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 655 uint8_t _int : 1; 656 uint8_t mroi : 1; 657 uint8_t n_th_s_z : 1; 658 uint8_t n_th_s_y : 1; 659 uint8_t n_th_s_x : 1; 660 uint8_t p_th_s_z : 1; 661 uint8_t p_th_s_y : 1; 662 uint8_t p_th_s_x : 1; 663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 664 uint8_t p_th_s_x : 1; 665 uint8_t p_th_s_y : 1; 666 uint8_t p_th_s_z : 1; 667 uint8_t n_th_s_x : 1; 668 uint8_t n_th_s_y : 1; 669 uint8_t n_th_s_z : 1; 670 uint8_t mroi : 1; 671 uint8_t _int : 1; 672 #endif /* DRV_BYTE_ORDER */ 673 } ism303dac_int_source_reg_m_t; 674 675 #define ISM303DAC_INT_THS_L_REG_M 0x65U 676 #define ISM303DAC_INT_THS_H_REG_M 0x66U 677 #define ISM303DAC_STATUS_REG_M 0x67U 678 typedef struct 679 { 680 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 681 uint8_t xda : 1; 682 uint8_t yda : 1; 683 uint8_t zda : 1; 684 uint8_t zyxda : 1; 685 uint8_t _xor : 1; 686 uint8_t yor : 1; 687 uint8_t zor : 1; 688 uint8_t zyxor : 1; 689 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 690 uint8_t zyxor : 1; 691 uint8_t zor : 1; 692 uint8_t yor : 1; 693 uint8_t _xor : 1; 694 uint8_t zyxda : 1; 695 uint8_t zda : 1; 696 uint8_t yda : 1; 697 uint8_t xda : 1; 698 #endif /* DRV_BYTE_ORDER */ 699 } ism303dac_status_reg_m_t; 700 701 #define ISM303DAC_OUTX_L_REG_M 0x68U 702 #define ISM303DAC_OUTX_H_REG_M 0x69U 703 #define ISM303DAC_OUTY_L_REG_M 0x6AU 704 #define ISM303DAC_OUTY_H_REG_M 0x6BU 705 #define ISM303DAC_OUTZ_L_REG_M 0x6CU 706 #define ISM303DAC_OUTZ_H_REG_M 0x6DU 707 708 /** 709 * @defgroup ISM303DAC_Register_Union 710 * @brief This union group all the registers having a bit-field 711 * description. 712 * This union is useful but it's not needed by the driver. 713 * 714 * REMOVING this union you are compliant with: 715 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 716 * 717 * @{ 718 * 719 */ 720 typedef union 721 { 722 ism303dac_ctrl1_a_t ctrl1_a; 723 ism303dac_ctrl2_a_t ctrl2_a; 724 ism303dac_ctrl3_a_t ctrl3_a; 725 ism303dac_ctrl4_a_t ctrl4_a; 726 ism303dac_ctrl5_a_t ctrl5_a; 727 ism303dac_fifo_ctrl_a_t fifo_ctrl_a; 728 ism303dac_status_a_t status_a; 729 ism303dac_fifo_src_a_t fifo_src_a; 730 ism303dac_fifo_samples_a_t fifo_samples_a; 731 ism303dac_tap_6d_ths_a_t tap_6d_ths_a; 732 ism303dac_int_dur_a_t int_dur_a; 733 ism303dac_wake_up_ths_a_t wake_up_ths_a; 734 ism303dac_wake_up_dur_a_t wake_up_dur_a; 735 ism303dac_free_fall_a_t free_fall_a; 736 ism303dac_status_dup_a_t status_dup_a; 737 ism303dac_wake_up_src_a_t wake_up_src_a; 738 ism303dac_tap_src_a_t tap_src_a; 739 ism303dac_6d_src_a_t _6d_src_a; 740 ism303dac_func_src_a_t func_src_a; 741 ism303dac_func_ctrl_a_t func_ctrl_a; 742 ism303dac_cfg_reg_a_m_t cfg_reg_a_m; 743 ism303dac_cfg_reg_b_m_t cfg_reg_b_m; 744 ism303dac_cfg_reg_c_m_t cfg_reg_c_m; 745 ism303dac_int_crtl_reg_m_t int_crtl_reg_m; 746 ism303dac_int_source_reg_m_t int_source_reg_m; 747 ism303dac_status_reg_m_t status_reg_m; 748 bitwise_t bitwise; 749 uint8_t byte; 750 } ism303dac_reg_t; 751 752 /** 753 * @} 754 * 755 */ 756 757 #ifndef __weak 758 #define __weak __attribute__((weak)) 759 #endif /* __weak */ 760 761 /* 762 * These are the basic platform dependent I/O routines to read 763 * and write device registers connected on a standard bus. 764 * The driver keeps offering a default implementation based on function 765 * pointers to read/write routines for backward compatibility. 766 * The __weak directive allows the final application to overwrite 767 * them with a custom implementation. 768 */ 769 770 int32_t ism303dac_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 771 uint8_t *data, 772 uint16_t len); 773 int32_t ism303dac_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 774 uint8_t *data, 775 uint16_t len); 776 777 float_t ism303dac_from_fs2g_to_mg(int16_t lsb); 778 float_t ism303dac_from_fs4g_to_mg(int16_t lsb); 779 float_t ism303dac_from_fs8g_to_mg(int16_t lsb); 780 float_t ism303dac_from_fs16g_to_mg(int16_t lsb); 781 782 float_t ism303dac_from_lsb_to_mG(int16_t lsb); 783 784 float_t ism303dac_from_lsb_to_celsius(int16_t lsb); 785 786 typedef struct 787 { 788 ism303dac_fifo_src_a_t fifo_src_a; 789 ism303dac_status_dup_a_t status_dup_a; 790 ism303dac_wake_up_src_a_t wake_up_src_a; 791 ism303dac_tap_src_a_t tap_src_a; 792 ism303dac_6d_src_a_t _6d_src_a; 793 ism303dac_func_src_a_t func_src_a; 794 } ism303dac_xl_all_sources_t; 795 int32_t ism303dac_xl_all_sources_get(const stmdev_ctx_t *ctx, 796 ism303dac_xl_all_sources_t *val); 797 798 int32_t ism303dac_xl_block_data_update_set(const stmdev_ctx_t *ctx, 799 uint8_t val); 800 int32_t ism303dac_xl_block_data_update_get(const stmdev_ctx_t *ctx, 801 uint8_t *val); 802 803 int32_t ism303dac_mg_block_data_update_set(const stmdev_ctx_t *ctx, 804 uint8_t val); 805 int32_t ism303dac_mg_block_data_update_get(const stmdev_ctx_t *ctx, 806 uint8_t *val); 807 808 typedef enum 809 { 810 ISM303DAC_MG_LSB_AT_LOW_ADD = 0, 811 ISM303DAC_MG_MSB_AT_LOW_ADD = 1, 812 } ism303dac_mg_ble_t; 813 int32_t ism303dac_mg_data_format_set(const stmdev_ctx_t *ctx, 814 ism303dac_mg_ble_t val); 815 int32_t ism303dac_mg_data_format_get(const stmdev_ctx_t *ctx, 816 ism303dac_mg_ble_t *val); 817 818 typedef enum 819 { 820 ISM303DAC_XL_2g = 0, 821 ISM303DAC_XL_16g = 1, 822 ISM303DAC_XL_4g = 2, 823 ISM303DAC_XL_8g = 3, 824 } ism303dac_xl_fs_t; 825 int32_t ism303dac_xl_full_scale_set(const stmdev_ctx_t *ctx, 826 ism303dac_xl_fs_t val); 827 int32_t ism303dac_xl_full_scale_get(const stmdev_ctx_t *ctx, 828 ism303dac_xl_fs_t *val); 829 830 typedef enum 831 { 832 ISM303DAC_XL_ODR_OFF = 0x00, 833 ISM303DAC_XL_ODR_1Hz_LP = 0x08, 834 ISM303DAC_XL_ODR_12Hz5_LP = 0x09, 835 ISM303DAC_XL_ODR_25Hz_LP = 0x0A, 836 ISM303DAC_XL_ODR_50Hz_LP = 0x0B, 837 ISM303DAC_XL_ODR_100Hz_LP = 0x0C, 838 ISM303DAC_XL_ODR_200Hz_LP = 0x0D, 839 ISM303DAC_XL_ODR_400Hz_LP = 0x0E, 840 ISM303DAC_XL_ODR_800Hz_LP = 0x0F, 841 ISM303DAC_XL_ODR_12Hz5_HR = 0x01, 842 ISM303DAC_XL_ODR_25Hz_HR = 0x02, 843 ISM303DAC_XL_ODR_50Hz_HR = 0x03, 844 ISM303DAC_XL_ODR_100Hz_HR = 0x04, 845 ISM303DAC_XL_ODR_200Hz_HR = 0x05, 846 ISM303DAC_XL_ODR_400Hz_HR = 0x06, 847 ISM303DAC_XL_ODR_800Hz_HR = 0x07, 848 ISM303DAC_XL_ODR_1k6Hz_HF = 0x15, 849 ISM303DAC_XL_ODR_3k2Hz_HF = 0x16, 850 ISM303DAC_XL_ODR_6k4Hz_HF = 0x17, 851 } ism303dac_xl_odr_t; 852 int32_t ism303dac_xl_data_rate_set(const stmdev_ctx_t *ctx, 853 ism303dac_xl_odr_t val); 854 int32_t ism303dac_xl_data_rate_get(const stmdev_ctx_t *ctx, 855 ism303dac_xl_odr_t *val); 856 857 int32_t ism303dac_xl_status_reg_get(const stmdev_ctx_t *ctx, 858 ism303dac_status_a_t *val); 859 860 int32_t ism303dac_mg_status_get(const stmdev_ctx_t *ctx, 861 ism303dac_status_reg_m_t *val); 862 863 int32_t ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 864 uint8_t *val); 865 866 int32_t ism303dac_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 867 int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 868 869 int32_t ism303dac_mg_user_offset_set(const stmdev_ctx_t *ctx, 870 uint16_t *val); 871 int32_t ism303dac_mg_user_offset_get(const stmdev_ctx_t *ctx, 872 uint16_t *val); 873 874 typedef enum 875 { 876 ISM303DAC_MG_CONTINUOUS_MODE = 0, 877 ISM303DAC_MG_SINGLE_TRIGGER = 1, 878 ISM303DAC_MG_POWER_DOWN = 2, 879 } ism303dac_mg_md_t; 880 int32_t ism303dac_mg_operating_mode_set(const stmdev_ctx_t *ctx, 881 ism303dac_mg_md_t val); 882 int32_t ism303dac_mg_operating_mode_get(const stmdev_ctx_t *ctx, 883 ism303dac_mg_md_t *val); 884 885 typedef enum 886 { 887 ISM303DAC_MG_ODR_10Hz = 0, 888 ISM303DAC_MG_ODR_20Hz = 1, 889 ISM303DAC_MG_ODR_50Hz = 2, 890 ISM303DAC_MG_ODR_100Hz = 3, 891 } ism303dac_mg_odr_t; 892 int32_t ism303dac_mg_data_rate_set(const stmdev_ctx_t *ctx, 893 ism303dac_mg_odr_t val); 894 int32_t ism303dac_mg_data_rate_get(const stmdev_ctx_t *ctx, 895 ism303dac_mg_odr_t *val); 896 897 typedef enum 898 { 899 ISM303DAC_MG_HIGH_RESOLUTION = 0, 900 ISM303DAC_MG_LOW_POWER = 1, 901 } ism303dac_mg_lp_t; 902 int32_t ism303dac_mg_power_mode_set(const stmdev_ctx_t *ctx, 903 ism303dac_mg_lp_t val); 904 int32_t ism303dac_mg_power_mode_get(const stmdev_ctx_t *ctx, 905 ism303dac_mg_lp_t *val); 906 907 int32_t ism303dac_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, 908 uint8_t val); 909 int32_t ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, 910 uint8_t *val); 911 912 typedef enum 913 { 914 ISM303DAC_MG_SET_SENS_ODR_DIV_63 = 0, 915 ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR = 1, 916 ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON = 2, 917 } ism303dac_mg_set_rst_t; 918 int32_t ism303dac_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, 919 ism303dac_mg_set_rst_t val); 920 int32_t ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, 921 ism303dac_mg_set_rst_t *val); 922 923 int32_t ism303dac_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, 924 uint8_t val); 925 int32_t ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, 926 uint8_t *val); 927 928 int32_t ism303dac_acceleration_module_raw_get(const stmdev_ctx_t *ctx, 929 uint8_t *buff); 930 931 int32_t ism303dac_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 932 933 int32_t ism303dac_xl_temperature_raw_get(const stmdev_ctx_t *ctx, 934 uint8_t *buff); 935 936 int32_t ism303dac_acceleration_raw_get(const stmdev_ctx_t *ctx, 937 int16_t *val); 938 939 int32_t ism303dac_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 940 941 int32_t ism303dac_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 942 943 int32_t ism303dac_xl_auto_increment_set(const stmdev_ctx_t *ctx, 944 uint8_t val); 945 int32_t ism303dac_xl_auto_increment_get(const stmdev_ctx_t *ctx, 946 uint8_t *val); 947 948 int32_t ism303dac_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 949 int32_t ism303dac_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 950 951 int32_t ism303dac_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 952 int32_t ism303dac_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 953 954 int32_t ism303dac_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 955 int32_t ism303dac_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 956 957 int32_t ism303dac_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 958 int32_t ism303dac_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 959 960 typedef enum 961 { 962 ISM303DAC_XL_ST_DISABLE = 0, 963 ISM303DAC_XL_ST_POSITIVE = 1, 964 ISM303DAC_XL_ST_NEGATIVE = 2, 965 } ism303dac_xl_st_t; 966 int32_t ism303dac_xl_self_test_set(const stmdev_ctx_t *ctx, 967 ism303dac_xl_st_t val); 968 int32_t ism303dac_xl_self_test_get(const stmdev_ctx_t *ctx, 969 ism303dac_xl_st_t *val); 970 971 int32_t ism303dac_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 972 int32_t ism303dac_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 973 974 typedef enum 975 { 976 ISM303DAC_XL_DRDY_LATCHED = 0, 977 ISM303DAC_XL_DRDY_PULSED = 1, 978 } ism303dac_xl_drdy_pulsed_t; 979 int32_t ism303dac_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, 980 ism303dac_xl_drdy_pulsed_t val); 981 int32_t ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, 982 ism303dac_xl_drdy_pulsed_t *val); 983 984 typedef enum 985 { 986 ISM303DAC_XL_HP_INTERNAL_ONLY = 0, 987 ISM303DAC_XL_HP_ON_OUTPUTS = 1, 988 } ism303dac_xl_fds_slope_t; 989 int32_t ism303dac_xl_hp_path_set(const stmdev_ctx_t *ctx, 990 ism303dac_xl_fds_slope_t val); 991 int32_t ism303dac_xl_hp_path_get(const stmdev_ctx_t *ctx, 992 ism303dac_xl_fds_slope_t *val); 993 994 typedef enum 995 { 996 ISM303DAC_MG_ODR_DIV_2 = 0, 997 ISM303DAC_MG_ODR_DIV_4 = 1, 998 } ism303dac_mg_lpf_t; 999 int32_t ism303dac_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, 1000 ism303dac_mg_lpf_t val); 1001 int32_t ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, 1002 ism303dac_mg_lpf_t *val); 1003 1004 typedef enum 1005 { 1006 ISM303DAC_XL_SPI_4_WIRE = 0, 1007 ISM303DAC_XL_SPI_3_WIRE = 1, 1008 } ism303dac_xl_sim_t; 1009 int32_t ism303dac_xl_spi_mode_set(const stmdev_ctx_t *ctx, 1010 ism303dac_xl_sim_t val); 1011 int32_t ism303dac_xl_spi_mode_get(const stmdev_ctx_t *ctx, 1012 ism303dac_xl_sim_t *val); 1013 1014 typedef enum 1015 { 1016 ISM303DAC_XL_I2C_ENABLE = 0, 1017 ISM303DAC_XL_I2C_DISABLE = 1, 1018 } ism303dac_xl_i2c_disable_t; 1019 int32_t ism303dac_xl_i2c_interface_set(const stmdev_ctx_t *ctx, 1020 ism303dac_xl_i2c_disable_t val); 1021 int32_t ism303dac_xl_i2c_interface_get(const stmdev_ctx_t *ctx, 1022 ism303dac_xl_i2c_disable_t *val); 1023 1024 typedef enum 1025 { 1026 ISM303DAC_MG_I2C_ENABLE = 0, 1027 ISM303DAC_MG_I2C_DISABLE = 1, 1028 } ism303dac_mg_i2c_dis_t; 1029 int32_t ism303dac_mg_i2c_interface_set(const stmdev_ctx_t *ctx, 1030 ism303dac_mg_i2c_dis_t val); 1031 int32_t ism303dac_mg_i2c_interface_get(const stmdev_ctx_t *ctx, 1032 ism303dac_mg_i2c_dis_t *val); 1033 1034 typedef enum 1035 { 1036 ISM303DAC_XL_PULL_UP_CONNECTED = 0, 1037 ISM303DAC_XL_PULL_UP_DISCONNECTED = 1, 1038 } ism303dac_xl_if_cs_pu_dis_t; 1039 int32_t ism303dac_xl_cs_mode_set(const stmdev_ctx_t *ctx, 1040 ism303dac_xl_if_cs_pu_dis_t val); 1041 int32_t ism303dac_xl_cs_mode_get(const stmdev_ctx_t *ctx, 1042 ism303dac_xl_if_cs_pu_dis_t *val); 1043 1044 typedef enum 1045 { 1046 ISM303DAC_XL_PUSH_PULL = 0, 1047 ISM303DAC_XL_OPEN_DRAIN = 1, 1048 } ism303dac_xl_pp_od_t; 1049 int32_t ism303dac_xl_pin_mode_set(const stmdev_ctx_t *ctx, 1050 ism303dac_xl_pp_od_t val); 1051 int32_t ism303dac_xl_pin_mode_get(const stmdev_ctx_t *ctx, 1052 ism303dac_xl_pp_od_t *val); 1053 1054 typedef enum 1055 { 1056 ISM303DAC_XL_ACTIVE_HIGH = 0, 1057 ISM303DAC_XL_ACTIVE_LOW = 1, 1058 } ism303dac_xl_h_lactive_t; 1059 int32_t ism303dac_xl_pin_polarity_set(const stmdev_ctx_t *ctx, 1060 ism303dac_xl_h_lactive_t val); 1061 int32_t ism303dac_xl_pin_polarity_get(const stmdev_ctx_t *ctx, 1062 ism303dac_xl_h_lactive_t *val); 1063 1064 typedef enum 1065 { 1066 ISM303DAC_XL_INT_PULSED = 0, 1067 ISM303DAC_XL_INT_LATCHED = 1, 1068 } ism303dac_xl_lir_t; 1069 int32_t ism303dac_xl_int_notification_set(const stmdev_ctx_t *ctx, 1070 ism303dac_xl_lir_t val); 1071 int32_t ism303dac_xl_int_notification_get(const stmdev_ctx_t *ctx, 1072 ism303dac_xl_lir_t *val); 1073 1074 typedef struct 1075 { 1076 uint8_t int1_drdy : 1; 1077 uint8_t int1_fth : 1; 1078 uint8_t int1_6d : 1; 1079 uint8_t int1_tap : 1; 1080 uint8_t int1_ff : 1; 1081 uint8_t int1_wu : 1; 1082 uint8_t int1_s_tap : 1; 1083 uint8_t int1_fss7 : 1; 1084 } ism303dac_xl_pin_int1_route_t; 1085 int32_t ism303dac_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, 1086 ism303dac_xl_pin_int1_route_t val); 1087 int32_t ism303dac_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, 1088 ism303dac_xl_pin_int1_route_t *val); 1089 1090 typedef struct 1091 { 1092 uint8_t int2_boot : 1; 1093 uint8_t int2_fth : 1; 1094 uint8_t int2_drdy : 1; 1095 } ism303dac_xl_pin_int2_route_t; 1096 int32_t ism303dac_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, 1097 ism303dac_xl_pin_int2_route_t val); 1098 int32_t ism303dac_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, 1099 ism303dac_xl_pin_int2_route_t *val); 1100 1101 int32_t ism303dac_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 1102 int32_t ism303dac_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 1103 1104 int32_t ism303dac_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1105 int32_t ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 1106 1107 int32_t ism303dac_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1108 int32_t ism303dac_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 1109 1110 int32_t ism303dac_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, 1111 ism303dac_int_crtl_reg_m_t *val); 1112 int32_t ism303dac_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, 1113 ism303dac_int_crtl_reg_m_t *val); 1114 1115 int32_t ism303dac_mg_int_gen_source_get(const stmdev_ctx_t *ctx, 1116 ism303dac_int_source_reg_m_t *val); 1117 1118 int32_t ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, 1119 uint16_t val); 1120 int32_t ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, 1121 uint16_t *val); 1122 1123 typedef enum 1124 { 1125 ISM303DAC_MG_CHECK_BEFORE = 0, 1126 ISM303DAC_MG_CHECK_AFTER = 1, 1127 } ism303dac_mg_int_on_dataoff_t; 1128 int32_t ism303dac_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, 1129 ism303dac_mg_int_on_dataoff_t val); 1130 int32_t ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, 1131 ism303dac_mg_int_on_dataoff_t *val); 1132 1133 int32_t ism303dac_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, 1134 uint8_t val); 1135 int32_t ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, 1136 uint8_t *val); 1137 1138 int32_t ism303dac_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1139 int32_t ism303dac_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1140 1141 int32_t ism303dac_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1142 int32_t ism303dac_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1143 1144 int32_t ism303dac_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, 1145 uint8_t val); 1146 int32_t ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, 1147 uint8_t *val); 1148 1149 int32_t ism303dac_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 1150 uint8_t val); 1151 int32_t ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 1152 uint8_t *val); 1153 1154 int32_t ism303dac_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 1155 uint8_t val); 1156 int32_t ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 1157 uint8_t *val); 1158 1159 int32_t ism303dac_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 1160 uint8_t val); 1161 int32_t ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 1162 uint8_t *val); 1163 1164 int32_t ism303dac_xl_tap_threshold_set(const stmdev_ctx_t *ctx, 1165 uint8_t val); 1166 int32_t ism303dac_xl_tap_threshold_get(const stmdev_ctx_t *ctx, 1167 uint8_t *val); 1168 1169 int32_t ism303dac_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 1170 int32_t ism303dac_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 1171 1172 int32_t ism303dac_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 1173 int32_t ism303dac_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 1174 1175 int32_t ism303dac_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1176 int32_t ism303dac_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1177 1178 typedef enum 1179 { 1180 ISM303DAC_XL_ONLY_SINGLE = 0, 1181 ISM303DAC_XL_ONLY_DOUBLE = 1, 1182 } ism303dac_xl_single_double_tap_t; 1183 int32_t ism303dac_xl_tap_mode_set(const stmdev_ctx_t *ctx, 1184 ism303dac_xl_single_double_tap_t val); 1185 int32_t ism303dac_xl_tap_mode_get(const stmdev_ctx_t *ctx, 1186 ism303dac_xl_single_double_tap_t *val); 1187 1188 int32_t ism303dac_xl_tap_src_get(const stmdev_ctx_t *ctx, 1189 ism303dac_tap_src_a_t *val); 1190 1191 typedef enum 1192 { 1193 ISM303DAC_XL_DEG_80 = 0, 1194 ISM303DAC_XL_DEG_70 = 1, 1195 ISM303DAC_XL_DEG_60 = 2, 1196 ISM303DAC_XL_DEG_50 = 3, 1197 } ism303dac_xl_6d_ths_t; 1198 int32_t ism303dac_xl_6d_threshold_set(const stmdev_ctx_t *ctx, 1199 ism303dac_xl_6d_ths_t val); 1200 int32_t ism303dac_xl_6d_threshold_get(const stmdev_ctx_t *ctx, 1201 ism303dac_xl_6d_ths_t *val); 1202 1203 int32_t ism303dac_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1204 int32_t ism303dac_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1205 1206 int32_t ism303dac_xl_6d_src_get(const stmdev_ctx_t *ctx, 1207 ism303dac_6d_src_a_t *val); 1208 1209 int32_t ism303dac_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1210 int32_t ism303dac_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1211 1212 int32_t ism303dac_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1213 int32_t ism303dac_xl_ff_threshold_get(const stmdev_ctx_t *ctx, 1214 uint8_t *val); 1215 1216 int32_t ism303dac_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, 1217 uint8_t val); 1218 int32_t ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, 1219 uint8_t *val); 1220 1221 typedef enum 1222 { 1223 ISM303DAC_XL_BYPASS_MODE = 0, 1224 ISM303DAC_XL_FIFO_MODE = 1, 1225 ISM303DAC_XL_STREAM_TO_FIFO_MODE = 3, 1226 ISM303DAC_XL_BYPASS_TO_STREAM_MODE = 4, 1227 ISM303DAC_XL_STREAM_MODE = 6, 1228 } ism303dac_xl_fmode_t; 1229 int32_t ism303dac_xl_fifo_mode_set(const stmdev_ctx_t *ctx, 1230 ism303dac_xl_fmode_t val); 1231 int32_t ism303dac_xl_fifo_mode_get(const stmdev_ctx_t *ctx, 1232 ism303dac_xl_fmode_t *val); 1233 1234 int32_t ism303dac_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, 1235 uint8_t val); 1236 int32_t ism303dac_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, 1237 uint8_t *val); 1238 1239 int32_t ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, 1240 uint8_t *val); 1241 1242 int32_t ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, 1243 uint8_t *val); 1244 1245 int32_t ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, 1246 uint8_t *val); 1247 1248 int32_t ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, 1249 uint16_t *val); 1250 1251 int32_t ism303dac_xl_fifo_src_get(const stmdev_ctx_t *ctx, 1252 ism303dac_fifo_src_a_t *val); 1253 1254 int32_t ism303dac_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 1255 int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 1256 1257 /** 1258 * @} 1259 * 1260 */ 1261 1262 /** 1263 *@} 1264 * 1265 */ 1266 1267 #ifdef __cplusplus 1268 } 1269 #endif 1270 1271 #endif /* ISM303DAC_REGS_H */ 1272 1273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1274
