1 /* 2 * Copyright (c) 2017-2019 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX) 8 struct lll_df_adv_cfg; 9 #endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */ 10 11 struct ll_adv_set { 12 struct ull_hdr ull; 13 struct lll_adv lll; 14 15 #if defined(CONFIG_BT_CTLR_AD_DATA_BACKUP) 16 /* Legacy AD Data backup when switching to legacy directed advertising 17 * or to Extended Advertising. 18 */ 19 struct { 20 uint8_t len; 21 uint8_t data[PDU_AC_LEG_DATA_SIZE_MAX]; 22 } ad_data_backup; 23 #endif /* CONFIG_BT_CTLR_AD_DATA_BACKUP */ 24 25 #if defined(CONFIG_BT_PERIPHERAL) 26 memq_link_t *link_cc_free; 27 struct node_rx_pdu *node_rx_cc_free; 28 #endif /* CONFIG_BT_PERIPHERAL */ 29 30 #if defined(CONFIG_BT_CTLR_ADV_EXT) 31 uint32_t interval; 32 uint8_t rnd_addr[BDADDR_SIZE]; 33 uint8_t sid:4; 34 uint8_t is_created:1; 35 uint8_t is_ad_data_cmplt:1; 36 #if defined(CONFIG_BT_CTLR_HCI_ADV_HANDLE_MAPPING) 37 uint8_t hci_handle; 38 #endif 39 uint16_t event_counter; 40 uint16_t max_events; 41 uint32_t remain_duration_us; 42 #else /* !CONFIG_BT_CTLR_ADV_EXT */ 43 uint16_t interval; 44 #endif /* !CONFIG_BT_CTLR_ADV_EXT */ 45 46 uint8_t is_enabled:1; 47 48 #if defined(CONFIG_BT_CTLR_PRIVACY) 49 uint8_t own_addr_type:2; 50 uint8_t peer_addr_type:1; 51 uint8_t peer_addr[BDADDR_SIZE]; 52 #endif /* CONFIG_BT_CTLR_PRIVACY */ 53 54 #if defined(CONFIG_BT_CTLR_CHECK_SAME_PEER_CONN) 55 uint8_t own_id_addr[BDADDR_SIZE]; 56 #endif /* CONFIG_BT_CTLR_CHECK_SAME_PEER_CONN */ 57 58 #if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX) 59 struct lll_df_adv_cfg *df_cfg; 60 #endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */ 61 #if defined(CONFIG_BT_CTLR_JIT_SCHEDULING) 62 uint32_t delay; 63 uint32_t delay_at_expire; 64 uint32_t ticks_at_expire; 65 #endif /* CONFIG_BT_CTLR_JIT_SCHEDULING */ 66 }; 67 68 struct ll_adv_aux_set { 69 struct ull_hdr ull; 70 struct lll_adv_aux lll; 71 72 uint16_t interval; 73 74 uint16_t data_chan_id; 75 struct { 76 uint8_t data_chan_map[PDU_CHANNEL_MAP_SIZE]; 77 uint8_t data_chan_count:6; 78 } chm[DOUBLE_BUFFER_SIZE]; 79 uint8_t chm_first; 80 uint8_t chm_last; 81 82 uint8_t is_started:1; 83 }; 84 85 struct ll_adv_sync_set { 86 struct ull_hdr ull; 87 struct lll_adv_sync lll; 88 89 uint16_t interval; 90 91 uint8_t is_enabled:1; 92 uint8_t is_started:1; 93 uint8_t is_data_cmplt:1; 94 95 #if !defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO) 96 uint32_t aux_remainder; 97 #endif /* !CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ 98 }; 99 100 struct ll_adv_iso_set { 101 struct ull_hdr ull; 102 struct lll_adv_iso lll; 103 104 uint32_t big_ref_point; /* Previously elapsed BIG reference point in 105 * microseconds of the free running Controller 106 * clock. 107 */ 108 109 struct { 110 struct node_rx_hdr hdr; 111 } node_rx_complete; 112 113 struct { 114 struct node_rx_hdr hdr; 115 union { 116 uint8_t pdu[0] __aligned(4); 117 uint8_t reason; 118 }; 119 } node_rx_terminate; 120 121 #if defined(CONFIG_BT_CTLR_HCI_ADV_HANDLE_MAPPING) 122 uint8_t hci_handle; 123 #endif /* CONFIG_BT_CTLR_HCI_ADV_HANDLE_MAPPING */ 124 }; 125
