1 /*
2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <common/debug.h>
9 #include <common/runtime_svc.h>
10 #include <lib/mmio.h>
11 #include <tools_share/uuid.h>
12
13 #include "socfpga_fcs.h"
14 #include "socfpga_mailbox.h"
15 #include "socfpga_plat_def.h"
16 #include "socfpga_reset_manager.h"
17 #include "socfpga_sip_svc.h"
18 #include "socfpga_system_manager.h"
19
20 /* Total buffer the driver can hold */
21 #define FPGA_CONFIG_BUFFER_SIZE 4
22
23 static config_type request_type = NO_REQUEST;
24 static int current_block, current_buffer;
25 static int read_block, max_blocks;
26 static uint32_t send_id, rcv_id;
27 static uint32_t bytes_per_block, blocks_submitted;
28 static bool bridge_disable;
29
30 /* RSU static variables */
31 static uint32_t rsu_dcmf_ver[4] = {0};
32 static uint16_t rsu_dcmf_stat[4] = {0};
33 static uint32_t rsu_max_retry;
34
35 /* SiP Service UUID */
36 DEFINE_SVC_UUID2(intl_svc_uid,
37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
39
socfpga_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)40 static uint64_t socfpga_sip_handler(uint32_t smc_fid,
41 uint64_t x1,
42 uint64_t x2,
43 uint64_t x3,
44 uint64_t x4,
45 void *cookie,
46 void *handle,
47 uint64_t flags)
48 {
49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
50 SMC_RET1(handle, SMC_UNK);
51 }
52
53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
54
intel_fpga_sdm_write_buffer(struct fpga_config_info * buffer)55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
56 {
57 uint32_t args[3];
58
59 while (max_blocks > 0 && buffer->size > buffer->size_written) {
60 args[0] = (1<<8);
61 args[1] = buffer->addr + buffer->size_written;
62 if (buffer->size - buffer->size_written <= bytes_per_block) {
63 args[2] = buffer->size - buffer->size_written;
64 current_buffer++;
65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
66 } else {
67 args[2] = bytes_per_block;
68 }
69
70 buffer->size_written += args[2];
71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
72 3U, CMD_INDIRECT);
73
74 buffer->subblocks_sent++;
75 max_blocks--;
76 }
77
78 return !max_blocks;
79 }
80
intel_fpga_sdm_write_all(void)81 static int intel_fpga_sdm_write_all(void)
82 {
83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
84 if (intel_fpga_sdm_write_buffer(
85 &fpga_config_buffers[current_buffer])) {
86 break;
87 }
88 }
89 return 0;
90 }
91
intel_mailbox_fpga_config_isdone(void)92 static uint32_t intel_mailbox_fpga_config_isdone(void)
93 {
94 uint32_t ret;
95
96 switch (request_type) {
97 case RECONFIGURATION:
98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
99 true);
100 break;
101 case BITSTREAM_AUTH:
102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
103 false);
104 break;
105 default:
106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
107 false);
108 break;
109 }
110
111 if (ret != 0U) {
112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
113 return INTEL_SIP_SMC_STATUS_BUSY;
114 } else {
115 request_type = NO_REQUEST;
116 return INTEL_SIP_SMC_STATUS_ERROR;
117 }
118 }
119
120 if (bridge_disable != 0U) {
121 socfpga_bridges_enable(~0); /* Enable bridge */
122 bridge_disable = false;
123 }
124 request_type = NO_REQUEST;
125
126 return INTEL_SIP_SMC_STATUS_OK;
127 }
128
mark_last_buffer_xfer_completed(uint32_t * buffer_addr_completed)129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
130 {
131 int i;
132
133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
134 if (fpga_config_buffers[i].block_number == current_block) {
135 fpga_config_buffers[i].subblocks_sent--;
136 if (fpga_config_buffers[i].subblocks_sent == 0
137 && fpga_config_buffers[i].size <=
138 fpga_config_buffers[i].size_written) {
139 fpga_config_buffers[i].write_requested = 0;
140 current_block++;
141 *buffer_addr_completed =
142 fpga_config_buffers[i].addr;
143 return 0;
144 }
145 }
146 }
147
148 return -1;
149 }
150
intel_fpga_config_completed_write(uint32_t * completed_addr,uint32_t * count,uint32_t * job_id)151 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
152 uint32_t *count, uint32_t *job_id)
153 {
154 uint32_t resp[5];
155 unsigned int resp_len = ARRAY_SIZE(resp);
156 int status = INTEL_SIP_SMC_STATUS_OK;
157 int all_completed = 1;
158 *count = 0;
159
160 while (*count < 3) {
161
162 status = mailbox_read_response(job_id,
163 resp, &resp_len);
164
165 if (status < 0) {
166 break;
167 }
168
169 max_blocks++;
170
171 if (mark_last_buffer_xfer_completed(
172 &completed_addr[*count]) == 0) {
173 *count = *count + 1;
174 } else {
175 break;
176 }
177 }
178
179 if (*count <= 0) {
180 if (status != MBOX_NO_RESPONSE &&
181 status != MBOX_TIMEOUT && resp_len != 0) {
182 mailbox_clear_response();
183 request_type = NO_REQUEST;
184 return INTEL_SIP_SMC_STATUS_ERROR;
185 }
186
187 *count = 0;
188 }
189
190 intel_fpga_sdm_write_all();
191
192 if (*count > 0) {
193 status = INTEL_SIP_SMC_STATUS_OK;
194 } else if (*count == 0) {
195 status = INTEL_SIP_SMC_STATUS_BUSY;
196 }
197
198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
199 if (fpga_config_buffers[i].write_requested != 0) {
200 all_completed = 0;
201 break;
202 }
203 }
204
205 if (all_completed == 1) {
206 return INTEL_SIP_SMC_STATUS_OK;
207 }
208
209 return status;
210 }
211
intel_fpga_config_start(uint32_t flag)212 static int intel_fpga_config_start(uint32_t flag)
213 {
214 uint32_t argument = 0x1;
215 uint32_t response[3];
216 int status = 0;
217 unsigned int size = 0;
218 unsigned int resp_len = ARRAY_SIZE(response);
219
220 request_type = RECONFIGURATION;
221
222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
223 bridge_disable = true;
224 }
225
226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
227 size = 1;
228 bridge_disable = false;
229 request_type = BITSTREAM_AUTH;
230 }
231
232 mailbox_clear_response();
233
234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
235 CMD_CASUAL, NULL, NULL);
236
237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
238 CMD_CASUAL, response, &resp_len);
239
240 if (status < 0) {
241 bridge_disable = false;
242 request_type = NO_REQUEST;
243 return INTEL_SIP_SMC_STATUS_ERROR;
244 }
245
246 max_blocks = response[0];
247 bytes_per_block = response[1];
248
249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
250 fpga_config_buffers[i].size = 0;
251 fpga_config_buffers[i].size_written = 0;
252 fpga_config_buffers[i].addr = 0;
253 fpga_config_buffers[i].write_requested = 0;
254 fpga_config_buffers[i].block_number = 0;
255 fpga_config_buffers[i].subblocks_sent = 0;
256 }
257
258 blocks_submitted = 0;
259 current_block = 0;
260 read_block = 0;
261 current_buffer = 0;
262
263 /* Disable bridge on full reconfiguration */
264 if (bridge_disable) {
265 socfpga_bridges_disable(~0);
266 }
267
268 return INTEL_SIP_SMC_STATUS_OK;
269 }
270
is_fpga_config_buffer_full(void)271 static bool is_fpga_config_buffer_full(void)
272 {
273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
274 if (!fpga_config_buffers[i].write_requested) {
275 return false;
276 }
277 }
278 return true;
279 }
280
is_address_in_ddr_range(uint64_t addr,uint64_t size)281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
282 {
283 if (!addr && !size) {
284 return true;
285 }
286 if (size > (UINT64_MAX - addr)) {
287 return false;
288 }
289 if (addr < BL31_LIMIT) {
290 return false;
291 }
292 if (addr + size > DRAM_BASE + DRAM_SIZE) {
293 return false;
294 }
295
296 return true;
297 }
298
intel_fpga_config_write(uint64_t mem,uint64_t size)299 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
300 {
301 int i;
302
303 intel_fpga_sdm_write_all();
304
305 if (!is_address_in_ddr_range(mem, size) ||
306 is_fpga_config_buffer_full()) {
307 return INTEL_SIP_SMC_STATUS_REJECTED;
308 }
309
310 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
311 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
312
313 if (!fpga_config_buffers[j].write_requested) {
314 fpga_config_buffers[j].addr = mem;
315 fpga_config_buffers[j].size = size;
316 fpga_config_buffers[j].size_written = 0;
317 fpga_config_buffers[j].write_requested = 1;
318 fpga_config_buffers[j].block_number =
319 blocks_submitted++;
320 fpga_config_buffers[j].subblocks_sent = 0;
321 break;
322 }
323 }
324
325 if (is_fpga_config_buffer_full()) {
326 return INTEL_SIP_SMC_STATUS_BUSY;
327 }
328
329 return INTEL_SIP_SMC_STATUS_OK;
330 }
331
is_out_of_sec_range(uint64_t reg_addr)332 static int is_out_of_sec_range(uint64_t reg_addr)
333 {
334 #if DEBUG
335 return 0;
336 #endif
337
338 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
339 switch (reg_addr) {
340 case(0xF8011100): /* ECCCTRL1 */
341 case(0xF8011104): /* ECCCTRL2 */
342 case(0xF8011110): /* ERRINTEN */
343 case(0xF8011114): /* ERRINTENS */
344 case(0xF8011118): /* ERRINTENR */
345 case(0xF801111C): /* INTMODE */
346 case(0xF8011120): /* INTSTAT */
347 case(0xF8011124): /* DIAGINTTEST */
348 case(0xF801112C): /* DERRADDRA */
349 case(0xFA000000): /* SMMU SCR0 */
350 case(0xFA000004): /* SMMU SCR1 */
351 case(0xFA000400): /* SMMU NSCR0 */
352 case(0xFA004000): /* SMMU SSD0_REG */
353 case(0xFA000820): /* SMMU SMR8 */
354 case(0xFA000c20): /* SMMU SCR8 */
355 case(0xFA028000): /* SMMU CB8_SCTRL */
356 case(0xFA001020): /* SMMU CBAR8 */
357 case(0xFA028030): /* SMMU TCR_LPAE */
358 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
359 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
360 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
361 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
362 case(0xFA028010): /* SMMU_CB8)TCR2 */
363 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
364 case(0xFA001820): /* SMMU_CBA2R8 */
365 case(0xFA000074): /* SMMU_STLBGSTATUS */
366 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
367 case(0xFA000060): /* SMMU_STLBIALL */
368 case(0xFA000070): /* SMMU_STLBGSYNC */
369 case(0xFA028618): /* CB8_TLBALL */
370 case(0xFA0287F0): /* CB8_TLBSYNC */
371 case(0xFFD12028): /* SDMMCGRP_CTRL */
372 case(0xFFD12044): /* EMAC0 */
373 case(0xFFD12048): /* EMAC1 */
374 case(0xFFD1204C): /* EMAC2 */
375 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
376 case(0xFFD12094): /* ECC_INT_MASK_SET */
377 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
378 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
379 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
380 case(0xFFD120C0): /* NOC_TIMEOUT */
381 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
382 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
383 case(0xFFD120D0): /* NOC_IDLEACK */
384 case(0xFFD120D4): /* NOC_IDLESTATUS */
385 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
386 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
387 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
388 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
389 return 0;
390 #else
391 switch (reg_addr) {
392
393 case(0xF8011104): /* ECCCTRL2 */
394 case(0xFFD12028): /* SDMMCGRP_CTRL */
395 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
396 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
397 case(0xFFD120D0): /* NOC_IDLEACK */
398
399
400 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */
401 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */
402 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */
403 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */
404 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */
405 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */
406 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
407 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
408
409 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
410 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
411 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
412 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
413 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
414 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
415 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
416 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */
417 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */
418 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */
419 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */
420 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
421 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
422 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
423 return 0;
424 #endif
425 default:
426 break;
427 }
428
429 return -1;
430 }
431
432 /* Secure register access */
433 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
434 {
435 if (is_out_of_sec_range(reg_addr)) {
436 return INTEL_SIP_SMC_STATUS_ERROR;
437 }
438
439 *retval = mmio_read_32(reg_addr);
440
441 return INTEL_SIP_SMC_STATUS_OK;
442 }
443
444 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
445 uint32_t *retval)
446 {
447 if (is_out_of_sec_range(reg_addr)) {
448 return INTEL_SIP_SMC_STATUS_ERROR;
449 }
450
451 mmio_write_32(reg_addr, val);
452
453 return intel_secure_reg_read(reg_addr, retval);
454 }
455
456 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
457 uint32_t val, uint32_t *retval)
458 {
459 if (!intel_secure_reg_read(reg_addr, retval)) {
460 *retval &= ~mask;
461 *retval |= val & mask;
462 return intel_secure_reg_write(reg_addr, *retval, retval);
463 }
464
465 return INTEL_SIP_SMC_STATUS_ERROR;
466 }
467
468 /* Intel Remote System Update (RSU) services */
469 uint64_t intel_rsu_update_address;
470
471 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
472 {
473 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
474 return INTEL_SIP_SMC_RSU_ERROR;
475 }
476
477 return INTEL_SIP_SMC_STATUS_OK;
478 }
479
480 uint32_t intel_rsu_update(uint64_t update_address)
481 {
482 if (update_address > SIZE_MAX) {
483 return INTEL_SIP_SMC_STATUS_REJECTED;
484 }
485
486 intel_rsu_update_address = update_address;
487 return INTEL_SIP_SMC_STATUS_OK;
488 }
489
490 static uint32_t intel_rsu_notify(uint32_t execution_stage)
491 {
492 if (mailbox_hps_stage_notify(execution_stage) < 0) {
493 return INTEL_SIP_SMC_RSU_ERROR;
494 }
495
496 return INTEL_SIP_SMC_STATUS_OK;
497 }
498
499 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
500 uint32_t *ret_stat)
501 {
502 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
503 return INTEL_SIP_SMC_RSU_ERROR;
504 }
505
506 *ret_stat = respbuf[8];
507 return INTEL_SIP_SMC_STATUS_OK;
508 }
509
510 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
511 uint64_t dcmf_ver_3_2)
512 {
513 rsu_dcmf_ver[0] = dcmf_ver_1_0;
514 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
515 rsu_dcmf_ver[2] = dcmf_ver_3_2;
516 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
517
518 return INTEL_SIP_SMC_STATUS_OK;
519 }
520
521 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
522 {
523 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
524 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
525 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
526 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
527
528 return INTEL_SIP_SMC_STATUS_OK;
529 }
530
531 /* Intel HWMON services */
532 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
533 {
534 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
535 return INTEL_SIP_SMC_STATUS_ERROR;
536 }
537
538 return INTEL_SIP_SMC_STATUS_OK;
539 }
540
541 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
542 {
543 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
544 return INTEL_SIP_SMC_STATUS_ERROR;
545 }
546
547 return INTEL_SIP_SMC_STATUS_OK;
548 }
549
550 /* Mailbox services */
551 static uint32_t intel_smc_fw_version(uint32_t *fw_version)
552 {
553 int status;
554 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
555 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
556
557 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
558 CMD_CASUAL, resp_data, &resp_len);
559
560 if (status < 0) {
561 return INTEL_SIP_SMC_STATUS_ERROR;
562 }
563
564 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
565 return INTEL_SIP_SMC_STATUS_ERROR;
566 }
567
568 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
569
570 return INTEL_SIP_SMC_STATUS_OK;
571 }
572
573 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
574 unsigned int len, uint32_t urgent, uint64_t response,
575 unsigned int resp_len, int *mbox_status,
576 unsigned int *len_in_resp)
577 {
578 *len_in_resp = 0;
579 *mbox_status = GENERIC_RESPONSE_ERROR;
580
581 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
582 return INTEL_SIP_SMC_STATUS_REJECTED;
583 }
584
585 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
586 (uint32_t *) response, &resp_len);
587
588 if (status < 0) {
589 *mbox_status = -status;
590 return INTEL_SIP_SMC_STATUS_ERROR;
591 }
592
593 *mbox_status = 0;
594 *len_in_resp = resp_len;
595
596 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
597
598 return INTEL_SIP_SMC_STATUS_OK;
599 }
600
601 static int intel_smc_get_usercode(uint32_t *user_code)
602 {
603 int status;
604 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
605
606 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
607 0U, CMD_CASUAL, user_code, &resp_len);
608
609 if (status < 0) {
610 return INTEL_SIP_SMC_STATUS_ERROR;
611 }
612
613 return INTEL_SIP_SMC_STATUS_OK;
614 }
615
616 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
617 uint32_t mode, uint32_t *job_id,
618 uint32_t *ret_size, uint32_t *mbox_error)
619 {
620 int status = 0;
621 uint32_t resp_len = size / MBOX_WORD_BYTE;
622
623 if (resp_len > MBOX_DATA_MAX_LEN) {
624 return INTEL_SIP_SMC_STATUS_REJECTED;
625 }
626
627 if (!is_address_in_ddr_range(addr, size)) {
628 return INTEL_SIP_SMC_STATUS_REJECTED;
629 }
630
631 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
632 status = mailbox_read_response_async(job_id,
633 NULL, (uint32_t *) addr, &resp_len, 0);
634 } else {
635 status = mailbox_read_response(job_id,
636 (uint32_t *) addr, &resp_len);
637
638 if (status == MBOX_NO_RESPONSE) {
639 status = MBOX_BUSY;
640 }
641 }
642
643 if (status == MBOX_NO_RESPONSE) {
644 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
645 }
646
647 if (status == MBOX_BUSY) {
648 return INTEL_SIP_SMC_STATUS_BUSY;
649 }
650
651 *ret_size = resp_len * MBOX_WORD_BYTE;
652 flush_dcache_range(addr, *ret_size);
653
654 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
655 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
656 *mbox_error = -status;
657 } else if (status != MBOX_RET_OK) {
658 *mbox_error = -status;
659 return INTEL_SIP_SMC_STATUS_ERROR;
660 }
661
662 return INTEL_SIP_SMC_STATUS_OK;
663 }
664
665 /* Miscellaneous HPS services */
666 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
667 {
668 int status = 0;
669
670 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
671 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
672 status = socfpga_bridges_enable((uint32_t)mask);
673 } else {
674 status = socfpga_bridges_enable(~0);
675 }
676 } else {
677 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
678 status = socfpga_bridges_disable((uint32_t)mask);
679 } else {
680 status = socfpga_bridges_disable(~0);
681 }
682 }
683
684 if (status < 0) {
685 return INTEL_SIP_SMC_STATUS_ERROR;
686 }
687
688 return INTEL_SIP_SMC_STATUS_OK;
689 }
690
691 /* SDM SEU Error services */
692 static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
693 {
694 if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
695 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
696 }
697
698 return INTEL_SIP_SMC_STATUS_OK;
699 }
700
701 /*
702 * This function is responsible for handling all SiP calls from the NS world
703 */
704
705 uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
706 u_register_t x1,
707 u_register_t x2,
708 u_register_t x3,
709 u_register_t x4,
710 void *cookie,
711 void *handle,
712 u_register_t flags)
713 {
714 uint32_t retval = 0, completed_addr[3];
715 uint32_t retval2 = 0;
716 uint32_t mbox_error = 0;
717 uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
718 int status = INTEL_SIP_SMC_STATUS_OK;
719 int mbox_status;
720 unsigned int len_in_resp;
721 u_register_t x5, x6, x7;
722
723 switch (smc_fid) {
724 case SIP_SVC_UID:
725 /* Return UID to the caller */
726 SMC_UUID_RET(handle, intl_svc_uid);
727
728 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
729 status = intel_mailbox_fpga_config_isdone();
730 SMC_RET4(handle, status, 0, 0, 0);
731
732 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
733 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
734 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
735 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
736 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
737
738 case INTEL_SIP_SMC_FPGA_CONFIG_START:
739 status = intel_fpga_config_start(x1);
740 SMC_RET4(handle, status, 0, 0, 0);
741
742 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
743 status = intel_fpga_config_write(x1, x2);
744 SMC_RET4(handle, status, 0, 0, 0);
745
746 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
747 status = intel_fpga_config_completed_write(completed_addr,
748 &retval, &rcv_id);
749 switch (retval) {
750 case 1:
751 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
752 completed_addr[0], 0, 0);
753
754 case 2:
755 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
756 completed_addr[0],
757 completed_addr[1], 0);
758
759 case 3:
760 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
761 completed_addr[0],
762 completed_addr[1],
763 completed_addr[2]);
764
765 case 0:
766 SMC_RET4(handle, status, 0, 0, 0);
767
768 default:
769 mailbox_clear_response();
770 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
771 }
772
773 case INTEL_SIP_SMC_REG_READ:
774 status = intel_secure_reg_read(x1, &retval);
775 SMC_RET3(handle, status, retval, x1);
776
777 case INTEL_SIP_SMC_REG_WRITE:
778 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
779 SMC_RET3(handle, status, retval, x1);
780
781 case INTEL_SIP_SMC_REG_UPDATE:
782 status = intel_secure_reg_update(x1, (uint32_t)x2,
783 (uint32_t)x3, &retval);
784 SMC_RET3(handle, status, retval, x1);
785
786 case INTEL_SIP_SMC_RSU_STATUS:
787 status = intel_rsu_status(rsu_respbuf,
788 ARRAY_SIZE(rsu_respbuf));
789 if (status) {
790 SMC_RET1(handle, status);
791 } else {
792 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
793 rsu_respbuf[2], rsu_respbuf[3]);
794 }
795
796 case INTEL_SIP_SMC_RSU_UPDATE:
797 status = intel_rsu_update(x1);
798 SMC_RET1(handle, status);
799
800 case INTEL_SIP_SMC_RSU_NOTIFY:
801 status = intel_rsu_notify(x1);
802 SMC_RET1(handle, status);
803
804 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
805 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
806 ARRAY_SIZE(rsu_respbuf), &retval);
807 if (status) {
808 SMC_RET1(handle, status);
809 } else {
810 SMC_RET2(handle, status, retval);
811 }
812
813 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
814 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
815 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
816 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
817
818 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
819 status = intel_rsu_copy_dcmf_version(x1, x2);
820 SMC_RET1(handle, status);
821
822 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
823 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
824 ((uint64_t)rsu_dcmf_stat[3] << 48) |
825 ((uint64_t)rsu_dcmf_stat[2] << 32) |
826 ((uint64_t)rsu_dcmf_stat[1] << 16) |
827 rsu_dcmf_stat[0]);
828
829 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
830 status = intel_rsu_copy_dcmf_status(x1);
831 SMC_RET1(handle, status);
832
833 case INTEL_SIP_SMC_RSU_MAX_RETRY:
834 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
835
836 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
837 rsu_max_retry = x1;
838 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
839
840 case INTEL_SIP_SMC_ECC_DBE:
841 status = intel_ecc_dbe_notification(x1);
842 SMC_RET1(handle, status);
843
844 case INTEL_SIP_SMC_SERVICE_COMPLETED:
845 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
846 &len_in_resp, &mbox_error);
847 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
848
849 case INTEL_SIP_SMC_FIRMWARE_VERSION:
850 status = intel_smc_fw_version(&retval);
851 SMC_RET2(handle, status, retval);
852
853 case INTEL_SIP_SMC_MBOX_SEND_CMD:
854 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
855 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
856 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
857 &mbox_status, &len_in_resp);
858 SMC_RET3(handle, status, mbox_status, len_in_resp);
859
860 case INTEL_SIP_SMC_GET_USERCODE:
861 status = intel_smc_get_usercode(&retval);
862 SMC_RET2(handle, status, retval);
863
864 case INTEL_SIP_SMC_FCS_CRYPTION:
865 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
866
867 if (x1 == FCS_MODE_DECRYPT) {
868 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
869 } else if (x1 == FCS_MODE_ENCRYPT) {
870 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
871 } else {
872 status = INTEL_SIP_SMC_STATUS_REJECTED;
873 }
874
875 SMC_RET3(handle, status, x4, x5);
876
877 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
878 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
879 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
880 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
881
882 if (x3 == FCS_MODE_DECRYPT) {
883 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
884 (uint32_t *) &x7, &mbox_error);
885 } else if (x3 == FCS_MODE_ENCRYPT) {
886 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
887 (uint32_t *) &x7, &mbox_error);
888 } else {
889 status = INTEL_SIP_SMC_STATUS_REJECTED;
890 }
891
892 SMC_RET4(handle, status, mbox_error, x6, x7);
893
894 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
895 status = intel_fcs_random_number_gen(x1, &retval64,
896 &mbox_error);
897 SMC_RET4(handle, status, mbox_error, x1, retval64);
898
899 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
900 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
901 &send_id);
902 SMC_RET1(handle, status);
903
904 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
905 status = intel_fcs_send_cert(x1, x2, &send_id);
906 SMC_RET1(handle, status);
907
908 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
909 status = intel_fcs_get_provision_data(&send_id);
910 SMC_RET1(handle, status);
911
912 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
913 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
914 &mbox_error);
915 SMC_RET2(handle, status, mbox_error);
916
917 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
918 status = intel_hps_set_bridges(x1, x2);
919 SMC_RET1(handle, status);
920
921 case INTEL_SIP_SMC_HWMON_READTEMP:
922 status = intel_hwmon_readtemp(x1, &retval);
923 SMC_RET2(handle, status, retval);
924
925 case INTEL_SIP_SMC_HWMON_READVOLT:
926 status = intel_hwmon_readvolt(x1, &retval);
927 SMC_RET2(handle, status, retval);
928
929 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
930 status = intel_fcs_sigma_teardown(x1, &mbox_error);
931 SMC_RET2(handle, status, mbox_error);
932
933 case INTEL_SIP_SMC_FCS_CHIP_ID:
934 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
935 SMC_RET4(handle, status, mbox_error, retval, retval2);
936
937 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
938 status = intel_fcs_attestation_subkey(x1, x2, x3,
939 (uint32_t *) &x4, &mbox_error);
940 SMC_RET4(handle, status, mbox_error, x3, x4);
941
942 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
943 status = intel_fcs_get_measurement(x1, x2, x3,
944 (uint32_t *) &x4, &mbox_error);
945 SMC_RET4(handle, status, mbox_error, x3, x4);
946
947 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
948 status = intel_fcs_get_attestation_cert(x1, x2,
949 (uint32_t *) &x3, &mbox_error);
950 SMC_RET4(handle, status, mbox_error, x2, x3);
951
952 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
953 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
954 SMC_RET2(handle, status, mbox_error);
955
956 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
957 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
958 SMC_RET3(handle, status, mbox_error, retval);
959
960 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
961 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
962 SMC_RET2(handle, status, mbox_error);
963
964 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
965 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
966 SMC_RET1(handle, status);
967
968 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
969 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
970 (uint32_t *) &x4, &mbox_error);
971 SMC_RET4(handle, status, mbox_error, x3, x4);
972
973 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
974 status = intel_fcs_remove_crypto_service_key(x1, x2,
975 &mbox_error);
976 SMC_RET2(handle, status, mbox_error);
977
978 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
979 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
980 (uint32_t *) &x4, &mbox_error);
981 SMC_RET4(handle, status, mbox_error, x3, x4);
982
983 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
984 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
985 status = intel_fcs_get_digest_init(x1, x2, x3,
986 x4, x5, &mbox_error);
987 SMC_RET2(handle, status, mbox_error);
988
989 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
990 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
991 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
992 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
993 x4, x5, (uint32_t *) &x6, false,
994 &mbox_error);
995 SMC_RET4(handle, status, mbox_error, x5, x6);
996
997 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
998 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
999 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1000 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1001 x4, x5, (uint32_t *) &x6, true,
1002 &mbox_error);
1003 SMC_RET4(handle, status, mbox_error, x5, x6);
1004
1005 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
1006 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1007 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1008 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1009 x4, x5, (uint32_t *) &x6, false,
1010 &mbox_error, &send_id);
1011 SMC_RET4(handle, status, mbox_error, x5, x6);
1012
1013 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
1014 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1015 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1016 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1017 x4, x5, (uint32_t *) &x6, true,
1018 &mbox_error, &send_id);
1019 SMC_RET4(handle, status, mbox_error, x5, x6);
1020
1021 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
1022 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1023 status = intel_fcs_mac_verify_init(x1, x2, x3,
1024 x4, x5, &mbox_error);
1025 SMC_RET2(handle, status, mbox_error);
1026
1027 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
1028 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1029 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1030 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1031 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1032 x4, x5, (uint32_t *) &x6, x7,
1033 false, &mbox_error);
1034 SMC_RET4(handle, status, mbox_error, x5, x6);
1035
1036 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
1037 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1038 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1039 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1040 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1041 x4, x5, (uint32_t *) &x6, x7,
1042 true, &mbox_error);
1043 SMC_RET4(handle, status, mbox_error, x5, x6);
1044
1045 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
1046 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1047 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1048 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1049 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1050 x4, x5, (uint32_t *) &x6, x7,
1051 false, &mbox_error, &send_id);
1052 SMC_RET4(handle, status, mbox_error, x5, x6);
1053
1054 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
1055 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1056 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1057 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1058 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1059 x4, x5, (uint32_t *) &x6, x7,
1060 true, &mbox_error, &send_id);
1061 SMC_RET4(handle, status, mbox_error, x5, x6);
1062
1063 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
1064 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1065 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1066 x4, x5, &mbox_error);
1067 SMC_RET2(handle, status, mbox_error);
1068
1069 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
1070 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1071 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1072 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1073 x3, x4, x5, (uint32_t *) &x6, false,
1074 &mbox_error);
1075 SMC_RET4(handle, status, mbox_error, x5, x6);
1076
1077 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
1078 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1079 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1080 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1081 x3, x4, x5, (uint32_t *) &x6, true,
1082 &mbox_error);
1083 SMC_RET4(handle, status, mbox_error, x5, x6);
1084
1085 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
1086 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1087 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1088 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1089 x2, x3, x4, x5, (uint32_t *) &x6, false,
1090 &mbox_error, &send_id);
1091 SMC_RET4(handle, status, mbox_error, x5, x6);
1092
1093 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
1094 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1095 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1096 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1097 x2, x3, x4, x5, (uint32_t *) &x6, true,
1098 &mbox_error, &send_id);
1099 SMC_RET4(handle, status, mbox_error, x5, x6);
1100
1101 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
1102 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1103 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1104 x4, x5, &mbox_error);
1105 SMC_RET2(handle, status, mbox_error);
1106
1107 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
1108 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1109 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1110 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1111 x4, x5, (uint32_t *) &x6, &mbox_error);
1112 SMC_RET4(handle, status, mbox_error, x5, x6);
1113
1114 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
1115 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1116 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1117 x4, x5, &mbox_error);
1118 SMC_RET2(handle, status, mbox_error);
1119
1120 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1121 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1122 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1123 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1124 x4, x5, (uint32_t *) &x6, &mbox_error);
1125 SMC_RET4(handle, status, mbox_error, x5, x6);
1126
1127 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1128 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1129 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1130 x4, x5, &mbox_error);
1131 SMC_RET2(handle, status, mbox_error);
1132
1133 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1134 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1135 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1136 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1137 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1138 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1139 x7, false, &mbox_error);
1140 SMC_RET4(handle, status, mbox_error, x5, x6);
1141
1142 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
1143 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1144 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1145 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1146 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1147 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1148 x7, false, &mbox_error, &send_id);
1149 SMC_RET4(handle, status, mbox_error, x5, x6);
1150
1151 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
1152 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1153 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1154 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1155 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1156 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1157 x7, true, &mbox_error, &send_id);
1158 SMC_RET4(handle, status, mbox_error, x5, x6);
1159
1160 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1162 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1163 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1164 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1165 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1166 x7, true, &mbox_error);
1167 SMC_RET4(handle, status, mbox_error, x5, x6);
1168
1169 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1170 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1171 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1172 x4, x5, &mbox_error);
1173 SMC_RET2(handle, status, mbox_error);
1174
1175 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1176 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1177 (uint32_t *) &x4, &mbox_error);
1178 SMC_RET4(handle, status, mbox_error, x3, x4);
1179
1180 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1181 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1182 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1183 x4, x5, &mbox_error);
1184 SMC_RET2(handle, status, mbox_error);
1185
1186 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1187 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1188 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1189 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1190 x4, x5, (uint32_t *) &x6, &mbox_error);
1191 SMC_RET4(handle, status, mbox_error, x5, x6);
1192
1193 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1194 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1195 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1196 &mbox_error);
1197 SMC_RET2(handle, status, mbox_error);
1198
1199 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1200 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1201 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1202 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1203 x5, x6, false, &send_id);
1204 SMC_RET1(handle, status);
1205
1206 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1207 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1208 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1209 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1210 x5, x6, true, &send_id);
1211 SMC_RET1(handle, status);
1212
1213 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1214 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1215 &mbox_error);
1216 SMC_RET4(handle, status, mbox_error, x1, retval64);
1217
1218 case INTEL_SIP_SMC_SVC_VERSION:
1219 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1220 SIP_SVC_VERSION_MAJOR,
1221 SIP_SVC_VERSION_MINOR);
1222
1223 case INTEL_SIP_SMC_SEU_ERR_STATUS:
1224 status = intel_sdm_seu_err_read(seu_respbuf,
1225 ARRAY_SIZE(seu_respbuf));
1226 if (status) {
1227 SMC_RET1(handle, status);
1228 } else {
1229 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
1230 }
1231
1232 default:
1233 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1234 cookie, handle, flags);
1235 }
1236 }
1237
1238 uintptr_t sip_smc_handler(uint32_t smc_fid,
1239 u_register_t x1,
1240 u_register_t x2,
1241 u_register_t x3,
1242 u_register_t x4,
1243 void *cookie,
1244 void *handle,
1245 u_register_t flags)
1246 {
1247 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1248
1249 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1250 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1251 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1252 cookie, handle, flags);
1253 } else {
1254 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1255 cookie, handle, flags);
1256 }
1257 }
1258
1259 DECLARE_RT_SVC(
1260 socfpga_sip_svc,
1261 OEN_SIP_START,
1262 OEN_SIP_END,
1263 SMC_TYPE_FAST,
1264 NULL,
1265 sip_smc_handler
1266 );
1267
1268 DECLARE_RT_SVC(
1269 socfpga_sip_svc_std,
1270 OEN_SIP_START,
1271 OEN_SIP_END,
1272 SMC_TYPE_YIELD,
1273 NULL,
1274 sip_smc_handler
1275 );
1276
