1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/xtensa.dtsi>
8#include <dt-bindings/i2c/i2c.h>
9#include <mem.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "cdns,tensilica-xtensa-lx4";
19			reg = <0>;
20		};
21
22		cpu1: cpu@1 {
23			device_type = "cpu";
24			compatible = "cdns,tensilica-xtensa-lx4";
25			reg = <1>;
26		};
27	};
28
29	sram0: memory@be000000 {
30		compatible = "mmio-sram";
31		reg = <0xbe000000 DT_SIZE_K(512)>;
32	};
33
34	sram1: memory@be800000 {
35		compatible = "mmio-sram";
36		reg = <0xbe800000 DT_SIZE_K(128)>;
37	};
38
39	soc {
40		core_intc: core_intc@0 {
41			compatible = "cdns,xtensa-core-intc";
42			reg = <0x00 0x400>;
43			interrupt-controller;
44			#interrupt-cells = <3>;
45		};
46
47		cavs0: cavs@1600  {
48			compatible = "intel,cavs-intc";
49			reg = <0x1600 0x10>;
50			interrupt-controller;
51			#interrupt-cells = <3>;
52			interrupts = <6 0 0>;
53			interrupt-parent = <&core_intc>;
54			label = "CAVS_0";
55		};
56
57		cavs1: cavs@1610  {
58			compatible = "intel,cavs-intc";
59			reg = <0x1610 0x10>;
60			interrupt-controller;
61			#interrupt-cells = <3>;
62			interrupts = <0xA 0 0>;
63			interrupt-parent = <&core_intc>;
64			label = "CAVS_1";
65		};
66
67		cavs2: cavs@1620  {
68			compatible = "intel,cavs-intc";
69			reg = <0x1620 0x10>;
70			interrupt-controller;
71			#interrupt-cells = <3>;
72			interrupts = <0XD 0 0>;
73			interrupt-parent = <&core_intc>;
74			label = "CAVS_2";
75		};
76
77		cavs3: cavs@1630  {
78			compatible = "intel,cavs-intc";
79			reg = <0x1630 0x10>;
80			interrupt-controller;
81			#interrupt-cells = <3>;
82			interrupts = <0x10 0 0>;
83			interrupt-parent = <&core_intc>;
84			label = "CAVS_3";
85		};
86
87		idc: idc@1200 {
88			compatible = "intel,cavs-idc";
89			label = "CAVS_IDC";
90			reg = <0x1200 0x80>;
91			interrupts = <8 0 0>;
92			interrupt-parent = <&cavs0>;
93		     };
94
95		mailbox: mailbox@1180 {
96			compatible = "intel,adsp-mailbox";
97			reg = <0x1180 0x20>;
98			interrupts = <0x7 0 3>;
99			interrupt-parent = <&cavs0>;
100			label = "IPM_0";
101		};
102
103		ipm_console: ipm_console {
104			compatible = "zephyr,ipm-console";
105			label="IPM_0";
106		};
107
108		mailbox: mailbox@1180 {
109			compatible = "intel,intel-adsp-mailbox";
110			reg = <0x1180 0x20>;
111			interrupts = <0x7 0 3>;
112			interrupt-parent = <&cavs0>;
113			label = "IPM_0";
114		};
115	};
116};
117