1 /*
2  * Copyright 2020 Carlo Caione <ccaione@baylibre.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_DRIVERS_PSCI_PSCI_H_
8 #define ZEPHYR_DRIVERS_PSCI_PSCI_H_
9 
10 #include <zephyr/drivers/pm_cpu_ops/psci.h>
11 
12 #ifdef CONFIG_64BIT
13 #define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
14 #else
15 #define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
16 #endif
17 
18 /* PSCI v0.2 interface */
19 #define PSCI_0_2_FN_BASE                  0x84000000
20 #define PSCI_0_2_FN(n)                    (PSCI_0_2_FN_BASE + (n))
21 #define PSCI_0_2_64BIT                    0x40000000
22 #define PSCI_0_2_FN64_BASE                (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
23 #define PSCI_0_2_FN64(n)                  (PSCI_0_2_FN64_BASE + (n))
24 #define PSCI_0_2_FN_PSCI_VERSION          PSCI_0_2_FN(0)
25 #define PSCI_0_2_FN_CPU_SUSPEND           PSCI_0_2_FN(1)
26 #define PSCI_0_2_FN_CPU_OFF               PSCI_0_2_FN(2)
27 #define PSCI_0_2_FN_CPU_ON                PSCI_0_2_FN(3)
28 #define PSCI_0_2_FN_AFFINITY_INFO         PSCI_0_2_FN(4)
29 #define PSCI_0_2_FN_MIGRATE               PSCI_0_2_FN(5)
30 #define PSCI_0_2_FN_MIGRATE_INFO_TYPE     PSCI_0_2_FN(6)
31 #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU   PSCI_0_2_FN(7)
32 #define PSCI_0_2_FN_SYSTEM_OFF            PSCI_0_2_FN(8)
33 #define PSCI_0_2_FN_SYSTEM_RESET          PSCI_0_2_FN(9)
34 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
35 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
36 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
37 #define PSCI_0_2_FN64_MIGRATE             PSCI_0_2_FN64(5)
38 #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
39 #define PSCI_0_2_FN64_SYSTEM_RESET        PSCI_0_2_FN(9)
40 
41 /* PSCI v1.0 interface */
42 #define PSCI_1_0_FN_BASE                  (0x84000000U)
43 #define PSCI_1_0_64BIT                    (0x40000000U)
44 #define PSCI_1_0_FN64_BASE                (PSCI_1_0_FN_BASE + PSCI_1_0_64BIT)
45 #define PSCI_1_0_FN(n)                    (PSCI_1_0_FN_BASE + (n))
46 #define PSCI_1_0_FN64(n)                  (PSCI_1_0_FN64_BASE + (n))
47 #define PSCI_1_0_FN_PSCI_VERSION          PSCI_1_0_FN(0)
48 #define PSCI_1_0_FN_CPU_SUSPEND           PSCI_1_0_FN(1)
49 #define PSCI_1_0_FN_CPU_OFF               PSCI_1_0_FN(2)
50 #define PSCI_1_0_FN_CPU_ON                PSCI_1_0_FN(3)
51 #define PSCI_1_0_FN_AFFINITY_INFO         PSCI_1_0_FN(4)
52 #define PSCI_1_0_FN_MIGRATE               PSCI_1_0_FN(5)
53 #define PSCI_1_0_FN_MIGRATE_INFO_TYPE     PSCI_1_0_FN(6)
54 #define PSCI_1_0_FN_MIGRATE_INFO_UP_CPU   PSCI_1_0_FN(7)
55 #define PSCI_1_0_FN_SYSTEM_OFF            PSCI_1_0_FN(8)
56 #define PSCI_1_0_FN_SYSTEM_RESET          PSCI_1_0_FN(9)
57 #define PSCI_1_0_FN_PSCI_FEATURES         PSCI_1_0_FN(10)
58 #define PSCI_1_0_FN64_CPU_SUSPEND         PSCI_1_0_FN64(1)
59 #define PSCI_1_0_FN64_CPU_ON              PSCI_1_0_FN64(3)
60 #define PSCI_1_0_FN64_AFFINITY_INFO       PSCI_1_0_FN64(4)
61 #define PSCI_1_0_FN64_MIGRATE             PSCI_1_0_FN64(5)
62 #define PSCI_1_0_FN64_MIGRATE_INFO_UP_CPU PSCI_1_0_FN64(7)
63 /* PSCI function ID is same for both 32 and 64 bit.*/
64 #define PSCI_1_0_FN64_SYSTEM_RESET        PSCI_1_0_FN(9)
65 #define PSCI_1_0_FN64_PSCI_FEATURES       PSCI_1_0_FN(10)
66 
67 /* PSCI v1.1 interface. */
68 #define PSCI_1_1_FN_BASE                  (0x84000000U)
69 #define PSCI_1_1_64BIT                    (0x40000000U)
70 #define PSCI_1_1_FN64_BASE                (PSCI_1_1_FN_BASE + PSCI_1_1_64BIT)
71 #define PSCI_1_1_FN(n)                    (PSCI_1_1_FN_BASE + (n))
72 #define PSCI_1_1_FN64(n)                  (PSCI_1_1_FN64_BASE + (n))
73 #define PSCI_1_1_FN_PSCI_VERSION          PSCI_1_1_FN(0)
74 #define PSCI_1_1_FN_CPU_SUSPEND           PSCI_1_1_FN(1)
75 #define PSCI_1_1_FN_CPU_OFF               PSCI_1_1_FN(2)
76 #define PSCI_1_1_FN_CPU_ON                PSCI_1_1_FN(3)
77 #define PSCI_1_1_FN_AFFINITY_INFO         PSCI_1_1_FN(4)
78 #define PSCI_1_1_FN_MIGRATE               PSCI_1_1_FN(5)
79 #define PSCI_1_1_FN_MIGRATE_INFO_TYPE     PSCI_1_1_FN(6)
80 #define PSCI_1_1_FN_MIGRATE_INFO_UP_CPU   PSCI_1_1_FN(7)
81 #define PSCI_1_1_FN_SYSTEM_OFF            PSCI_1_1_FN(8)
82 #define PSCI_1_1_FN_SYSTEM_RESET          PSCI_1_1_FN(9)
83 #define PSCI_1_1_FN_PSCI_FEATURES         PSCI_1_1_FN(10)
84 #define PSCI_1_1_FN_SYSTEM_RESET2         PSCI_1_1_FN(18)
85 #define PSCI_1_1_FN64_CPU_SUSPEND         PSCI_1_1_FN64(1)
86 #define PSCI_1_1_FN64_CPU_ON              PSCI_1_1_FN64(3)
87 #define PSCI_1_1_FN64_AFFINITY_INFO       PSCI_1_1_FN64(4)
88 #define PSCI_1_1_FN64_MIGRATE             PSCI_1_1_FN64(5)
89 #define PSCI_1_1_FN64_MIGRATE_INFO_UP_CPU PSCI_1_1_FN64(7)
90 /* PSCI function ID is same for both 32 and 64 bit.*/
91 #define PSCI_1_1_FN64_SYSTEM_RESET        PSCI_1_1_FN(9)
92 #define PSCI_1_1_FN64_PSCI_FEATURES       PSCI_1_1_FN(10)
93 #define PSCI_1_1_FN64_SYSTEM_RESET2       PSCI_1_1_FN64(18)
94 
95 /* PSCI return values (inclusive of all PSCI versions) */
96 #define PSCI_RET_SUCCESS          0
97 #define PSCI_RET_NOT_SUPPORTED    -1
98 #define PSCI_RET_INVALID_PARAMS   -2
99 #define PSCI_RET_DENIED           -3
100 #define PSCI_RET_ALREADY_ON       -4
101 #define PSCI_RET_ON_PENDING       -5
102 #define PSCI_RET_INTERNAL_FAILURE -6
103 #define PSCI_RET_NOT_PRESENT      -7
104 #define PSCI_RET_DISABLED         -8
105 #define PSCI_RET_INVALID_ADDRESS  -9
106 
107 typedef unsigned long (psci_fn)(unsigned long, unsigned long,
108 				unsigned long, unsigned long);
109 
110 struct psci_data_t {
111 	enum arm_smccc_conduit conduit;
112 	psci_fn *invoke_psci_fn;
113 	uint32_t ver;
114 };
115 
116 /* PSCI configuration data. */
117 struct psci_config_t {
118 	const char *method;
119 };
120 
121 #endif /* ZEPHYR_DRIVERS_PSCI_PSCI_H_ */
122