1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include <stdbool.h>
9 #include <math.h>
10 #include <esp_types.h>
11 #include "freertos/FreeRTOS.h"
12 #include "freertos/queue.h"
13 #include "freertos/semphr.h"
14
15 #include "sdkconfig.h"
16
17 #if CONFIG_I2S_ENABLE_DEBUG_LOG
18 // The local log level must be defined before including esp_log.h
19 // Set the maximum log level for this source file
20 #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
21 #endif
22
23 #include "soc/lldesc.h"
24 #include "driver/gpio.h"
25 #include "hal/gpio_hal.h"
26 #include "driver/i2s_types_legacy.h"
27 #include "hal/i2s_hal.h"
28 #if SOC_I2S_SUPPORTS_DAC
29 #include "hal/dac_ll.h"
30 #include "hal/dac_types.h"
31 #include "esp_private/adc_share_hw_ctrl.h"
32 #include "esp_private/sar_periph_ctrl.h"
33 #include "adc1_private.h"
34 #include "driver/adc_i2s_legacy.h"
35 #include "driver/adc_types_legacy.h"
36 #endif // SOC_I2S_SUPPORTS_ADC
37
38 #if SOC_GDMA_SUPPORTED
39 #include "esp_private/gdma.h"
40 #endif
41
42 #include "clk_ctrl_os.h"
43 #include "esp_intr_alloc.h"
44 #include "esp_err.h"
45 #include "esp_check.h"
46 #include "esp_attr.h"
47 #include "esp_log.h"
48 #include "esp_pm.h"
49 #include "esp_efuse.h"
50 #include "esp_rom_gpio.h"
51 #include "esp_private/periph_ctrl.h"
52 #include "esp_private/esp_clk.h"
53
54 static const char *TAG = "i2s(legacy)";
55
56 #define I2S_ENTER_CRITICAL_ISR(i2s_num) portENTER_CRITICAL_ISR(&i2s_spinlock[i2s_num])
57 #define I2S_EXIT_CRITICAL_ISR(i2s_num) portEXIT_CRITICAL_ISR(&i2s_spinlock[i2s_num])
58 #define I2S_ENTER_CRITICAL(i2s_num) portENTER_CRITICAL(&i2s_spinlock[i2s_num])
59 #define I2S_EXIT_CRITICAL(i2s_num) portEXIT_CRITICAL(&i2s_spinlock[i2s_num])
60
61 #define I2S_DMA_BUFFER_MAX_SIZE 4092
62
63 #if SOC_I2S_SUPPORTS_ADC_DAC
64 #define I2S_COMM_MODE_ADC_DAC -1
65 #endif
66
67 /**
68 * @brief General clock configuration information
69 * @note It is a general purpose struct, not supposed to be used directly by user
70 */
71 typedef struct {
72 uint32_t sample_rate_hz; /*!< I2S sample rate */
73 i2s_clock_src_t clk_src; /*!< Choose clock source */
74 i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of mclk to the sample rate */
75 #if SOC_I2S_SUPPORTS_PDM_TX
76 uint32_t up_sample_fp; /*!< Up-sampling param fp */
77 uint32_t up_sample_fs; /*!< Up-sampling param fs */
78 #endif
79 #if SOC_I2S_SUPPORTS_PDM_RX
80 i2s_pdm_dsr_t dn_sample_mode; /*!< Down-sampling rate mode */
81 #endif
82 } i2s_clk_config_t;
83
84 /**
85 * @brief DMA buffer object
86 *
87 */
88 typedef struct {
89 char **buf;
90 int buf_size;
91 volatile int rw_pos;
92 volatile void *curr_ptr;
93 SemaphoreHandle_t mux;
94 QueueHandle_t queue;
95 lldesc_t **desc;
96 } i2s_dma_t;
97
98 /**
99 * @brief I2S object instance
100 *
101 */
102 typedef struct {
103 i2s_port_t i2s_num; /*!< I2S port number*/
104 int queue_size; /*!< I2S event queue size*/
105 QueueHandle_t i2s_queue; /*!< I2S queue handler*/
106 uint32_t last_buf_size; /*!< DMA last buffer size */
107 i2s_dma_t *tx; /*!< DMA Tx buffer*/
108 i2s_dma_t *rx; /*!< DMA Rx buffer*/
109 #if SOC_GDMA_SUPPORTED
110 gdma_channel_handle_t rx_dma_chan; /*!< I2S rx gDMA channel handle*/
111 gdma_channel_handle_t tx_dma_chan; /*!< I2S tx gDMA channel handle*/
112 #else
113 intr_handle_t i2s_isr_handle; /*!< I2S Interrupt handle*/
114 #endif
115 uint32_t dma_desc_num;
116 uint32_t dma_frame_num;
117 bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
118 bool use_apll; /*!< I2S use APLL clock */
119 int fixed_mclk; /*!< I2S fixed MLCK clock */
120 i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of I2S master clock(MCLK) to sample rate */
121
122 #ifdef CONFIG_PM_ENABLE
123 esp_pm_lock_handle_t pm_lock;
124 #endif
125 i2s_hal_context_t hal; /*!< I2S hal context*/
126
127 /* New config */
128 i2s_dir_t dir;
129 i2s_role_t role;
130 i2s_comm_mode_t mode;
131 i2s_hal_slot_config_t slot_cfg;
132 i2s_clk_config_t clk_cfg;
133 uint32_t active_slot; /*!< Active slot number */
134 uint32_t total_slot; /*!< Total slot number */
135 } i2s_obj_t;
136
137 // Record the component name that using I2S peripheral
138 static const char *comp_using_i2s[SOC_I2S_NUM] = {[0 ... SOC_I2S_NUM - 1] = NULL};
139
140 // Global I2S object pointer
141 static i2s_obj_t *p_i2s[SOC_I2S_NUM] = {
142 [0 ... SOC_I2S_NUM - 1] = NULL,
143 };
144
145 // Global spin lock for all i2s controllers
146 static portMUX_TYPE i2s_spinlock[SOC_I2S_NUM] = {
147 [0 ... SOC_I2S_NUM - 1] = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED,
148 };
149
150
151 __attribute__((weak)) esp_err_t i2s_platform_acquire_occupation(int id, const char *comp_name);
152
153 __attribute__((weak)) esp_err_t i2s_platform_release_occupation(int id);
154
155 /*-------------------------------------------------------------
156 I2S DMA operation
157 -------------------------------------------------------------*/
158 #if SOC_GDMA_SUPPORTED
i2s_dma_rx_callback(gdma_channel_handle_t dma_chan,gdma_event_data_t * event_data,void * user_data)159 static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
160 {
161 i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
162 portBASE_TYPE need_awoke = 0;
163 portBASE_TYPE tmp = 0;
164 int dummy;
165 i2s_event_t i2s_event;
166 uint32_t finish_desc;
167
168 if (p_i2s->rx) {
169 finish_desc = event_data->rx_eof_desc_addr;
170 i2s_event.size = ((lldesc_t *)finish_desc)->size;
171 if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) {
172 xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp);
173 need_awoke |= tmp;
174 if (p_i2s->i2s_queue) {
175 i2s_event.type = I2S_EVENT_RX_Q_OVF;
176 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
177 need_awoke |= tmp;
178 }
179 }
180 xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
181 need_awoke |= tmp;
182 if (p_i2s->i2s_queue) {
183 i2s_event.type = I2S_EVENT_RX_DONE;
184 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
185 need_awoke |= tmp;
186 }
187 }
188 return need_awoke;
189 }
190
i2s_dma_tx_callback(gdma_channel_handle_t dma_chan,gdma_event_data_t * event_data,void * user_data)191 static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
192 {
193 i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
194 portBASE_TYPE need_awoke = 0;
195 portBASE_TYPE tmp = 0;
196 int dummy;
197 i2s_event_t i2s_event;
198 uint32_t finish_desc;
199 if (p_i2s->tx) {
200 finish_desc = event_data->tx_eof_desc_addr;
201 i2s_event.size = ((lldesc_t *)finish_desc)->size;
202 if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) {
203 xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp);
204 need_awoke |= tmp;
205 if (p_i2s->i2s_queue) {
206 i2s_event.type = I2S_EVENT_TX_Q_OVF;
207 i2s_event.size = p_i2s->tx->buf_size;
208 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
209 need_awoke |= tmp;
210 }
211 }
212 if (p_i2s->tx_desc_auto_clear) {
213 memset((void *) (((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size);
214 }
215 xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
216 need_awoke |= tmp;
217 if (p_i2s->i2s_queue) {
218 i2s_event.type = I2S_EVENT_TX_DONE;
219 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
220 need_awoke |= tmp;
221 }
222 }
223 return need_awoke;
224 }
225
226 #else
i2s_intr_handler_default(void * arg)227 static void IRAM_ATTR i2s_intr_handler_default(void *arg)
228 {
229 i2s_obj_t *p_i2s = (i2s_obj_t *) arg;
230 uint32_t status = i2s_hal_get_intr_status(&(p_i2s->hal));
231 if (status == 0) {
232 //Avoid spurious interrupt
233 return;
234 }
235
236 i2s_event_t i2s_event;
237 int dummy;
238 portBASE_TYPE need_awoke = 0;
239 portBASE_TYPE tmp = 0;
240 uint32_t finish_desc = 0;
241 if ((status & I2S_LL_EVENT_TX_DSCR_ERR) || (status & I2S_LL_EVENT_RX_DSCR_ERR)) {
242 ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status);
243 if (p_i2s->i2s_queue) {
244 i2s_event.type = I2S_EVENT_DMA_ERROR;
245 if (xQueueIsQueueFullFromISR(p_i2s->i2s_queue)) {
246 xQueueReceiveFromISR(p_i2s->i2s_queue, &dummy, &tmp);
247 need_awoke |= tmp;
248 }
249 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
250 need_awoke |= tmp;
251 }
252 }
253
254 if ((status & I2S_LL_EVENT_TX_EOF) && p_i2s->tx) {
255 i2s_hal_get_out_eof_des_addr(&(p_i2s->hal), &finish_desc);
256 i2s_event.size = ((lldesc_t *)finish_desc)->size;
257 // All buffers are empty. This means we have an underflow on our hands.
258 if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) {
259 xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp);
260 need_awoke |= tmp;
261 if (p_i2s->i2s_queue) {
262 i2s_event.type = I2S_EVENT_TX_Q_OVF;
263 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
264 need_awoke |= tmp;
265 }
266 }
267 // See if tx descriptor needs to be auto cleared:
268 // This will avoid any kind of noise that may get introduced due to transmission
269 // of previous data from tx descriptor on I2S line.
270 if (p_i2s->tx_desc_auto_clear == true) {
271 memset((void *)(((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size);
272 }
273 xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
274 need_awoke |= tmp;
275 if (p_i2s->i2s_queue) {
276 i2s_event.type = I2S_EVENT_TX_DONE;
277 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
278 need_awoke |= tmp;
279 }
280 }
281
282 if ((status & I2S_LL_EVENT_RX_EOF) && p_i2s->rx) {
283 // All buffers are full. This means we have an overflow.
284 i2s_hal_get_in_eof_des_addr(&(p_i2s->hal), &finish_desc);
285 i2s_event.size = ((lldesc_t *)finish_desc)->size;
286 if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) {
287 xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp);
288 need_awoke |= tmp;
289 if (p_i2s->i2s_queue) {
290 i2s_event.type = I2S_EVENT_RX_Q_OVF;
291 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
292 need_awoke |= tmp;
293 }
294 }
295 xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
296 need_awoke |= tmp;
297 if (p_i2s->i2s_queue) {
298 i2s_event.type = I2S_EVENT_RX_DONE;
299 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
300 need_awoke |= tmp;
301 }
302 }
303 i2s_hal_clear_intr_status(&(p_i2s->hal), status);
304
305 if (need_awoke == pdTRUE) {
306 portYIELD_FROM_ISR();
307 }
308 }
309 #endif
310
i2s_dma_intr_init(i2s_port_t i2s_num,int intr_flag)311 static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
312 {
313 #if SOC_GDMA_SUPPORTED
314 /* Set GDMA trigger module */
315 gdma_trigger_t trig = {.periph = GDMA_TRIG_PERIPH_I2S};
316
317 switch (i2s_num) {
318 #if SOC_I2S_NUM > 1
319 case I2S_NUM_1:
320 trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S1;
321 break;
322 #endif
323 default:
324 trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S0;
325 break;
326 }
327
328 /* Set GDMA config */
329 gdma_channel_alloc_config_t dma_cfg = {};
330 if ( p_i2s[i2s_num]->dir & I2S_DIR_TX) {
331 dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
332 /* Register a new GDMA tx channel */
333 ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
334 ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->tx_dma_chan, trig), TAG, "Connect tx dma channel error");
335 gdma_tx_event_callbacks_t cb = {.on_trans_eof = i2s_dma_tx_callback};
336 /* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
337 gdma_register_tx_event_callbacks(p_i2s[i2s_num]->tx_dma_chan, &cb, p_i2s[i2s_num]);
338 }
339 if ( p_i2s[i2s_num]->dir & I2S_DIR_RX) {
340 dma_cfg.direction = GDMA_CHANNEL_DIRECTION_RX;
341 /* Register a new GDMA rx channel */
342 ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
343 ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->rx_dma_chan, trig), TAG, "Connect rx dma channel error");
344 gdma_rx_event_callbacks_t cb = {.on_recv_eof = i2s_dma_rx_callback};
345 /* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
346 gdma_register_rx_event_callbacks(p_i2s[i2s_num]->rx_dma_chan, &cb, p_i2s[i2s_num]);
347 }
348 #else
349 /* Initial I2S module interrupt */
350 ESP_RETURN_ON_ERROR(esp_intr_alloc(i2s_periph_signal[i2s_num].irq, intr_flag, i2s_intr_handler_default, p_i2s[i2s_num], &p_i2s[i2s_num]->i2s_isr_handle), TAG, "Register I2S Interrupt error");
351 #endif // SOC_GDMA_SUPPORTED
352 return ESP_OK;
353 }
354
i2s_tx_reset(i2s_port_t i2s_num)355 static void i2s_tx_reset(i2s_port_t i2s_num)
356 {
357 p_i2s[i2s_num]->tx->curr_ptr = NULL;
358 p_i2s[i2s_num]->tx->rw_pos = 0;
359 i2s_hal_tx_reset(&(p_i2s[i2s_num]->hal));
360 #if SOC_GDMA_SUPPORTED
361 gdma_reset(p_i2s[i2s_num]->tx_dma_chan);
362 #else
363 i2s_hal_tx_reset_dma(&(p_i2s[i2s_num]->hal));
364 #endif
365 i2s_hal_tx_reset_fifo(&(p_i2s[i2s_num]->hal));
366 }
367
368 /**
369 * @brief I2S rx reset
370 *
371 * @param i2s_num I2S device number
372 */
i2s_rx_reset(i2s_port_t i2s_num)373 static void i2s_rx_reset(i2s_port_t i2s_num)
374 {
375 p_i2s[i2s_num]->rx->curr_ptr = NULL;
376 p_i2s[i2s_num]->rx->rw_pos = 0;
377 i2s_hal_rx_reset(&(p_i2s[i2s_num]->hal));
378 #if SOC_GDMA_SUPPORTED
379 gdma_reset(p_i2s[i2s_num]->rx_dma_chan);
380 #else
381 i2s_hal_rx_reset_dma(&(p_i2s[i2s_num]->hal));
382 #endif
383 i2s_hal_rx_reset_fifo(&(p_i2s[i2s_num]->hal));
384 }
385
i2s_tx_start(i2s_port_t i2s_num)386 static void i2s_tx_start(i2s_port_t i2s_num)
387 {
388 #if SOC_GDMA_SUPPORTED
389 gdma_start(p_i2s[i2s_num]->tx_dma_chan, (uint32_t) p_i2s[i2s_num]->tx->desc[0]);
390 #else
391 i2s_hal_tx_enable_dma(&(p_i2s[i2s_num]->hal));
392 i2s_hal_tx_enable_intr(&(p_i2s[i2s_num]->hal));
393 i2s_hal_tx_start_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->tx->desc[0]);
394 #endif
395 i2s_hal_tx_start(&(p_i2s[i2s_num]->hal));
396 }
397
i2s_rx_start(i2s_port_t i2s_num)398 static void i2s_rx_start(i2s_port_t i2s_num)
399 {
400 #if SOC_GDMA_SUPPORTED
401 gdma_start(p_i2s[i2s_num]->rx_dma_chan, (uint32_t) p_i2s[i2s_num]->rx->desc[0]);
402 #else
403 i2s_hal_rx_enable_dma(&(p_i2s[i2s_num]->hal));
404 i2s_hal_rx_enable_intr(&(p_i2s[i2s_num]->hal));
405 i2s_hal_rx_start_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->rx->desc[0]);
406 #endif
407 i2s_hal_rx_start(&(p_i2s[i2s_num]->hal));
408 }
409
i2s_tx_stop(i2s_port_t i2s_num)410 static void i2s_tx_stop(i2s_port_t i2s_num)
411 {
412 i2s_hal_tx_stop(&(p_i2s[i2s_num]->hal));
413 #if SOC_GDMA_SUPPORTED
414 gdma_stop(p_i2s[i2s_num]->tx_dma_chan);
415 #else
416 i2s_hal_tx_stop_link(&(p_i2s[i2s_num]->hal));
417 i2s_hal_tx_disable_intr(&(p_i2s[i2s_num]->hal));
418 i2s_hal_tx_disable_dma(&(p_i2s[i2s_num]->hal));
419 #endif
420 }
421
i2s_rx_stop(i2s_port_t i2s_num)422 static void i2s_rx_stop(i2s_port_t i2s_num)
423 {
424 i2s_hal_rx_stop(&(p_i2s[i2s_num]->hal));
425 #if SOC_GDMA_SUPPORTED
426 gdma_stop(p_i2s[i2s_num]->rx_dma_chan);
427 #else
428 i2s_hal_rx_stop_link(&(p_i2s[i2s_num]->hal));
429 i2s_hal_rx_disable_intr(&(p_i2s[i2s_num]->hal));
430 i2s_hal_rx_disable_dma(&(p_i2s[i2s_num]->hal));
431 #endif
432 }
433
i2s_start(i2s_port_t i2s_num)434 esp_err_t i2s_start(i2s_port_t i2s_num)
435 {
436 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
437 //start DMA link
438 I2S_ENTER_CRITICAL(i2s_num);
439
440 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
441 i2s_tx_reset(i2s_num);
442 i2s_tx_start(i2s_num);
443 }
444 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
445 i2s_rx_reset(i2s_num);
446 i2s_rx_start(i2s_num);
447 }
448 #if !SOC_GDMA_SUPPORTED
449 esp_intr_enable(p_i2s[i2s_num]->i2s_isr_handle);
450 #endif
451 I2S_EXIT_CRITICAL(i2s_num);
452 return ESP_OK;
453 }
454
i2s_stop(i2s_port_t i2s_num)455 esp_err_t i2s_stop(i2s_port_t i2s_num)
456 {
457 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
458 I2S_ENTER_CRITICAL(i2s_num);
459 #if !SOC_GDMA_SUPPORTED
460 esp_intr_disable(p_i2s[i2s_num]->i2s_isr_handle);
461 #endif
462 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
463 i2s_tx_stop(i2s_num);
464 }
465 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
466 i2s_rx_stop(i2s_num);
467 }
468 #if !SOC_GDMA_SUPPORTED
469 i2s_hal_clear_intr_status(&(p_i2s[i2s_num]->hal), I2S_INTR_MAX);
470 #endif
471 I2S_EXIT_CRITICAL(i2s_num);
472 return ESP_OK;
473 }
474
475 /*-------------------------------------------------------------
476 I2S buffer operation
477 -------------------------------------------------------------*/
i2s_get_buf_size(i2s_port_t i2s_num)478 static inline uint32_t i2s_get_buf_size(i2s_port_t i2s_num)
479 {
480 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg;
481 /* Calculate bytes per sample, align to 16 bit */
482 uint32_t bytes_per_sample = ((slot_cfg->data_bit_width + 15) / 16) * 2;
483 /* The DMA buffer limitation is 4092 bytes */
484 uint32_t bytes_per_frame = bytes_per_sample * p_i2s[i2s_num]->active_slot;
485 p_i2s[i2s_num]->dma_frame_num = (p_i2s[i2s_num]->dma_frame_num * bytes_per_frame > I2S_DMA_BUFFER_MAX_SIZE) ?
486 I2S_DMA_BUFFER_MAX_SIZE / bytes_per_frame : p_i2s[i2s_num]->dma_frame_num;
487 return p_i2s[i2s_num]->dma_frame_num * bytes_per_frame;
488 }
489
i2s_delete_dma_buffer(i2s_port_t i2s_num,i2s_dma_t * dma_obj)490 static esp_err_t i2s_delete_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
491 {
492 ESP_RETURN_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, TAG, "I2S DMA object can't be NULL");
493 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num;
494 /* Loop to destroy every descriptor and buffer */
495 for (int cnt = 0; cnt < buf_cnt; cnt++) {
496 if (dma_obj->desc && dma_obj->desc[cnt]) {
497 free(dma_obj->desc[cnt]);
498 dma_obj->desc[cnt] = NULL;
499 }
500 if (dma_obj->buf && dma_obj->buf[cnt]) {
501 free(dma_obj->buf[cnt]);
502 dma_obj->buf[cnt] = NULL;
503 }
504 }
505 return ESP_OK;
506 }
507
i2s_alloc_dma_buffer(i2s_port_t i2s_num,i2s_dma_t * dma_obj)508 static esp_err_t i2s_alloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
509 {
510 esp_err_t ret = ESP_OK;
511 ESP_GOTO_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, err, TAG, "I2S DMA object can't be NULL");
512
513 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num;
514 for (int cnt = 0; cnt < buf_cnt; cnt++) {
515 /* Allocate DMA buffer */
516 dma_obj->buf[cnt] = (char *) heap_caps_calloc(dma_obj->buf_size, sizeof(char), MALLOC_CAP_DMA);
517 ESP_GOTO_ON_FALSE(dma_obj->buf[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma buffer");
518 /* Initialize DMA buffer to 0 */
519 memset(dma_obj->buf[cnt], 0, dma_obj->buf_size);
520
521 /* Allocate DMA descpriptor */
522 dma_obj->desc[cnt] = (lldesc_t *) heap_caps_calloc(1, sizeof(lldesc_t), MALLOC_CAP_DMA);
523 ESP_GOTO_ON_FALSE(dma_obj->desc[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma description entry");
524 }
525 /* DMA descriptor must be initialize after all descriptor has been created, otherwise they can't be linked together as a chain */
526 for (int cnt = 0; cnt < buf_cnt; cnt++) {
527 /* Initialize DMA descriptor */
528 dma_obj->desc[cnt]->owner = 1;
529 dma_obj->desc[cnt]->eof = 1;
530 dma_obj->desc[cnt]->sosf = 0;
531 dma_obj->desc[cnt]->length = dma_obj->buf_size;
532 dma_obj->desc[cnt]->size = dma_obj->buf_size;
533 dma_obj->desc[cnt]->buf = (uint8_t *) dma_obj->buf[cnt];
534 dma_obj->desc[cnt]->offset = 0;
535 /* Link to the next descriptor */
536 dma_obj->desc[cnt]->empty = (uint32_t)((cnt < (buf_cnt - 1)) ? (dma_obj->desc[cnt + 1]) : dma_obj->desc[0]);
537 }
538 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
539 i2s_ll_rx_set_eof_num(p_i2s[i2s_num]->hal.dev, dma_obj->buf_size);
540 }
541 ESP_LOGD(TAG, "DMA Malloc info, datalen=blocksize=%d, dma_desc_num=%"PRIu32, dma_obj->buf_size, buf_cnt);
542 return ESP_OK;
543 err:
544 /* Delete DMA buffer if failed to allocate memory */
545 i2s_delete_dma_buffer(i2s_num, dma_obj);
546 return ret;
547 }
548
i2s_realloc_dma_buffer(i2s_port_t i2s_num,i2s_dma_t * dma_obj)549 static esp_err_t i2s_realloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
550 {
551 ESP_RETURN_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, TAG, "I2S DMA object can't be NULL");
552
553 /* Destroy old dma descriptor and buffer */
554 i2s_delete_dma_buffer(i2s_num, dma_obj);
555 /* Alloc new dma descriptor and buffer */
556 ESP_RETURN_ON_ERROR(i2s_alloc_dma_buffer(i2s_num, dma_obj), TAG, "Failed to allocate dma buffer");
557
558 return ESP_OK;
559 }
560
i2s_destroy_dma_object(i2s_port_t i2s_num,i2s_dma_t ** dma)561 static esp_err_t i2s_destroy_dma_object(i2s_port_t i2s_num, i2s_dma_t **dma)
562 {
563 /* Check if DMA truely need destroy */
564 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_ARG, TAG, "I2S not initialized yet");
565 if (!(*dma)) {
566 return ESP_OK;
567 }
568 /* Destroy every descriptor and buffer */
569 i2s_delete_dma_buffer(i2s_num, (*dma));
570 /* Destroy descriptor pointer */
571 if ((*dma)->desc) {
572 free((*dma)->desc);
573 (*dma)->desc = NULL;
574 }
575 /* Destroy buffer pointer */
576 if ((*dma)->buf) {
577 free((*dma)->buf);
578 (*dma)->buf = NULL;
579 }
580 /* Delete DMA mux */
581 vSemaphoreDelete((*dma)->mux);
582 /* Delete DMA queue */
583 vQueueDelete((*dma)->queue);
584 /* Free DMA structure */
585 free(*dma);
586 *dma = NULL;
587 ESP_LOGD(TAG, "DMA queue destroyed");
588 return ESP_OK;
589 }
590
i2s_create_dma_object(i2s_port_t i2s_num,i2s_dma_t ** dma)591 static esp_err_t i2s_create_dma_object(i2s_port_t i2s_num, i2s_dma_t **dma)
592 {
593 ESP_RETURN_ON_FALSE(dma, ESP_ERR_INVALID_ARG, TAG, "DMA object secondary pointer is NULL");
594 ESP_RETURN_ON_FALSE((*dma == NULL), ESP_ERR_INVALID_ARG, TAG, "DMA object has been created");
595 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num;
596 /* Allocate new DMA structure */
597 *dma = (i2s_dma_t *) calloc(1, sizeof(i2s_dma_t));
598 ESP_RETURN_ON_FALSE(*dma, ESP_ERR_NO_MEM, TAG, "DMA object allocate failed");
599 /* Allocate DMA buffer poiter */
600 (*dma)->buf = (char **)heap_caps_calloc(buf_cnt, sizeof(char *), MALLOC_CAP_DMA);
601 if (!(*dma)->buf) {
602 goto err;
603 }
604 /* Allocate secondary pointer of DMA descriptor chain */
605 (*dma)->desc = (lldesc_t **)heap_caps_calloc(buf_cnt, sizeof(lldesc_t *), MALLOC_CAP_DMA);
606 if (!(*dma)->desc) {
607 goto err;
608 }
609 /* Create queue and mutex */
610 (*dma)->queue = xQueueCreate(buf_cnt - 1, sizeof(char *));
611 if (!(*dma)->queue) {
612 goto err;
613 }
614 (*dma)->mux = xSemaphoreCreateMutex();
615 if (!(*dma)->mux) {
616 goto err;
617 }
618
619 return ESP_OK;
620 err:
621 ESP_LOGE(TAG, "I2S DMA object create failed, preparing to uninstall");
622 /* Destroy DMA queue if failed to allocate memory */
623 i2s_destroy_dma_object(i2s_num, dma);
624 return ESP_ERR_NO_MEM;
625 }
626
627 /*-------------------------------------------------------------
628 I2S clock operation
629 -------------------------------------------------------------*/
630 // [clk_tree] TODO: replace the following switch table by clk_tree API
i2s_config_source_clock(i2s_port_t i2s_num,bool use_apll,uint32_t mclk)631 static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
632 {
633 #if SOC_I2S_SUPPORTS_APLL
634 if (use_apll) {
635 /* Calculate the expected APLL */
636 int div = (int)((SOC_APLL_MIN_HZ / mclk) + 1);
637 /* apll_freq = mclk * div
638 * when div = 1, hardware will still divide 2
639 * when div = 0, the final mclk will be unpredictable
640 * So the div here should be at least 2 */
641 div = div < 2 ? 2 : div;
642 uint32_t expt_freq = mclk * div;
643 /* Set APLL coefficients to the given frequency */
644 uint32_t real_freq = 0;
645 esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
646 if (ret == ESP_ERR_INVALID_ARG) {
647 ESP_LOGE(TAG, "set APLL coefficients failed");
648 return 0;
649 }
650 if (ret == ESP_ERR_INVALID_STATE) {
651 ESP_LOGW(TAG, "APLL is occupied already, it is working at %"PRIu32" Hz", real_freq);
652 }
653 ESP_LOGD(TAG, "APLL expected frequency is %"PRIu32" Hz, real frequency is %"PRIu32" Hz", expt_freq, real_freq);
654 /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
655 return real_freq;
656 }
657 return I2S_LL_DEFAULT_PLL_CLK_FREQ;
658 #else
659 if (use_apll) {
660 ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source");
661 }
662 return I2S_LL_DEFAULT_PLL_CLK_FREQ;
663 #endif
664 }
665
666 #if SOC_I2S_SUPPORTS_ADC || SOC_I2S_SUPPORTS_DAC
i2s_calculate_adc_dac_clock(int i2s_num,i2s_hal_clock_info_t * clk_info)667 static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_info_t *clk_info)
668 {
669 /* For ADC/DAC mode, the built-in ADC/DAC is driven by 'mclk' instead of 'bclk'
670 * 'bclk' should be fixed to the double of sample rate
671 * 'bclk_div' is the real coefficient that affects the slot bit */
672 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
673 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg;
674 uint32_t slot_bits = slot_cfg->slot_bit_width;
675 /* Set I2S bit clock */
676 clk_info->bclk = clk_cfg->sample_rate_hz * I2S_LL_AD_BCK_FACTOR;
677 /* Set I2S bit clock default division */
678 clk_info->bclk_div = slot_bits;
679 /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = bclk * bclk_div */
680 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
681 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div;
682 /* Calculate bclk_div = mclk / bclk */
683 clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
684 /* Get I2S system clock by config source clock */
685 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);
686 /* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
687 clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
688
689 /* Check if the configuration is correct */
690 ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large, the mclk division is below minimum value 2");
691 ESP_RETURN_ON_FALSE(clk_info->mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the maximum value 255");
692
693 return ESP_OK;
694 }
695 #endif // SOC_I2S_SUPPORTS_ADC || SOC_I2S_SUPPORTS_DAC
696
697 #if SOC_I2S_SUPPORTS_PDM_TX
i2s_calculate_pdm_tx_clock(int i2s_num,i2s_hal_clock_info_t * clk_info)698 static esp_err_t i2s_calculate_pdm_tx_clock(int i2s_num, i2s_hal_clock_info_t *clk_info)
699 {
700 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
701
702 int fp = clk_cfg->up_sample_fp;
703 int fs = clk_cfg->up_sample_fs;
704 /* Set I2S bit clock */
705 clk_info->bclk = clk_cfg->sample_rate_hz * I2S_LL_PDM_BCK_FACTOR * fp / fs;
706 /* Set I2S bit clock default division */
707 clk_info->bclk_div = 8;
708 /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate_hz * multiple */
709 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
710 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div;
711 /* Calculate bclk_div = mclk / bclk */
712 clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
713 /* Get I2S system clock by config source clock */
714 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);
715 /* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
716 clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
717
718 /* Check if the configuration is correct */
719 ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large, the mclk division is below minimum value 2");
720 ESP_RETURN_ON_FALSE(clk_info->mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the maximum value 255");
721
722 return ESP_OK;
723 }
724 #endif // SOC_I2S_SUPPORTS_PDM_TX
725
726 #if SOC_I2S_SUPPORTS_PDM_RX
i2s_calculate_pdm_rx_clock(int i2s_num,i2s_hal_clock_info_t * clk_info)727 static esp_err_t i2s_calculate_pdm_rx_clock(int i2s_num, i2s_hal_clock_info_t *clk_info)
728 {
729 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
730 i2s_pdm_dsr_t dsr = clk_cfg->dn_sample_mode;
731 /* Set I2S bit clock */
732 clk_info->bclk = clk_cfg->sample_rate_hz * I2S_LL_PDM_BCK_FACTOR * (dsr == I2S_PDM_DSR_16S ? 2 : 1);
733 /* Set I2S bit clock default division */
734 clk_info->bclk_div = 8;
735 /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate_hz * multiple */
736 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
737 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div;
738 /* Calculate bclk_div = mclk / bclk */
739 clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
740 /* Get I2S system clock by config source clock */
741 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);
742 /* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
743 clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
744
745 /* Check if the configuration is correct */
746 ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large, the mclk division is below minimum value 2");
747 ESP_RETURN_ON_FALSE(clk_info->mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the maximum value 255");
748
749 return ESP_OK;
750 }
751 #endif // SOC_I2S_SUPPORTS_PDM_RX
i2s_calculate_common_clock(int i2s_num,i2s_hal_clock_info_t * clk_info)752 static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_info_t *clk_info)
753 {
754 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
755 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg;
756 uint32_t rate = clk_cfg->sample_rate_hz;
757 uint32_t slot_num = p_i2s[i2s_num]->total_slot < 2 ? 2 : p_i2s[i2s_num]->total_slot;
758 uint32_t slot_bits = slot_cfg->slot_bit_width;
759 /* Calculate multiple */
760 if (p_i2s[i2s_num]->role == I2S_ROLE_MASTER) {
761 clk_info->bclk = rate * slot_num * slot_bits;
762 clk_info->mclk = rate * clk_cfg->mclk_multiple;
763 clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
764 } else {
765 /* For slave mode, mclk >= bclk * 8, so fix bclk_div to 8 first */
766 clk_info->bclk_div = 8;
767 clk_info->bclk = rate * slot_num * slot_bits;
768 clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
769 }
770 /* Get I2S system clock by config source clock */
771 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);
772 /* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
773 clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
774
775 /* Check if the configuration is correct */
776 ESP_RETURN_ON_FALSE(clk_info->mclk <= clk_info->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
777
778 return ESP_OK;
779 }
780
781
i2s_calculate_clock(i2s_port_t i2s_num,i2s_hal_clock_info_t * clk_info)782 static esp_err_t i2s_calculate_clock(i2s_port_t i2s_num, i2s_hal_clock_info_t *clk_info)
783 {
784 /* Calculate clock for ADC/DAC mode */
785 #if SOC_I2S_SUPPORTS_ADC_DAC
786 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) {
787 ESP_RETURN_ON_ERROR(i2s_calculate_adc_dac_clock(i2s_num, clk_info), TAG, "ADC/DAC clock calculate failed");
788 return ESP_OK;
789 }
790 #endif // SOC_I2S_SUPPORTS_ADC
791
792 /* Calculate clock for PDM mode */
793 #if SOC_I2S_SUPPORTS_PDM
794 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
795 #if SOC_I2S_SUPPORTS_PDM_TX
796 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
797 ESP_RETURN_ON_ERROR(i2s_calculate_pdm_tx_clock(i2s_num, clk_info), TAG, "PDM TX clock calculate failed");
798 }
799 #endif // SOC_I2S_SUPPORTS_PDM_TX
800 #if SOC_I2S_SUPPORTS_PDM_RX
801 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
802 ESP_RETURN_ON_ERROR(i2s_calculate_pdm_rx_clock(i2s_num, clk_info), TAG, "PDM RX clock calculate failed");
803 }
804 #endif // SOC_I2S_SUPPORTS_PDM_RX
805 return ESP_OK;
806 }
807 #endif // SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
808
809 /* Calculate clock for common mode */
810 ESP_RETURN_ON_ERROR(i2s_calculate_common_clock(i2s_num, clk_info), TAG, "Common clock calculate failed");
811 ESP_LOGD(TAG, "[sclk] %"PRIu32" [mclk] %"PRIu32" [mclk_div] %d [bclk] %"PRIu32" [bclk_div] %d",
812 clk_info->sclk, clk_info->mclk, clk_info->mclk_div, clk_info->bclk, clk_info->bclk_div);
813 return ESP_OK;
814 }
815
816 /*-------------------------------------------------------------
817 I2S configuration
818 -------------------------------------------------------------*/
819 #if SOC_I2S_SUPPORTS_ADC_DAC
i2s_dac_set_slot_legacy(void)820 static void i2s_dac_set_slot_legacy(void)
821 {
822 i2s_dev_t *dev = p_i2s[0]->hal.dev;
823 i2s_hal_slot_config_t *slot_cfg = &p_i2s[0]->slot_cfg;
824
825 i2s_ll_tx_reset(dev);
826 i2s_ll_tx_set_slave_mod(dev, false);
827 i2s_ll_tx_set_sample_bit(dev, slot_cfg->slot_bit_width, slot_cfg->data_bit_width);
828 i2s_ll_tx_enable_mono_mode(dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO);
829 i2s_ll_tx_enable_msb_shift(dev, false);
830 i2s_ll_tx_set_ws_width(dev, slot_cfg->slot_bit_width);
831 i2s_ll_tx_enable_msb_right(dev, false);
832 i2s_ll_tx_enable_right_first(dev, true);
833 /* Should always enable fifo */
834 i2s_ll_tx_force_enable_fifo_mod(dev, true);
835 }
836
i2s_set_dac_mode(i2s_dac_mode_t dac_mode)837 esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode)
838 {
839 ESP_RETURN_ON_FALSE((dac_mode < I2S_DAC_CHANNEL_MAX), ESP_ERR_INVALID_ARG, TAG, "i2s dac mode error");
840 if (dac_mode == I2S_DAC_CHANNEL_DISABLE) {
841 dac_ll_power_down(DAC_CHAN_0);
842 dac_ll_power_down(DAC_CHAN_1);
843 dac_ll_digi_enable_dma(false);
844 } else {
845 dac_ll_digi_enable_dma(true);
846 }
847
848 if (dac_mode & I2S_DAC_CHANNEL_RIGHT_EN) {
849 //DAC1, right channel
850 dac_ll_power_on(DAC_CHAN_0);
851 dac_ll_rtc_sync_by_adc(false);
852 }
853 if (dac_mode & I2S_DAC_CHANNEL_LEFT_EN) {
854 //DAC2, left channel
855 dac_ll_power_on(DAC_CHAN_1);
856 dac_ll_rtc_sync_by_adc(false);
857 }
858 return ESP_OK;
859 }
860
i2s_adc_set_slot_legacy(void)861 static void i2s_adc_set_slot_legacy(void)
862 {
863 i2s_dev_t *dev = p_i2s[0]->hal.dev;
864 i2s_hal_slot_config_t *slot_cfg = &p_i2s[0]->slot_cfg;
865 // When ADC/DAC are installed as duplex mode, ADC will share the WS and BCLK clock by working in slave mode
866 i2s_ll_rx_set_slave_mod(dev, false);
867 i2s_ll_rx_set_sample_bit(dev, slot_cfg->slot_bit_width, slot_cfg->data_bit_width);
868 i2s_ll_rx_enable_mono_mode(dev, true); // ADC should use mono mode to meet the sample rate
869 i2s_ll_rx_enable_msb_shift(dev, false);
870 i2s_ll_rx_set_ws_width(dev, slot_cfg->slot_bit_width);
871 i2s_ll_rx_enable_msb_right(dev, false);
872 i2s_ll_rx_enable_right_first(dev, false);
873 /* Should always enable fifo */
874 i2s_ll_rx_force_enable_fifo_mod(dev, true);
875 }
876
877 static int _i2s_adc_unit = -1;
878 static int _i2s_adc_channel = -1;
879
_i2s_adc_mode_recover(void)880 static esp_err_t _i2s_adc_mode_recover(void)
881 {
882 ESP_RETURN_ON_FALSE(((_i2s_adc_unit != -1) && (_i2s_adc_channel != -1)), ESP_ERR_INVALID_ARG, TAG, "i2s ADC recover error, not initialized...");
883 return adc_i2s_mode_init(_i2s_adc_unit, _i2s_adc_channel);
884 }
885
i2s_set_adc_mode(adc_unit_t adc_unit,adc1_channel_t adc_channel)886 esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel)
887 {
888 ESP_RETURN_ON_FALSE((adc_unit < ADC_UNIT_2), ESP_ERR_INVALID_ARG, TAG, "i2s ADC unit error, only support ADC1 for now");
889 // For now, we only support SAR ADC1.
890 _i2s_adc_unit = adc_unit;
891 _i2s_adc_channel = adc_channel;
892 return adc_i2s_mode_init(adc_unit, adc_channel);
893 }
894
i2s_adc_enable(i2s_port_t i2s_num)895 esp_err_t i2s_adc_enable(i2s_port_t i2s_num)
896 {
897 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
898 ESP_RETURN_ON_FALSE((p_i2s[i2s_num] != NULL), ESP_ERR_INVALID_STATE, TAG, "Not initialized yet");
899 ESP_RETURN_ON_FALSE(((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) && (p_i2s[i2s_num]->dir & I2S_DIR_RX),
900 ESP_ERR_INVALID_STATE, TAG, "i2s built-in adc not enabled");
901
902 adc1_dma_mode_acquire();
903 _i2s_adc_mode_recover();
904 i2s_rx_reset(i2s_num);
905 return i2s_start(i2s_num);
906 }
907
i2s_adc_disable(i2s_port_t i2s_num)908 esp_err_t i2s_adc_disable(i2s_port_t i2s_num)
909 {
910 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
911 ESP_RETURN_ON_FALSE((p_i2s[i2s_num] != NULL), ESP_ERR_INVALID_STATE, TAG, "Not initialized yet");
912 ESP_RETURN_ON_FALSE(((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) && (p_i2s[i2s_num]->dir & I2S_DIR_RX),
913 ESP_ERR_INVALID_STATE, TAG, "i2s built-in adc not enabled");
914
915 i2s_hal_rx_stop(&(p_i2s[i2s_num]->hal));
916 adc1_lock_release();
917 return ESP_OK;
918 }
919 #endif
920
i2s_check_cfg_validity(i2s_port_t i2s_num,const i2s_config_t * cfg)921 static esp_err_t i2s_check_cfg_validity(i2s_port_t i2s_num, const i2s_config_t *cfg)
922 {
923 /* Step 1: Check the validity of input parameters */
924 /* Check the validity of i2s device number */
925 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
926 ESP_RETURN_ON_FALSE(p_i2s[i2s_num] == NULL, ESP_ERR_INVALID_STATE, TAG, "this i2s port is in use");
927 ESP_RETURN_ON_FALSE(cfg, ESP_ERR_INVALID_ARG, TAG, "I2S configuration must not be NULL");
928 /* Check the size of DMA buffer */
929 ESP_RETURN_ON_FALSE((cfg->dma_desc_num >= 2 && cfg->dma_desc_num <= 128), ESP_ERR_INVALID_ARG, TAG, "I2S buffer count less than 128 and more than 2");
930 ESP_RETURN_ON_FALSE((cfg->dma_frame_num >= 8 && cfg->dma_frame_num <= 1024), ESP_ERR_INVALID_ARG, TAG, "I2S buffer length at most 1024 and more than 8");
931
932
933 #if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
934 /* Check PDM mode */
935 if (cfg->mode & I2S_MODE_PDM) {
936 ESP_RETURN_ON_FALSE(i2s_num == I2S_NUM_0, ESP_ERR_INVALID_ARG, TAG, "I2S PDM mode only support on I2S0");
937 #if !SOC_I2S_SUPPORTS_PDM_TX
938 ESP_RETURN_ON_FALSE(!(cfg->mode & I2S_MODE_TX), ESP_ERR_INVALID_ARG, TAG, "PDM does not support TX on this chip");
939 #endif // SOC_I2S_SUPPORTS_PDM_TX
940 #if !SOC_I2S_SUPPORTS_PDM_RX
941 ESP_RETURN_ON_FALSE(!(cfg->mode & I2S_MODE_RX), ESP_ERR_INVALID_ARG, TAG, "PDM does not support RX on this chip");
942 #endif // SOC_I2S_SUPPORTS_PDM_RX
943 }
944 #else
945 ESP_RETURN_ON_FALSE(!(cfg->mode & I2S_MODE_PDM), ESP_ERR_INVALID_ARG, TAG, "I2S PDM mode not supported on current chip");
946 #endif // SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
947
948 #if SOC_I2S_SUPPORTS_ADC || SOC_I2S_SUPPORTS_DAC
949 /* Check built-in ADC/DAC mode */
950 if (cfg->mode & (I2S_MODE_ADC_BUILT_IN | I2S_MODE_DAC_BUILT_IN)) {
951 ESP_RETURN_ON_FALSE(i2s_num == I2S_NUM_0, ESP_ERR_INVALID_ARG, TAG, "I2S built-in ADC/DAC only support on I2S0");
952 }
953 #else
954 /* Check the transmit/receive mode */
955 ESP_RETURN_ON_FALSE((cfg->mode & I2S_MODE_TX) || (cfg->mode & I2S_MODE_RX), ESP_ERR_INVALID_ARG, TAG, "I2S no TX/RX mode selected");
956 /* Check communication format */
957 ESP_RETURN_ON_FALSE(cfg->communication_format && (cfg->communication_format < I2S_COMM_FORMAT_STAND_MAX), ESP_ERR_INVALID_ARG, TAG, "invalid communication formats");
958 #endif // SOC_I2S_SUPPORTS_ADC || SOC_I2S_SUPPORTS_DAC
959
960 return ESP_OK;
961 }
962
i2s_set_slot_legacy(i2s_port_t i2s_num)963 static void i2s_set_slot_legacy(i2s_port_t i2s_num)
964 {
965 bool is_tx_slave = p_i2s[i2s_num]->role == I2S_ROLE_SLAVE;
966 bool is_rx_slave = is_tx_slave;
967 if (p_i2s[i2s_num]->dir == (I2S_DIR_TX | I2S_DIR_RX)) {
968 i2s_ll_share_bck_ws(p_i2s[i2s_num]->hal.dev, true);
969 /* Since bck and ws are shared, only tx or rx can be master
970 Force to set rx as slave to avoid conflict of clock signal */
971 is_rx_slave = true;
972 } else {
973 i2s_ll_share_bck_ws(p_i2s[i2s_num]->hal.dev, false);
974 }
975 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
976 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
977 i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
978 }
979 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
980 i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
981 }
982 }
983 #if SOC_I2S_SUPPORTS_PDM
984 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
985 #if SOC_I2S_SUPPORTS_PDM_TX
986 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
987 i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
988 }
989 #endif
990 #if SOC_I2S_SUPPORTS_PDM_RX
991 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
992 i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
993 }
994 #endif
995 }
996 #endif
997 #if SOC_I2S_SUPPORTS_TDM
998 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
999 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1000 i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
1001 }
1002 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1003 i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
1004 }
1005 }
1006 #endif
1007 #if SOC_I2S_SUPPORTS_ADC_DAC
1008 else if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) {
1009 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1010 i2s_dac_set_slot_legacy();
1011 }
1012 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1013 i2s_adc_set_slot_legacy();
1014 }
1015 }
1016 #endif
1017 }
1018
i2s_set_clock_legacy(i2s_port_t i2s_num)1019 static void i2s_set_clock_legacy(i2s_port_t i2s_num)
1020 {
1021 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
1022 i2s_hal_clock_info_t clk_info;
1023 i2s_calculate_clock(i2s_num, &clk_info);
1024 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1025 i2s_hal_set_tx_clock(&(p_i2s[i2s_num]->hal), &clk_info, clk_cfg->clk_src);
1026 }
1027 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1028 i2s_hal_set_rx_clock(&(p_i2s[i2s_num]->hal), &clk_info, clk_cfg->clk_src);
1029 }
1030 }
1031
i2s_get_clk(i2s_port_t i2s_num)1032 float i2s_get_clk(i2s_port_t i2s_num)
1033 {
1034 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1035 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
1036 return (float)clk_cfg->sample_rate_hz;
1037 }
1038
i2s_set_clk(i2s_port_t i2s_num,uint32_t rate,uint32_t bits_cfg,i2s_channel_t ch)1039 esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, uint32_t bits_cfg, i2s_channel_t ch)
1040 {
1041 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1042 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_ARG, TAG, "I2S%d has not installed yet", i2s_num);
1043
1044 /* Acquire the lock before stop i2s, otherwise reading/writing operation will stuck on receiving the message queue from interrupt */
1045 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) {
1046 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY);
1047 }
1048 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) {
1049 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY);
1050 }
1051
1052 /* Stop I2S */
1053 i2s_stop(i2s_num);
1054
1055 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg;
1056 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg;
1057
1058 clk_cfg->sample_rate_hz = rate;
1059 slot_cfg->data_bit_width = bits_cfg & 0xFFFF;
1060 ESP_RETURN_ON_FALSE((slot_cfg->data_bit_width % 8 == 0), ESP_ERR_INVALID_ARG, TAG, "Invalid bits per sample");
1061 slot_cfg->slot_bit_width = (bits_cfg >> 16) > slot_cfg->data_bit_width ?
1062 (bits_cfg >> 16) : slot_cfg->data_bit_width;
1063 ESP_RETURN_ON_FALSE((slot_cfg->slot_bit_width % 8 == 0), ESP_ERR_INVALID_ARG, TAG, "Invalid bits per channel");
1064 ESP_RETURN_ON_FALSE(((int)slot_cfg->slot_bit_width <= (int)I2S_BITS_PER_SAMPLE_32BIT), ESP_ERR_INVALID_ARG, TAG, "Invalid bits per sample");
1065 slot_cfg->slot_mode = ((ch & 0xFFFF) == I2S_CHANNEL_MONO) ? I2S_SLOT_MODE_MONO : I2S_SLOT_MODE_STEREO;
1066 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
1067 if (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) {
1068 if (slot_cfg->std.slot_mask == I2S_STD_SLOT_BOTH) {
1069 slot_cfg->std.slot_mask = I2S_STD_SLOT_LEFT;
1070 #if SOC_I2S_HW_VERSION_1
1071 // Enable right first to get correct data sequence
1072 slot_cfg->std.ws_pol = !slot_cfg->std.ws_pol;
1073 #endif
1074 }
1075 } else {
1076 slot_cfg->std.slot_mask = I2S_STD_SLOT_BOTH;
1077 }
1078 }
1079 #if SOC_I2S_SUPPORTS_TDM
1080 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
1081 uint32_t slot_mask = ch >> 16;
1082 if (slot_mask == 0) {
1083 slot_mask = (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? 1 : 2;
1084 }
1085 ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->total_slot >= (32 - __builtin_clz(slot_mask)), ESP_ERR_INVALID_ARG, TAG,
1086 "The max channel number can't be greater than CH%"PRIu32, p_i2s[i2s_num]->total_slot);
1087 p_i2s[i2s_num]->active_slot = __builtin_popcount(slot_mask);
1088 } else
1089 #endif
1090 {
1091 p_i2s[i2s_num]->active_slot = (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? 1 : 2;
1092 }
1093
1094 i2s_set_slot_legacy(i2s_num);
1095 i2s_set_clock_legacy(i2s_num);
1096
1097 uint32_t buf_size = i2s_get_buf_size(i2s_num);
1098 bool need_realloc = buf_size != p_i2s[i2s_num]->last_buf_size;
1099
1100 if (need_realloc) {
1101 esp_err_t ret = ESP_OK;
1102 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1103 p_i2s[i2s_num]->tx->buf_size = buf_size;
1104 ret = i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->tx);
1105 xQueueReset(p_i2s[i2s_num]->tx->queue);
1106 ESP_RETURN_ON_ERROR(ret, TAG, "I2S%d tx DMA buffer malloc failed", i2s_num);
1107 }
1108 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1109 p_i2s[i2s_num]->rx->buf_size = buf_size;
1110 ret = i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->rx);
1111 xQueueReset(p_i2s[i2s_num]->rx->queue);
1112 ESP_RETURN_ON_ERROR(ret, TAG, "I2S%d rx DMA buffer malloc failed", i2s_num);
1113 }
1114 }
1115 /* Update last buffer size */
1116 p_i2s[i2s_num]->last_buf_size = buf_size;
1117
1118 /* I2S start */
1119 i2s_start(i2s_num);
1120
1121 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) {
1122 xSemaphoreGive(p_i2s[i2s_num]->tx->mux);
1123 }
1124 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) {
1125 xSemaphoreGive(p_i2s[i2s_num]->rx->mux);
1126 }
1127
1128 return ESP_OK;
1129 }
1130
i2s_set_sample_rates(i2s_port_t i2s_num,uint32_t rate)1131 esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate)
1132 {
1133 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1134 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg;
1135 uint32_t mask = 0;
1136 #if SOC_I2S_SUPPORTS_TDM
1137 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
1138 mask = slot_cfg->tdm.slot_mask;
1139 }
1140 #endif
1141 return i2s_set_clk(i2s_num, rate, slot_cfg->data_bit_width, slot_cfg->slot_mode | (mask << 16));
1142 }
1143
1144 #if SOC_I2S_SUPPORTS_PCM
1145
i2s_pcm_config(i2s_port_t i2s_num,const i2s_pcm_cfg_t * pcm_cfg)1146 esp_err_t i2s_pcm_config(i2s_port_t i2s_num, const i2s_pcm_cfg_t *pcm_cfg)
1147 {
1148 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet");
1149
1150 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) {
1151 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY);
1152 }
1153 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) {
1154 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY);
1155 }
1156
1157 i2s_stop(i2s_num);
1158 I2S_ENTER_CRITICAL(i2s_num);
1159 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1160 i2s_ll_tx_set_pcm_type(p_i2s[i2s_num]->hal.dev, pcm_cfg->pcm_type);
1161 }
1162 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1163 i2s_ll_rx_set_pcm_type(p_i2s[i2s_num]->hal.dev, pcm_cfg->pcm_type);
1164 }
1165 I2S_EXIT_CRITICAL(i2s_num);
1166 i2s_start(i2s_num);
1167
1168 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) {
1169 xSemaphoreGive(p_i2s[i2s_num]->tx->mux);
1170 }
1171 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) {
1172 xSemaphoreGive(p_i2s[i2s_num]->rx->mux);
1173 }
1174
1175 return ESP_OK;
1176 }
1177 #endif
1178
1179 #if SOC_I2S_SUPPORTS_PDM_RX
i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num,i2s_pdm_dsr_t downsample)1180 esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t downsample)
1181 {
1182 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet");
1183 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM), ESP_ERR_INVALID_ARG, TAG, "i2s mode is not PDM mode");
1184 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY);
1185 i2s_stop(i2s_num);
1186 p_i2s[i2s_num]->clk_cfg.dn_sample_mode = downsample;
1187 i2s_ll_rx_set_pdm_dsr(p_i2s[i2s_num]->hal.dev, downsample);
1188 i2s_start(i2s_num);
1189 xSemaphoreGive(p_i2s[i2s_num]->rx->mux);
1190 return i2s_set_clk(i2s_num, p_i2s[i2s_num]->clk_cfg.sample_rate_hz, p_i2s[i2s_num]->slot_cfg.data_bit_width, p_i2s[i2s_num]->slot_cfg.slot_mode);
1191 }
1192 #endif
1193
1194 #if SOC_I2S_SUPPORTS_PDM_TX
i2s_set_pdm_tx_up_sample(i2s_port_t i2s_num,const i2s_pdm_tx_upsample_cfg_t * upsample_cfg)1195 esp_err_t i2s_set_pdm_tx_up_sample(i2s_port_t i2s_num, const i2s_pdm_tx_upsample_cfg_t *upsample_cfg)
1196 {
1197 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet");
1198 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) && (p_i2s[i2s_num]->dir & I2S_DIR_TX),
1199 ESP_ERR_INVALID_ARG, TAG, "i2s mode is not PDM mode");
1200 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY);
1201 i2s_stop(i2s_num);
1202 p_i2s[i2s_num]->clk_cfg.up_sample_fp = upsample_cfg->fp;
1203 p_i2s[i2s_num]->clk_cfg.up_sample_fs = upsample_cfg->fs;
1204 i2s_ll_tx_set_pdm_fpfs(p_i2s[i2s_num]->hal.dev, upsample_cfg->fp, upsample_cfg->fs);
1205 i2s_ll_tx_set_pdm_over_sample_ratio(p_i2s[i2s_num]->hal.dev, upsample_cfg->fp / upsample_cfg->fs);
1206 i2s_start(i2s_num);
1207 xSemaphoreGive(p_i2s[i2s_num]->tx->mux);
1208 return i2s_set_clk(i2s_num, p_i2s[i2s_num]->clk_cfg.sample_rate_hz, p_i2s[i2s_num]->slot_cfg.data_bit_width, p_i2s[i2s_num]->slot_cfg.slot_mode);
1209 }
1210 #endif
1211
i2s_dma_object_init(i2s_port_t i2s_num)1212 static esp_err_t i2s_dma_object_init(i2s_port_t i2s_num)
1213 {
1214 uint32_t buf_size = i2s_get_buf_size(i2s_num);
1215 p_i2s[i2s_num]->last_buf_size = buf_size;
1216 /* Create DMA object */
1217 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1218 ESP_RETURN_ON_ERROR(i2s_create_dma_object(i2s_num, &p_i2s[i2s_num]->tx), TAG, "I2S TX DMA object create failed");
1219 p_i2s[i2s_num]->tx->buf_size = buf_size;
1220 }
1221 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1222 ESP_RETURN_ON_ERROR(i2s_create_dma_object(i2s_num, &p_i2s[i2s_num]->rx), TAG, "I2S RX DMA object create failed");
1223 p_i2s[i2s_num]->rx->buf_size = buf_size;
1224 }
1225 return ESP_OK;
1226 }
1227
i2s_mode_identify(i2s_port_t i2s_num,const i2s_config_t * i2s_config)1228 static void i2s_mode_identify(i2s_port_t i2s_num, const i2s_config_t *i2s_config)
1229 {
1230
1231 p_i2s[i2s_num]->mode = I2S_COMM_MODE_STD;
1232
1233 if (i2s_config->mode & I2S_MODE_MASTER) {
1234 p_i2s[i2s_num]->role = I2S_ROLE_MASTER;
1235 } else if (i2s_config->mode & I2S_MODE_SLAVE) {
1236 p_i2s[i2s_num]->role = I2S_ROLE_SLAVE;
1237 }
1238 if (i2s_config->mode & I2S_MODE_TX) {
1239 p_i2s[i2s_num]->dir |= I2S_DIR_TX;
1240 }
1241 if (i2s_config->mode & I2S_MODE_RX) {
1242 p_i2s[i2s_num]->dir |= I2S_DIR_RX;
1243 }
1244 #if SOC_I2S_SUPPORTS_PDM
1245 if (i2s_config->mode & I2S_MODE_PDM) {
1246 p_i2s[i2s_num]->mode = I2S_COMM_MODE_PDM;
1247 }
1248 #endif // SOC_I2S_SUPPORTS_PDM
1249
1250 #if SOC_I2S_SUPPORTS_TDM
1251 if (i2s_config->channel_format == I2S_CHANNEL_FMT_MULTIPLE) {
1252 p_i2s[i2s_num]->mode = I2S_COMM_MODE_TDM;
1253 }
1254 #endif // SOC_I2S_SUPPORTS_TDM
1255
1256 #if SOC_I2S_SUPPORTS_ADC_DAC
1257 if ((i2s_config->mode & I2S_MODE_DAC_BUILT_IN) ||
1258 (i2s_config->mode & I2S_MODE_ADC_BUILT_IN)) {
1259 p_i2s[i2s_num]->mode = (i2s_comm_mode_t)I2S_COMM_MODE_ADC_DAC;
1260 }
1261 #endif // SOC_I2S_SUPPORTS_ADC_DAC
1262 }
1263
i2s_config_transfer(i2s_port_t i2s_num,const i2s_config_t * i2s_config)1264 static esp_err_t i2s_config_transfer(i2s_port_t i2s_num, const i2s_config_t *i2s_config)
1265 {
1266 #define SLOT_CFG(m) p_i2s[i2s_num]->slot_cfg.m
1267 #define CLK_CFG() p_i2s[i2s_num]->clk_cfg
1268 /* Convert legacy configuration into general part of slot and clock configuration */
1269 p_i2s[i2s_num]->slot_cfg.data_bit_width = i2s_config->bits_per_sample;
1270 p_i2s[i2s_num]->slot_cfg.slot_bit_width = (int)i2s_config->bits_per_chan < (int)i2s_config->bits_per_sample ?
1271 i2s_config->bits_per_sample : i2s_config->bits_per_chan;
1272
1273 p_i2s[i2s_num]->slot_cfg.slot_mode = i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ?
1274 I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO;
1275 CLK_CFG().sample_rate_hz = i2s_config->sample_rate;
1276 CLK_CFG().mclk_multiple = i2s_config->mclk_multiple == 0 ? I2S_MCLK_MULTIPLE_256 : i2s_config->mclk_multiple;
1277 CLK_CFG().clk_src = I2S_CLK_SRC_DEFAULT;
1278 p_i2s[i2s_num]->fixed_mclk = i2s_config->fixed_mclk;
1279 p_i2s[i2s_num]->use_apll = false;
1280 #if SOC_I2S_SUPPORTS_APLL
1281 CLK_CFG().clk_src = i2s_config->use_apll ? I2S_CLK_SRC_APLL : I2S_CLK_SRC_DEFAULT;
1282 p_i2s[i2s_num]->use_apll = i2s_config->use_apll;
1283 #endif // SOC_I2S_SUPPORTS_APLL
1284
1285 /* Convert legacy configuration into particular part of slot and clock configuration */
1286 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
1287 /* Generate STD slot configuration */
1288 SLOT_CFG(std).ws_width = i2s_config->bits_per_sample;
1289 SLOT_CFG(std).ws_pol = false;
1290 if (i2s_config->channel_format == I2S_CHANNEL_FMT_RIGHT_LEFT) {
1291 SLOT_CFG(std).slot_mask = I2S_STD_SLOT_BOTH;
1292 } else if (i2s_config->channel_format == I2S_CHANNEL_FMT_ALL_LEFT ||
1293 i2s_config->channel_format == I2S_CHANNEL_FMT_ONLY_LEFT) {
1294 SLOT_CFG(std).slot_mask = I2S_STD_SLOT_LEFT;
1295 } else {
1296 SLOT_CFG(std).slot_mask = I2S_STD_SLOT_RIGHT;
1297 }
1298 if (i2s_config->communication_format == I2S_COMM_FORMAT_STAND_I2S) {
1299 SLOT_CFG(std).bit_shift = true;
1300 }
1301 if (i2s_config->communication_format & I2S_COMM_FORMAT_STAND_PCM_SHORT) {
1302 SLOT_CFG(std).bit_shift = true;
1303 SLOT_CFG(std).ws_width = 1;
1304 SLOT_CFG(std).ws_pol = true;
1305 }
1306 #if SOC_I2S_HW_VERSION_1
1307 SLOT_CFG(std).msb_right = true;
1308 #elif SOC_I2S_HW_VERSION_2
1309 SLOT_CFG(std).left_align = i2s_config->left_align;
1310 SLOT_CFG(std).big_endian = i2s_config->big_edin;
1311 SLOT_CFG(std).bit_order_lsb = i2s_config->bit_order_msb; // The old name is incorrect
1312 #endif // SOC_I2S_HW_VERSION_1
1313
1314 p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2;
1315 p_i2s[i2s_num]->total_slot = 2;
1316 goto finish;
1317 }
1318 #if SOC_I2S_SUPPORTS_PDM_TX
1319 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
1320 /* Generate PDM TX slot configuration */
1321 SLOT_CFG(pdm_tx).sd_prescale = 0;
1322 SLOT_CFG(pdm_tx).sd_scale = I2S_PDM_SIG_SCALING_MUL_1;
1323 SLOT_CFG(pdm_tx).hp_scale = I2S_PDM_SIG_SCALING_MUL_1;
1324 SLOT_CFG(pdm_tx).lp_scale = I2S_PDM_SIG_SCALING_MUL_1;
1325 SLOT_CFG(pdm_tx).sinc_scale = I2S_PDM_SIG_SCALING_MUL_1;
1326 #if SOC_I2S_HW_VERSION_2
1327 SLOT_CFG(pdm_tx).line_mode = I2S_PDM_TX_ONE_LINE_CODEC;
1328 SLOT_CFG(pdm_tx).hp_en = true;
1329 SLOT_CFG(pdm_tx).hp_cut_off_freq_hz = 49;
1330 SLOT_CFG(pdm_tx).sd_dither = 0;
1331 SLOT_CFG(pdm_tx).sd_dither2 = 1;
1332 #endif // SOC_I2S_HW_VERSION_2
1333
1334 /* Generate PDM TX clock configuration */
1335 CLK_CFG().up_sample_fp = 960;
1336 CLK_CFG().up_sample_fs = i2s_config->sample_rate / 100;
1337 p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2;
1338 p_i2s[i2s_num]->total_slot = 2;
1339 goto finish;
1340 }
1341 #endif // SOC_I2S_SUPPORTS_PDM_TX
1342
1343 #if SOC_I2S_SUPPORTS_PDM_RX
1344 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
1345 /* Generate PDM RX clock configuration */
1346 CLK_CFG().dn_sample_mode = I2S_PDM_DSR_8S;
1347 p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2;
1348 p_i2s[i2s_num]->total_slot = 2;
1349 goto finish;
1350 }
1351 #endif // SOC_I2S_SUPPOTYS_PDM_RX
1352
1353 #if SOC_I2S_SUPPORTS_TDM
1354 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
1355 /* Generate TDM slot configuration */
1356 SLOT_CFG(tdm).slot_mask = i2s_config->chan_mask >> 16;
1357
1358 SLOT_CFG(tdm).ws_width = 0; // I2S_TDM_AUTO_WS_WIDTH
1359 p_i2s[i2s_num]->slot_cfg.slot_mode = I2S_SLOT_MODE_STEREO;
1360 SLOT_CFG(tdm).ws_pol = false;
1361 if (i2s_config->communication_format == I2S_COMM_FORMAT_STAND_I2S) {
1362 SLOT_CFG(tdm).bit_shift = true;
1363 } else if (i2s_config->communication_format == I2S_COMM_FORMAT_STAND_PCM_SHORT) {
1364 SLOT_CFG(tdm).bit_shift = true;
1365 SLOT_CFG(tdm).ws_width = 1;
1366 SLOT_CFG(tdm).ws_pol = true;
1367 } else if (i2s_config->communication_format == I2S_COMM_FORMAT_STAND_PCM_LONG) {
1368 SLOT_CFG(tdm).bit_shift = true;
1369 SLOT_CFG(tdm).ws_width = p_i2s[i2s_num]->slot_cfg.slot_bit_width;
1370 SLOT_CFG(tdm).ws_pol = true;
1371 }
1372 SLOT_CFG(tdm).left_align = i2s_config->left_align;
1373 SLOT_CFG(tdm).big_endian = i2s_config->big_edin;
1374 SLOT_CFG(tdm).bit_order_lsb = i2s_config->bit_order_msb; // The old name is incorrect
1375 SLOT_CFG(tdm).skip_mask = i2s_config->skip_msk;
1376
1377 /* Generate TDM clock configuration */
1378 p_i2s[i2s_num]->active_slot = __builtin_popcount(SLOT_CFG(tdm).slot_mask);
1379 uint32_t mx_slot = 32 - __builtin_clz(SLOT_CFG(tdm).slot_mask);
1380 mx_slot = mx_slot < 2 ? 2 : mx_slot;
1381 p_i2s[i2s_num]->total_slot = mx_slot < i2s_config->total_chan ? mx_slot : i2s_config->total_chan;
1382 goto finish;
1383 }
1384 #endif // SOC_I2S_SUPPORTS_TDM
1385
1386 #if SOC_I2S_SUPPORTS_ADC_DAC
1387 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) {
1388 p_i2s[i2s_num]->slot_cfg.slot_mode = (p_i2s[i2s_num]->dir & I2S_DIR_TX) ?
1389 I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO;
1390 p_i2s[i2s_num]->active_slot = (p_i2s[i2s_num]->dir & I2S_DIR_TX) ? 2 : 1;
1391 p_i2s[i2s_num]->total_slot = 2;
1392 }
1393 #endif // SOC_I2S_SUPPORTS_ADC_DAC
1394
1395 #undef SLOT_CFG
1396 #undef CLK_CFG
1397
1398 finish:
1399 return ESP_OK;
1400 }
1401
i2s_init_legacy(i2s_port_t i2s_num,int intr_alloc_flag)1402 static esp_err_t i2s_init_legacy(i2s_port_t i2s_num, int intr_alloc_flag)
1403 {
1404 /* Create power management lock */
1405 #ifdef CONFIG_PM_ENABLE
1406 esp_pm_lock_type_t pm_lock = ESP_PM_APB_FREQ_MAX;
1407 #if SOC_I2S_SUPPORTS_APLL
1408 if (p_i2s[i2s_num]->use_apll) {
1409 pm_lock = ESP_PM_NO_LIGHT_SLEEP;
1410 }
1411 #endif // SOC_I2S_SUPPORTS_APLL
1412 ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock, 0, "i2s_driver", &p_i2s[i2s_num]->pm_lock), TAG, "I2S pm lock error");
1413 #endif //CONFIG_PM_ENABLE
1414
1415 #if SOC_I2S_SUPPORTS_APLL
1416 if (p_i2s[i2s_num]->use_apll) {
1417 periph_rtc_apll_acquire();
1418 }
1419 #endif
1420
1421 /* Enable communicaiton mode */
1422 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
1423 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1424 i2s_hal_std_enable_tx_channel(&(p_i2s[i2s_num]->hal));
1425 }
1426 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1427 i2s_hal_std_enable_rx_channel(&(p_i2s[i2s_num]->hal));
1428 }
1429 }
1430 #if SOC_I2S_SUPPORTS_PDM
1431 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
1432 #if SOC_I2S_SUPPORTS_PDM_TX
1433 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1434 i2s_hal_pdm_enable_tx_channel(&(p_i2s[i2s_num]->hal));
1435 }
1436 #endif
1437 #if SOC_I2S_SUPPORTS_PDM_RX
1438 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1439 i2s_hal_pdm_enable_rx_channel(&(p_i2s[i2s_num]->hal));
1440 }
1441 #endif
1442 }
1443 #endif
1444 #if SOC_I2S_SUPPORTS_TDM
1445 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
1446 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1447 i2s_hal_tdm_enable_tx_channel(&(p_i2s[i2s_num]->hal));
1448 }
1449 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1450 i2s_hal_tdm_enable_rx_channel(&(p_i2s[i2s_num]->hal));
1451 }
1452 }
1453 #endif
1454 #if SOC_I2S_SUPPORTS_ADC_DAC
1455 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) {
1456 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1457 sar_periph_ctrl_adc_continuous_power_acquire();
1458 adc_set_i2s_data_source(ADC_I2S_DATA_SRC_ADC);
1459 i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, true);
1460 }
1461 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1462 i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, true);
1463 }
1464 } else {
1465 adc_set_i2s_data_source(ADC_I2S_DATA_SRC_IO_SIG);
1466 i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, false);
1467 i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, false);
1468 }
1469 #endif
1470
1471 i2s_set_slot_legacy(i2s_num);
1472 i2s_set_clock_legacy(i2s_num);
1473 ESP_RETURN_ON_ERROR(i2s_dma_intr_init(i2s_num, intr_alloc_flag), TAG, "I2S interrupt initailze failed");
1474 ESP_RETURN_ON_ERROR(i2s_dma_object_init(i2s_num), TAG, "I2S dma object create failed");
1475 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1476 ESP_RETURN_ON_ERROR(i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->tx), TAG, "Allocate I2S dma tx buffer failed");
1477 }
1478 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1479 ESP_RETURN_ON_ERROR(i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->rx), TAG, "Allocate I2S dma rx buffer failed");
1480 }
1481
1482 /* Initialize I2S DMA object */
1483 #if SOC_I2S_HW_VERSION_2
1484 /* Enable tx/rx submodule clock */
1485 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1486 i2s_ll_tx_enable_clock(p_i2s[i2s_num]->hal.dev);
1487 }
1488 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1489 i2s_ll_rx_enable_clock(p_i2s[i2s_num]->hal.dev);
1490 }
1491 #endif
1492
1493 return ESP_OK;
1494 }
1495
i2s_driver_uninstall(i2s_port_t i2s_num)1496 esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num)
1497 {
1498 ESP_RETURN_ON_FALSE(i2s_num < SOC_I2S_NUM, ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1499 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_STATE, TAG, "I2S port %d has not installed", i2s_num);
1500 i2s_obj_t *obj = p_i2s[i2s_num];
1501 i2s_stop(i2s_num);
1502
1503 #if SOC_I2S_SUPPORTS_ADC_DAC
1504 if ((int)(obj->mode) == I2S_COMM_MODE_ADC_DAC) {
1505 if (obj->dir & I2S_DIR_TX) {
1506 // Deinit DAC
1507 i2s_set_dac_mode(I2S_DAC_CHANNEL_DISABLE);
1508 }
1509 if (obj->dir & I2S_DIR_RX) {
1510 // Deinit ADC
1511 adc_set_i2s_data_source(ADC_I2S_DATA_SRC_IO_SIG);
1512 sar_periph_ctrl_adc_continuous_power_release();
1513 }
1514 }
1515 #endif
1516 #if SOC_GDMA_SUPPORTED
1517 if (obj->tx_dma_chan) {
1518 gdma_disconnect(obj->tx_dma_chan);
1519 gdma_del_channel(obj->tx_dma_chan);
1520 }
1521 if (obj->rx_dma_chan) {
1522 gdma_disconnect(obj->rx_dma_chan);
1523 gdma_del_channel(obj->rx_dma_chan);
1524 }
1525 #else
1526 if (obj->i2s_isr_handle) {
1527 esp_intr_free(obj->i2s_isr_handle);
1528 }
1529 #endif
1530 /* Destroy dma object if exist */
1531 i2s_destroy_dma_object(i2s_num, &obj->tx);
1532 i2s_destroy_dma_object(i2s_num, &obj->rx);
1533
1534 if (obj->i2s_queue) {
1535 vQueueDelete(obj->i2s_queue);
1536 obj->i2s_queue = NULL;
1537 }
1538
1539 #if SOC_I2S_SUPPORTS_APLL
1540 if (obj->use_apll) {
1541 // switch back to PLL clock source
1542 if (obj->dir & I2S_DIR_TX) {
1543 i2s_ll_tx_clk_set_src(obj->hal.dev, I2S_CLK_SRC_DEFAULT);
1544 }
1545 if (obj->dir & I2S_DIR_RX) {
1546 i2s_ll_rx_clk_set_src(obj->hal.dev, I2S_CLK_SRC_DEFAULT);
1547 }
1548 periph_rtc_apll_release();
1549 }
1550 #endif
1551
1552 #ifdef CONFIG_PM_ENABLE
1553 if (obj->pm_lock) {
1554 esp_pm_lock_delete(obj->pm_lock);
1555 obj->pm_lock = NULL;
1556 }
1557 #endif
1558 #if SOC_I2S_HW_VERSION_2
1559 if (obj->dir & I2S_DIR_TX) {
1560 i2s_ll_tx_disable_clock(obj->hal.dev);
1561 }
1562 if (obj->dir & I2S_DIR_RX) {
1563 i2s_ll_rx_disable_clock(obj->hal.dev);
1564 }
1565 #endif
1566 /* Disable module clock */
1567 i2s_platform_release_occupation(i2s_num);
1568 free(obj);
1569 p_i2s[i2s_num] = NULL;
1570 return ESP_OK;
1571 }
1572
1573
i2s_driver_install(i2s_port_t i2s_num,const i2s_config_t * i2s_config,int queue_size,void * i2s_queue)1574 esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue)
1575 {
1576 #if CONFIG_I2S_ENABLE_DEBUG_LOG
1577 esp_log_level_set(TAG, ESP_LOG_DEBUG);
1578 #endif
1579 esp_err_t ret = ESP_OK;
1580
1581 /* Step 1: Check the validity of input parameters */
1582 ESP_RETURN_ON_ERROR(i2s_check_cfg_validity(i2s_num, i2s_config), TAG, "I2S configuration is invalid");
1583
1584 /* Step 2: Allocate driver object and register to platform */
1585 i2s_obj_t *i2s_obj = calloc(1, sizeof(i2s_obj_t));
1586 ESP_RETURN_ON_FALSE(i2s_obj, ESP_ERR_NO_MEM, TAG, "no mem for I2S driver");
1587 if (i2s_platform_acquire_occupation(i2s_num, "i2s_legacy") != ESP_OK) {
1588 free(i2s_obj);
1589 ESP_LOGE(TAG, "register I2S object to platform failed");
1590 return ESP_ERR_INVALID_STATE;
1591 }
1592 p_i2s[i2s_num] = i2s_obj;
1593 i2s_hal_init(&i2s_obj->hal, i2s_num);
1594
1595 /* Step 3: Store and assign configarations */
1596 i2s_mode_identify(i2s_num, i2s_config);
1597 ESP_GOTO_ON_ERROR(i2s_config_transfer(i2s_num, i2s_config), err, TAG, "I2S install failed");
1598 i2s_obj->dma_desc_num = i2s_config->dma_desc_num;
1599 i2s_obj->dma_frame_num = i2s_config->dma_frame_num;
1600 i2s_obj->tx_desc_auto_clear = i2s_config->tx_desc_auto_clear;
1601
1602 /* Step 4: Apply configurations and init hardware */
1603 ESP_GOTO_ON_ERROR(i2s_init_legacy(i2s_num, i2s_config->intr_alloc_flags), err, TAG, "I2S init failed");
1604
1605 /* Step 5: Initialise i2s event queue if user needs */
1606 if (i2s_queue) {
1607 i2s_obj->i2s_queue = xQueueCreate(queue_size, sizeof(i2s_event_t));
1608 ESP_GOTO_ON_FALSE(i2s_obj->i2s_queue, ESP_ERR_NO_MEM, err, TAG, "I2S queue create failed");
1609 *((QueueHandle_t *) i2s_queue) = i2s_obj->i2s_queue;
1610 ESP_LOGD(TAG, "queue free spaces: %d", uxQueueSpacesAvailable(i2s_obj->i2s_queue));
1611 } else {
1612 i2s_obj->i2s_queue = NULL;
1613 }
1614
1615 /* Step 6: Start I2S for backward compatibility */
1616 ESP_GOTO_ON_ERROR(i2s_start(i2s_num), err, TAG, "I2S start failed");
1617
1618 return ESP_OK;
1619
1620 err:
1621 /* I2S install failed, prepare to uninstall */
1622 i2s_driver_uninstall(i2s_num);
1623 return ret;
1624 }
1625
i2s_write(i2s_port_t i2s_num,const void * src,size_t size,size_t * bytes_written,TickType_t ticks_to_wait)1626 esp_err_t i2s_write(i2s_port_t i2s_num, const void *src, size_t size, size_t *bytes_written, TickType_t ticks_to_wait)
1627 {
1628 char *data_ptr;
1629 char *src_byte;
1630 size_t bytes_can_write;
1631 *bytes_written = 0;
1632 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1633 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->tx), ESP_ERR_INVALID_ARG, TAG, "TX mode is not enabled");
1634 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY);
1635 #ifdef CONFIG_PM_ENABLE
1636 esp_pm_lock_acquire(p_i2s[i2s_num]->pm_lock);
1637 #endif
1638 src_byte = (char *)src;
1639 while (size > 0) {
1640 if (p_i2s[i2s_num]->tx->rw_pos == p_i2s[i2s_num]->tx->buf_size || p_i2s[i2s_num]->tx->curr_ptr == NULL) {
1641 if (xQueueReceive(p_i2s[i2s_num]->tx->queue, &p_i2s[i2s_num]->tx->curr_ptr, ticks_to_wait) == pdFALSE) {
1642 break;
1643 }
1644 p_i2s[i2s_num]->tx->rw_pos = 0;
1645 }
1646 ESP_LOGD(TAG, "size: %d, rw_pos: %d, buf_size: %d, curr_ptr: %d", size, p_i2s[i2s_num]->tx->rw_pos, p_i2s[i2s_num]->tx->buf_size, (int)p_i2s[i2s_num]->tx->curr_ptr);
1647 data_ptr = (char *)p_i2s[i2s_num]->tx->curr_ptr;
1648 data_ptr += p_i2s[i2s_num]->tx->rw_pos;
1649 bytes_can_write = p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos;
1650 if (bytes_can_write > size) {
1651 bytes_can_write = size;
1652 }
1653 memcpy(data_ptr, src_byte, bytes_can_write);
1654 size -= bytes_can_write;
1655 src_byte += bytes_can_write;
1656 p_i2s[i2s_num]->tx->rw_pos += bytes_can_write;
1657 (*bytes_written) += bytes_can_write;
1658 }
1659 #ifdef CONFIG_PM_ENABLE
1660 esp_pm_lock_release(p_i2s[i2s_num]->pm_lock);
1661 #endif
1662 xSemaphoreGive(p_i2s[i2s_num]->tx->mux);
1663 return ESP_OK;
1664 }
1665
i2s_write_expand(i2s_port_t i2s_num,const void * src,size_t size,size_t src_bits,size_t aim_bits,size_t * bytes_written,TickType_t ticks_to_wait)1666 esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, size_t src_bits, size_t aim_bits, size_t *bytes_written, TickType_t ticks_to_wait)
1667 {
1668 char *data_ptr;
1669 int bytes_can_write;
1670 int tail;
1671 int src_bytes;
1672 int aim_bytes;
1673 int zero_bytes;
1674 *bytes_written = 0;
1675 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1676 ESP_RETURN_ON_FALSE((size > 0), ESP_ERR_INVALID_ARG, TAG, "size must greater than zero");
1677 ESP_RETURN_ON_FALSE((aim_bits >= src_bits), ESP_ERR_INVALID_ARG, TAG, "aim_bits mustn't be less than src_bits");
1678 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->tx), ESP_ERR_INVALID_ARG, TAG, "TX mode is not enabled");
1679 if (src_bits < I2S_BITS_PER_SAMPLE_8BIT || aim_bits < I2S_BITS_PER_SAMPLE_8BIT) {
1680 ESP_LOGE(TAG, "bits mustn't be less than 8, src_bits %d aim_bits %d", src_bits, aim_bits);
1681 return ESP_ERR_INVALID_ARG;
1682 }
1683 if (src_bits > I2S_BITS_PER_SAMPLE_32BIT || aim_bits > I2S_BITS_PER_SAMPLE_32BIT) {
1684 ESP_LOGE(TAG, "bits mustn't be greater than 32, src_bits %d aim_bits %d", src_bits, aim_bits);
1685 return ESP_ERR_INVALID_ARG;
1686 }
1687 if ((src_bits == I2S_BITS_PER_SAMPLE_16BIT || src_bits == I2S_BITS_PER_SAMPLE_32BIT) && (size % 2 != 0)) {
1688 ESP_LOGE(TAG, "size must be a even number while src_bits is even, src_bits %d size %d", src_bits, size);
1689 return ESP_ERR_INVALID_ARG;
1690 }
1691 if (src_bits == I2S_BITS_PER_SAMPLE_24BIT && (size % 3 != 0)) {
1692 ESP_LOGE(TAG, "size must be a multiple of 3 while src_bits is 24, size %d", size);
1693 return ESP_ERR_INVALID_ARG;
1694 }
1695
1696 src_bytes = src_bits / 8;
1697 aim_bytes = aim_bits / 8;
1698 zero_bytes = aim_bytes - src_bytes;
1699 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY);
1700 size = size * aim_bytes / src_bytes;
1701 ESP_LOGD(TAG, "aim_bytes %d src_bytes %d size %d", aim_bytes, src_bytes, size);
1702 while (size > 0) {
1703 if (p_i2s[i2s_num]->tx->rw_pos == p_i2s[i2s_num]->tx->buf_size || p_i2s[i2s_num]->tx->curr_ptr == NULL) {
1704 if (xQueueReceive(p_i2s[i2s_num]->tx->queue, &p_i2s[i2s_num]->tx->curr_ptr, ticks_to_wait) == pdFALSE) {
1705 break;
1706 }
1707 p_i2s[i2s_num]->tx->rw_pos = 0;
1708 }
1709 data_ptr = (char *)p_i2s[i2s_num]->tx->curr_ptr;
1710 data_ptr += p_i2s[i2s_num]->tx->rw_pos;
1711 bytes_can_write = p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos;
1712 if (bytes_can_write > (int)size) {
1713 bytes_can_write = size;
1714 }
1715 tail = bytes_can_write % aim_bytes;
1716 bytes_can_write = bytes_can_write - tail;
1717
1718 memset(data_ptr, 0, bytes_can_write);
1719 for (int j = 0; j < bytes_can_write; j += (aim_bytes - zero_bytes)) {
1720 j += zero_bytes;
1721 memcpy(&data_ptr[j], (const char *)(src + *bytes_written), aim_bytes - zero_bytes);
1722 (*bytes_written) += (aim_bytes - zero_bytes);
1723 }
1724 size -= bytes_can_write;
1725 p_i2s[i2s_num]->tx->rw_pos += bytes_can_write;
1726 }
1727 xSemaphoreGive(p_i2s[i2s_num]->tx->mux);
1728 return ESP_OK;
1729 }
1730
i2s_read(i2s_port_t i2s_num,void * dest,size_t size,size_t * bytes_read,TickType_t ticks_to_wait)1731 esp_err_t i2s_read(i2s_port_t i2s_num, void *dest, size_t size, size_t *bytes_read, TickType_t ticks_to_wait)
1732 {
1733 char *data_ptr;;
1734 char *dest_byte;
1735 int bytes_can_read;
1736 *bytes_read = 0;
1737 dest_byte = (char *)dest;
1738 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1739 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->rx), ESP_ERR_INVALID_ARG, TAG, "RX mode is not enabled");
1740 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY);
1741 #ifdef CONFIG_PM_ENABLE
1742 esp_pm_lock_acquire(p_i2s[i2s_num]->pm_lock);
1743 #endif
1744 while (size > 0) {
1745 if (p_i2s[i2s_num]->rx->rw_pos == p_i2s[i2s_num]->rx->buf_size || p_i2s[i2s_num]->rx->curr_ptr == NULL) {
1746 if (xQueueReceive(p_i2s[i2s_num]->rx->queue, &p_i2s[i2s_num]->rx->curr_ptr, ticks_to_wait) == pdFALSE) {
1747 break;
1748 }
1749 p_i2s[i2s_num]->rx->rw_pos = 0;
1750 }
1751 data_ptr = (char *)p_i2s[i2s_num]->rx->curr_ptr;
1752 data_ptr += p_i2s[i2s_num]->rx->rw_pos;
1753 bytes_can_read = p_i2s[i2s_num]->rx->buf_size - p_i2s[i2s_num]->rx->rw_pos;
1754 if (bytes_can_read > (int)size) {
1755 bytes_can_read = size;
1756 }
1757 memcpy(dest_byte, data_ptr, bytes_can_read);
1758 size -= bytes_can_read;
1759 dest_byte += bytes_can_read;
1760 p_i2s[i2s_num]->rx->rw_pos += bytes_can_read;
1761 (*bytes_read) += bytes_can_read;
1762 }
1763 #ifdef CONFIG_PM_ENABLE
1764 esp_pm_lock_release(p_i2s[i2s_num]->pm_lock);
1765 #endif
1766 xSemaphoreGive(p_i2s[i2s_num]->rx->mux);
1767 return ESP_OK;
1768 }
1769
1770 /*-------------------------------------------------------------
1771 I2S GPIO operation
1772 -------------------------------------------------------------*/
gpio_matrix_out_check_and_set(gpio_num_t gpio,uint32_t signal_idx,bool out_inv,bool oen_inv)1773 static void gpio_matrix_out_check_and_set(gpio_num_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv)
1774 {
1775 //if pin = -1, do not need to configure
1776 if (gpio != -1) {
1777 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
1778 gpio_set_direction(gpio, GPIO_MODE_OUTPUT);
1779 esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv);
1780 }
1781 }
1782
gpio_matrix_in_check_and_set(gpio_num_t gpio,uint32_t signal_idx,bool inv)1783 static void gpio_matrix_in_check_and_set(gpio_num_t gpio, uint32_t signal_idx, bool inv)
1784 {
1785 if (gpio != -1) {
1786 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
1787 /* Set direction, for some GPIOs, the input function are not enabled as default */
1788 gpio_set_direction(gpio, GPIO_MODE_INPUT);
1789 esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv);
1790 }
1791 }
1792
i2s_check_set_mclk(i2s_port_t i2s_num,gpio_num_t gpio_num)1793 static esp_err_t i2s_check_set_mclk(i2s_port_t i2s_num, gpio_num_t gpio_num)
1794 {
1795 if (gpio_num == -1) {
1796 return ESP_OK;
1797 }
1798 #if CONFIG_IDF_TARGET_ESP32
1799 ESP_RETURN_ON_FALSE((gpio_num == GPIO_NUM_0 || gpio_num == GPIO_NUM_1 || gpio_num == GPIO_NUM_3),
1800 ESP_ERR_INVALID_ARG, TAG,
1801 "ESP32 only support to set GPIO0/GPIO1/GPIO3 as mclk signal, error GPIO number:%d", gpio_num);
1802 bool is_i2s0 = i2s_num == I2S_NUM_0;
1803 if (gpio_num == GPIO_NUM_0) {
1804 PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
1805 WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xFFF0 : 0xFFFF);
1806 } else if (gpio_num == GPIO_NUM_1) {
1807 PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_CLK_OUT3);
1808 WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xF0F0 : 0xF0FF);
1809 } else {
1810 PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_CLK_OUT2);
1811 WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xFF00 : 0xFF0F);
1812 }
1813 #else
1814 ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "mck_io_num invalid");
1815 gpio_matrix_out_check_and_set(gpio_num, i2s_periph_signal[i2s_num].mck_out_sig, 0, 0);
1816 #endif
1817 ESP_LOGD(TAG, "I2S%d, MCLK output by GPIO%d", i2s_num, gpio_num);
1818 return ESP_OK;
1819 }
1820
i2s_zero_dma_buffer(i2s_port_t i2s_num)1821 esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num)
1822 {
1823 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1824 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num;
1825
1826 /* Clear I2S RX DMA buffer */
1827 if (p_i2s[i2s_num]->rx && p_i2s[i2s_num]->rx->buf != NULL && p_i2s[i2s_num]->rx->buf_size != 0) {
1828 for (int i = 0; i < buf_cnt; i++) {
1829 memset(p_i2s[i2s_num]->rx->buf[i], 0, p_i2s[i2s_num]->rx->buf_size);
1830 }
1831 }
1832
1833 /* Clear I2S TX DMA buffer */
1834 if (p_i2s[i2s_num]->tx && p_i2s[i2s_num]->tx->buf != NULL && p_i2s[i2s_num]->tx->buf_size != 0) {
1835 /* Finish to write all tx data */
1836 int bytes_left = (p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos) % 4;
1837 if (bytes_left) {
1838 size_t zero_bytes = 0;
1839 size_t bytes_written;
1840 i2s_write(i2s_num, (void *)&zero_bytes, bytes_left, &bytes_written, portMAX_DELAY);
1841 }
1842 for (int i = 0; i < buf_cnt; i++) {
1843 memset(p_i2s[i2s_num]->tx->buf[i], 0, p_i2s[i2s_num]->tx->buf_size);
1844 }
1845 }
1846 return ESP_OK;
1847 }
1848
i2s_set_pin(i2s_port_t i2s_num,const i2s_pin_config_t * pin)1849 esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin)
1850 {
1851 ESP_RETURN_ON_FALSE((i2s_num < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
1852 if (pin == NULL) {
1853 #if SOC_I2S_SUPPORTS_DAC
1854 return i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN);
1855 #else
1856 return ESP_ERR_INVALID_ARG;
1857 #endif
1858 }
1859 /* Check validity of selected pins */
1860 ESP_RETURN_ON_FALSE((pin->bck_io_num == -1 || GPIO_IS_VALID_GPIO(pin->bck_io_num)),
1861 ESP_ERR_INVALID_ARG, TAG, "bck_io_num invalid");
1862 ESP_RETURN_ON_FALSE((pin->ws_io_num == -1 || GPIO_IS_VALID_GPIO(pin->ws_io_num)),
1863 ESP_ERR_INVALID_ARG, TAG, "ws_io_num invalid");
1864 ESP_RETURN_ON_FALSE((pin->data_out_num == -1 || GPIO_IS_VALID_GPIO(pin->data_out_num)),
1865 ESP_ERR_INVALID_ARG, TAG, "data_out_num invalid");
1866 ESP_RETURN_ON_FALSE((pin->data_in_num == -1 || GPIO_IS_VALID_GPIO(pin->data_in_num)),
1867 ESP_ERR_INVALID_ARG, TAG, "data_in_num invalid");
1868
1869 if (p_i2s[i2s_num]->role == I2S_ROLE_SLAVE) {
1870 /* For "tx + rx + slave" or "rx + slave" mode, we should select RX signal index for ws and bck */
1871 if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
1872 gpio_matrix_in_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].s_rx_ws_sig, 0);
1873 gpio_matrix_in_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].s_rx_bck_sig, 0);
1874 /* For "tx + slave" mode, we should select TX signal index for ws and bck */
1875 } else {
1876 gpio_matrix_in_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].s_tx_ws_sig, 0);
1877 gpio_matrix_in_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].s_tx_bck_sig, 0);
1878 }
1879 } else {
1880 /* mclk only available in master mode */
1881 ESP_RETURN_ON_ERROR(i2s_check_set_mclk(i2s_num, pin->mck_io_num), TAG, "mclk config failed");
1882 /* For "tx + rx + master" or "tx + master" mode, we should select TX signal index for ws and bck */
1883 if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
1884 gpio_matrix_out_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].m_tx_ws_sig, 0, 0);
1885 gpio_matrix_out_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].m_tx_bck_sig, 0, 0);
1886 /* For "rx + master" mode, we should select RX signal index for ws and bck */
1887 } else {
1888 gpio_matrix_out_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].m_rx_ws_sig, 0, 0);
1889 gpio_matrix_out_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].m_rx_bck_sig, 0, 0);
1890 }
1891 }
1892
1893 /* Set data input/ouput GPIO */
1894 gpio_matrix_out_check_and_set(pin->data_out_num, i2s_periph_signal[i2s_num].data_out_sig, 0, 0);
1895 gpio_matrix_in_check_and_set(pin->data_in_num, i2s_periph_signal[i2s_num].data_in_sig, 0);
1896 return ESP_OK;
1897 }
1898
i2s_platform_acquire_occupation(int id,const char * comp_name)1899 esp_err_t i2s_platform_acquire_occupation(int id, const char *comp_name)
1900 {
1901 esp_err_t ret = ESP_ERR_NOT_FOUND;
1902 ESP_RETURN_ON_FALSE(id < SOC_I2S_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
1903 portENTER_CRITICAL(&i2s_spinlock[id]);
1904 if (!comp_using_i2s[id]) {
1905 ret = ESP_OK;
1906 comp_using_i2s[id] = comp_name;
1907 periph_module_enable(i2s_periph_signal[id].module);
1908 i2s_ll_enable_clock(I2S_LL_GET_HW(id));
1909 }
1910 portEXIT_CRITICAL(&i2s_spinlock[id]);
1911 return ret;
1912 }
1913
i2s_platform_release_occupation(int id)1914 esp_err_t i2s_platform_release_occupation(int id)
1915 {
1916 esp_err_t ret = ESP_ERR_INVALID_STATE;
1917 ESP_RETURN_ON_FALSE(id < SOC_I2S_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
1918 portENTER_CRITICAL(&i2s_spinlock[id]);
1919 if (comp_using_i2s[id]) {
1920 ret = ESP_OK;
1921 comp_using_i2s[id] = NULL;
1922 /* Disable module clock */
1923 periph_module_disable(i2s_periph_signal[id].module);
1924 i2s_ll_disable_clock(I2S_LL_GET_HW(id));
1925 }
1926 portEXIT_CRITICAL(&i2s_spinlock[id]);
1927 return ret;
1928 }
1929
1930 /**
1931 * @brief This function will be called during start up, to check that the new i2s driver is not running along with the legacy i2s driver
1932 */
check_i2s_driver_conflict(void)1933 static __attribute__((constructor)) void check_i2s_driver_conflict(void)
1934 {
1935 extern __attribute__((weak)) esp_err_t i2s_del_channel(void *handle);
1936 /* If the new I2S driver is linked, the weak function will point to the actual function in the new driver, otherwise it is NULL*/
1937 if ((void *)i2s_del_channel != NULL) {
1938 ESP_EARLY_LOGE(TAG, "CONFLICT! The new i2s driver can't work along with the legacy i2s driver");
1939 abort();
1940 }
1941 ESP_EARLY_LOGW(TAG, "legacy i2s driver is deprecated, please migrate to use driver/i2s_std.h, driver/i2s_pdm.h or driver/i2s_tdm.h");
1942 }
1943
